mbed-dev - fixed drive strength

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fixed drive strength

targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51_bitfields.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:: bogdanm
Date:: Thu Oct 01 15:25:22 2015 +0300
Revision:: 0:9b334a45a8ff
Child:: 144:ef7eb2e8f9f7

Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/* Copyright (c) 2013, Nordic Semiconductor ASA
bogdanm	0:9b334a45a8ff	2	* All rights reserved.
bogdanm	0:9b334a45a8ff	3	*
bogdanm	0:9b334a45a8ff	4	* Redistribution and use in source and binary forms, with or without
bogdanm	0:9b334a45a8ff	5	* modification, are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	6	*
bogdanm	0:9b334a45a8ff	7	* * Redistributions of source code must retain the above copyright notice, this
bogdanm	0:9b334a45a8ff	8	* list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	9	*
bogdanm	0:9b334a45a8ff	10	* * Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	11	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	12	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	13	*
bogdanm	0:9b334a45a8ff	14	* * Neither the name of Nordic Semiconductor ASA nor the names of its
bogdanm	0:9b334a45a8ff	15	* contributors may be used to endorse or promote products derived from
bogdanm	0:9b334a45a8ff	16	* this software without specific prior written permission.
bogdanm	0:9b334a45a8ff	17	*
bogdanm	0:9b334a45a8ff	18	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	19	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	20	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	21	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	22	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	23	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	24	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	25	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	26	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	27	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	28	*
bogdanm	0:9b334a45a8ff	29	*/
bogdanm	0:9b334a45a8ff	30	#ifndef __NRF51_BITS_H
bogdanm	0:9b334a45a8ff	31	#define __NRF51_BITS_H
bogdanm	0:9b334a45a8ff	32
bogdanm	0:9b334a45a8ff	33	/lint ++flb "Enter library region /
bogdanm	0:9b334a45a8ff	34
bogdanm	0:9b334a45a8ff	35	#include <core_cm0.h>
bogdanm	0:9b334a45a8ff	36
bogdanm	0:9b334a45a8ff	37	/* Peripheral: AAR */
bogdanm	0:9b334a45a8ff	38	/* Description: Accelerated Address Resolver. */
bogdanm	0:9b334a45a8ff	39
bogdanm	0:9b334a45a8ff	40	/* Register: AAR_INTENSET */
bogdanm	0:9b334a45a8ff	41	/* Description: Interrupt enable set register. */
bogdanm	0:9b334a45a8ff	42
bogdanm	0:9b334a45a8ff	43	/* Bit 2 : Enable interrupt on NOTRESOLVED event. */
bogdanm	0:9b334a45a8ff	44	#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /!< Position of NOTRESOLVED field. /
bogdanm	0:9b334a45a8ff	45	#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /!< Bit mask of NOTRESOLVED field. /
bogdanm	0:9b334a45a8ff	46	#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	47	#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	48	#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	49
bogdanm	0:9b334a45a8ff	50	/* Bit 1 : Enable interrupt on RESOLVED event. */
bogdanm	0:9b334a45a8ff	51	#define AAR_INTENSET_RESOLVED_Pos (1UL) /!< Position of RESOLVED field. /
bogdanm	0:9b334a45a8ff	52	#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /!< Bit mask of RESOLVED field. /
bogdanm	0:9b334a45a8ff	53	#define AAR_INTENSET_RESOLVED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	54	#define AAR_INTENSET_RESOLVED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	55	#define AAR_INTENSET_RESOLVED_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	56
bogdanm	0:9b334a45a8ff	57	/* Bit 0 : Enable interrupt on END event. */
bogdanm	0:9b334a45a8ff	58	#define AAR_INTENSET_END_Pos (0UL) /!< Position of END field. /
bogdanm	0:9b334a45a8ff	59	#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /!< Bit mask of END field. /
bogdanm	0:9b334a45a8ff	60	#define AAR_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	61	#define AAR_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	62	#define AAR_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	63
bogdanm	0:9b334a45a8ff	64	/* Register: AAR_INTENCLR */
bogdanm	0:9b334a45a8ff	65	/* Description: Interrupt enable clear register. */
bogdanm	0:9b334a45a8ff	66
bogdanm	0:9b334a45a8ff	67	/* Bit 2 : Disable interrupt on NOTRESOLVED event. */
bogdanm	0:9b334a45a8ff	68	#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /!< Position of NOTRESOLVED field. /
bogdanm	0:9b334a45a8ff	69	#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /!< Bit mask of NOTRESOLVED field. /
bogdanm	0:9b334a45a8ff	70	#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	71	#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	72	#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	73
bogdanm	0:9b334a45a8ff	74	/* Bit 1 : Disable interrupt on RESOLVED event. */
bogdanm	0:9b334a45a8ff	75	#define AAR_INTENCLR_RESOLVED_Pos (1UL) /!< Position of RESOLVED field. /
bogdanm	0:9b334a45a8ff	76	#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /!< Bit mask of RESOLVED field. /
bogdanm	0:9b334a45a8ff	77	#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	78	#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	79	#define AAR_INTENCLR_RESOLVED_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	80
bogdanm	0:9b334a45a8ff	81	/* Bit 0 : Disable interrupt on ENDKSGEN event. */
bogdanm	0:9b334a45a8ff	82	#define AAR_INTENCLR_END_Pos (0UL) /!< Position of END field. /
bogdanm	0:9b334a45a8ff	83	#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /!< Bit mask of END field. /
bogdanm	0:9b334a45a8ff	84	#define AAR_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	85	#define AAR_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	86	#define AAR_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	87
bogdanm	0:9b334a45a8ff	88	/* Register: AAR_STATUS */
bogdanm	0:9b334a45a8ff	89	/* Description: Resolution status. */
bogdanm	0:9b334a45a8ff	90
bogdanm	0:9b334a45a8ff	91	/* Bits 3..0 : The IRK used last time an address was resolved. */
bogdanm	0:9b334a45a8ff	92	#define AAR_STATUS_STATUS_Pos (0UL) /!< Position of STATUS field. /
bogdanm	0:9b334a45a8ff	93	#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /!< Bit mask of STATUS field. /
bogdanm	0:9b334a45a8ff	94
bogdanm	0:9b334a45a8ff	95	/* Register: AAR_ENABLE */
bogdanm	0:9b334a45a8ff	96	/* Description: Enable AAR. */
bogdanm	0:9b334a45a8ff	97
bogdanm	0:9b334a45a8ff	98	/* Bits 1..0 : Enable AAR. */
bogdanm	0:9b334a45a8ff	99	#define AAR_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
bogdanm	0:9b334a45a8ff	100	#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
bogdanm	0:9b334a45a8ff	101	#define AAR_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled AAR. /
bogdanm	0:9b334a45a8ff	102	#define AAR_ENABLE_ENABLE_Enabled (0x03UL) /!< Enable AAR. /
bogdanm	0:9b334a45a8ff	103
bogdanm	0:9b334a45a8ff	104	/* Register: AAR_NIRK */
bogdanm	0:9b334a45a8ff	105	/* Description: Number of Identity root Keys in the IRK data structure. */
bogdanm	0:9b334a45a8ff	106
bogdanm	0:9b334a45a8ff	107	/* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */
bogdanm	0:9b334a45a8ff	108	#define AAR_NIRK_NIRK_Pos (0UL) /!< Position of NIRK field. /
bogdanm	0:9b334a45a8ff	109	#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /!< Bit mask of NIRK field. /
bogdanm	0:9b334a45a8ff	110
bogdanm	0:9b334a45a8ff	111	/* Register: AAR_POWER */
bogdanm	0:9b334a45a8ff	112	/* Description: Peripheral power control. */
bogdanm	0:9b334a45a8ff	113
bogdanm	0:9b334a45a8ff	114	/* Bit 0 : Peripheral power control. */
bogdanm	0:9b334a45a8ff	115	#define AAR_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	0:9b334a45a8ff	116	#define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	0:9b334a45a8ff	117	#define AAR_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	0:9b334a45a8ff	118	#define AAR_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	0:9b334a45a8ff	119
bogdanm	0:9b334a45a8ff	120
bogdanm	0:9b334a45a8ff	121	/* Peripheral: ADC */
bogdanm	0:9b334a45a8ff	122	/* Description: Analog to digital converter. */
bogdanm	0:9b334a45a8ff	123
bogdanm	0:9b334a45a8ff	124	/* Register: ADC_INTENSET */
bogdanm	0:9b334a45a8ff	125	/* Description: Interrupt enable set register. */
bogdanm	0:9b334a45a8ff	126
bogdanm	0:9b334a45a8ff	127	/* Bit 0 : Enable interrupt on END event. */
bogdanm	0:9b334a45a8ff	128	#define ADC_INTENSET_END_Pos (0UL) /!< Position of END field. /
bogdanm	0:9b334a45a8ff	129	#define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /!< Bit mask of END field. /
bogdanm	0:9b334a45a8ff	130	#define ADC_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	131	#define ADC_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	132	#define ADC_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	133
bogdanm	0:9b334a45a8ff	134	/* Register: ADC_INTENCLR */
bogdanm	0:9b334a45a8ff	135	/* Description: Interrupt enable clear register. */
bogdanm	0:9b334a45a8ff	136
bogdanm	0:9b334a45a8ff	137	/* Bit 0 : Disable interrupt on END event. */
bogdanm	0:9b334a45a8ff	138	#define ADC_INTENCLR_END_Pos (0UL) /!< Position of END field. /
bogdanm	0:9b334a45a8ff	139	#define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /!< Bit mask of END field. /
bogdanm	0:9b334a45a8ff	140	#define ADC_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	141	#define ADC_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	142	#define ADC_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	143
bogdanm	0:9b334a45a8ff	144	/* Register: ADC_BUSY */
bogdanm	0:9b334a45a8ff	145	/* Description: ADC busy register. */
bogdanm	0:9b334a45a8ff	146
bogdanm	0:9b334a45a8ff	147	/* Bit 0 : ADC busy register. */
bogdanm	0:9b334a45a8ff	148	#define ADC_BUSY_BUSY_Pos (0UL) /!< Position of BUSY field. /
bogdanm	0:9b334a45a8ff	149	#define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /!< Bit mask of BUSY field. /
bogdanm	0:9b334a45a8ff	150	#define ADC_BUSY_BUSY_Ready (0UL) /!< No ongoing ADC conversion is taking place. ADC is ready. /
bogdanm	0:9b334a45a8ff	151	#define ADC_BUSY_BUSY_Busy (1UL) /!< An ADC conversion is taking place. ADC is busy. /
bogdanm	0:9b334a45a8ff	152
bogdanm	0:9b334a45a8ff	153	/* Register: ADC_ENABLE */
bogdanm	0:9b334a45a8ff	154	/* Description: ADC enable. */
bogdanm	0:9b334a45a8ff	155
bogdanm	0:9b334a45a8ff	156	/* Bits 1..0 : ADC enable. */
bogdanm	0:9b334a45a8ff	157	#define ADC_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
bogdanm	0:9b334a45a8ff	158	#define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
bogdanm	0:9b334a45a8ff	159	#define ADC_ENABLE_ENABLE_Disabled (0x00UL) /!< ADC is disabled. /
bogdanm	0:9b334a45a8ff	160	#define ADC_ENABLE_ENABLE_Enabled (0x01UL) /!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. /
bogdanm	0:9b334a45a8ff	161
bogdanm	0:9b334a45a8ff	162	/* Register: ADC_CONFIG */
bogdanm	0:9b334a45a8ff	163	/* Description: ADC configuration register. */
bogdanm	0:9b334a45a8ff	164
bogdanm	0:9b334a45a8ff	165	/* Bits 17..16 : ADC external reference pin selection. */
bogdanm	0:9b334a45a8ff	166	#define ADC_CONFIG_EXTREFSEL_Pos (16UL) /!< Position of EXTREFSEL field. /
bogdanm	0:9b334a45a8ff	167	#define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /!< Bit mask of EXTREFSEL field. /
bogdanm	0:9b334a45a8ff	168	#define ADC_CONFIG_EXTREFSEL_None (0UL) /!< Analog external reference inputs disabled. /
bogdanm	0:9b334a45a8ff	169	#define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /!< Use analog reference 0 as reference. /
bogdanm	0:9b334a45a8ff	170	#define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /!< Use analog reference 1 as reference. /
bogdanm	0:9b334a45a8ff	171
bogdanm	0:9b334a45a8ff	172	/* Bits 15..8 : ADC analog pin selection. */
bogdanm	0:9b334a45a8ff	173	#define ADC_CONFIG_PSEL_Pos (8UL) /!< Position of PSEL field. /
bogdanm	0:9b334a45a8ff	174	#define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /!< Bit mask of PSEL field. /
bogdanm	0:9b334a45a8ff	175	#define ADC_CONFIG_PSEL_Disabled (0UL) /!< Analog input pins disabled. /
bogdanm	0:9b334a45a8ff	176	#define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /!< Use analog input 0 as analog input. /
bogdanm	0:9b334a45a8ff	177	#define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /!< Use analog input 1 as analog input. /
bogdanm	0:9b334a45a8ff	178	#define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /!< Use analog input 2 as analog input. /
bogdanm	0:9b334a45a8ff	179	#define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /!< Use analog input 3 as analog input. /
bogdanm	0:9b334a45a8ff	180	#define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /!< Use analog input 4 as analog input. /
bogdanm	0:9b334a45a8ff	181	#define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /!< Use analog input 5 as analog input. /
bogdanm	0:9b334a45a8ff	182	#define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /!< Use analog input 6 as analog input. /
bogdanm	0:9b334a45a8ff	183	#define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /!< Use analog input 7 as analog input. /
bogdanm	0:9b334a45a8ff	184
bogdanm	0:9b334a45a8ff	185	/* Bits 6..5 : ADC reference selection. */
bogdanm	0:9b334a45a8ff	186	#define ADC_CONFIG_REFSEL_Pos (5UL) /!< Position of REFSEL field. /
bogdanm	0:9b334a45a8ff	187	#define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /!< Bit mask of REFSEL field. /
bogdanm	0:9b334a45a8ff	188	#define ADC_CONFIG_REFSEL_VBG (0x00UL) /!< Use internal 1.2V bandgap voltage as reference for conversion. /
bogdanm	0:9b334a45a8ff	189	#define ADC_CONFIG_REFSEL_External (0x01UL) /!< Use external source configured by EXTREFSEL as reference for conversion. /
bogdanm	0:9b334a45a8ff	190	#define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. /
bogdanm	0:9b334a45a8ff	191	#define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. /
bogdanm	0:9b334a45a8ff	192
bogdanm	0:9b334a45a8ff	193	/* Bits 4..2 : ADC input selection. */
bogdanm	0:9b334a45a8ff	194	#define ADC_CONFIG_INPSEL_Pos (2UL) /!< Position of INPSEL field. /
bogdanm	0:9b334a45a8ff	195	#define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /!< Bit mask of INPSEL field. /
bogdanm	0:9b334a45a8ff	196	#define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /!< Analog input specified by PSEL with no prescaling used as input for the conversion. /
bogdanm	0:9b334a45a8ff	197	#define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. /
bogdanm	0:9b334a45a8ff	198	#define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. /
bogdanm	0:9b334a45a8ff	199	#define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /!< Supply voltage with 2/3 prescaling used as input for the conversion. /
bogdanm	0:9b334a45a8ff	200	#define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /!< Supply voltage with 1/3 prescaling used as input for the conversion. /
bogdanm	0:9b334a45a8ff	201
bogdanm	0:9b334a45a8ff	202	/* Bits 1..0 : ADC resolution. */
bogdanm	0:9b334a45a8ff	203	#define ADC_CONFIG_RES_Pos (0UL) /!< Position of RES field. /
bogdanm	0:9b334a45a8ff	204	#define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /!< Bit mask of RES field. /
bogdanm	0:9b334a45a8ff	205	#define ADC_CONFIG_RES_8bit (0x00UL) /!< 8bit ADC resolution. /
bogdanm	0:9b334a45a8ff	206	#define ADC_CONFIG_RES_9bit (0x01UL) /!< 9bit ADC resolution. /
bogdanm	0:9b334a45a8ff	207	#define ADC_CONFIG_RES_10bit (0x02UL) /!< 10bit ADC resolution. /
bogdanm	0:9b334a45a8ff	208
bogdanm	0:9b334a45a8ff	209	/* Register: ADC_RESULT */
bogdanm	0:9b334a45a8ff	210	/* Description: Result of ADC conversion. */
bogdanm	0:9b334a45a8ff	211
bogdanm	0:9b334a45a8ff	212	/* Bits 9..0 : Result of ADC conversion. */
bogdanm	0:9b334a45a8ff	213	#define ADC_RESULT_RESULT_Pos (0UL) /!< Position of RESULT field. /
bogdanm	0:9b334a45a8ff	214	#define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /!< Bit mask of RESULT field. /
bogdanm	0:9b334a45a8ff	215
bogdanm	0:9b334a45a8ff	216	/* Register: ADC_POWER */
bogdanm	0:9b334a45a8ff	217	/* Description: Peripheral power control. */
bogdanm	0:9b334a45a8ff	218
bogdanm	0:9b334a45a8ff	219	/* Bit 0 : Peripheral power control. */
bogdanm	0:9b334a45a8ff	220	#define ADC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	0:9b334a45a8ff	221	#define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	0:9b334a45a8ff	222	#define ADC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	0:9b334a45a8ff	223	#define ADC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	0:9b334a45a8ff	224
bogdanm	0:9b334a45a8ff	225
bogdanm	0:9b334a45a8ff	226	/* Peripheral: AMLI */
bogdanm	0:9b334a45a8ff	227	/* Description: AHB Multi-Layer Interface. */
bogdanm	0:9b334a45a8ff	228
bogdanm	0:9b334a45a8ff	229	/* Register: AMLI_RAMPRI_CPU0 */
bogdanm	0:9b334a45a8ff	230	/* Description: Configurable priority configuration register for CPU0. */
bogdanm	0:9b334a45a8ff	231
bogdanm	0:9b334a45a8ff	232	/* Bits 31..28 : Configuration field for RAM block 7. */
bogdanm	0:9b334a45a8ff	233	#define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /!< Position of RAM7 field. /
bogdanm	0:9b334a45a8ff	234	#define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /!< Bit mask of RAM7 field. /
bogdanm	0:9b334a45a8ff	235	#define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	236	#define AMLI_RAMPRI_CPU0_RAM7_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	237	#define AMLI_RAMPRI_CPU0_RAM7_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	238	#define AMLI_RAMPRI_CPU0_RAM7_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	239	#define AMLI_RAMPRI_CPU0_RAM7_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	240	#define AMLI_RAMPRI_CPU0_RAM7_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	241	#define AMLI_RAMPRI_CPU0_RAM7_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	242	#define AMLI_RAMPRI_CPU0_RAM7_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	243
bogdanm	0:9b334a45a8ff	244	/* Bits 27..24 : Configuration field for RAM block 6. */
bogdanm	0:9b334a45a8ff	245	#define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /!< Position of RAM6 field. /
bogdanm	0:9b334a45a8ff	246	#define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /!< Bit mask of RAM6 field. /
bogdanm	0:9b334a45a8ff	247	#define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	248	#define AMLI_RAMPRI_CPU0_RAM6_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	249	#define AMLI_RAMPRI_CPU0_RAM6_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	250	#define AMLI_RAMPRI_CPU0_RAM6_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	251	#define AMLI_RAMPRI_CPU0_RAM6_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	252	#define AMLI_RAMPRI_CPU0_RAM6_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	253	#define AMLI_RAMPRI_CPU0_RAM6_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	254	#define AMLI_RAMPRI_CPU0_RAM6_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	255
bogdanm	0:9b334a45a8ff	256	/* Bits 23..20 : Configuration field for RAM block 5. */
bogdanm	0:9b334a45a8ff	257	#define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /!< Position of RAM5 field. /
bogdanm	0:9b334a45a8ff	258	#define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /!< Bit mask of RAM5 field. /
bogdanm	0:9b334a45a8ff	259	#define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	260	#define AMLI_RAMPRI_CPU0_RAM5_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	261	#define AMLI_RAMPRI_CPU0_RAM5_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	262	#define AMLI_RAMPRI_CPU0_RAM5_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	263	#define AMLI_RAMPRI_CPU0_RAM5_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	264	#define AMLI_RAMPRI_CPU0_RAM5_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	265	#define AMLI_RAMPRI_CPU0_RAM5_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	266	#define AMLI_RAMPRI_CPU0_RAM5_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	267
bogdanm	0:9b334a45a8ff	268	/* Bits 19..16 : Configuration field for RAM block 4. */
bogdanm	0:9b334a45a8ff	269	#define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /!< Position of RAM4 field. /
bogdanm	0:9b334a45a8ff	270	#define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /!< Bit mask of RAM4 field. /
bogdanm	0:9b334a45a8ff	271	#define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	272	#define AMLI_RAMPRI_CPU0_RAM4_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	273	#define AMLI_RAMPRI_CPU0_RAM4_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	274	#define AMLI_RAMPRI_CPU0_RAM4_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	275	#define AMLI_RAMPRI_CPU0_RAM4_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	276	#define AMLI_RAMPRI_CPU0_RAM4_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	277	#define AMLI_RAMPRI_CPU0_RAM4_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	278	#define AMLI_RAMPRI_CPU0_RAM4_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	279
bogdanm	0:9b334a45a8ff	280	/* Bits 15..12 : Configuration field for RAM block 3. */
bogdanm	0:9b334a45a8ff	281	#define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /!< Position of RAM3 field. /
bogdanm	0:9b334a45a8ff	282	#define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /!< Bit mask of RAM3 field. /
bogdanm	0:9b334a45a8ff	283	#define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	284	#define AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	285	#define AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	286	#define AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	287	#define AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	288	#define AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	289	#define AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	290	#define AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	291
bogdanm	0:9b334a45a8ff	292	/* Bits 11..8 : Configuration field for RAM block 2. */
bogdanm	0:9b334a45a8ff	293	#define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /!< Position of RAM2 field. /
bogdanm	0:9b334a45a8ff	294	#define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /!< Bit mask of RAM2 field. /
bogdanm	0:9b334a45a8ff	295	#define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	296	#define AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	297	#define AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	298	#define AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	299	#define AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	300	#define AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	301	#define AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	302	#define AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	303
bogdanm	0:9b334a45a8ff	304	/* Bits 7..4 : Configuration field for RAM block 1. */
bogdanm	0:9b334a45a8ff	305	#define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /!< Position of RAM1 field. /
bogdanm	0:9b334a45a8ff	306	#define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /!< Bit mask of RAM1 field. /
bogdanm	0:9b334a45a8ff	307	#define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	308	#define AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	309	#define AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	310	#define AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	311	#define AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	312	#define AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	313	#define AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	314	#define AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	315
bogdanm	0:9b334a45a8ff	316	/* Bits 3..0 : Configuration field for RAM block 0. */
bogdanm	0:9b334a45a8ff	317	#define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /!< Position of RAM0 field. /
bogdanm	0:9b334a45a8ff	318	#define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /!< Bit mask of RAM0 field. /
bogdanm	0:9b334a45a8ff	319	#define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	320	#define AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	321	#define AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	322	#define AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	323	#define AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	324	#define AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	325	#define AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	326	#define AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	327
bogdanm	0:9b334a45a8ff	328	/* Register: AMLI_RAMPRI_SPIS1 */
bogdanm	0:9b334a45a8ff	329	/* Description: Configurable priority configuration register for SPIS1. */
bogdanm	0:9b334a45a8ff	330
bogdanm	0:9b334a45a8ff	331	/* Bits 31..28 : Configuration field for RAM block 7. */
bogdanm	0:9b334a45a8ff	332	#define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /!< Position of RAM7 field. /
bogdanm	0:9b334a45a8ff	333	#define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /!< Bit mask of RAM7 field. /
bogdanm	0:9b334a45a8ff	334	#define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	335	#define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	336	#define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	337	#define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	338	#define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	339	#define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	340	#define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	341	#define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	342
bogdanm	0:9b334a45a8ff	343	/* Bits 27..24 : Configuration field for RAM block 6. */
bogdanm	0:9b334a45a8ff	344	#define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /!< Position of RAM6 field. /
bogdanm	0:9b334a45a8ff	345	#define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /!< Bit mask of RAM6 field. /
bogdanm	0:9b334a45a8ff	346	#define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	347	#define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	348	#define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	349	#define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	350	#define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	351	#define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	352	#define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	353	#define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	354
bogdanm	0:9b334a45a8ff	355	/* Bits 23..20 : Configuration field for RAM block 5. */
bogdanm	0:9b334a45a8ff	356	#define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /!< Position of RAM5 field. /
bogdanm	0:9b334a45a8ff	357	#define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /!< Bit mask of RAM5 field. /
bogdanm	0:9b334a45a8ff	358	#define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	359	#define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	360	#define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	361	#define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	362	#define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	363	#define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	364	#define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	365	#define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	366
bogdanm	0:9b334a45a8ff	367	/* Bits 19..16 : Configuration field for RAM block 4. */
bogdanm	0:9b334a45a8ff	368	#define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /!< Position of RAM4 field. /
bogdanm	0:9b334a45a8ff	369	#define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /!< Bit mask of RAM4 field. /
bogdanm	0:9b334a45a8ff	370	#define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	371	#define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	372	#define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	373	#define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	374	#define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	375	#define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	376	#define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	377	#define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	378
bogdanm	0:9b334a45a8ff	379	/* Bits 15..12 : Configuration field for RAM block 3. */
bogdanm	0:9b334a45a8ff	380	#define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /!< Position of RAM3 field. /
bogdanm	0:9b334a45a8ff	381	#define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /!< Bit mask of RAM3 field. /
bogdanm	0:9b334a45a8ff	382	#define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	383	#define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	384	#define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	385	#define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	386	#define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	387	#define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	388	#define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	389	#define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	390
bogdanm	0:9b334a45a8ff	391	/* Bits 11..8 : Configuration field for RAM block 2. */
bogdanm	0:9b334a45a8ff	392	#define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /!< Position of RAM2 field. /
bogdanm	0:9b334a45a8ff	393	#define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /!< Bit mask of RAM2 field. /
bogdanm	0:9b334a45a8ff	394	#define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	395	#define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	396	#define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	397	#define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	398	#define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	399	#define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	400	#define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	401	#define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	402
bogdanm	0:9b334a45a8ff	403	/* Bits 7..4 : Configuration field for RAM block 1. */
bogdanm	0:9b334a45a8ff	404	#define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /!< Position of RAM1 field. /
bogdanm	0:9b334a45a8ff	405	#define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /!< Bit mask of RAM1 field. /
bogdanm	0:9b334a45a8ff	406	#define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	407	#define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	408	#define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	409	#define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	410	#define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	411	#define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	412	#define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	413	#define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	414
bogdanm	0:9b334a45a8ff	415	/* Bits 3..0 : Configuration field for RAM block 0. */
bogdanm	0:9b334a45a8ff	416	#define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /!< Position of RAM0 field. /
bogdanm	0:9b334a45a8ff	417	#define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /!< Bit mask of RAM0 field. /
bogdanm	0:9b334a45a8ff	418	#define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	419	#define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	420	#define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	421	#define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	422	#define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	423	#define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	424	#define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	425	#define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	426
bogdanm	0:9b334a45a8ff	427	/* Register: AMLI_RAMPRI_RADIO */
bogdanm	0:9b334a45a8ff	428	/* Description: Configurable priority configuration register for RADIO. */
bogdanm	0:9b334a45a8ff	429
bogdanm	0:9b334a45a8ff	430	/* Bits 31..28 : Configuration field for RAM block 7. */
bogdanm	0:9b334a45a8ff	431	#define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /!< Position of RAM7 field. /
bogdanm	0:9b334a45a8ff	432	#define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /!< Bit mask of RAM7 field. /
bogdanm	0:9b334a45a8ff	433	#define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	434	#define AMLI_RAMPRI_RADIO_RAM7_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	435	#define AMLI_RAMPRI_RADIO_RAM7_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	436	#define AMLI_RAMPRI_RADIO_RAM7_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	437	#define AMLI_RAMPRI_RADIO_RAM7_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	438	#define AMLI_RAMPRI_RADIO_RAM7_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	439	#define AMLI_RAMPRI_RADIO_RAM7_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	440	#define AMLI_RAMPRI_RADIO_RAM7_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	441
bogdanm	0:9b334a45a8ff	442	/* Bits 27..24 : Configuration field for RAM block 6. */
bogdanm	0:9b334a45a8ff	443	#define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /!< Position of RAM6 field. /
bogdanm	0:9b334a45a8ff	444	#define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /!< Bit mask of RAM6 field. /
bogdanm	0:9b334a45a8ff	445	#define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	446	#define AMLI_RAMPRI_RADIO_RAM6_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	447	#define AMLI_RAMPRI_RADIO_RAM6_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	448	#define AMLI_RAMPRI_RADIO_RAM6_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	449	#define AMLI_RAMPRI_RADIO_RAM6_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	450	#define AMLI_RAMPRI_RADIO_RAM6_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	451	#define AMLI_RAMPRI_RADIO_RAM6_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	452	#define AMLI_RAMPRI_RADIO_RAM6_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	453
bogdanm	0:9b334a45a8ff	454	/* Bits 23..20 : Configuration field for RAM block 5. */
bogdanm	0:9b334a45a8ff	455	#define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /!< Position of RAM5 field. /
bogdanm	0:9b334a45a8ff	456	#define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /!< Bit mask of RAM5 field. /
bogdanm	0:9b334a45a8ff	457	#define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	458	#define AMLI_RAMPRI_RADIO_RAM5_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	459	#define AMLI_RAMPRI_RADIO_RAM5_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	460	#define AMLI_RAMPRI_RADIO_RAM5_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	461	#define AMLI_RAMPRI_RADIO_RAM5_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	462	#define AMLI_RAMPRI_RADIO_RAM5_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	463	#define AMLI_RAMPRI_RADIO_RAM5_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	464	#define AMLI_RAMPRI_RADIO_RAM5_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	465
bogdanm	0:9b334a45a8ff	466	/* Bits 19..16 : Configuration field for RAM block 4. */
bogdanm	0:9b334a45a8ff	467	#define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /!< Position of RAM4 field. /
bogdanm	0:9b334a45a8ff	468	#define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /!< Bit mask of RAM4 field. /
bogdanm	0:9b334a45a8ff	469	#define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	470	#define AMLI_RAMPRI_RADIO_RAM4_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	471	#define AMLI_RAMPRI_RADIO_RAM4_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	472	#define AMLI_RAMPRI_RADIO_RAM4_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	473	#define AMLI_RAMPRI_RADIO_RAM4_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	474	#define AMLI_RAMPRI_RADIO_RAM4_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	475	#define AMLI_RAMPRI_RADIO_RAM4_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	476	#define AMLI_RAMPRI_RADIO_RAM4_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	477
bogdanm	0:9b334a45a8ff	478	/* Bits 15..12 : Configuration field for RAM block 3. */
bogdanm	0:9b334a45a8ff	479	#define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /!< Position of RAM3 field. /
bogdanm	0:9b334a45a8ff	480	#define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /!< Bit mask of RAM3 field. /
bogdanm	0:9b334a45a8ff	481	#define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	482	#define AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	483	#define AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	484	#define AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	485	#define AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	486	#define AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	487	#define AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	488	#define AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	489
bogdanm	0:9b334a45a8ff	490	/* Bits 11..8 : Configuration field for RAM block 2. */
bogdanm	0:9b334a45a8ff	491	#define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /!< Position of RAM2 field. /
bogdanm	0:9b334a45a8ff	492	#define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /!< Bit mask of RAM2 field. /
bogdanm	0:9b334a45a8ff	493	#define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	494	#define AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	495	#define AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	496	#define AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	497	#define AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	498	#define AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	499	#define AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	500	#define AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	501
bogdanm	0:9b334a45a8ff	502	/* Bits 7..4 : Configuration field for RAM block 1. */
bogdanm	0:9b334a45a8ff	503	#define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /!< Position of RAM1 field. /
bogdanm	0:9b334a45a8ff	504	#define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /!< Bit mask of RAM1 field. /
bogdanm	0:9b334a45a8ff	505	#define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	506	#define AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	507	#define AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	508	#define AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	509	#define AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	510	#define AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	511	#define AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	512	#define AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	513
bogdanm	0:9b334a45a8ff	514	/* Bits 3..0 : Configuration field for RAM block 0. */
bogdanm	0:9b334a45a8ff	515	#define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /!< Position of RAM0 field. /
bogdanm	0:9b334a45a8ff	516	#define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /!< Bit mask of RAM0 field. /
bogdanm	0:9b334a45a8ff	517	#define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	518	#define AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	519	#define AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	520	#define AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	521	#define AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	522	#define AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	523	#define AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	524	#define AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	525
bogdanm	0:9b334a45a8ff	526	/* Register: AMLI_RAMPRI_ECB */
bogdanm	0:9b334a45a8ff	527	/* Description: Configurable priority configuration register for ECB. */
bogdanm	0:9b334a45a8ff	528
bogdanm	0:9b334a45a8ff	529	/* Bits 31..28 : Configuration field for RAM block 7. */
bogdanm	0:9b334a45a8ff	530	#define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /!< Position of RAM7 field. /
bogdanm	0:9b334a45a8ff	531	#define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /!< Bit mask of RAM7 field. /
bogdanm	0:9b334a45a8ff	532	#define AMLI_RAMPRI_ECB_RAM7_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	533	#define AMLI_RAMPRI_ECB_RAM7_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	534	#define AMLI_RAMPRI_ECB_RAM7_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	535	#define AMLI_RAMPRI_ECB_RAM7_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	536	#define AMLI_RAMPRI_ECB_RAM7_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	537	#define AMLI_RAMPRI_ECB_RAM7_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	538	#define AMLI_RAMPRI_ECB_RAM7_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	539	#define AMLI_RAMPRI_ECB_RAM7_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	540
bogdanm	0:9b334a45a8ff	541	/* Bits 27..24 : Configuration field for RAM block 6. */
bogdanm	0:9b334a45a8ff	542	#define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /!< Position of RAM6 field. /
bogdanm	0:9b334a45a8ff	543	#define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /!< Bit mask of RAM6 field. /
bogdanm	0:9b334a45a8ff	544	#define AMLI_RAMPRI_ECB_RAM6_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	545	#define AMLI_RAMPRI_ECB_RAM6_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	546	#define AMLI_RAMPRI_ECB_RAM6_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	547	#define AMLI_RAMPRI_ECB_RAM6_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	548	#define AMLI_RAMPRI_ECB_RAM6_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	549	#define AMLI_RAMPRI_ECB_RAM6_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	550	#define AMLI_RAMPRI_ECB_RAM6_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	551	#define AMLI_RAMPRI_ECB_RAM6_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	552
bogdanm	0:9b334a45a8ff	553	/* Bits 23..20 : Configuration field for RAM block 5. */
bogdanm	0:9b334a45a8ff	554	#define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /!< Position of RAM5 field. /
bogdanm	0:9b334a45a8ff	555	#define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /!< Bit mask of RAM5 field. /
bogdanm	0:9b334a45a8ff	556	#define AMLI_RAMPRI_ECB_RAM5_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	557	#define AMLI_RAMPRI_ECB_RAM5_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	558	#define AMLI_RAMPRI_ECB_RAM5_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	559	#define AMLI_RAMPRI_ECB_RAM5_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	560	#define AMLI_RAMPRI_ECB_RAM5_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	561	#define AMLI_RAMPRI_ECB_RAM5_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	562	#define AMLI_RAMPRI_ECB_RAM5_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	563	#define AMLI_RAMPRI_ECB_RAM5_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	564
bogdanm	0:9b334a45a8ff	565	/* Bits 19..16 : Configuration field for RAM block 4. */
bogdanm	0:9b334a45a8ff	566	#define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /!< Position of RAM4 field. /
bogdanm	0:9b334a45a8ff	567	#define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /!< Bit mask of RAM4 field. /
bogdanm	0:9b334a45a8ff	568	#define AMLI_RAMPRI_ECB_RAM4_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	569	#define AMLI_RAMPRI_ECB_RAM4_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	570	#define AMLI_RAMPRI_ECB_RAM4_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	571	#define AMLI_RAMPRI_ECB_RAM4_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	572	#define AMLI_RAMPRI_ECB_RAM4_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	573	#define AMLI_RAMPRI_ECB_RAM4_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	574	#define AMLI_RAMPRI_ECB_RAM4_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	575	#define AMLI_RAMPRI_ECB_RAM4_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	576
bogdanm	0:9b334a45a8ff	577	/* Bits 15..12 : Configuration field for RAM block 3. */
bogdanm	0:9b334a45a8ff	578	#define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /!< Position of RAM3 field. /
bogdanm	0:9b334a45a8ff	579	#define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /!< Bit mask of RAM3 field. /
bogdanm	0:9b334a45a8ff	580	#define AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	581	#define AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	582	#define AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	583	#define AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	584	#define AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	585	#define AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	586	#define AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	587	#define AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	588
bogdanm	0:9b334a45a8ff	589	/* Bits 11..8 : Configuration field for RAM block 2. */
bogdanm	0:9b334a45a8ff	590	#define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /!< Position of RAM2 field. /
bogdanm	0:9b334a45a8ff	591	#define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /!< Bit mask of RAM2 field. /
bogdanm	0:9b334a45a8ff	592	#define AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	593	#define AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	594	#define AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	595	#define AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	596	#define AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	597	#define AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	598	#define AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	599	#define AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	600
bogdanm	0:9b334a45a8ff	601	/* Bits 7..4 : Configuration field for RAM block 1. */
bogdanm	0:9b334a45a8ff	602	#define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /!< Position of RAM1 field. /
bogdanm	0:9b334a45a8ff	603	#define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /!< Bit mask of RAM1 field. /
bogdanm	0:9b334a45a8ff	604	#define AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	605	#define AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	606	#define AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	607	#define AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	608	#define AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	609	#define AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	610	#define AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	611	#define AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	612
bogdanm	0:9b334a45a8ff	613	/* Bits 3..0 : Configuration field for RAM block 0. */
bogdanm	0:9b334a45a8ff	614	#define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /!< Position of RAM0 field. /
bogdanm	0:9b334a45a8ff	615	#define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /!< Bit mask of RAM0 field. /
bogdanm	0:9b334a45a8ff	616	#define AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	617	#define AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	618	#define AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	619	#define AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	620	#define AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	621	#define AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	622	#define AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	623	#define AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	624
bogdanm	0:9b334a45a8ff	625	/* Register: AMLI_RAMPRI_CCM */
bogdanm	0:9b334a45a8ff	626	/* Description: Configurable priority configuration register for CCM. */
bogdanm	0:9b334a45a8ff	627
bogdanm	0:9b334a45a8ff	628	/* Bits 31..28 : Configuration field for RAM block 7. */
bogdanm	0:9b334a45a8ff	629	#define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /!< Position of RAM7 field. /
bogdanm	0:9b334a45a8ff	630	#define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /!< Bit mask of RAM7 field. /
bogdanm	0:9b334a45a8ff	631	#define AMLI_RAMPRI_CCM_RAM7_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	632	#define AMLI_RAMPRI_CCM_RAM7_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	633	#define AMLI_RAMPRI_CCM_RAM7_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	634	#define AMLI_RAMPRI_CCM_RAM7_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	635	#define AMLI_RAMPRI_CCM_RAM7_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	636	#define AMLI_RAMPRI_CCM_RAM7_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	637	#define AMLI_RAMPRI_CCM_RAM7_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	638	#define AMLI_RAMPRI_CCM_RAM7_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	639
bogdanm	0:9b334a45a8ff	640	/* Bits 27..24 : Configuration field for RAM block 6. */
bogdanm	0:9b334a45a8ff	641	#define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /!< Position of RAM6 field. /
bogdanm	0:9b334a45a8ff	642	#define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /!< Bit mask of RAM6 field. /
bogdanm	0:9b334a45a8ff	643	#define AMLI_RAMPRI_CCM_RAM6_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	644	#define AMLI_RAMPRI_CCM_RAM6_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	645	#define AMLI_RAMPRI_CCM_RAM6_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	646	#define AMLI_RAMPRI_CCM_RAM6_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	647	#define AMLI_RAMPRI_CCM_RAM6_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	648	#define AMLI_RAMPRI_CCM_RAM6_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	649	#define AMLI_RAMPRI_CCM_RAM6_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	650	#define AMLI_RAMPRI_CCM_RAM6_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	651
bogdanm	0:9b334a45a8ff	652	/* Bits 23..20 : Configuration field for RAM block 5. */
bogdanm	0:9b334a45a8ff	653	#define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /!< Position of RAM5 field. /
bogdanm	0:9b334a45a8ff	654	#define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /!< Bit mask of RAM5 field. /
bogdanm	0:9b334a45a8ff	655	#define AMLI_RAMPRI_CCM_RAM5_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	656	#define AMLI_RAMPRI_CCM_RAM5_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	657	#define AMLI_RAMPRI_CCM_RAM5_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	658	#define AMLI_RAMPRI_CCM_RAM5_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	659	#define AMLI_RAMPRI_CCM_RAM5_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	660	#define AMLI_RAMPRI_CCM_RAM5_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	661	#define AMLI_RAMPRI_CCM_RAM5_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	662	#define AMLI_RAMPRI_CCM_RAM5_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	663
bogdanm	0:9b334a45a8ff	664	/* Bits 19..16 : Configuration field for RAM block 4. */
bogdanm	0:9b334a45a8ff	665	#define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /!< Position of RAM4 field. /
bogdanm	0:9b334a45a8ff	666	#define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /!< Bit mask of RAM4 field. /
bogdanm	0:9b334a45a8ff	667	#define AMLI_RAMPRI_CCM_RAM4_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	668	#define AMLI_RAMPRI_CCM_RAM4_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	669	#define AMLI_RAMPRI_CCM_RAM4_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	670	#define AMLI_RAMPRI_CCM_RAM4_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	671	#define AMLI_RAMPRI_CCM_RAM4_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	672	#define AMLI_RAMPRI_CCM_RAM4_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	673	#define AMLI_RAMPRI_CCM_RAM4_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	674	#define AMLI_RAMPRI_CCM_RAM4_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	675
bogdanm	0:9b334a45a8ff	676	/* Bits 15..12 : Configuration field for RAM block 3. */
bogdanm	0:9b334a45a8ff	677	#define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /!< Position of RAM3 field. /
bogdanm	0:9b334a45a8ff	678	#define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /!< Bit mask of RAM3 field. /
bogdanm	0:9b334a45a8ff	679	#define AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	680	#define AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	681	#define AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	682	#define AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	683	#define AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	684	#define AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	685	#define AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	686	#define AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	687
bogdanm	0:9b334a45a8ff	688	/* Bits 11..8 : Configuration field for RAM block 2. */
bogdanm	0:9b334a45a8ff	689	#define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /!< Position of RAM2 field. /
bogdanm	0:9b334a45a8ff	690	#define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /!< Bit mask of RAM2 field. /
bogdanm	0:9b334a45a8ff	691	#define AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	692	#define AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	693	#define AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	694	#define AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	695	#define AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	696	#define AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	697	#define AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	698	#define AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	699
bogdanm	0:9b334a45a8ff	700	/* Bits 7..4 : Configuration field for RAM block 1. */
bogdanm	0:9b334a45a8ff	701	#define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /!< Position of RAM1 field. /
bogdanm	0:9b334a45a8ff	702	#define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /!< Bit mask of RAM1 field. /
bogdanm	0:9b334a45a8ff	703	#define AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	704	#define AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	705	#define AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	706	#define AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	707	#define AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	708	#define AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	709	#define AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	710	#define AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	711
bogdanm	0:9b334a45a8ff	712	/* Bits 3..0 : Configuration field for RAM block 0. */
bogdanm	0:9b334a45a8ff	713	#define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /!< Position of RAM0 field. /
bogdanm	0:9b334a45a8ff	714	#define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /!< Bit mask of RAM0 field. /
bogdanm	0:9b334a45a8ff	715	#define AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	716	#define AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	717	#define AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	718	#define AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	719	#define AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	720	#define AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	721	#define AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	722	#define AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	723
bogdanm	0:9b334a45a8ff	724	/* Register: AMLI_RAMPRI_AAR */
bogdanm	0:9b334a45a8ff	725	/* Description: Configurable priority configuration register for AAR. */
bogdanm	0:9b334a45a8ff	726
bogdanm	0:9b334a45a8ff	727	/* Bits 31..28 : Configuration field for RAM block 7. */
bogdanm	0:9b334a45a8ff	728	#define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /!< Position of RAM7 field. /
bogdanm	0:9b334a45a8ff	729	#define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /!< Bit mask of RAM7 field. /
bogdanm	0:9b334a45a8ff	730	#define AMLI_RAMPRI_AAR_RAM7_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	731	#define AMLI_RAMPRI_AAR_RAM7_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	732	#define AMLI_RAMPRI_AAR_RAM7_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	733	#define AMLI_RAMPRI_AAR_RAM7_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	734	#define AMLI_RAMPRI_AAR_RAM7_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	735	#define AMLI_RAMPRI_AAR_RAM7_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	736	#define AMLI_RAMPRI_AAR_RAM7_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	737	#define AMLI_RAMPRI_AAR_RAM7_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	738
bogdanm	0:9b334a45a8ff	739	/* Bits 27..24 : Configuration field for RAM block 6. */
bogdanm	0:9b334a45a8ff	740	#define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /!< Position of RAM6 field. /
bogdanm	0:9b334a45a8ff	741	#define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /!< Bit mask of RAM6 field. /
bogdanm	0:9b334a45a8ff	742	#define AMLI_RAMPRI_AAR_RAM6_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	743	#define AMLI_RAMPRI_AAR_RAM6_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	744	#define AMLI_RAMPRI_AAR_RAM6_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	745	#define AMLI_RAMPRI_AAR_RAM6_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	746	#define AMLI_RAMPRI_AAR_RAM6_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	747	#define AMLI_RAMPRI_AAR_RAM6_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	748	#define AMLI_RAMPRI_AAR_RAM6_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	749	#define AMLI_RAMPRI_AAR_RAM6_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	750
bogdanm	0:9b334a45a8ff	751	/* Bits 23..20 : Configuration field for RAM block 5. */
bogdanm	0:9b334a45a8ff	752	#define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /!< Position of RAM5 field. /
bogdanm	0:9b334a45a8ff	753	#define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /!< Bit mask of RAM5 field. /
bogdanm	0:9b334a45a8ff	754	#define AMLI_RAMPRI_AAR_RAM5_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	755	#define AMLI_RAMPRI_AAR_RAM5_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	756	#define AMLI_RAMPRI_AAR_RAM5_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	757	#define AMLI_RAMPRI_AAR_RAM5_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	758	#define AMLI_RAMPRI_AAR_RAM5_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	759	#define AMLI_RAMPRI_AAR_RAM5_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	760	#define AMLI_RAMPRI_AAR_RAM5_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	761	#define AMLI_RAMPRI_AAR_RAM5_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	762
bogdanm	0:9b334a45a8ff	763	/* Bits 19..16 : Configuration field for RAM block 4. */
bogdanm	0:9b334a45a8ff	764	#define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /!< Position of RAM4 field. /
bogdanm	0:9b334a45a8ff	765	#define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /!< Bit mask of RAM4 field. /
bogdanm	0:9b334a45a8ff	766	#define AMLI_RAMPRI_AAR_RAM4_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	767	#define AMLI_RAMPRI_AAR_RAM4_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	768	#define AMLI_RAMPRI_AAR_RAM4_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	769	#define AMLI_RAMPRI_AAR_RAM4_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	770	#define AMLI_RAMPRI_AAR_RAM4_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	771	#define AMLI_RAMPRI_AAR_RAM4_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	772	#define AMLI_RAMPRI_AAR_RAM4_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	773	#define AMLI_RAMPRI_AAR_RAM4_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	774
bogdanm	0:9b334a45a8ff	775	/* Bits 15..12 : Configuration field for RAM block 3. */
bogdanm	0:9b334a45a8ff	776	#define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /!< Position of RAM3 field. /
bogdanm	0:9b334a45a8ff	777	#define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /!< Bit mask of RAM3 field. /
bogdanm	0:9b334a45a8ff	778	#define AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	779	#define AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	780	#define AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	781	#define AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	782	#define AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	783	#define AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	784	#define AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	785	#define AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	786
bogdanm	0:9b334a45a8ff	787	/* Bits 11..8 : Configuration field for RAM block 2. */
bogdanm	0:9b334a45a8ff	788	#define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /!< Position of RAM2 field. /
bogdanm	0:9b334a45a8ff	789	#define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /!< Bit mask of RAM2 field. /
bogdanm	0:9b334a45a8ff	790	#define AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	791	#define AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	792	#define AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	793	#define AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	794	#define AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	795	#define AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	796	#define AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	797	#define AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	798
bogdanm	0:9b334a45a8ff	799	/* Bits 7..4 : Configuration field for RAM block 1. */
bogdanm	0:9b334a45a8ff	800	#define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /!< Position of RAM1 field. /
bogdanm	0:9b334a45a8ff	801	#define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /!< Bit mask of RAM1 field. /
bogdanm	0:9b334a45a8ff	802	#define AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	803	#define AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	804	#define AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	805	#define AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	806	#define AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	807	#define AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	808	#define AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	809	#define AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	810
bogdanm	0:9b334a45a8ff	811	/* Bits 3..0 : Configuration field for RAM block 0. */
bogdanm	0:9b334a45a8ff	812	#define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /!< Position of RAM0 field. /
bogdanm	0:9b334a45a8ff	813	#define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /!< Bit mask of RAM0 field. /
bogdanm	0:9b334a45a8ff	814	#define AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL) /!< Priority 0. /
bogdanm	0:9b334a45a8ff	815	#define AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL) /!< Priority 2. /
bogdanm	0:9b334a45a8ff	816	#define AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL) /!< Priority 4. /
bogdanm	0:9b334a45a8ff	817	#define AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL) /!< Priority 6. /
bogdanm	0:9b334a45a8ff	818	#define AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL) /!< Priority 8. /
bogdanm	0:9b334a45a8ff	819	#define AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL) /!< Priority 10. /
bogdanm	0:9b334a45a8ff	820	#define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /!< Priority 12. /
bogdanm	0:9b334a45a8ff	821	#define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	0:9b334a45a8ff	822
bogdanm	0:9b334a45a8ff	823	/* Peripheral: CCM */
bogdanm	0:9b334a45a8ff	824	/* Description: AES CCM Mode Encryption. */
bogdanm	0:9b334a45a8ff	825
bogdanm	0:9b334a45a8ff	826	/* Register: CCM_SHORTS */
bogdanm	0:9b334a45a8ff	827	/* Description: Shortcuts for the CCM. */
bogdanm	0:9b334a45a8ff	828
bogdanm	0:9b334a45a8ff	829	/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */
bogdanm	0:9b334a45a8ff	830	#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /!< Position of ENDKSGEN_CRYPT field. /
bogdanm	0:9b334a45a8ff	831	#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /!< Bit mask of ENDKSGEN_CRYPT field. /
bogdanm	0:9b334a45a8ff	832	#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	0:9b334a45a8ff	833	#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	0:9b334a45a8ff	834
bogdanm	0:9b334a45a8ff	835	/* Register: CCM_INTENSET */
bogdanm	0:9b334a45a8ff	836	/* Description: Interrupt enable set register. */
bogdanm	0:9b334a45a8ff	837
bogdanm	0:9b334a45a8ff	838	/* Bit 2 : Enable interrupt on ERROR event. */
bogdanm	0:9b334a45a8ff	839	#define CCM_INTENSET_ERROR_Pos (2UL) /!< Position of ERROR field. /
bogdanm	0:9b334a45a8ff	840	#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
bogdanm	0:9b334a45a8ff	841	#define CCM_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	842	#define CCM_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	843	#define CCM_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	844
bogdanm	0:9b334a45a8ff	845	/* Bit 1 : Enable interrupt on ENDCRYPT event. */
bogdanm	0:9b334a45a8ff	846	#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /!< Position of ENDCRYPT field. /
bogdanm	0:9b334a45a8ff	847	#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /!< Bit mask of ENDCRYPT field. /
bogdanm	0:9b334a45a8ff	848	#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	849	#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	850	#define CCM_INTENSET_ENDCRYPT_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	851
bogdanm	0:9b334a45a8ff	852	/* Bit 0 : Enable interrupt on ENDKSGEN event. */
bogdanm	0:9b334a45a8ff	853	#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /!< Position of ENDKSGEN field. /
bogdanm	0:9b334a45a8ff	854	#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /!< Bit mask of ENDKSGEN field. /
bogdanm	0:9b334a45a8ff	855	#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	856	#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	857	#define CCM_INTENSET_ENDKSGEN_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	858
bogdanm	0:9b334a45a8ff	859	/* Register: CCM_INTENCLR */
bogdanm	0:9b334a45a8ff	860	/* Description: Interrupt enable clear register. */
bogdanm	0:9b334a45a8ff	861
bogdanm	0:9b334a45a8ff	862	/* Bit 2 : Disable interrupt on ERROR event. */
bogdanm	0:9b334a45a8ff	863	#define CCM_INTENCLR_ERROR_Pos (2UL) /!< Position of ERROR field. /
bogdanm	0:9b334a45a8ff	864	#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
bogdanm	0:9b334a45a8ff	865	#define CCM_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	866	#define CCM_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	867	#define CCM_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	868
bogdanm	0:9b334a45a8ff	869	/* Bit 1 : Disable interrupt on ENDCRYPT event. */
bogdanm	0:9b334a45a8ff	870	#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /!< Position of ENDCRYPT field. /
bogdanm	0:9b334a45a8ff	871	#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /!< Bit mask of ENDCRYPT field. /
bogdanm	0:9b334a45a8ff	872	#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	873	#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	874	#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	875
bogdanm	0:9b334a45a8ff	876	/* Bit 0 : Disable interrupt on ENDKSGEN event. */
bogdanm	0:9b334a45a8ff	877	#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /!< Position of ENDKSGEN field. /
bogdanm	0:9b334a45a8ff	878	#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /!< Bit mask of ENDKSGEN field. /
bogdanm	0:9b334a45a8ff	879	#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	880	#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	881	#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	882
bogdanm	0:9b334a45a8ff	883	/* Register: CCM_MICSTATUS */
bogdanm	0:9b334a45a8ff	884	/* Description: CCM RX MIC check result. */
bogdanm	0:9b334a45a8ff	885
bogdanm	0:9b334a45a8ff	886	/* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */
bogdanm	0:9b334a45a8ff	887	#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /!< Position of MICSTATUS field. /
bogdanm	0:9b334a45a8ff	888	#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /!< Bit mask of MICSTATUS field. /
bogdanm	0:9b334a45a8ff	889	#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /!< MIC check failed. /
bogdanm	0:9b334a45a8ff	890	#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /!< MIC check passed. /
bogdanm	0:9b334a45a8ff	891
bogdanm	0:9b334a45a8ff	892	/* Register: CCM_ENABLE */
bogdanm	0:9b334a45a8ff	893	/* Description: CCM enable. */
bogdanm	0:9b334a45a8ff	894
bogdanm	0:9b334a45a8ff	895	/* Bits 1..0 : CCM enable. */
bogdanm	0:9b334a45a8ff	896	#define CCM_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
bogdanm	0:9b334a45a8ff	897	#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
bogdanm	0:9b334a45a8ff	898	#define CCM_ENABLE_ENABLE_Disabled (0x00UL) /!< CCM is disabled. /
bogdanm	0:9b334a45a8ff	899	#define CCM_ENABLE_ENABLE_Enabled (0x02UL) /!< CCM is enabled. /
bogdanm	0:9b334a45a8ff	900
bogdanm	0:9b334a45a8ff	901	/* Register: CCM_MODE */
bogdanm	0:9b334a45a8ff	902	/* Description: Operation mode. */
bogdanm	0:9b334a45a8ff	903
bogdanm	0:9b334a45a8ff	904	/* Bit 0 : CCM mode operation. */
bogdanm	0:9b334a45a8ff	905	#define CCM_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
bogdanm	0:9b334a45a8ff	906	#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /!< Bit mask of MODE field. /
bogdanm	0:9b334a45a8ff	907	#define CCM_MODE_MODE_Encryption (0UL) /!< CCM mode TX /
bogdanm	0:9b334a45a8ff	908	#define CCM_MODE_MODE_Decryption (1UL) /!< CCM mode TX /
bogdanm	0:9b334a45a8ff	909
bogdanm	0:9b334a45a8ff	910	/* Register: CCM_POWER */
bogdanm	0:9b334a45a8ff	911	/* Description: Peripheral power control. */
bogdanm	0:9b334a45a8ff	912
bogdanm	0:9b334a45a8ff	913	/* Bit 0 : Peripheral power control. */
bogdanm	0:9b334a45a8ff	914	#define CCM_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	0:9b334a45a8ff	915	#define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	0:9b334a45a8ff	916	#define CCM_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	0:9b334a45a8ff	917	#define CCM_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	0:9b334a45a8ff	918
bogdanm	0:9b334a45a8ff	919
bogdanm	0:9b334a45a8ff	920	/* Peripheral: CLOCK */
bogdanm	0:9b334a45a8ff	921	/* Description: Clock control. */
bogdanm	0:9b334a45a8ff	922
bogdanm	0:9b334a45a8ff	923	/* Register: CLOCK_INTENSET */
bogdanm	0:9b334a45a8ff	924	/* Description: Interrupt enable set register. */
bogdanm	0:9b334a45a8ff	925
bogdanm	0:9b334a45a8ff	926	/* Bit 4 : Enable interrupt on CTTO event. */
bogdanm	0:9b334a45a8ff	927	#define CLOCK_INTENSET_CTTO_Pos (4UL) /!< Position of CTTO field. /
bogdanm	0:9b334a45a8ff	928	#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /!< Bit mask of CTTO field. /
bogdanm	0:9b334a45a8ff	929	#define CLOCK_INTENSET_CTTO_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	930	#define CLOCK_INTENSET_CTTO_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	931	#define CLOCK_INTENSET_CTTO_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	932
bogdanm	0:9b334a45a8ff	933	/* Bit 3 : Enable interrupt on DONE event. */
bogdanm	0:9b334a45a8ff	934	#define CLOCK_INTENSET_DONE_Pos (3UL) /!< Position of DONE field. /
bogdanm	0:9b334a45a8ff	935	#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /!< Bit mask of DONE field. /
bogdanm	0:9b334a45a8ff	936	#define CLOCK_INTENSET_DONE_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	937	#define CLOCK_INTENSET_DONE_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	938	#define CLOCK_INTENSET_DONE_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	939
bogdanm	0:9b334a45a8ff	940	/* Bit 1 : Enable interrupt on LFCLKSTARTED event. */
bogdanm	0:9b334a45a8ff	941	#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /!< Position of LFCLKSTARTED field. /
bogdanm	0:9b334a45a8ff	942	#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /!< Bit mask of LFCLKSTARTED field. /
bogdanm	0:9b334a45a8ff	943	#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	944	#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	945	#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	946
bogdanm	0:9b334a45a8ff	947	/* Bit 0 : Enable interrupt on HFCLKSTARTED event. */
bogdanm	0:9b334a45a8ff	948	#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /!< Position of HFCLKSTARTED field. /
bogdanm	0:9b334a45a8ff	949	#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /!< Bit mask of HFCLKSTARTED field. /
bogdanm	0:9b334a45a8ff	950	#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	951	#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	952	#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	953
bogdanm	0:9b334a45a8ff	954	/* Register: CLOCK_INTENCLR */
bogdanm	0:9b334a45a8ff	955	/* Description: Interrupt enable clear register. */
bogdanm	0:9b334a45a8ff	956
bogdanm	0:9b334a45a8ff	957	/* Bit 4 : Disable interrupt on CTTO event. */
bogdanm	0:9b334a45a8ff	958	#define CLOCK_INTENCLR_CTTO_Pos (4UL) /!< Position of CTTO field. /
bogdanm	0:9b334a45a8ff	959	#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /!< Bit mask of CTTO field. /
bogdanm	0:9b334a45a8ff	960	#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	961	#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	962	#define CLOCK_INTENCLR_CTTO_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	963
bogdanm	0:9b334a45a8ff	964	/* Bit 3 : Disable interrupt on DONE event. */
bogdanm	0:9b334a45a8ff	965	#define CLOCK_INTENCLR_DONE_Pos (3UL) /!< Position of DONE field. /
bogdanm	0:9b334a45a8ff	966	#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /!< Bit mask of DONE field. /
bogdanm	0:9b334a45a8ff	967	#define CLOCK_INTENCLR_DONE_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	968	#define CLOCK_INTENCLR_DONE_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	969	#define CLOCK_INTENCLR_DONE_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	970
bogdanm	0:9b334a45a8ff	971	/* Bit 1 : Disable interrupt on LFCLKSTARTED event. */
bogdanm	0:9b334a45a8ff	972	#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /!< Position of LFCLKSTARTED field. /
bogdanm	0:9b334a45a8ff	973	#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /!< Bit mask of LFCLKSTARTED field. /
bogdanm	0:9b334a45a8ff	974	#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	975	#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	976	#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	977
bogdanm	0:9b334a45a8ff	978	/* Bit 0 : Disable interrupt on HFCLKSTARTED event. */
bogdanm	0:9b334a45a8ff	979	#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /!< Position of HFCLKSTARTED field. /
bogdanm	0:9b334a45a8ff	980	#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /!< Bit mask of HFCLKSTARTED field. /
bogdanm	0:9b334a45a8ff	981	#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	982	#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	983	#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	984
bogdanm	0:9b334a45a8ff	985	/* Register: CLOCK_HFCLKRUN */
bogdanm	0:9b334a45a8ff	986	/* Description: Task HFCLKSTART trigger status. */
bogdanm	0:9b334a45a8ff	987
bogdanm	0:9b334a45a8ff	988	/* Bit 0 : Task HFCLKSTART trigger status. */
bogdanm	0:9b334a45a8ff	989	#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /!< Position of STATUS field. /
bogdanm	0:9b334a45a8ff	990	#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /!< Bit mask of STATUS field. /
bogdanm	0:9b334a45a8ff	991	#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /!< Task HFCLKSTART has not been triggered. /
bogdanm	0:9b334a45a8ff	992	#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /!< Task HFCLKSTART has been triggered. /
bogdanm	0:9b334a45a8ff	993
bogdanm	0:9b334a45a8ff	994	/* Register: CLOCK_HFCLKSTAT */
bogdanm	0:9b334a45a8ff	995	/* Description: High frequency clock status. */
bogdanm	0:9b334a45a8ff	996
bogdanm	0:9b334a45a8ff	997	/* Bit 16 : State for the HFCLK. */
bogdanm	0:9b334a45a8ff	998	#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /!< Position of STATE field. /
bogdanm	0:9b334a45a8ff	999	#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /!< Bit mask of STATE field. /
bogdanm	0:9b334a45a8ff	1000	#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /!< HFCLK clock not running. /
bogdanm	0:9b334a45a8ff	1001	#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /!< HFCLK clock running. /
bogdanm	0:9b334a45a8ff	1002
bogdanm	0:9b334a45a8ff	1003	/* Bit 0 : Active clock source for the HF clock. */
bogdanm	0:9b334a45a8ff	1004	#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /!< Position of SRC field. /
bogdanm	0:9b334a45a8ff	1005	#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /!< Bit mask of SRC field. /
bogdanm	0:9b334a45a8ff	1006	#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /!< Internal 16MHz RC oscillator running and generating the HFCLK clock. /
bogdanm	0:9b334a45a8ff	1007	#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. /
bogdanm	0:9b334a45a8ff	1008
bogdanm	0:9b334a45a8ff	1009	/* Register: CLOCK_LFCLKRUN */
bogdanm	0:9b334a45a8ff	1010	/* Description: Task LFCLKSTART triggered status. */
bogdanm	0:9b334a45a8ff	1011
bogdanm	0:9b334a45a8ff	1012	/* Bit 0 : Task LFCLKSTART triggered status. */
bogdanm	0:9b334a45a8ff	1013	#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /!< Position of STATUS field. /
bogdanm	0:9b334a45a8ff	1014	#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /!< Bit mask of STATUS field. /
bogdanm	0:9b334a45a8ff	1015	#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /!< Task LFCLKSTART has not been triggered. /
bogdanm	0:9b334a45a8ff	1016	#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /!< Task LFCLKSTART has been triggered. /
bogdanm	0:9b334a45a8ff	1017
bogdanm	0:9b334a45a8ff	1018	/* Register: CLOCK_LFCLKSTAT */
bogdanm	0:9b334a45a8ff	1019	/* Description: Low frequency clock status. */
bogdanm	0:9b334a45a8ff	1020
bogdanm	0:9b334a45a8ff	1021	/* Bit 16 : State for the LF clock. */
bogdanm	0:9b334a45a8ff	1022	#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /!< Position of STATE field. /
bogdanm	0:9b334a45a8ff	1023	#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /!< Bit mask of STATE field. /
bogdanm	0:9b334a45a8ff	1024	#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /!< LFCLK clock not running. /
bogdanm	0:9b334a45a8ff	1025	#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /!< LFCLK clock running. /
bogdanm	0:9b334a45a8ff	1026
bogdanm	0:9b334a45a8ff	1027	/* Bits 1..0 : Active clock source for the LF clock. */
bogdanm	0:9b334a45a8ff	1028	#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /!< Position of SRC field. /
bogdanm	0:9b334a45a8ff	1029	#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /!< Bit mask of SRC field. /
bogdanm	0:9b334a45a8ff	1030	#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. /
bogdanm	0:9b334a45a8ff	1031	#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /!< External 32KiHz crystal oscillator running and generating the LFCLK clock. /
bogdanm	0:9b334a45a8ff	1032	#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. /
bogdanm	0:9b334a45a8ff	1033
bogdanm	0:9b334a45a8ff	1034	/* Register: CLOCK_LFCLKSRCCOPY */
bogdanm	0:9b334a45a8ff	1035	/* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
bogdanm	0:9b334a45a8ff	1036
bogdanm	0:9b334a45a8ff	1037	/* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
bogdanm	0:9b334a45a8ff	1038	#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /!< Position of SRC field. /
bogdanm	0:9b334a45a8ff	1039	#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /!< Bit mask of SRC field. /
bogdanm	0:9b334a45a8ff	1040	#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator. /
bogdanm	0:9b334a45a8ff	1041	#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /!< External 32KiHz crystal. /
bogdanm	0:9b334a45a8ff	1042	#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from HFCLK system clock. /
bogdanm	0:9b334a45a8ff	1043
bogdanm	0:9b334a45a8ff	1044	/* Register: CLOCK_LFCLKSRC */
bogdanm	0:9b334a45a8ff	1045	/* Description: Clock source for the LFCLK clock. */
bogdanm	0:9b334a45a8ff	1046
bogdanm	0:9b334a45a8ff	1047	/* Bits 1..0 : Clock source. */
bogdanm	0:9b334a45a8ff	1048	#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /!< Position of SRC field. /
bogdanm	0:9b334a45a8ff	1049	#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /!< Bit mask of SRC field. /
bogdanm	0:9b334a45a8ff	1050	#define CLOCK_LFCLKSRC_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator. /
bogdanm	0:9b334a45a8ff	1051	#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /!< External 32KiHz crystal. /
bogdanm	0:9b334a45a8ff	1052	#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from HFCLK system clock. /
bogdanm	0:9b334a45a8ff	1053
bogdanm	0:9b334a45a8ff	1054	/* Register: CLOCK_CTIV */
bogdanm	0:9b334a45a8ff	1055	/* Description: Calibration timer interval. */
bogdanm	0:9b334a45a8ff	1056
bogdanm	0:9b334a45a8ff	1057	/* Bits 6..0 : Calibration timer interval in 0.25s resolution. */
bogdanm	0:9b334a45a8ff	1058	#define CLOCK_CTIV_CTIV_Pos (0UL) /!< Position of CTIV field. /
bogdanm	0:9b334a45a8ff	1059	#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /!< Bit mask of CTIV field. /
bogdanm	0:9b334a45a8ff	1060
bogdanm	0:9b334a45a8ff	1061	/* Register: CLOCK_XTALFREQ */
bogdanm	0:9b334a45a8ff	1062	/* Description: Crystal frequency. */
bogdanm	0:9b334a45a8ff	1063
bogdanm	0:9b334a45a8ff	1064	/* Bits 7..0 : External Xtal frequency selection. */
bogdanm	0:9b334a45a8ff	1065	#define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /!< Position of XTALFREQ field. /
bogdanm	0:9b334a45a8ff	1066	#define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /!< Bit mask of XTALFREQ field. /
bogdanm	0:9b334a45a8ff	1067	#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /!< 16MHz xtal is used as source for the HFCLK oscillator. /
bogdanm	0:9b334a45a8ff	1068	#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /!< 32MHz xtal is used as source for the HFCLK oscillator. /
bogdanm	0:9b334a45a8ff	1069
bogdanm	0:9b334a45a8ff	1070
bogdanm	0:9b334a45a8ff	1071	/* Peripheral: ECB */
bogdanm	0:9b334a45a8ff	1072	/* Description: AES ECB Mode Encryption. */
bogdanm	0:9b334a45a8ff	1073
bogdanm	0:9b334a45a8ff	1074	/* Register: ECB_INTENSET */
bogdanm	0:9b334a45a8ff	1075	/* Description: Interrupt enable set register. */
bogdanm	0:9b334a45a8ff	1076
bogdanm	0:9b334a45a8ff	1077	/* Bit 1 : Enable interrupt on ERRORECB event. */
bogdanm	0:9b334a45a8ff	1078	#define ECB_INTENSET_ERRORECB_Pos (1UL) /!< Position of ERRORECB field. /
bogdanm	0:9b334a45a8ff	1079	#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /!< Bit mask of ERRORECB field. /
bogdanm	0:9b334a45a8ff	1080	#define ECB_INTENSET_ERRORECB_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	1081	#define ECB_INTENSET_ERRORECB_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	1082	#define ECB_INTENSET_ERRORECB_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	1083
bogdanm	0:9b334a45a8ff	1084	/* Bit 0 : Enable interrupt on ENDECB event. */
bogdanm	0:9b334a45a8ff	1085	#define ECB_INTENSET_ENDECB_Pos (0UL) /!< Position of ENDECB field. /
bogdanm	0:9b334a45a8ff	1086	#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /!< Bit mask of ENDECB field. /
bogdanm	0:9b334a45a8ff	1087	#define ECB_INTENSET_ENDECB_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	1088	#define ECB_INTENSET_ENDECB_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	1089	#define ECB_INTENSET_ENDECB_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	1090
bogdanm	0:9b334a45a8ff	1091	/* Register: ECB_INTENCLR */
bogdanm	0:9b334a45a8ff	1092	/* Description: Interrupt enable clear register. */
bogdanm	0:9b334a45a8ff	1093
bogdanm	0:9b334a45a8ff	1094	/* Bit 1 : Disable interrupt on ERRORECB event. */
bogdanm	0:9b334a45a8ff	1095	#define ECB_INTENCLR_ERRORECB_Pos (1UL) /!< Position of ERRORECB field. /
bogdanm	0:9b334a45a8ff	1096	#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /!< Bit mask of ERRORECB field. /
bogdanm	0:9b334a45a8ff	1097	#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	1098	#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	1099	#define ECB_INTENCLR_ERRORECB_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	1100
bogdanm	0:9b334a45a8ff	1101	/* Bit 0 : Disable interrupt on ENDECB event. */
bogdanm	0:9b334a45a8ff	1102	#define ECB_INTENCLR_ENDECB_Pos (0UL) /!< Position of ENDECB field. /
bogdanm	0:9b334a45a8ff	1103	#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /!< Bit mask of ENDECB field. /
bogdanm	0:9b334a45a8ff	1104	#define ECB_INTENCLR_ENDECB_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	1105	#define ECB_INTENCLR_ENDECB_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	1106	#define ECB_INTENCLR_ENDECB_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	1107
bogdanm	0:9b334a45a8ff	1108	/* Register: ECB_POWER */
bogdanm	0:9b334a45a8ff	1109	/* Description: Peripheral power control. */
bogdanm	0:9b334a45a8ff	1110
bogdanm	0:9b334a45a8ff	1111	/* Bit 0 : Peripheral power control. */
bogdanm	0:9b334a45a8ff	1112	#define ECB_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	0:9b334a45a8ff	1113	#define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	0:9b334a45a8ff	1114	#define ECB_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	0:9b334a45a8ff	1115	#define ECB_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	0:9b334a45a8ff	1116
bogdanm	0:9b334a45a8ff	1117
bogdanm	0:9b334a45a8ff	1118	/* Peripheral: FICR */
bogdanm	0:9b334a45a8ff	1119	/* Description: Factory Information Configuration. */
bogdanm	0:9b334a45a8ff	1120
bogdanm	0:9b334a45a8ff	1121	/* Register: FICR_PPFC */
bogdanm	0:9b334a45a8ff	1122	/* Description: Pre-programmed factory code present. */
bogdanm	0:9b334a45a8ff	1123
bogdanm	0:9b334a45a8ff	1124	/* Bits 7..0 : Pre-programmed factory code present. */
bogdanm	0:9b334a45a8ff	1125	#define FICR_PPFC_PPFC_Pos (0UL) /!< Position of PPFC field. /
bogdanm	0:9b334a45a8ff	1126	#define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /!< Bit mask of PPFC field. /
bogdanm	0:9b334a45a8ff	1127	#define FICR_PPFC_PPFC_NotPresent (0xFFUL) /!< Not present. /
bogdanm	0:9b334a45a8ff	1128	#define FICR_PPFC_PPFC_Present (0x00UL) /!< Present. /
bogdanm	0:9b334a45a8ff	1129
bogdanm	0:9b334a45a8ff	1130	/* Register: FICR_CONFIGID */
bogdanm	0:9b334a45a8ff	1131	/* Description: Configuration identifier. */
bogdanm	0:9b334a45a8ff	1132
bogdanm	0:9b334a45a8ff	1133	/* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */
bogdanm	0:9b334a45a8ff	1134	#define FICR_CONFIGID_FWID_Pos (16UL) /!< Position of FWID field. /
bogdanm	0:9b334a45a8ff	1135	#define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /!< Bit mask of FWID field. /
bogdanm	0:9b334a45a8ff	1136
bogdanm	0:9b334a45a8ff	1137	/* Bits 15..0 : Hardware Identification Number. */
bogdanm	0:9b334a45a8ff	1138	#define FICR_CONFIGID_HWID_Pos (0UL) /!< Position of HWID field. /
bogdanm	0:9b334a45a8ff	1139	#define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /!< Bit mask of HWID field. /
bogdanm	0:9b334a45a8ff	1140
bogdanm	0:9b334a45a8ff	1141	/* Register: FICR_DEVICEADDRTYPE */
bogdanm	0:9b334a45a8ff	1142	/* Description: Device address type. */
bogdanm	0:9b334a45a8ff	1143
bogdanm	0:9b334a45a8ff	1144	/* Bit 0 : Device address type. */
bogdanm	0:9b334a45a8ff	1145	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /!< Position of DEVICEADDRTYPE field. /
bogdanm	0:9b334a45a8ff	1146	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /!< Bit mask of DEVICEADDRTYPE field. /
bogdanm	0:9b334a45a8ff	1147	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /!< Public address. /
bogdanm	0:9b334a45a8ff	1148	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /!< Random address. /
bogdanm	0:9b334a45a8ff	1149
bogdanm	0:9b334a45a8ff	1150	/* Register: FICR_OVERRIDEEN */
bogdanm	0:9b334a45a8ff	1151	/* Description: Radio calibration override enable. */
bogdanm	0:9b334a45a8ff	1152
bogdanm	0:9b334a45a8ff	1153	/* Bit 3 : Override default values for BLE_1Mbit mode. */
bogdanm	0:9b334a45a8ff	1154	#define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /!< Position of BLE_1MBIT field. /
bogdanm	0:9b334a45a8ff	1155	#define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /!< Bit mask of BLE_1MBIT field. /
bogdanm	0:9b334a45a8ff	1156	#define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /!< Override the default values for BLE_1Mbit mode. /
bogdanm	0:9b334a45a8ff	1157	#define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /!< Do not override the default values for BLE_1Mbit mode. /
bogdanm	0:9b334a45a8ff	1158
bogdanm	0:9b334a45a8ff	1159	/* Bit 0 : Override default values for NRF_1Mbit mode. */
bogdanm	0:9b334a45a8ff	1160	#define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /!< Position of NRF_1MBIT field. /
bogdanm	0:9b334a45a8ff	1161	#define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /!< Bit mask of NRF_1MBIT field. /
bogdanm	0:9b334a45a8ff	1162	#define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /!< Override the default values for NRF_1Mbit mode. /
bogdanm	0:9b334a45a8ff	1163	#define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /!< Do not override the default values for NRF_1Mbit mode. /
bogdanm	0:9b334a45a8ff	1164
bogdanm	0:9b334a45a8ff	1165	/* Register: FICR_INFO_PART */
bogdanm	0:9b334a45a8ff	1166	/* Description: Part code */
bogdanm	0:9b334a45a8ff	1167
bogdanm	0:9b334a45a8ff	1168	/* Bits 31..0 : Part code */
bogdanm	0:9b334a45a8ff	1169	#define FICR_INFO_PART_PART_Pos (0UL) /!< Position of PART field. /
bogdanm	0:9b334a45a8ff	1170	#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /!< Bit mask of PART field. /
bogdanm	0:9b334a45a8ff	1171	#define FICR_INFO_PART_PART_N51822 (0x51822UL) /!< nRF51822 /
bogdanm	0:9b334a45a8ff	1172	#define FICR_INFO_PART_PART_N51422 (0x51422UL) /!< nRF51422 /
bogdanm	0:9b334a45a8ff	1173	#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /!< Unspecified /
bogdanm	0:9b334a45a8ff	1174
bogdanm	0:9b334a45a8ff	1175	/* Register: FICR_INFO_VARIANT */
bogdanm	0:9b334a45a8ff	1176	/* Description: Part variant */
bogdanm	0:9b334a45a8ff	1177
bogdanm	0:9b334a45a8ff	1178	/* Bits 31..0 : Part variant */
bogdanm	0:9b334a45a8ff	1179	#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /!< Position of VARIANT field. /
bogdanm	0:9b334a45a8ff	1180	#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /!< Bit mask of VARIANT field. /
bogdanm	0:9b334a45a8ff	1181	#define FICR_INFO_VARIANT_VARIANT_nRF51C (0x1002UL) /!< nRF51-C (XLR3) /
bogdanm	0:9b334a45a8ff	1182	#define FICR_INFO_VARIANT_VARIANT_nRF51D (0x1003UL) /!< nRF51-D (L3) /
bogdanm	0:9b334a45a8ff	1183	#define FICR_INFO_VARIANT_VARIANT_nRF51E (0x1004UL) /!< nRF51-E (XLR3P) /
bogdanm	0:9b334a45a8ff	1184	#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /!< Unspecified /
bogdanm	0:9b334a45a8ff	1185
bogdanm	0:9b334a45a8ff	1186	/* Register: FICR_INFO_PACKAGE */
bogdanm	0:9b334a45a8ff	1187	/* Description: Package option */
bogdanm	0:9b334a45a8ff	1188
bogdanm	0:9b334a45a8ff	1189	/* Bits 31..0 : Package option */
bogdanm	0:9b334a45a8ff	1190	#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /!< Position of PACKAGE field. /
bogdanm	0:9b334a45a8ff	1191	#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /!< Bit mask of PACKAGE field. /
bogdanm	0:9b334a45a8ff	1192	#define FICR_INFO_PACKAGE_PACKAGE_QFN48 (0x0000UL) /!< 48-pin QFN with 31 GPIO /
bogdanm	0:9b334a45a8ff	1193	#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP56A (0x1000UL) /!< nRF51x22 CDxx - WLCSP 56 balls /
bogdanm	0:9b334a45a8ff	1194	#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62A (0x1001UL) /!< nRF51x22 CExx - WLCSP 62 balls /
bogdanm	0:9b334a45a8ff	1195	#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62B (0x1002UL) /!< nRF51x22 CFxx - WLCSP 62 balls /
bogdanm	0:9b334a45a8ff	1196	#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62C (0x1003UL) /!< nRF51x22 CTxx - WLCSP 62 balls /
bogdanm	0:9b334a45a8ff	1197	#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /!< Unspecified /
bogdanm	0:9b334a45a8ff	1198
bogdanm	0:9b334a45a8ff	1199	/* Register: FICR_INFO_RAM */
bogdanm	0:9b334a45a8ff	1200	/* Description: RAM variant */
bogdanm	0:9b334a45a8ff	1201
bogdanm	0:9b334a45a8ff	1202	/* Bits 31..0 : RAM variant */
bogdanm	0:9b334a45a8ff	1203	#define FICR_INFO_RAM_RAM_Pos (0UL) /!< Position of RAM field. /
bogdanm	0:9b334a45a8ff	1204	#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /!< Bit mask of RAM field. /
bogdanm	0:9b334a45a8ff	1205	#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /!< Unspecified /
bogdanm	0:9b334a45a8ff	1206	#define FICR_INFO_RAM_RAM_K16 (16UL) /!< 16 kByte RAM. /
bogdanm	0:9b334a45a8ff	1207	#define FICR_INFO_RAM_RAM_K32 (32UL) /!< 32 kByte RAM. /
bogdanm	0:9b334a45a8ff	1208
bogdanm	0:9b334a45a8ff	1209	/* Register: FICR_INFO_FLASH */
bogdanm	0:9b334a45a8ff	1210	/* Description: Flash variant */
bogdanm	0:9b334a45a8ff	1211
bogdanm	0:9b334a45a8ff	1212	/* Bits 31..0 : Flash variant */
bogdanm	0:9b334a45a8ff	1213	#define FICR_INFO_FLASH_FLASH_Pos (0UL) /!< Position of FLASH field. /
bogdanm	0:9b334a45a8ff	1214	#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /!< Bit mask of FLASH field. /
bogdanm	0:9b334a45a8ff	1215	#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /!< Unspecified /
bogdanm	0:9b334a45a8ff	1216	#define FICR_INFO_FLASH_FLASH_K128 (128UL) /!< 128 kByte FLASH. /
bogdanm	0:9b334a45a8ff	1217	#define FICR_INFO_FLASH_FLASH_K256 (256UL) /!< 256 kByte FLASH. /
bogdanm	0:9b334a45a8ff	1218
bogdanm	0:9b334a45a8ff	1219
bogdanm	0:9b334a45a8ff	1220	/* Peripheral: GPIO */
bogdanm	0:9b334a45a8ff	1221	/* Description: General purpose input and output. */
bogdanm	0:9b334a45a8ff	1222
bogdanm	0:9b334a45a8ff	1223	/* Register: GPIO_OUT */
bogdanm	0:9b334a45a8ff	1224	/* Description: Write GPIO port. */
bogdanm	0:9b334a45a8ff	1225
bogdanm	0:9b334a45a8ff	1226	/* Bit 31 : Pin 31. */
bogdanm	0:9b334a45a8ff	1227	#define GPIO_OUT_PIN31_Pos (31UL) /!< Position of PIN31 field. /
bogdanm	0:9b334a45a8ff	1228	#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /!< Bit mask of PIN31 field. /
bogdanm	0:9b334a45a8ff	1229	#define GPIO_OUT_PIN31_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1230	#define GPIO_OUT_PIN31_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1231
bogdanm	0:9b334a45a8ff	1232	/* Bit 30 : Pin 30. */
bogdanm	0:9b334a45a8ff	1233	#define GPIO_OUT_PIN30_Pos (30UL) /!< Position of PIN30 field. /
bogdanm	0:9b334a45a8ff	1234	#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /!< Bit mask of PIN30 field. /
bogdanm	0:9b334a45a8ff	1235	#define GPIO_OUT_PIN30_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1236	#define GPIO_OUT_PIN30_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1237
bogdanm	0:9b334a45a8ff	1238	/* Bit 29 : Pin 29. */
bogdanm	0:9b334a45a8ff	1239	#define GPIO_OUT_PIN29_Pos (29UL) /!< Position of PIN29 field. /
bogdanm	0:9b334a45a8ff	1240	#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /!< Bit mask of PIN29 field. /
bogdanm	0:9b334a45a8ff	1241	#define GPIO_OUT_PIN29_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1242	#define GPIO_OUT_PIN29_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1243
bogdanm	0:9b334a45a8ff	1244	/* Bit 28 : Pin 28. */
bogdanm	0:9b334a45a8ff	1245	#define GPIO_OUT_PIN28_Pos (28UL) /!< Position of PIN28 field. /
bogdanm	0:9b334a45a8ff	1246	#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /!< Bit mask of PIN28 field. /
bogdanm	0:9b334a45a8ff	1247	#define GPIO_OUT_PIN28_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1248	#define GPIO_OUT_PIN28_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1249
bogdanm	0:9b334a45a8ff	1250	/* Bit 27 : Pin 27. */
bogdanm	0:9b334a45a8ff	1251	#define GPIO_OUT_PIN27_Pos (27UL) /!< Position of PIN27 field. /
bogdanm	0:9b334a45a8ff	1252	#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /!< Bit mask of PIN27 field. /
bogdanm	0:9b334a45a8ff	1253	#define GPIO_OUT_PIN27_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1254	#define GPIO_OUT_PIN27_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1255
bogdanm	0:9b334a45a8ff	1256	/* Bit 26 : Pin 26. */
bogdanm	0:9b334a45a8ff	1257	#define GPIO_OUT_PIN26_Pos (26UL) /!< Position of PIN26 field. /
bogdanm	0:9b334a45a8ff	1258	#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /!< Bit mask of PIN26 field. /
bogdanm	0:9b334a45a8ff	1259	#define GPIO_OUT_PIN26_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1260	#define GPIO_OUT_PIN26_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1261
bogdanm	0:9b334a45a8ff	1262	/* Bit 25 : Pin 25. */
bogdanm	0:9b334a45a8ff	1263	#define GPIO_OUT_PIN25_Pos (25UL) /!< Position of PIN25 field. /
bogdanm	0:9b334a45a8ff	1264	#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /!< Bit mask of PIN25 field. /
bogdanm	0:9b334a45a8ff	1265	#define GPIO_OUT_PIN25_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1266	#define GPIO_OUT_PIN25_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1267
bogdanm	0:9b334a45a8ff	1268	/* Bit 24 : Pin 24. */
bogdanm	0:9b334a45a8ff	1269	#define GPIO_OUT_PIN24_Pos (24UL) /!< Position of PIN24 field. /
bogdanm	0:9b334a45a8ff	1270	#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /!< Bit mask of PIN24 field. /
bogdanm	0:9b334a45a8ff	1271	#define GPIO_OUT_PIN24_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1272	#define GPIO_OUT_PIN24_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1273
bogdanm	0:9b334a45a8ff	1274	/* Bit 23 : Pin 23. */
bogdanm	0:9b334a45a8ff	1275	#define GPIO_OUT_PIN23_Pos (23UL) /!< Position of PIN23 field. /
bogdanm	0:9b334a45a8ff	1276	#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /!< Bit mask of PIN23 field. /
bogdanm	0:9b334a45a8ff	1277	#define GPIO_OUT_PIN23_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1278	#define GPIO_OUT_PIN23_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1279
bogdanm	0:9b334a45a8ff	1280	/* Bit 22 : Pin 22. */
bogdanm	0:9b334a45a8ff	1281	#define GPIO_OUT_PIN22_Pos (22UL) /!< Position of PIN22 field. /
bogdanm	0:9b334a45a8ff	1282	#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /!< Bit mask of PIN22 field. /
bogdanm	0:9b334a45a8ff	1283	#define GPIO_OUT_PIN22_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1284	#define GPIO_OUT_PIN22_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1285
bogdanm	0:9b334a45a8ff	1286	/* Bit 21 : Pin 21. */
bogdanm	0:9b334a45a8ff	1287	#define GPIO_OUT_PIN21_Pos (21UL) /!< Position of PIN21 field. /
bogdanm	0:9b334a45a8ff	1288	#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /!< Bit mask of PIN21 field. /
bogdanm	0:9b334a45a8ff	1289	#define GPIO_OUT_PIN21_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1290	#define GPIO_OUT_PIN21_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1291
bogdanm	0:9b334a45a8ff	1292	/* Bit 20 : Pin 20. */
bogdanm	0:9b334a45a8ff	1293	#define GPIO_OUT_PIN20_Pos (20UL) /!< Position of PIN20 field. /
bogdanm	0:9b334a45a8ff	1294	#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /!< Bit mask of PIN20 field. /
bogdanm	0:9b334a45a8ff	1295	#define GPIO_OUT_PIN20_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1296	#define GPIO_OUT_PIN20_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1297
bogdanm	0:9b334a45a8ff	1298	/* Bit 19 : Pin 19. */
bogdanm	0:9b334a45a8ff	1299	#define GPIO_OUT_PIN19_Pos (19UL) /!< Position of PIN19 field. /
bogdanm	0:9b334a45a8ff	1300	#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /!< Bit mask of PIN19 field. /
bogdanm	0:9b334a45a8ff	1301	#define GPIO_OUT_PIN19_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1302	#define GPIO_OUT_PIN19_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1303
bogdanm	0:9b334a45a8ff	1304	/* Bit 18 : Pin 18. */
bogdanm	0:9b334a45a8ff	1305	#define GPIO_OUT_PIN18_Pos (18UL) /!< Position of PIN18 field. /
bogdanm	0:9b334a45a8ff	1306	#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /!< Bit mask of PIN18 field. /
bogdanm	0:9b334a45a8ff	1307	#define GPIO_OUT_PIN18_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1308	#define GPIO_OUT_PIN18_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1309
bogdanm	0:9b334a45a8ff	1310	/* Bit 17 : Pin 17. */
bogdanm	0:9b334a45a8ff	1311	#define GPIO_OUT_PIN17_Pos (17UL) /!< Position of PIN17 field. /
bogdanm	0:9b334a45a8ff	1312	#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /!< Bit mask of PIN17 field. /
bogdanm	0:9b334a45a8ff	1313	#define GPIO_OUT_PIN17_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1314	#define GPIO_OUT_PIN17_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1315
bogdanm	0:9b334a45a8ff	1316	/* Bit 16 : Pin 16. */
bogdanm	0:9b334a45a8ff	1317	#define GPIO_OUT_PIN16_Pos (16UL) /!< Position of PIN16 field. /
bogdanm	0:9b334a45a8ff	1318	#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /!< Bit mask of PIN16 field. /
bogdanm	0:9b334a45a8ff	1319	#define GPIO_OUT_PIN16_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1320	#define GPIO_OUT_PIN16_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1321
bogdanm	0:9b334a45a8ff	1322	/* Bit 15 : Pin 15. */
bogdanm	0:9b334a45a8ff	1323	#define GPIO_OUT_PIN15_Pos (15UL) /!< Position of PIN15 field. /
bogdanm	0:9b334a45a8ff	1324	#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /!< Bit mask of PIN15 field. /
bogdanm	0:9b334a45a8ff	1325	#define GPIO_OUT_PIN15_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1326	#define GPIO_OUT_PIN15_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1327
bogdanm	0:9b334a45a8ff	1328	/* Bit 14 : Pin 14. */
bogdanm	0:9b334a45a8ff	1329	#define GPIO_OUT_PIN14_Pos (14UL) /!< Position of PIN14 field. /
bogdanm	0:9b334a45a8ff	1330	#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /!< Bit mask of PIN14 field. /
bogdanm	0:9b334a45a8ff	1331	#define GPIO_OUT_PIN14_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1332	#define GPIO_OUT_PIN14_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1333
bogdanm	0:9b334a45a8ff	1334	/* Bit 13 : Pin 13. */
bogdanm	0:9b334a45a8ff	1335	#define GPIO_OUT_PIN13_Pos (13UL) /!< Position of PIN13 field. /
bogdanm	0:9b334a45a8ff	1336	#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /!< Bit mask of PIN13 field. /
bogdanm	0:9b334a45a8ff	1337	#define GPIO_OUT_PIN13_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1338	#define GPIO_OUT_PIN13_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1339
bogdanm	0:9b334a45a8ff	1340	/* Bit 12 : Pin 12. */
bogdanm	0:9b334a45a8ff	1341	#define GPIO_OUT_PIN12_Pos (12UL) /!< Position of PIN12 field. /
bogdanm	0:9b334a45a8ff	1342	#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /!< Bit mask of PIN12 field. /
bogdanm	0:9b334a45a8ff	1343	#define GPIO_OUT_PIN12_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1344	#define GPIO_OUT_PIN12_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1345
bogdanm	0:9b334a45a8ff	1346	/* Bit 11 : Pin 11. */
bogdanm	0:9b334a45a8ff	1347	#define GPIO_OUT_PIN11_Pos (11UL) /!< Position of PIN11 field. /
bogdanm	0:9b334a45a8ff	1348	#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /!< Bit mask of PIN11 field. /
bogdanm	0:9b334a45a8ff	1349	#define GPIO_OUT_PIN11_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1350	#define GPIO_OUT_PIN11_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1351
bogdanm	0:9b334a45a8ff	1352	/* Bit 10 : Pin 10. */
bogdanm	0:9b334a45a8ff	1353	#define GPIO_OUT_PIN10_Pos (10UL) /!< Position of PIN10 field. /
bogdanm	0:9b334a45a8ff	1354	#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /!< Bit mask of PIN10 field. /
bogdanm	0:9b334a45a8ff	1355	#define GPIO_OUT_PIN10_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1356	#define GPIO_OUT_PIN10_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1357
bogdanm	0:9b334a45a8ff	1358	/* Bit 9 : Pin 9. */
bogdanm	0:9b334a45a8ff	1359	#define GPIO_OUT_PIN9_Pos (9UL) /!< Position of PIN9 field. /
bogdanm	0:9b334a45a8ff	1360	#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /!< Bit mask of PIN9 field. /
bogdanm	0:9b334a45a8ff	1361	#define GPIO_OUT_PIN9_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1362	#define GPIO_OUT_PIN9_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1363
bogdanm	0:9b334a45a8ff	1364	/* Bit 8 : Pin 8. */
bogdanm	0:9b334a45a8ff	1365	#define GPIO_OUT_PIN8_Pos (8UL) /!< Position of PIN8 field. /
bogdanm	0:9b334a45a8ff	1366	#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /!< Bit mask of PIN8 field. /
bogdanm	0:9b334a45a8ff	1367	#define GPIO_OUT_PIN8_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1368	#define GPIO_OUT_PIN8_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1369
bogdanm	0:9b334a45a8ff	1370	/* Bit 7 : Pin 7. */
bogdanm	0:9b334a45a8ff	1371	#define GPIO_OUT_PIN7_Pos (7UL) /!< Position of PIN7 field. /
bogdanm	0:9b334a45a8ff	1372	#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /!< Bit mask of PIN7 field. /
bogdanm	0:9b334a45a8ff	1373	#define GPIO_OUT_PIN7_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1374	#define GPIO_OUT_PIN7_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1375
bogdanm	0:9b334a45a8ff	1376	/* Bit 6 : Pin 6. */
bogdanm	0:9b334a45a8ff	1377	#define GPIO_OUT_PIN6_Pos (6UL) /!< Position of PIN6 field. /
bogdanm	0:9b334a45a8ff	1378	#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /!< Bit mask of PIN6 field. /
bogdanm	0:9b334a45a8ff	1379	#define GPIO_OUT_PIN6_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1380	#define GPIO_OUT_PIN6_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1381
bogdanm	0:9b334a45a8ff	1382	/* Bit 5 : Pin 5. */
bogdanm	0:9b334a45a8ff	1383	#define GPIO_OUT_PIN5_Pos (5UL) /!< Position of PIN5 field. /
bogdanm	0:9b334a45a8ff	1384	#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /!< Bit mask of PIN5 field. /
bogdanm	0:9b334a45a8ff	1385	#define GPIO_OUT_PIN5_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1386	#define GPIO_OUT_PIN5_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1387
bogdanm	0:9b334a45a8ff	1388	/* Bit 4 : Pin 4. */
bogdanm	0:9b334a45a8ff	1389	#define GPIO_OUT_PIN4_Pos (4UL) /!< Position of PIN4 field. /
bogdanm	0:9b334a45a8ff	1390	#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /!< Bit mask of PIN4 field. /
bogdanm	0:9b334a45a8ff	1391	#define GPIO_OUT_PIN4_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1392	#define GPIO_OUT_PIN4_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1393
bogdanm	0:9b334a45a8ff	1394	/* Bit 3 : Pin 3. */
bogdanm	0:9b334a45a8ff	1395	#define GPIO_OUT_PIN3_Pos (3UL) /!< Position of PIN3 field. /
bogdanm	0:9b334a45a8ff	1396	#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /!< Bit mask of PIN3 field. /
bogdanm	0:9b334a45a8ff	1397	#define GPIO_OUT_PIN3_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1398	#define GPIO_OUT_PIN3_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1399
bogdanm	0:9b334a45a8ff	1400	/* Bit 2 : Pin 2. */
bogdanm	0:9b334a45a8ff	1401	#define GPIO_OUT_PIN2_Pos (2UL) /!< Position of PIN2 field. /
bogdanm	0:9b334a45a8ff	1402	#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /!< Bit mask of PIN2 field. /
bogdanm	0:9b334a45a8ff	1403	#define GPIO_OUT_PIN2_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1404	#define GPIO_OUT_PIN2_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1405
bogdanm	0:9b334a45a8ff	1406	/* Bit 1 : Pin 1. */
bogdanm	0:9b334a45a8ff	1407	#define GPIO_OUT_PIN1_Pos (1UL) /!< Position of PIN1 field. /
bogdanm	0:9b334a45a8ff	1408	#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /!< Bit mask of PIN1 field. /
bogdanm	0:9b334a45a8ff	1409	#define GPIO_OUT_PIN1_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1410	#define GPIO_OUT_PIN1_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1411
bogdanm	0:9b334a45a8ff	1412	/* Bit 0 : Pin 0. */
bogdanm	0:9b334a45a8ff	1413	#define GPIO_OUT_PIN0_Pos (0UL) /!< Position of PIN0 field. /
bogdanm	0:9b334a45a8ff	1414	#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /!< Bit mask of PIN0 field. /
bogdanm	0:9b334a45a8ff	1415	#define GPIO_OUT_PIN0_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1416	#define GPIO_OUT_PIN0_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1417
bogdanm	0:9b334a45a8ff	1418	/* Register: GPIO_OUTSET */
bogdanm	0:9b334a45a8ff	1419	/* Description: Set individual bits in GPIO port. */
bogdanm	0:9b334a45a8ff	1420
bogdanm	0:9b334a45a8ff	1421	/* Bit 31 : Pin 31. */
bogdanm	0:9b334a45a8ff	1422	#define GPIO_OUTSET_PIN31_Pos (31UL) /!< Position of PIN31 field. /
bogdanm	0:9b334a45a8ff	1423	#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /!< Bit mask of PIN31 field. /
bogdanm	0:9b334a45a8ff	1424	#define GPIO_OUTSET_PIN31_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1425	#define GPIO_OUTSET_PIN31_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1426	#define GPIO_OUTSET_PIN31_Set (1UL) /!< Set pin driver high. /
bogdanm	0:9b334a45a8ff	1427
bogdanm	0:9b334a45a8ff	1428	/* Bit 30 : Pin 30. */
bogdanm	0:9b334a45a8ff	1429	#define GPIO_OUTSET_PIN30_Pos (30UL) /!< Position of PIN30 field. /
bogdanm	0:9b334a45a8ff	1430	#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /!< Bit mask of PIN30 field. /
bogdanm	0:9b334a45a8ff	1431	#define GPIO_OUTSET_PIN30_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1432	#define GPIO_OUTSET_PIN30_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1433	#define GPIO_OUTSET_PIN30_Set (1UL) /!< Set pin driver high. /
bogdanm	0:9b334a45a8ff	1434
bogdanm	0:9b334a45a8ff	1435	/* Bit 29 : Pin 29. */
bogdanm	0:9b334a45a8ff	1436	#define GPIO_OUTSET_PIN29_Pos (29UL) /!< Position of PIN29 field. /
bogdanm	0:9b334a45a8ff	1437	#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /!< Bit mask of PIN29 field. /
bogdanm	0:9b334a45a8ff	1438	#define GPIO_OUTSET_PIN29_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1439	#define GPIO_OUTSET_PIN29_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1440	#define GPIO_OUTSET_PIN29_Set (1UL) /!< Set pin driver high. /
bogdanm	0:9b334a45a8ff	1441
bogdanm	0:9b334a45a8ff	1442	/* Bit 28 : Pin 28. */
bogdanm	0:9b334a45a8ff	1443	#define GPIO_OUTSET_PIN28_Pos (28UL) /!< Position of PIN28 field. /
bogdanm	0:9b334a45a8ff	1444	#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /!< Bit mask of PIN28 field. /
bogdanm	0:9b334a45a8ff	1445	#define GPIO_OUTSET_PIN28_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1446	#define GPIO_OUTSET_PIN28_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1447	#define GPIO_OUTSET_PIN28_Set (1UL) /!< Set pin driver high. /
bogdanm	0:9b334a45a8ff	1448
bogdanm	0:9b334a45a8ff	1449	/* Bit 27 : Pin 27. */
bogdanm	0:9b334a45a8ff	1450	#define GPIO_OUTSET_PIN27_Pos (27UL) /!< Position of PIN27 field. /
bogdanm	0:9b334a45a8ff	1451	#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /!< Bit mask of PIN27 field. /
bogdanm	0:9b334a45a8ff	1452	#define GPIO_OUTSET_PIN27_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1453	#define GPIO_OUTSET_PIN27_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1454	#define GPIO_OUTSET_PIN27_Set (1UL) /!< Set pin driver high. /
bogdanm	0:9b334a45a8ff	1455
bogdanm	0:9b334a45a8ff	1456	/* Bit 26 : Pin 26. */
bogdanm	0:9b334a45a8ff	1457	#define GPIO_OUTSET_PIN26_Pos (26UL) /!< Position of PIN26 field. /
bogdanm	0:9b334a45a8ff	1458	#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /!< Bit mask of PIN26 field. /
bogdanm	0:9b334a45a8ff	1459	#define GPIO_OUTSET_PIN26_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1460	#define GPIO_OUTSET_PIN26_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1461	#define GPIO_OUTSET_PIN26_Set (1UL) /!< Set pin driver high. /
bogdanm	0:9b334a45a8ff	1462
bogdanm	0:9b334a45a8ff	1463	/* Bit 25 : Pin 25. */
bogdanm	0:9b334a45a8ff	1464	#define GPIO_OUTSET_PIN25_Pos (25UL) /!< Position of PIN25 field. /
bogdanm	0:9b334a45a8ff	1465	#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /!< Bit mask of PIN25 field. /
bogdanm	0:9b334a45a8ff	1466	#define GPIO_OUTSET_PIN25_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1467	#define GPIO_OUTSET_PIN25_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1468	#define GPIO_OUTSET_PIN25_Set (1UL) /!< Set pin driver high. /
bogdanm	0:9b334a45a8ff	1469
bogdanm	0:9b334a45a8ff	1470	/* Bit 24 : Pin 24. */
bogdanm	0:9b334a45a8ff	1471	#define GPIO_OUTSET_PIN24_Pos (24UL) /!< Position of PIN24 field. /
bogdanm	0:9b334a45a8ff	1472	#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /!< Bit mask of PIN24 field. /
bogdanm	0:9b334a45a8ff	1473	#define GPIO_OUTSET_PIN24_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1474	#define GPIO_OUTSET_PIN24_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1475	#define GPIO_OUTSET_PIN24_Set (1UL) /!< Set pin driver high. /
bogdanm	0:9b334a45a8ff	1476
bogdanm	0:9b334a45a8ff	1477	/* Bit 23 : Pin 23. */
bogdanm	0:9b334a45a8ff	1478	#define GPIO_OUTSET_PIN23_Pos (23UL) /!< Position of PIN23 field. /
bogdanm	0:9b334a45a8ff	1479	#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /!< Bit mask of PIN23 field. /
bogdanm	0:9b334a45a8ff	1480	#define GPIO_OUTSET_PIN23_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1481	#define GPIO_OUTSET_PIN23_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1482	#define GPIO_OUTSET_PIN23_Set (1UL) /!< Set pin driver high. /
bogdanm	0:9b334a45a8ff	1483
bogdanm	0:9b334a45a8ff	1484	/* Bit 22 : Pin 22. */
bogdanm	0:9b334a45a8ff	1485	#define GPIO_OUTSET_PIN22_Pos (22UL) /!< Position of PIN22 field. /
bogdanm	0:9b334a45a8ff	1486	#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /!< Bit mask of PIN22 field. /
bogdanm	0:9b334a45a8ff	1487	#define GPIO_OUTSET_PIN22_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1488	#define GPIO_OUTSET_PIN22_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1489	#define GPIO_OUTSET_PIN22_Set (1UL) /!< Set pin driver high. /
bogdanm	0:9b334a45a8ff	1490
bogdanm	0:9b334a45a8ff	1491	/* Bit 21 : Pin 21. */
bogdanm	0:9b334a45a8ff	1492	#define GPIO_OUTSET_PIN21_Pos (21UL) /!< Position of PIN21 field. /
bogdanm	0:9b334a45a8ff	1493	#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /!< Bit mask of PIN21 field. /
bogdanm	0:9b334a45a8ff	1494	#define GPIO_OUTSET_PIN21_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1495	#define GPIO_OUTSET_PIN21_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1496	#define GPIO_OUTSET_PIN21_Set (1UL) /!< Set pin driver high. /
bogdanm	0:9b334a45a8ff	1497
bogdanm	0:9b334a45a8ff	1498	/* Bit 20 : Pin 20. */
bogdanm	0:9b334a45a8ff	1499	#define GPIO_OUTSET_PIN20_Pos (20UL) /!< Position of PIN20 field. /
bogdanm	0:9b334a45a8ff	1500	#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /!< Bit mask of PIN20 field. /
bogdanm	0:9b334a45a8ff	1501	#define GPIO_OUTSET_PIN20_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1502	#define GPIO_OUTSET_PIN20_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1503	#define GPIO_OUTSET_PIN20_Set (1UL) /!< Set pin driver high. /
bogdanm	0:9b334a45a8ff	1504
bogdanm	0:9b334a45a8ff	1505	/* Bit 19 : Pin 19. */
bogdanm	0:9b334a45a8ff	1506	#define GPIO_OUTSET_PIN19_Pos (19UL) /!< Position of PIN19 field. /
bogdanm	0:9b334a45a8ff	1507	#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /!< Bit mask of PIN19 field. /
bogdanm	0:9b334a45a8ff	1508	#define GPIO_OUTSET_PIN19_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1509	#define GPIO_OUTSET_PIN19_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1510	#define GPIO_OUTSET_PIN19_Set (1UL) /!< Set pin driver high. /
bogdanm	0:9b334a45a8ff	1511
bogdanm	0:9b334a45a8ff	1512	/* Bit 18 : Pin 18. */
bogdanm	0:9b334a45a8ff	1513	#define GPIO_OUTSET_PIN18_Pos (18UL) /!< Position of PIN18 field. /
bogdanm	0:9b334a45a8ff	1514	#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /!< Bit mask of PIN18 field. /
bogdanm	0:9b334a45a8ff	1515	#define GPIO_OUTSET_PIN18_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1516	#define GPIO_OUTSET_PIN18_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1517	#define GPIO_OUTSET_PIN18_Set (1UL) /!< Set pin driver high. /
bogdanm	0:9b334a45a8ff	1518
bogdanm	0:9b334a45a8ff	1519	/* Bit 17 : Pin 17. */
bogdanm	0:9b334a45a8ff	1520	#define GPIO_OUTSET_PIN17_Pos (17UL) /!< Position of PIN17 field. /
bogdanm	0:9b334a45a8ff	1521	#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /!< Bit mask of PIN17 field. /
bogdanm	0:9b334a45a8ff	1522	#define GPIO_OUTSET_PIN17_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1523	#define GPIO_OUTSET_PIN17_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1524	#define GPIO_OUTSET_PIN17_Set (1UL) /!< Set pin driver high. /
bogdanm	0:9b334a45a8ff	1525
bogdanm	0:9b334a45a8ff	1526	/* Bit 16 : Pin 16. */
bogdanm	0:9b334a45a8ff	1527	#define GPIO_OUTSET_PIN16_Pos (16UL) /!< Position of PIN16 field. /
bogdanm	0:9b334a45a8ff	1528	#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /!< Bit mask of PIN16 field. /
bogdanm	0:9b334a45a8ff	1529	#define GPIO_OUTSET_PIN16_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1530	#define GPIO_OUTSET_PIN16_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1531	#define GPIO_OUTSET_PIN16_Set (1UL) /!< Set pin driver high. /
bogdanm	0:9b334a45a8ff	1532
bogdanm	0:9b334a45a8ff	1533	/* Bit 15 : Pin 15. */
bogdanm	0:9b334a45a8ff	1534	#define GPIO_OUTSET_PIN15_Pos (15UL) /!< Position of PIN15 field. /
bogdanm	0:9b334a45a8ff	1535	#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /!< Bit mask of PIN15 field. /
bogdanm	0:9b334a45a8ff	1536	#define GPIO_OUTSET_PIN15_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1537	#define GPIO_OUTSET_PIN15_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1538	#define GPIO_OUTSET_PIN15_Set (1UL) /!< Set pin driver high. /
bogdanm	0:9b334a45a8ff	1539
bogdanm	0:9b334a45a8ff	1540	/* Bit 14 : Pin 14. */
bogdanm	0:9b334a45a8ff	1541	#define GPIO_OUTSET_PIN14_Pos (14UL) /!< Position of PIN14 field. /
bogdanm	0:9b334a45a8ff	1542	#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /!< Bit mask of PIN14 field. /
bogdanm	0:9b334a45a8ff	1543	#define GPIO_OUTSET_PIN14_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1544	#define GPIO_OUTSET_PIN14_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1545	#define GPIO_OUTSET_PIN14_Set (1UL) /!< Set pin driver high. /
bogdanm	0:9b334a45a8ff	1546
bogdanm	0:9b334a45a8ff	1547	/* Bit 13 : Pin 13. */
bogdanm	0:9b334a45a8ff	1548	#define GPIO_OUTSET_PIN13_Pos (13UL) /!< Position of PIN13 field. /
bogdanm	0:9b334a45a8ff	1549	#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /!< Bit mask of PIN13 field. /
bogdanm	0:9b334a45a8ff	1550	#define GPIO_OUTSET_PIN13_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1551	#define GPIO_OUTSET_PIN13_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1552	#define GPIO_OUTSET_PIN13_Set (1UL) /!< Set pin driver high. /
bogdanm	0:9b334a45a8ff	1553
bogdanm	0:9b334a45a8ff	1554	/* Bit 12 : Pin 12. */
bogdanm	0:9b334a45a8ff	1555	#define GPIO_OUTSET_PIN12_Pos (12UL) /!< Position of PIN12 field. /
bogdanm	0:9b334a45a8ff	1556	#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /!< Bit mask of PIN12 field. /
bogdanm	0:9b334a45a8ff	1557	#define GPIO_OUTSET_PIN12_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1558	#define GPIO_OUTSET_PIN12_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1559	#define GPIO_OUTSET_PIN12_Set (1UL) /!< Set pin driver high. /
bogdanm	0:9b334a45a8ff	1560
bogdanm	0:9b334a45a8ff	1561	/* Bit 11 : Pin 11. */
bogdanm	0:9b334a45a8ff	1562	#define GPIO_OUTSET_PIN11_Pos (11UL) /!< Position of PIN11 field. /
bogdanm	0:9b334a45a8ff	1563	#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /!< Bit mask of PIN11 field. /
bogdanm	0:9b334a45a8ff	1564	#define GPIO_OUTSET_PIN11_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1565	#define GPIO_OUTSET_PIN11_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1566	#define GPIO_OUTSET_PIN11_Set (1UL) /!< Set pin driver high. /
bogdanm	0:9b334a45a8ff	1567
bogdanm	0:9b334a45a8ff	1568	/* Bit 10 : Pin 10. */
bogdanm	0:9b334a45a8ff	1569	#define GPIO_OUTSET_PIN10_Pos (10UL) /!< Position of PIN10 field. /
bogdanm	0:9b334a45a8ff	1570	#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /!< Bit mask of PIN10 field. /
bogdanm	0:9b334a45a8ff	1571	#define GPIO_OUTSET_PIN10_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1572	#define GPIO_OUTSET_PIN10_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1573	#define GPIO_OUTSET_PIN10_Set (1UL) /!< Set pin driver high. /
bogdanm	0:9b334a45a8ff	1574
bogdanm	0:9b334a45a8ff	1575	/* Bit 9 : Pin 9. */
bogdanm	0:9b334a45a8ff	1576	#define GPIO_OUTSET_PIN9_Pos (9UL) /!< Position of PIN9 field. /
bogdanm	0:9b334a45a8ff	1577	#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /!< Bit mask of PIN9 field. /
bogdanm	0:9b334a45a8ff	1578	#define GPIO_OUTSET_PIN9_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1579	#define GPIO_OUTSET_PIN9_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1580	#define GPIO_OUTSET_PIN9_Set (1UL) /!< Set pin driver high. /
bogdanm	0:9b334a45a8ff	1581
bogdanm	0:9b334a45a8ff	1582	/* Bit 8 : Pin 8. */
bogdanm	0:9b334a45a8ff	1583	#define GPIO_OUTSET_PIN8_Pos (8UL) /!< Position of PIN8 field. /
bogdanm	0:9b334a45a8ff	1584	#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /!< Bit mask of PIN8 field. /
bogdanm	0:9b334a45a8ff	1585	#define GPIO_OUTSET_PIN8_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1586	#define GPIO_OUTSET_PIN8_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1587	#define GPIO_OUTSET_PIN8_Set (1UL) /!< Set pin driver high. /
bogdanm	0:9b334a45a8ff	1588
bogdanm	0:9b334a45a8ff	1589	/* Bit 7 : Pin 7. */
bogdanm	0:9b334a45a8ff	1590	#define GPIO_OUTSET_PIN7_Pos (7UL) /!< Position of PIN7 field. /
bogdanm	0:9b334a45a8ff	1591	#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /!< Bit mask of PIN7 field. /
bogdanm	0:9b334a45a8ff	1592	#define GPIO_OUTSET_PIN7_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1593	#define GPIO_OUTSET_PIN7_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1594	#define GPIO_OUTSET_PIN7_Set (1UL) /!< Set pin driver high. /
bogdanm	0:9b334a45a8ff	1595
bogdanm	0:9b334a45a8ff	1596	/* Bit 6 : Pin 6. */
bogdanm	0:9b334a45a8ff	1597	#define GPIO_OUTSET_PIN6_Pos (6UL) /!< Position of PIN6 field. /
bogdanm	0:9b334a45a8ff	1598	#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /!< Bit mask of PIN6 field. /
bogdanm	0:9b334a45a8ff	1599	#define GPIO_OUTSET_PIN6_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1600	#define GPIO_OUTSET_PIN6_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1601	#define GPIO_OUTSET_PIN6_Set (1UL) /!< Set pin driver high. /
bogdanm	0:9b334a45a8ff	1602
bogdanm	0:9b334a45a8ff	1603	/* Bit 5 : Pin 5. */
bogdanm	0:9b334a45a8ff	1604	#define GPIO_OUTSET_PIN5_Pos (5UL) /!< Position of PIN5 field. /
bogdanm	0:9b334a45a8ff	1605	#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /!< Bit mask of PIN5 field. /
bogdanm	0:9b334a45a8ff	1606	#define GPIO_OUTSET_PIN5_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1607	#define GPIO_OUTSET_PIN5_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1608	#define GPIO_OUTSET_PIN5_Set (1UL) /!< Set pin driver high. /
bogdanm	0:9b334a45a8ff	1609
bogdanm	0:9b334a45a8ff	1610	/* Bit 4 : Pin 4. */
bogdanm	0:9b334a45a8ff	1611	#define GPIO_OUTSET_PIN4_Pos (4UL) /!< Position of PIN4 field. /
bogdanm	0:9b334a45a8ff	1612	#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /!< Bit mask of PIN4 field. /
bogdanm	0:9b334a45a8ff	1613	#define GPIO_OUTSET_PIN4_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1614	#define GPIO_OUTSET_PIN4_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1615	#define GPIO_OUTSET_PIN4_Set (1UL) /!< Set pin driver high. /
bogdanm	0:9b334a45a8ff	1616
bogdanm	0:9b334a45a8ff	1617	/* Bit 3 : Pin 3. */
bogdanm	0:9b334a45a8ff	1618	#define GPIO_OUTSET_PIN3_Pos (3UL) /!< Position of PIN3 field. /
bogdanm	0:9b334a45a8ff	1619	#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /!< Bit mask of PIN3 field. /
bogdanm	0:9b334a45a8ff	1620	#define GPIO_OUTSET_PIN3_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1621	#define GPIO_OUTSET_PIN3_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1622	#define GPIO_OUTSET_PIN3_Set (1UL) /!< Set pin driver high. /
bogdanm	0:9b334a45a8ff	1623
bogdanm	0:9b334a45a8ff	1624	/* Bit 2 : Pin 2. */
bogdanm	0:9b334a45a8ff	1625	#define GPIO_OUTSET_PIN2_Pos (2UL) /!< Position of PIN2 field. /
bogdanm	0:9b334a45a8ff	1626	#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /!< Bit mask of PIN2 field. /
bogdanm	0:9b334a45a8ff	1627	#define GPIO_OUTSET_PIN2_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1628	#define GPIO_OUTSET_PIN2_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1629	#define GPIO_OUTSET_PIN2_Set (1UL) /!< Set pin driver high. /
bogdanm	0:9b334a45a8ff	1630
bogdanm	0:9b334a45a8ff	1631	/* Bit 1 : Pin 1. */
bogdanm	0:9b334a45a8ff	1632	#define GPIO_OUTSET_PIN1_Pos (1UL) /!< Position of PIN1 field. /
bogdanm	0:9b334a45a8ff	1633	#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /!< Bit mask of PIN1 field. /
bogdanm	0:9b334a45a8ff	1634	#define GPIO_OUTSET_PIN1_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1635	#define GPIO_OUTSET_PIN1_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1636	#define GPIO_OUTSET_PIN1_Set (1UL) /!< Set pin driver high. /
bogdanm	0:9b334a45a8ff	1637
bogdanm	0:9b334a45a8ff	1638	/* Bit 0 : Pin 0. */
bogdanm	0:9b334a45a8ff	1639	#define GPIO_OUTSET_PIN0_Pos (0UL) /!< Position of PIN0 field. /
bogdanm	0:9b334a45a8ff	1640	#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /!< Bit mask of PIN0 field. /
bogdanm	0:9b334a45a8ff	1641	#define GPIO_OUTSET_PIN0_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1642	#define GPIO_OUTSET_PIN0_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1643	#define GPIO_OUTSET_PIN0_Set (1UL) /!< Set pin driver high. /
bogdanm	0:9b334a45a8ff	1644
bogdanm	0:9b334a45a8ff	1645	/* Register: GPIO_OUTCLR */
bogdanm	0:9b334a45a8ff	1646	/* Description: Clear individual bits in GPIO port. */
bogdanm	0:9b334a45a8ff	1647
bogdanm	0:9b334a45a8ff	1648	/* Bit 31 : Pin 31. */
bogdanm	0:9b334a45a8ff	1649	#define GPIO_OUTCLR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
bogdanm	0:9b334a45a8ff	1650	#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /!< Bit mask of PIN31 field. /
bogdanm	0:9b334a45a8ff	1651	#define GPIO_OUTCLR_PIN31_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1652	#define GPIO_OUTCLR_PIN31_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1653	#define GPIO_OUTCLR_PIN31_Clear (1UL) /!< Set pin driver low. /
bogdanm	0:9b334a45a8ff	1654
bogdanm	0:9b334a45a8ff	1655	/* Bit 30 : Pin 30. */
bogdanm	0:9b334a45a8ff	1656	#define GPIO_OUTCLR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
bogdanm	0:9b334a45a8ff	1657	#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /!< Bit mask of PIN30 field. /
bogdanm	0:9b334a45a8ff	1658	#define GPIO_OUTCLR_PIN30_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1659	#define GPIO_OUTCLR_PIN30_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1660	#define GPIO_OUTCLR_PIN30_Clear (1UL) /!< Set pin driver low. /
bogdanm	0:9b334a45a8ff	1661
bogdanm	0:9b334a45a8ff	1662	/* Bit 29 : Pin 29. */
bogdanm	0:9b334a45a8ff	1663	#define GPIO_OUTCLR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
bogdanm	0:9b334a45a8ff	1664	#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /!< Bit mask of PIN29 field. /
bogdanm	0:9b334a45a8ff	1665	#define GPIO_OUTCLR_PIN29_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1666	#define GPIO_OUTCLR_PIN29_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1667	#define GPIO_OUTCLR_PIN29_Clear (1UL) /!< Set pin driver low. /
bogdanm	0:9b334a45a8ff	1668
bogdanm	0:9b334a45a8ff	1669	/* Bit 28 : Pin 28. */
bogdanm	0:9b334a45a8ff	1670	#define GPIO_OUTCLR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
bogdanm	0:9b334a45a8ff	1671	#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /!< Bit mask of PIN28 field. /
bogdanm	0:9b334a45a8ff	1672	#define GPIO_OUTCLR_PIN28_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1673	#define GPIO_OUTCLR_PIN28_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1674	#define GPIO_OUTCLR_PIN28_Clear (1UL) /!< Set pin driver low. /
bogdanm	0:9b334a45a8ff	1675
bogdanm	0:9b334a45a8ff	1676	/* Bit 27 : Pin 27. */
bogdanm	0:9b334a45a8ff	1677	#define GPIO_OUTCLR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
bogdanm	0:9b334a45a8ff	1678	#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /!< Bit mask of PIN27 field. /
bogdanm	0:9b334a45a8ff	1679	#define GPIO_OUTCLR_PIN27_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1680	#define GPIO_OUTCLR_PIN27_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1681	#define GPIO_OUTCLR_PIN27_Clear (1UL) /!< Set pin driver low. /
bogdanm	0:9b334a45a8ff	1682
bogdanm	0:9b334a45a8ff	1683	/* Bit 26 : Pin 26. */
bogdanm	0:9b334a45a8ff	1684	#define GPIO_OUTCLR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
bogdanm	0:9b334a45a8ff	1685	#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /!< Bit mask of PIN26 field. /
bogdanm	0:9b334a45a8ff	1686	#define GPIO_OUTCLR_PIN26_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1687	#define GPIO_OUTCLR_PIN26_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1688	#define GPIO_OUTCLR_PIN26_Clear (1UL) /!< Set pin driver low. /
bogdanm	0:9b334a45a8ff	1689
bogdanm	0:9b334a45a8ff	1690	/* Bit 25 : Pin 25. */
bogdanm	0:9b334a45a8ff	1691	#define GPIO_OUTCLR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
bogdanm	0:9b334a45a8ff	1692	#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /!< Bit mask of PIN25 field. /
bogdanm	0:9b334a45a8ff	1693	#define GPIO_OUTCLR_PIN25_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1694	#define GPIO_OUTCLR_PIN25_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1695	#define GPIO_OUTCLR_PIN25_Clear (1UL) /!< Set pin driver low. /
bogdanm	0:9b334a45a8ff	1696
bogdanm	0:9b334a45a8ff	1697	/* Bit 24 : Pin 24. */
bogdanm	0:9b334a45a8ff	1698	#define GPIO_OUTCLR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
bogdanm	0:9b334a45a8ff	1699	#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /!< Bit mask of PIN24 field. /
bogdanm	0:9b334a45a8ff	1700	#define GPIO_OUTCLR_PIN24_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1701	#define GPIO_OUTCLR_PIN24_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1702	#define GPIO_OUTCLR_PIN24_Clear (1UL) /!< Set pin driver low. /
bogdanm	0:9b334a45a8ff	1703
bogdanm	0:9b334a45a8ff	1704	/* Bit 23 : Pin 23. */
bogdanm	0:9b334a45a8ff	1705	#define GPIO_OUTCLR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
bogdanm	0:9b334a45a8ff	1706	#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /!< Bit mask of PIN23 field. /
bogdanm	0:9b334a45a8ff	1707	#define GPIO_OUTCLR_PIN23_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1708	#define GPIO_OUTCLR_PIN23_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1709	#define GPIO_OUTCLR_PIN23_Clear (1UL) /!< Set pin driver low. /
bogdanm	0:9b334a45a8ff	1710
bogdanm	0:9b334a45a8ff	1711	/* Bit 22 : Pin 22. */
bogdanm	0:9b334a45a8ff	1712	#define GPIO_OUTCLR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
bogdanm	0:9b334a45a8ff	1713	#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /!< Bit mask of PIN22 field. /
bogdanm	0:9b334a45a8ff	1714	#define GPIO_OUTCLR_PIN22_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1715	#define GPIO_OUTCLR_PIN22_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1716	#define GPIO_OUTCLR_PIN22_Clear (1UL) /!< Set pin driver low. /
bogdanm	0:9b334a45a8ff	1717
bogdanm	0:9b334a45a8ff	1718	/* Bit 21 : Pin 21. */
bogdanm	0:9b334a45a8ff	1719	#define GPIO_OUTCLR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
bogdanm	0:9b334a45a8ff	1720	#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /!< Bit mask of PIN21 field. /
bogdanm	0:9b334a45a8ff	1721	#define GPIO_OUTCLR_PIN21_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1722	#define GPIO_OUTCLR_PIN21_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1723	#define GPIO_OUTCLR_PIN21_Clear (1UL) /!< Set pin driver low. /
bogdanm	0:9b334a45a8ff	1724
bogdanm	0:9b334a45a8ff	1725	/* Bit 20 : Pin 20. */
bogdanm	0:9b334a45a8ff	1726	#define GPIO_OUTCLR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
bogdanm	0:9b334a45a8ff	1727	#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /!< Bit mask of PIN20 field. /
bogdanm	0:9b334a45a8ff	1728	#define GPIO_OUTCLR_PIN20_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1729	#define GPIO_OUTCLR_PIN20_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1730	#define GPIO_OUTCLR_PIN20_Clear (1UL) /!< Set pin driver low. /
bogdanm	0:9b334a45a8ff	1731
bogdanm	0:9b334a45a8ff	1732	/* Bit 19 : Pin 19. */
bogdanm	0:9b334a45a8ff	1733	#define GPIO_OUTCLR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
bogdanm	0:9b334a45a8ff	1734	#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /!< Bit mask of PIN19 field. /
bogdanm	0:9b334a45a8ff	1735	#define GPIO_OUTCLR_PIN19_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1736	#define GPIO_OUTCLR_PIN19_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1737	#define GPIO_OUTCLR_PIN19_Clear (1UL) /!< Set pin driver low. /
bogdanm	0:9b334a45a8ff	1738
bogdanm	0:9b334a45a8ff	1739	/* Bit 18 : Pin 18. */
bogdanm	0:9b334a45a8ff	1740	#define GPIO_OUTCLR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
bogdanm	0:9b334a45a8ff	1741	#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /!< Bit mask of PIN18 field. /
bogdanm	0:9b334a45a8ff	1742	#define GPIO_OUTCLR_PIN18_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1743	#define GPIO_OUTCLR_PIN18_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1744	#define GPIO_OUTCLR_PIN18_Clear (1UL) /!< Set pin driver low. /
bogdanm	0:9b334a45a8ff	1745
bogdanm	0:9b334a45a8ff	1746	/* Bit 17 : Pin 17. */
bogdanm	0:9b334a45a8ff	1747	#define GPIO_OUTCLR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
bogdanm	0:9b334a45a8ff	1748	#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /!< Bit mask of PIN17 field. /
bogdanm	0:9b334a45a8ff	1749	#define GPIO_OUTCLR_PIN17_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1750	#define GPIO_OUTCLR_PIN17_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1751	#define GPIO_OUTCLR_PIN17_Clear (1UL) /!< Set pin driver low. /
bogdanm	0:9b334a45a8ff	1752
bogdanm	0:9b334a45a8ff	1753	/* Bit 16 : Pin 16. */
bogdanm	0:9b334a45a8ff	1754	#define GPIO_OUTCLR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
bogdanm	0:9b334a45a8ff	1755	#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /!< Bit mask of PIN16 field. /
bogdanm	0:9b334a45a8ff	1756	#define GPIO_OUTCLR_PIN16_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1757	#define GPIO_OUTCLR_PIN16_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1758	#define GPIO_OUTCLR_PIN16_Clear (1UL) /!< Set pin driver low. /
bogdanm	0:9b334a45a8ff	1759
bogdanm	0:9b334a45a8ff	1760	/* Bit 15 : Pin 15. */
bogdanm	0:9b334a45a8ff	1761	#define GPIO_OUTCLR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
bogdanm	0:9b334a45a8ff	1762	#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /!< Bit mask of PIN15 field. /
bogdanm	0:9b334a45a8ff	1763	#define GPIO_OUTCLR_PIN15_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1764	#define GPIO_OUTCLR_PIN15_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1765	#define GPIO_OUTCLR_PIN15_Clear (1UL) /!< Set pin driver low. /
bogdanm	0:9b334a45a8ff	1766
bogdanm	0:9b334a45a8ff	1767	/* Bit 14 : Pin 14. */
bogdanm	0:9b334a45a8ff	1768	#define GPIO_OUTCLR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
bogdanm	0:9b334a45a8ff	1769	#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /!< Bit mask of PIN14 field. /
bogdanm	0:9b334a45a8ff	1770	#define GPIO_OUTCLR_PIN14_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1771	#define GPIO_OUTCLR_PIN14_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1772	#define GPIO_OUTCLR_PIN14_Clear (1UL) /!< Set pin driver low. /
bogdanm	0:9b334a45a8ff	1773
bogdanm	0:9b334a45a8ff	1774	/* Bit 13 : Pin 13. */
bogdanm	0:9b334a45a8ff	1775	#define GPIO_OUTCLR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
bogdanm	0:9b334a45a8ff	1776	#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /!< Bit mask of PIN13 field. /
bogdanm	0:9b334a45a8ff	1777	#define GPIO_OUTCLR_PIN13_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1778	#define GPIO_OUTCLR_PIN13_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1779	#define GPIO_OUTCLR_PIN13_Clear (1UL) /!< Set pin driver low. /
bogdanm	0:9b334a45a8ff	1780
bogdanm	0:9b334a45a8ff	1781	/* Bit 12 : Pin 12. */
bogdanm	0:9b334a45a8ff	1782	#define GPIO_OUTCLR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
bogdanm	0:9b334a45a8ff	1783	#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /!< Bit mask of PIN12 field. /
bogdanm	0:9b334a45a8ff	1784	#define GPIO_OUTCLR_PIN12_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1785	#define GPIO_OUTCLR_PIN12_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1786	#define GPIO_OUTCLR_PIN12_Clear (1UL) /!< Set pin driver low. /
bogdanm	0:9b334a45a8ff	1787
bogdanm	0:9b334a45a8ff	1788	/* Bit 11 : Pin 11. */
bogdanm	0:9b334a45a8ff	1789	#define GPIO_OUTCLR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
bogdanm	0:9b334a45a8ff	1790	#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /!< Bit mask of PIN11 field. /
bogdanm	0:9b334a45a8ff	1791	#define GPIO_OUTCLR_PIN11_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1792	#define GPIO_OUTCLR_PIN11_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1793	#define GPIO_OUTCLR_PIN11_Clear (1UL) /!< Set pin driver low. /
bogdanm	0:9b334a45a8ff	1794
bogdanm	0:9b334a45a8ff	1795	/* Bit 10 : Pin 10. */
bogdanm	0:9b334a45a8ff	1796	#define GPIO_OUTCLR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
bogdanm	0:9b334a45a8ff	1797	#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /!< Bit mask of PIN10 field. /
bogdanm	0:9b334a45a8ff	1798	#define GPIO_OUTCLR_PIN10_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1799	#define GPIO_OUTCLR_PIN10_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1800	#define GPIO_OUTCLR_PIN10_Clear (1UL) /!< Set pin driver low. /
bogdanm	0:9b334a45a8ff	1801
bogdanm	0:9b334a45a8ff	1802	/* Bit 9 : Pin 9. */
bogdanm	0:9b334a45a8ff	1803	#define GPIO_OUTCLR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
bogdanm	0:9b334a45a8ff	1804	#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /!< Bit mask of PIN9 field. /
bogdanm	0:9b334a45a8ff	1805	#define GPIO_OUTCLR_PIN9_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1806	#define GPIO_OUTCLR_PIN9_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1807	#define GPIO_OUTCLR_PIN9_Clear (1UL) /!< Set pin driver low. /
bogdanm	0:9b334a45a8ff	1808
bogdanm	0:9b334a45a8ff	1809	/* Bit 8 : Pin 8. */
bogdanm	0:9b334a45a8ff	1810	#define GPIO_OUTCLR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
bogdanm	0:9b334a45a8ff	1811	#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /!< Bit mask of PIN8 field. /
bogdanm	0:9b334a45a8ff	1812	#define GPIO_OUTCLR_PIN8_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1813	#define GPIO_OUTCLR_PIN8_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1814	#define GPIO_OUTCLR_PIN8_Clear (1UL) /!< Set pin driver low. /
bogdanm	0:9b334a45a8ff	1815
bogdanm	0:9b334a45a8ff	1816	/* Bit 7 : Pin 7. */
bogdanm	0:9b334a45a8ff	1817	#define GPIO_OUTCLR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
bogdanm	0:9b334a45a8ff	1818	#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /!< Bit mask of PIN7 field. /
bogdanm	0:9b334a45a8ff	1819	#define GPIO_OUTCLR_PIN7_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1820	#define GPIO_OUTCLR_PIN7_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1821	#define GPIO_OUTCLR_PIN7_Clear (1UL) /!< Set pin driver low. /
bogdanm	0:9b334a45a8ff	1822
bogdanm	0:9b334a45a8ff	1823	/* Bit 6 : Pin 6. */
bogdanm	0:9b334a45a8ff	1824	#define GPIO_OUTCLR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
bogdanm	0:9b334a45a8ff	1825	#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /!< Bit mask of PIN6 field. /
bogdanm	0:9b334a45a8ff	1826	#define GPIO_OUTCLR_PIN6_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1827	#define GPIO_OUTCLR_PIN6_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1828	#define GPIO_OUTCLR_PIN6_Clear (1UL) /!< Set pin driver low. /
bogdanm	0:9b334a45a8ff	1829
bogdanm	0:9b334a45a8ff	1830	/* Bit 5 : Pin 5. */
bogdanm	0:9b334a45a8ff	1831	#define GPIO_OUTCLR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
bogdanm	0:9b334a45a8ff	1832	#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /!< Bit mask of PIN5 field. /
bogdanm	0:9b334a45a8ff	1833	#define GPIO_OUTCLR_PIN5_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1834	#define GPIO_OUTCLR_PIN5_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1835	#define GPIO_OUTCLR_PIN5_Clear (1UL) /!< Set pin driver low. /
bogdanm	0:9b334a45a8ff	1836
bogdanm	0:9b334a45a8ff	1837	/* Bit 4 : Pin 4. */
bogdanm	0:9b334a45a8ff	1838	#define GPIO_OUTCLR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
bogdanm	0:9b334a45a8ff	1839	#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /!< Bit mask of PIN4 field. /
bogdanm	0:9b334a45a8ff	1840	#define GPIO_OUTCLR_PIN4_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1841	#define GPIO_OUTCLR_PIN4_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1842	#define GPIO_OUTCLR_PIN4_Clear (1UL) /!< Set pin driver low. /
bogdanm	0:9b334a45a8ff	1843
bogdanm	0:9b334a45a8ff	1844	/* Bit 3 : Pin 3. */
bogdanm	0:9b334a45a8ff	1845	#define GPIO_OUTCLR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
bogdanm	0:9b334a45a8ff	1846	#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /!< Bit mask of PIN3 field. /
bogdanm	0:9b334a45a8ff	1847	#define GPIO_OUTCLR_PIN3_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1848	#define GPIO_OUTCLR_PIN3_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1849	#define GPIO_OUTCLR_PIN3_Clear (1UL) /!< Set pin driver low. /
bogdanm	0:9b334a45a8ff	1850
bogdanm	0:9b334a45a8ff	1851	/* Bit 2 : Pin 2. */
bogdanm	0:9b334a45a8ff	1852	#define GPIO_OUTCLR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
bogdanm	0:9b334a45a8ff	1853	#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /!< Bit mask of PIN2 field. /
bogdanm	0:9b334a45a8ff	1854	#define GPIO_OUTCLR_PIN2_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1855	#define GPIO_OUTCLR_PIN2_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1856	#define GPIO_OUTCLR_PIN2_Clear (1UL) /!< Set pin driver low. /
bogdanm	0:9b334a45a8ff	1857
bogdanm	0:9b334a45a8ff	1858	/* Bit 1 : Pin 1. */
bogdanm	0:9b334a45a8ff	1859	#define GPIO_OUTCLR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
bogdanm	0:9b334a45a8ff	1860	#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /!< Bit mask of PIN1 field. /
bogdanm	0:9b334a45a8ff	1861	#define GPIO_OUTCLR_PIN1_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1862	#define GPIO_OUTCLR_PIN1_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1863	#define GPIO_OUTCLR_PIN1_Clear (1UL) /!< Set pin driver low. /
bogdanm	0:9b334a45a8ff	1864
bogdanm	0:9b334a45a8ff	1865	/* Bit 0 : Pin 0. */
bogdanm	0:9b334a45a8ff	1866	#define GPIO_OUTCLR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
bogdanm	0:9b334a45a8ff	1867	#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /!< Bit mask of PIN0 field. /
bogdanm	0:9b334a45a8ff	1868	#define GPIO_OUTCLR_PIN0_Low (0UL) /!< Pin driver is low. /
bogdanm	0:9b334a45a8ff	1869	#define GPIO_OUTCLR_PIN0_High (1UL) /!< Pin driver is high. /
bogdanm	0:9b334a45a8ff	1870	#define GPIO_OUTCLR_PIN0_Clear (1UL) /!< Set pin driver low. /
bogdanm	0:9b334a45a8ff	1871
bogdanm	0:9b334a45a8ff	1872	/* Register: GPIO_IN */
bogdanm	0:9b334a45a8ff	1873	/* Description: Read GPIO port. */
bogdanm	0:9b334a45a8ff	1874
bogdanm	0:9b334a45a8ff	1875	/* Bit 31 : Pin 31. */
bogdanm	0:9b334a45a8ff	1876	#define GPIO_IN_PIN31_Pos (31UL) /!< Position of PIN31 field. /
bogdanm	0:9b334a45a8ff	1877	#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /!< Bit mask of PIN31 field. /
bogdanm	0:9b334a45a8ff	1878	#define GPIO_IN_PIN31_Low (0UL) /!< Pin input is low. /
bogdanm	0:9b334a45a8ff	1879	#define GPIO_IN_PIN31_High (1UL) /!< Pin input is high. /
bogdanm	0:9b334a45a8ff	1880
bogdanm	0:9b334a45a8ff	1881	/* Bit 30 : Pin 30. */
bogdanm	0:9b334a45a8ff	1882	#define GPIO_IN_PIN30_Pos (30UL) /!< Position of PIN30 field. /
bogdanm	0:9b334a45a8ff	1883	#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /!< Bit mask of PIN30 field. /
bogdanm	0:9b334a45a8ff	1884	#define GPIO_IN_PIN30_Low (0UL) /!< Pin input is low. /
bogdanm	0:9b334a45a8ff	1885	#define GPIO_IN_PIN30_High (1UL) /!< Pin input is high. /
bogdanm	0:9b334a45a8ff	1886
bogdanm	0:9b334a45a8ff	1887	/* Bit 29 : Pin 29. */
bogdanm	0:9b334a45a8ff	1888	#define GPIO_IN_PIN29_Pos (29UL) /!< Position of PIN29 field. /
bogdanm	0:9b334a45a8ff	1889	#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /!< Bit mask of PIN29 field. /
bogdanm	0:9b334a45a8ff	1890	#define GPIO_IN_PIN29_Low (0UL) /!< Pin input is low. /
bogdanm	0:9b334a45a8ff	1891	#define GPIO_IN_PIN29_High (1UL) /!< Pin input is high. /
bogdanm	0:9b334a45a8ff	1892
bogdanm	0:9b334a45a8ff	1893	/* Bit 28 : Pin 28. */
bogdanm	0:9b334a45a8ff	1894	#define GPIO_IN_PIN28_Pos (28UL) /!< Position of PIN28 field. /
bogdanm	0:9b334a45a8ff	1895	#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /!< Bit mask of PIN28 field. /
bogdanm	0:9b334a45a8ff	1896	#define GPIO_IN_PIN28_Low (0UL) /!< Pin input is low. /
bogdanm	0:9b334a45a8ff	1897	#define GPIO_IN_PIN28_High (1UL) /!< Pin input is high. /
bogdanm	0:9b334a45a8ff	1898
bogdanm	0:9b334a45a8ff	1899	/* Bit 27 : Pin 27. */
bogdanm	0:9b334a45a8ff	1900	#define GPIO_IN_PIN27_Pos (27UL) /!< Position of PIN27 field. /
bogdanm	0:9b334a45a8ff	1901	#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /!< Bit mask of PIN27 field. /
bogdanm	0:9b334a45a8ff	1902	#define GPIO_IN_PIN27_Low (0UL) /!< Pin input is low. /
bogdanm	0:9b334a45a8ff	1903	#define GPIO_IN_PIN27_High (1UL) /!< Pin input is high. /
bogdanm	0:9b334a45a8ff	1904
bogdanm	0:9b334a45a8ff	1905	/* Bit 26 : Pin 26. */
bogdanm	0:9b334a45a8ff	1906	#define GPIO_IN_PIN26_Pos (26UL) /!< Position of PIN26 field. /
bogdanm	0:9b334a45a8ff	1907	#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /!< Bit mask of PIN26 field. /
bogdanm	0:9b334a45a8ff	1908	#define GPIO_IN_PIN26_Low (0UL) /!< Pin input is low. /
bogdanm	0:9b334a45a8ff	1909	#define GPIO_IN_PIN26_High (1UL) /!< Pin input is high. /
bogdanm	0:9b334a45a8ff	1910
bogdanm	0:9b334a45a8ff	1911	/* Bit 25 : Pin 25. */
bogdanm	0:9b334a45a8ff	1912	#define GPIO_IN_PIN25_Pos (25UL) /!< Position of PIN25 field. /
bogdanm	0:9b334a45a8ff	1913	#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /!< Bit mask of PIN25 field. /
bogdanm	0:9b334a45a8ff	1914	#define GPIO_IN_PIN25_Low (0UL) /!< Pin input is low. /
bogdanm	0:9b334a45a8ff	1915	#define GPIO_IN_PIN25_High (1UL) /!< Pin input is high. /
bogdanm	0:9b334a45a8ff	1916
bogdanm	0:9b334a45a8ff	1917	/* Bit 24 : Pin 24. */
bogdanm	0:9b334a45a8ff	1918	#define GPIO_IN_PIN24_Pos (24UL) /!< Position of PIN24 field. /
bogdanm	0:9b334a45a8ff	1919	#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /!< Bit mask of PIN24 field. /
bogdanm	0:9b334a45a8ff	1920	#define GPIO_IN_PIN24_Low (0UL) /!< Pin input is low. /
bogdanm	0:9b334a45a8ff	1921	#define GPIO_IN_PIN24_High (1UL) /!< Pin input is high. /
bogdanm	0:9b334a45a8ff	1922
bogdanm	0:9b334a45a8ff	1923	/* Bit 23 : Pin 23. */
bogdanm	0:9b334a45a8ff	1924	#define GPIO_IN_PIN23_Pos (23UL) /!< Position of PIN23 field. /
bogdanm	0:9b334a45a8ff	1925	#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /!< Bit mask of PIN23 field. /
bogdanm	0:9b334a45a8ff	1926	#define GPIO_IN_PIN23_Low (0UL) /!< Pin input is low. /
bogdanm	0:9b334a45a8ff	1927	#define GPIO_IN_PIN23_High (1UL) /!< Pin input is high. /
bogdanm	0:9b334a45a8ff	1928
bogdanm	0:9b334a45a8ff	1929	/* Bit 22 : Pin 22. */
bogdanm	0:9b334a45a8ff	1930	#define GPIO_IN_PIN22_Pos (22UL) /!< Position of PIN22 field. /
bogdanm	0:9b334a45a8ff	1931	#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /!< Bit mask of PIN22 field. /
bogdanm	0:9b334a45a8ff	1932	#define GPIO_IN_PIN22_Low (0UL) /!< Pin input is low. /
bogdanm	0:9b334a45a8ff	1933	#define GPIO_IN_PIN22_High (1UL) /!< Pin input is high. /
bogdanm	0:9b334a45a8ff	1934
bogdanm	0:9b334a45a8ff	1935	/* Bit 21 : Pin 21. */
bogdanm	0:9b334a45a8ff	1936	#define GPIO_IN_PIN21_Pos (21UL) /!< Position of PIN21 field. /
bogdanm	0:9b334a45a8ff	1937	#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /!< Bit mask of PIN21 field. /
bogdanm	0:9b334a45a8ff	1938	#define GPIO_IN_PIN21_Low (0UL) /!< Pin input is low. /
bogdanm	0:9b334a45a8ff	1939	#define GPIO_IN_PIN21_High (1UL) /!< Pin input is high. /
bogdanm	0:9b334a45a8ff	1940
bogdanm	0:9b334a45a8ff	1941	/* Bit 20 : Pin 20. */
bogdanm	0:9b334a45a8ff	1942	#define GPIO_IN_PIN20_Pos (20UL) /!< Position of PIN20 field. /
bogdanm	0:9b334a45a8ff	1943	#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /!< Bit mask of PIN20 field. /
bogdanm	0:9b334a45a8ff	1944	#define GPIO_IN_PIN20_Low (0UL) /!< Pin input is low. /
bogdanm	0:9b334a45a8ff	1945	#define GPIO_IN_PIN20_High (1UL) /!< Pin input is high. /
bogdanm	0:9b334a45a8ff	1946
bogdanm	0:9b334a45a8ff	1947	/* Bit 19 : Pin 19. */
bogdanm	0:9b334a45a8ff	1948	#define GPIO_IN_PIN19_Pos (19UL) /!< Position of PIN19 field. /
bogdanm	0:9b334a45a8ff	1949	#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /!< Bit mask of PIN19 field. /
bogdanm	0:9b334a45a8ff	1950	#define GPIO_IN_PIN19_Low (0UL) /!< Pin input is low. /
bogdanm	0:9b334a45a8ff	1951	#define GPIO_IN_PIN19_High (1UL) /!< Pin input is high. /
bogdanm	0:9b334a45a8ff	1952
bogdanm	0:9b334a45a8ff	1953	/* Bit 18 : Pin 18. */
bogdanm	0:9b334a45a8ff	1954	#define GPIO_IN_PIN18_Pos (18UL) /!< Position of PIN18 field. /
bogdanm	0:9b334a45a8ff	1955	#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /!< Bit mask of PIN18 field. /
bogdanm	0:9b334a45a8ff	1956	#define GPIO_IN_PIN18_Low (0UL) /!< Pin input is low. /
bogdanm	0:9b334a45a8ff	1957	#define GPIO_IN_PIN18_High (1UL) /!< Pin input is high. /
bogdanm	0:9b334a45a8ff	1958
bogdanm	0:9b334a45a8ff	1959	/* Bit 17 : Pin 17. */
bogdanm	0:9b334a45a8ff	1960	#define GPIO_IN_PIN17_Pos (17UL) /!< Position of PIN17 field. /
bogdanm	0:9b334a45a8ff	1961	#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /!< Bit mask of PIN17 field. /
bogdanm	0:9b334a45a8ff	1962	#define GPIO_IN_PIN17_Low (0UL) /!< Pin input is low. /
bogdanm	0:9b334a45a8ff	1963	#define GPIO_IN_PIN17_High (1UL) /!< Pin input is high. /
bogdanm	0:9b334a45a8ff	1964
bogdanm	0:9b334a45a8ff	1965	/* Bit 16 : Pin 16. */
bogdanm	0:9b334a45a8ff	1966	#define GPIO_IN_PIN16_Pos (16UL) /!< Position of PIN16 field. /
bogdanm	0:9b334a45a8ff	1967	#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /!< Bit mask of PIN16 field. /
bogdanm	0:9b334a45a8ff	1968	#define GPIO_IN_PIN16_Low (0UL) /!< Pin input is low. /
bogdanm	0:9b334a45a8ff	1969	#define GPIO_IN_PIN16_High (1UL) /!< Pin input is high. /
bogdanm	0:9b334a45a8ff	1970
bogdanm	0:9b334a45a8ff	1971	/* Bit 15 : Pin 15. */
bogdanm	0:9b334a45a8ff	1972	#define GPIO_IN_PIN15_Pos (15UL) /!< Position of PIN15 field. /
bogdanm	0:9b334a45a8ff	1973	#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /!< Bit mask of PIN15 field. /
bogdanm	0:9b334a45a8ff	1974	#define GPIO_IN_PIN15_Low (0UL) /!< Pin input is low. /
bogdanm	0:9b334a45a8ff	1975	#define GPIO_IN_PIN15_High (1UL) /!< Pin input is high. /
bogdanm	0:9b334a45a8ff	1976
bogdanm	0:9b334a45a8ff	1977	/* Bit 14 : Pin 14. */
bogdanm	0:9b334a45a8ff	1978	#define GPIO_IN_PIN14_Pos (14UL) /!< Position of PIN14 field. /
bogdanm	0:9b334a45a8ff	1979	#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /!< Bit mask of PIN14 field. /
bogdanm	0:9b334a45a8ff	1980	#define GPIO_IN_PIN14_Low (0UL) /!< Pin input is low. /
bogdanm	0:9b334a45a8ff	1981	#define GPIO_IN_PIN14_High (1UL) /!< Pin input is high. /
bogdanm	0:9b334a45a8ff	1982
bogdanm	0:9b334a45a8ff	1983	/* Bit 13 : Pin 13. */
bogdanm	0:9b334a45a8ff	1984	#define GPIO_IN_PIN13_Pos (13UL) /!< Position of PIN13 field. /
bogdanm	0:9b334a45a8ff	1985	#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /!< Bit mask of PIN13 field. /
bogdanm	0:9b334a45a8ff	1986	#define GPIO_IN_PIN13_Low (0UL) /!< Pin input is low. /
bogdanm	0:9b334a45a8ff	1987	#define GPIO_IN_PIN13_High (1UL) /!< Pin input is high. /
bogdanm	0:9b334a45a8ff	1988
bogdanm	0:9b334a45a8ff	1989	/* Bit 12 : Pin 12. */
bogdanm	0:9b334a45a8ff	1990	#define GPIO_IN_PIN12_Pos (12UL) /!< Position of PIN12 field. /
bogdanm	0:9b334a45a8ff	1991	#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /!< Bit mask of PIN12 field. /
bogdanm	0:9b334a45a8ff	1992	#define GPIO_IN_PIN12_Low (0UL) /!< Pin input is low. /
bogdanm	0:9b334a45a8ff	1993	#define GPIO_IN_PIN12_High (1UL) /!< Pin input is high. /
bogdanm	0:9b334a45a8ff	1994
bogdanm	0:9b334a45a8ff	1995	/* Bit 11 : Pin 11. */
bogdanm	0:9b334a45a8ff	1996	#define GPIO_IN_PIN11_Pos (11UL) /!< Position of PIN11 field. /
bogdanm	0:9b334a45a8ff	1997	#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /!< Bit mask of PIN11 field. /
bogdanm	0:9b334a45a8ff	1998	#define GPIO_IN_PIN11_Low (0UL) /!< Pin input is low. /
bogdanm	0:9b334a45a8ff	1999	#define GPIO_IN_PIN11_High (1UL) /!< Pin input is high. /
bogdanm	0:9b334a45a8ff	2000
bogdanm	0:9b334a45a8ff	2001	/* Bit 10 : Pin 10. */
bogdanm	0:9b334a45a8ff	2002	#define GPIO_IN_PIN10_Pos (10UL) /!< Position of PIN10 field. /
bogdanm	0:9b334a45a8ff	2003	#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /!< Bit mask of PIN10 field. /
bogdanm	0:9b334a45a8ff	2004	#define GPIO_IN_PIN10_Low (0UL) /!< Pin input is low. /
bogdanm	0:9b334a45a8ff	2005	#define GPIO_IN_PIN10_High (1UL) /!< Pin input is high. /
bogdanm	0:9b334a45a8ff	2006
bogdanm	0:9b334a45a8ff	2007	/* Bit 9 : Pin 9. */
bogdanm	0:9b334a45a8ff	2008	#define GPIO_IN_PIN9_Pos (9UL) /!< Position of PIN9 field. /
bogdanm	0:9b334a45a8ff	2009	#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /!< Bit mask of PIN9 field. /
bogdanm	0:9b334a45a8ff	2010	#define GPIO_IN_PIN9_Low (0UL) /!< Pin input is low. /
bogdanm	0:9b334a45a8ff	2011	#define GPIO_IN_PIN9_High (1UL) /!< Pin input is high. /
bogdanm	0:9b334a45a8ff	2012
bogdanm	0:9b334a45a8ff	2013	/* Bit 8 : Pin 8. */
bogdanm	0:9b334a45a8ff	2014	#define GPIO_IN_PIN8_Pos (8UL) /!< Position of PIN8 field. /
bogdanm	0:9b334a45a8ff	2015	#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /!< Bit mask of PIN8 field. /
bogdanm	0:9b334a45a8ff	2016	#define GPIO_IN_PIN8_Low (0UL) /!< Pin input is low. /
bogdanm	0:9b334a45a8ff	2017	#define GPIO_IN_PIN8_High (1UL) /!< Pin input is high. /
bogdanm	0:9b334a45a8ff	2018
bogdanm	0:9b334a45a8ff	2019	/* Bit 7 : Pin 7. */
bogdanm	0:9b334a45a8ff	2020	#define GPIO_IN_PIN7_Pos (7UL) /!< Position of PIN7 field. /
bogdanm	0:9b334a45a8ff	2021	#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /!< Bit mask of PIN7 field. /
bogdanm	0:9b334a45a8ff	2022	#define GPIO_IN_PIN7_Low (0UL) /!< Pin input is low. /
bogdanm	0:9b334a45a8ff	2023	#define GPIO_IN_PIN7_High (1UL) /!< Pin input is high. /
bogdanm	0:9b334a45a8ff	2024
bogdanm	0:9b334a45a8ff	2025	/* Bit 6 : Pin 6. */
bogdanm	0:9b334a45a8ff	2026	#define GPIO_IN_PIN6_Pos (6UL) /!< Position of PIN6 field. /
bogdanm	0:9b334a45a8ff	2027	#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /!< Bit mask of PIN6 field. /
bogdanm	0:9b334a45a8ff	2028	#define GPIO_IN_PIN6_Low (0UL) /!< Pin input is low. /
bogdanm	0:9b334a45a8ff	2029	#define GPIO_IN_PIN6_High (1UL) /!< Pin input is high. /
bogdanm	0:9b334a45a8ff	2030
bogdanm	0:9b334a45a8ff	2031	/* Bit 5 : Pin 5. */
bogdanm	0:9b334a45a8ff	2032	#define GPIO_IN_PIN5_Pos (5UL) /!< Position of PIN5 field. /
bogdanm	0:9b334a45a8ff	2033	#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /!< Bit mask of PIN5 field. /
bogdanm	0:9b334a45a8ff	2034	#define GPIO_IN_PIN5_Low (0UL) /!< Pin input is low. /
bogdanm	0:9b334a45a8ff	2035	#define GPIO_IN_PIN5_High (1UL) /!< Pin input is high. /
bogdanm	0:9b334a45a8ff	2036
bogdanm	0:9b334a45a8ff	2037	/* Bit 4 : Pin 4. */
bogdanm	0:9b334a45a8ff	2038	#define GPIO_IN_PIN4_Pos (4UL) /!< Position of PIN4 field. /
bogdanm	0:9b334a45a8ff	2039	#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /!< Bit mask of PIN4 field. /
bogdanm	0:9b334a45a8ff	2040	#define GPIO_IN_PIN4_Low (0UL) /!< Pin input is low. /
bogdanm	0:9b334a45a8ff	2041	#define GPIO_IN_PIN4_High (1UL) /!< Pin input is high. /
bogdanm	0:9b334a45a8ff	2042
bogdanm	0:9b334a45a8ff	2043	/* Bit 3 : Pin 3. */
bogdanm	0:9b334a45a8ff	2044	#define GPIO_IN_PIN3_Pos (3UL) /!< Position of PIN3 field. /
bogdanm	0:9b334a45a8ff	2045	#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /!< Bit mask of PIN3 field. /
bogdanm	0:9b334a45a8ff	2046	#define GPIO_IN_PIN3_Low (0UL) /!< Pin input is low. /
bogdanm	0:9b334a45a8ff	2047	#define GPIO_IN_PIN3_High (1UL) /!< Pin input is high. /
bogdanm	0:9b334a45a8ff	2048
bogdanm	0:9b334a45a8ff	2049	/* Bit 2 : Pin 2. */
bogdanm	0:9b334a45a8ff	2050	#define GPIO_IN_PIN2_Pos (2UL) /!< Position of PIN2 field. /
bogdanm	0:9b334a45a8ff	2051	#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /!< Bit mask of PIN2 field. /
bogdanm	0:9b334a45a8ff	2052	#define GPIO_IN_PIN2_Low (0UL) /!< Pin input is low. /
bogdanm	0:9b334a45a8ff	2053	#define GPIO_IN_PIN2_High (1UL) /!< Pin input is high. /
bogdanm	0:9b334a45a8ff	2054
bogdanm	0:9b334a45a8ff	2055	/* Bit 1 : Pin 1. */
bogdanm	0:9b334a45a8ff	2056	#define GPIO_IN_PIN1_Pos (1UL) /!< Position of PIN1 field. /
bogdanm	0:9b334a45a8ff	2057	#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /!< Bit mask of PIN1 field. /
bogdanm	0:9b334a45a8ff	2058	#define GPIO_IN_PIN1_Low (0UL) /!< Pin input is low. /
bogdanm	0:9b334a45a8ff	2059	#define GPIO_IN_PIN1_High (1UL) /!< Pin input is high. /
bogdanm	0:9b334a45a8ff	2060
bogdanm	0:9b334a45a8ff	2061	/* Bit 0 : Pin 0. */
bogdanm	0:9b334a45a8ff	2062	#define GPIO_IN_PIN0_Pos (0UL) /!< Position of PIN0 field. /
bogdanm	0:9b334a45a8ff	2063	#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /!< Bit mask of PIN0 field. /
bogdanm	0:9b334a45a8ff	2064	#define GPIO_IN_PIN0_Low (0UL) /!< Pin input is low. /
bogdanm	0:9b334a45a8ff	2065	#define GPIO_IN_PIN0_High (1UL) /!< Pin input is high. /
bogdanm	0:9b334a45a8ff	2066
bogdanm	0:9b334a45a8ff	2067	/* Register: GPIO_DIR */
bogdanm	0:9b334a45a8ff	2068	/* Description: Direction of GPIO pins. */
bogdanm	0:9b334a45a8ff	2069
bogdanm	0:9b334a45a8ff	2070	/* Bit 31 : Pin 31. */
bogdanm	0:9b334a45a8ff	2071	#define GPIO_DIR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
bogdanm	0:9b334a45a8ff	2072	#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /!< Bit mask of PIN31 field. /
bogdanm	0:9b334a45a8ff	2073	#define GPIO_DIR_PIN31_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2074	#define GPIO_DIR_PIN31_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2075
bogdanm	0:9b334a45a8ff	2076	/* Bit 30 : Pin 30. */
bogdanm	0:9b334a45a8ff	2077	#define GPIO_DIR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
bogdanm	0:9b334a45a8ff	2078	#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /!< Bit mask of PIN30 field. /
bogdanm	0:9b334a45a8ff	2079	#define GPIO_DIR_PIN30_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2080	#define GPIO_DIR_PIN30_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2081
bogdanm	0:9b334a45a8ff	2082	/* Bit 29 : Pin 29. */
bogdanm	0:9b334a45a8ff	2083	#define GPIO_DIR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
bogdanm	0:9b334a45a8ff	2084	#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /!< Bit mask of PIN29 field. /
bogdanm	0:9b334a45a8ff	2085	#define GPIO_DIR_PIN29_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2086	#define GPIO_DIR_PIN29_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2087
bogdanm	0:9b334a45a8ff	2088	/* Bit 28 : Pin 28. */
bogdanm	0:9b334a45a8ff	2089	#define GPIO_DIR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
bogdanm	0:9b334a45a8ff	2090	#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /!< Bit mask of PIN28 field. /
bogdanm	0:9b334a45a8ff	2091	#define GPIO_DIR_PIN28_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2092	#define GPIO_DIR_PIN28_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2093
bogdanm	0:9b334a45a8ff	2094	/* Bit 27 : Pin 27. */
bogdanm	0:9b334a45a8ff	2095	#define GPIO_DIR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
bogdanm	0:9b334a45a8ff	2096	#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /!< Bit mask of PIN27 field. /
bogdanm	0:9b334a45a8ff	2097	#define GPIO_DIR_PIN27_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2098	#define GPIO_DIR_PIN27_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2099
bogdanm	0:9b334a45a8ff	2100	/* Bit 26 : Pin 26. */
bogdanm	0:9b334a45a8ff	2101	#define GPIO_DIR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
bogdanm	0:9b334a45a8ff	2102	#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /!< Bit mask of PIN26 field. /
bogdanm	0:9b334a45a8ff	2103	#define GPIO_DIR_PIN26_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2104	#define GPIO_DIR_PIN26_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2105
bogdanm	0:9b334a45a8ff	2106	/* Bit 25 : Pin 25. */
bogdanm	0:9b334a45a8ff	2107	#define GPIO_DIR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
bogdanm	0:9b334a45a8ff	2108	#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /!< Bit mask of PIN25 field. /
bogdanm	0:9b334a45a8ff	2109	#define GPIO_DIR_PIN25_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2110	#define GPIO_DIR_PIN25_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2111
bogdanm	0:9b334a45a8ff	2112	/* Bit 24 : Pin 24. */
bogdanm	0:9b334a45a8ff	2113	#define GPIO_DIR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
bogdanm	0:9b334a45a8ff	2114	#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /!< Bit mask of PIN24 field. /
bogdanm	0:9b334a45a8ff	2115	#define GPIO_DIR_PIN24_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2116	#define GPIO_DIR_PIN24_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2117
bogdanm	0:9b334a45a8ff	2118	/* Bit 23 : Pin 23. */
bogdanm	0:9b334a45a8ff	2119	#define GPIO_DIR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
bogdanm	0:9b334a45a8ff	2120	#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /!< Bit mask of PIN23 field. /
bogdanm	0:9b334a45a8ff	2121	#define GPIO_DIR_PIN23_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2122	#define GPIO_DIR_PIN23_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2123
bogdanm	0:9b334a45a8ff	2124	/* Bit 22 : Pin 22. */
bogdanm	0:9b334a45a8ff	2125	#define GPIO_DIR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
bogdanm	0:9b334a45a8ff	2126	#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /!< Bit mask of PIN22 field. /
bogdanm	0:9b334a45a8ff	2127	#define GPIO_DIR_PIN22_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2128	#define GPIO_DIR_PIN22_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2129
bogdanm	0:9b334a45a8ff	2130	/* Bit 21 : Pin 21. */
bogdanm	0:9b334a45a8ff	2131	#define GPIO_DIR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
bogdanm	0:9b334a45a8ff	2132	#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /!< Bit mask of PIN21 field. /
bogdanm	0:9b334a45a8ff	2133	#define GPIO_DIR_PIN21_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2134	#define GPIO_DIR_PIN21_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2135
bogdanm	0:9b334a45a8ff	2136	/* Bit 20 : Pin 20. */
bogdanm	0:9b334a45a8ff	2137	#define GPIO_DIR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
bogdanm	0:9b334a45a8ff	2138	#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /!< Bit mask of PIN20 field. /
bogdanm	0:9b334a45a8ff	2139	#define GPIO_DIR_PIN20_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2140	#define GPIO_DIR_PIN20_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2141
bogdanm	0:9b334a45a8ff	2142	/* Bit 19 : Pin 19. */
bogdanm	0:9b334a45a8ff	2143	#define GPIO_DIR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
bogdanm	0:9b334a45a8ff	2144	#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /!< Bit mask of PIN19 field. /
bogdanm	0:9b334a45a8ff	2145	#define GPIO_DIR_PIN19_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2146	#define GPIO_DIR_PIN19_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2147
bogdanm	0:9b334a45a8ff	2148	/* Bit 18 : Pin 18. */
bogdanm	0:9b334a45a8ff	2149	#define GPIO_DIR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
bogdanm	0:9b334a45a8ff	2150	#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /!< Bit mask of PIN18 field. /
bogdanm	0:9b334a45a8ff	2151	#define GPIO_DIR_PIN18_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2152	#define GPIO_DIR_PIN18_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2153
bogdanm	0:9b334a45a8ff	2154	/* Bit 17 : Pin 17. */
bogdanm	0:9b334a45a8ff	2155	#define GPIO_DIR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
bogdanm	0:9b334a45a8ff	2156	#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /!< Bit mask of PIN17 field. /
bogdanm	0:9b334a45a8ff	2157	#define GPIO_DIR_PIN17_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2158	#define GPIO_DIR_PIN17_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2159
bogdanm	0:9b334a45a8ff	2160	/* Bit 16 : Pin 16. */
bogdanm	0:9b334a45a8ff	2161	#define GPIO_DIR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
bogdanm	0:9b334a45a8ff	2162	#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /!< Bit mask of PIN16 field. /
bogdanm	0:9b334a45a8ff	2163	#define GPIO_DIR_PIN16_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2164	#define GPIO_DIR_PIN16_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2165
bogdanm	0:9b334a45a8ff	2166	/* Bit 15 : Pin 15. */
bogdanm	0:9b334a45a8ff	2167	#define GPIO_DIR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
bogdanm	0:9b334a45a8ff	2168	#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /!< Bit mask of PIN15 field. /
bogdanm	0:9b334a45a8ff	2169	#define GPIO_DIR_PIN15_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2170	#define GPIO_DIR_PIN15_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2171
bogdanm	0:9b334a45a8ff	2172	/* Bit 14 : Pin 14. */
bogdanm	0:9b334a45a8ff	2173	#define GPIO_DIR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
bogdanm	0:9b334a45a8ff	2174	#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /!< Bit mask of PIN14 field. /
bogdanm	0:9b334a45a8ff	2175	#define GPIO_DIR_PIN14_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2176	#define GPIO_DIR_PIN14_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2177
bogdanm	0:9b334a45a8ff	2178	/* Bit 13 : Pin 13. */
bogdanm	0:9b334a45a8ff	2179	#define GPIO_DIR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
bogdanm	0:9b334a45a8ff	2180	#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /!< Bit mask of PIN13 field. /
bogdanm	0:9b334a45a8ff	2181	#define GPIO_DIR_PIN13_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2182	#define GPIO_DIR_PIN13_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2183
bogdanm	0:9b334a45a8ff	2184	/* Bit 12 : Pin 12. */
bogdanm	0:9b334a45a8ff	2185	#define GPIO_DIR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
bogdanm	0:9b334a45a8ff	2186	#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /!< Bit mask of PIN12 field. /
bogdanm	0:9b334a45a8ff	2187	#define GPIO_DIR_PIN12_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2188	#define GPIO_DIR_PIN12_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2189
bogdanm	0:9b334a45a8ff	2190	/* Bit 11 : Pin 11. */
bogdanm	0:9b334a45a8ff	2191	#define GPIO_DIR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
bogdanm	0:9b334a45a8ff	2192	#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /!< Bit mask of PIN11 field. /
bogdanm	0:9b334a45a8ff	2193	#define GPIO_DIR_PIN11_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2194	#define GPIO_DIR_PIN11_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2195
bogdanm	0:9b334a45a8ff	2196	/* Bit 10 : Pin 10. */
bogdanm	0:9b334a45a8ff	2197	#define GPIO_DIR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
bogdanm	0:9b334a45a8ff	2198	#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /!< Bit mask of PIN10 field. /
bogdanm	0:9b334a45a8ff	2199	#define GPIO_DIR_PIN10_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2200	#define GPIO_DIR_PIN10_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2201
bogdanm	0:9b334a45a8ff	2202	/* Bit 9 : Pin 9. */
bogdanm	0:9b334a45a8ff	2203	#define GPIO_DIR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
bogdanm	0:9b334a45a8ff	2204	#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /!< Bit mask of PIN9 field. /
bogdanm	0:9b334a45a8ff	2205	#define GPIO_DIR_PIN9_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2206	#define GPIO_DIR_PIN9_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2207
bogdanm	0:9b334a45a8ff	2208	/* Bit 8 : Pin 8. */
bogdanm	0:9b334a45a8ff	2209	#define GPIO_DIR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
bogdanm	0:9b334a45a8ff	2210	#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /!< Bit mask of PIN8 field. /
bogdanm	0:9b334a45a8ff	2211	#define GPIO_DIR_PIN8_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2212	#define GPIO_DIR_PIN8_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2213
bogdanm	0:9b334a45a8ff	2214	/* Bit 7 : Pin 7. */
bogdanm	0:9b334a45a8ff	2215	#define GPIO_DIR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
bogdanm	0:9b334a45a8ff	2216	#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /!< Bit mask of PIN7 field. /
bogdanm	0:9b334a45a8ff	2217	#define GPIO_DIR_PIN7_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2218	#define GPIO_DIR_PIN7_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2219
bogdanm	0:9b334a45a8ff	2220	/* Bit 6 : Pin 6. */
bogdanm	0:9b334a45a8ff	2221	#define GPIO_DIR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
bogdanm	0:9b334a45a8ff	2222	#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /!< Bit mask of PIN6 field. /
bogdanm	0:9b334a45a8ff	2223	#define GPIO_DIR_PIN6_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2224	#define GPIO_DIR_PIN6_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2225
bogdanm	0:9b334a45a8ff	2226	/* Bit 5 : Pin 5. */
bogdanm	0:9b334a45a8ff	2227	#define GPIO_DIR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
bogdanm	0:9b334a45a8ff	2228	#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /!< Bit mask of PIN5 field. /
bogdanm	0:9b334a45a8ff	2229	#define GPIO_DIR_PIN5_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2230	#define GPIO_DIR_PIN5_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2231
bogdanm	0:9b334a45a8ff	2232	/* Bit 4 : Pin 4. */
bogdanm	0:9b334a45a8ff	2233	#define GPIO_DIR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
bogdanm	0:9b334a45a8ff	2234	#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /!< Bit mask of PIN4 field. /
bogdanm	0:9b334a45a8ff	2235	#define GPIO_DIR_PIN4_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2236	#define GPIO_DIR_PIN4_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2237
bogdanm	0:9b334a45a8ff	2238	/* Bit 3 : Pin 3. */
bogdanm	0:9b334a45a8ff	2239	#define GPIO_DIR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
bogdanm	0:9b334a45a8ff	2240	#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /!< Bit mask of PIN3 field. /
bogdanm	0:9b334a45a8ff	2241	#define GPIO_DIR_PIN3_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2242	#define GPIO_DIR_PIN3_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2243
bogdanm	0:9b334a45a8ff	2244	/* Bit 2 : Pin 2. */
bogdanm	0:9b334a45a8ff	2245	#define GPIO_DIR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
bogdanm	0:9b334a45a8ff	2246	#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /!< Bit mask of PIN2 field. /
bogdanm	0:9b334a45a8ff	2247	#define GPIO_DIR_PIN2_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2248	#define GPIO_DIR_PIN2_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2249
bogdanm	0:9b334a45a8ff	2250	/* Bit 1 : Pin 1. */
bogdanm	0:9b334a45a8ff	2251	#define GPIO_DIR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
bogdanm	0:9b334a45a8ff	2252	#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /!< Bit mask of PIN1 field. /
bogdanm	0:9b334a45a8ff	2253	#define GPIO_DIR_PIN1_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2254	#define GPIO_DIR_PIN1_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2255
bogdanm	0:9b334a45a8ff	2256	/* Bit 0 : Pin 0. */
bogdanm	0:9b334a45a8ff	2257	#define GPIO_DIR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
bogdanm	0:9b334a45a8ff	2258	#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /!< Bit mask of PIN0 field. /
bogdanm	0:9b334a45a8ff	2259	#define GPIO_DIR_PIN0_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2260	#define GPIO_DIR_PIN0_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2261
bogdanm	0:9b334a45a8ff	2262	/* Register: GPIO_DIRSET */
bogdanm	0:9b334a45a8ff	2263	/* Description: DIR set register. */
bogdanm	0:9b334a45a8ff	2264
bogdanm	0:9b334a45a8ff	2265	/* Bit 31 : Set as output pin 31. */
bogdanm	0:9b334a45a8ff	2266	#define GPIO_DIRSET_PIN31_Pos (31UL) /!< Position of PIN31 field. /
bogdanm	0:9b334a45a8ff	2267	#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /!< Bit mask of PIN31 field. /
bogdanm	0:9b334a45a8ff	2268	#define GPIO_DIRSET_PIN31_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2269	#define GPIO_DIRSET_PIN31_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2270	#define GPIO_DIRSET_PIN31_Set (1UL) /!< Set pin as output. /
bogdanm	0:9b334a45a8ff	2271
bogdanm	0:9b334a45a8ff	2272	/* Bit 30 : Set as output pin 30. */
bogdanm	0:9b334a45a8ff	2273	#define GPIO_DIRSET_PIN30_Pos (30UL) /!< Position of PIN30 field. /
bogdanm	0:9b334a45a8ff	2274	#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /!< Bit mask of PIN30 field. /
bogdanm	0:9b334a45a8ff	2275	#define GPIO_DIRSET_PIN30_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2276	#define GPIO_DIRSET_PIN30_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2277	#define GPIO_DIRSET_PIN30_Set (1UL) /!< Set pin as output. /
bogdanm	0:9b334a45a8ff	2278
bogdanm	0:9b334a45a8ff	2279	/* Bit 29 : Set as output pin 29. */
bogdanm	0:9b334a45a8ff	2280	#define GPIO_DIRSET_PIN29_Pos (29UL) /!< Position of PIN29 field. /
bogdanm	0:9b334a45a8ff	2281	#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /!< Bit mask of PIN29 field. /
bogdanm	0:9b334a45a8ff	2282	#define GPIO_DIRSET_PIN29_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2283	#define GPIO_DIRSET_PIN29_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2284	#define GPIO_DIRSET_PIN29_Set (1UL) /!< Set pin as output. /
bogdanm	0:9b334a45a8ff	2285
bogdanm	0:9b334a45a8ff	2286	/* Bit 28 : Set as output pin 28. */
bogdanm	0:9b334a45a8ff	2287	#define GPIO_DIRSET_PIN28_Pos (28UL) /!< Position of PIN28 field. /
bogdanm	0:9b334a45a8ff	2288	#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /!< Bit mask of PIN28 field. /
bogdanm	0:9b334a45a8ff	2289	#define GPIO_DIRSET_PIN28_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2290	#define GPIO_DIRSET_PIN28_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2291	#define GPIO_DIRSET_PIN28_Set (1UL) /!< Set pin as output. /
bogdanm	0:9b334a45a8ff	2292
bogdanm	0:9b334a45a8ff	2293	/* Bit 27 : Set as output pin 27. */
bogdanm	0:9b334a45a8ff	2294	#define GPIO_DIRSET_PIN27_Pos (27UL) /!< Position of PIN27 field. /
bogdanm	0:9b334a45a8ff	2295	#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /!< Bit mask of PIN27 field. /
bogdanm	0:9b334a45a8ff	2296	#define GPIO_DIRSET_PIN27_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2297	#define GPIO_DIRSET_PIN27_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2298	#define GPIO_DIRSET_PIN27_Set (1UL) /!< Set pin as output. /
bogdanm	0:9b334a45a8ff	2299
bogdanm	0:9b334a45a8ff	2300	/* Bit 26 : Set as output pin 26. */
bogdanm	0:9b334a45a8ff	2301	#define GPIO_DIRSET_PIN26_Pos (26UL) /!< Position of PIN26 field. /
bogdanm	0:9b334a45a8ff	2302	#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /!< Bit mask of PIN26 field. /
bogdanm	0:9b334a45a8ff	2303	#define GPIO_DIRSET_PIN26_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2304	#define GPIO_DIRSET_PIN26_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2305	#define GPIO_DIRSET_PIN26_Set (1UL) /!< Set pin as output. /
bogdanm	0:9b334a45a8ff	2306
bogdanm	0:9b334a45a8ff	2307	/* Bit 25 : Set as output pin 25. */
bogdanm	0:9b334a45a8ff	2308	#define GPIO_DIRSET_PIN25_Pos (25UL) /!< Position of PIN25 field. /
bogdanm	0:9b334a45a8ff	2309	#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /!< Bit mask of PIN25 field. /
bogdanm	0:9b334a45a8ff	2310	#define GPIO_DIRSET_PIN25_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2311	#define GPIO_DIRSET_PIN25_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2312	#define GPIO_DIRSET_PIN25_Set (1UL) /!< Set pin as output. /
bogdanm	0:9b334a45a8ff	2313
bogdanm	0:9b334a45a8ff	2314	/* Bit 24 : Set as output pin 24. */
bogdanm	0:9b334a45a8ff	2315	#define GPIO_DIRSET_PIN24_Pos (24UL) /!< Position of PIN24 field. /
bogdanm	0:9b334a45a8ff	2316	#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /!< Bit mask of PIN24 field. /
bogdanm	0:9b334a45a8ff	2317	#define GPIO_DIRSET_PIN24_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2318	#define GPIO_DIRSET_PIN24_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2319	#define GPIO_DIRSET_PIN24_Set (1UL) /!< Set pin as output. /
bogdanm	0:9b334a45a8ff	2320
bogdanm	0:9b334a45a8ff	2321	/* Bit 23 : Set as output pin 23. */
bogdanm	0:9b334a45a8ff	2322	#define GPIO_DIRSET_PIN23_Pos (23UL) /!< Position of PIN23 field. /
bogdanm	0:9b334a45a8ff	2323	#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /!< Bit mask of PIN23 field. /
bogdanm	0:9b334a45a8ff	2324	#define GPIO_DIRSET_PIN23_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2325	#define GPIO_DIRSET_PIN23_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2326	#define GPIO_DIRSET_PIN23_Set (1UL) /!< Set pin as output. /
bogdanm	0:9b334a45a8ff	2327
bogdanm	0:9b334a45a8ff	2328	/* Bit 22 : Set as output pin 22. */
bogdanm	0:9b334a45a8ff	2329	#define GPIO_DIRSET_PIN22_Pos (22UL) /!< Position of PIN22 field. /
bogdanm	0:9b334a45a8ff	2330	#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /!< Bit mask of PIN22 field. /
bogdanm	0:9b334a45a8ff	2331	#define GPIO_DIRSET_PIN22_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2332	#define GPIO_DIRSET_PIN22_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2333	#define GPIO_DIRSET_PIN22_Set (1UL) /!< Set pin as output. /
bogdanm	0:9b334a45a8ff	2334
bogdanm	0:9b334a45a8ff	2335	/* Bit 21 : Set as output pin 21. */
bogdanm	0:9b334a45a8ff	2336	#define GPIO_DIRSET_PIN21_Pos (21UL) /!< Position of PIN21 field. /
bogdanm	0:9b334a45a8ff	2337	#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /!< Bit mask of PIN21 field. /
bogdanm	0:9b334a45a8ff	2338	#define GPIO_DIRSET_PIN21_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2339	#define GPIO_DIRSET_PIN21_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2340	#define GPIO_DIRSET_PIN21_Set (1UL) /!< Set pin as output. /
bogdanm	0:9b334a45a8ff	2341
bogdanm	0:9b334a45a8ff	2342	/* Bit 20 : Set as output pin 20. */
bogdanm	0:9b334a45a8ff	2343	#define GPIO_DIRSET_PIN20_Pos (20UL) /!< Position of PIN20 field. /
bogdanm	0:9b334a45a8ff	2344	#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /!< Bit mask of PIN20 field. /
bogdanm	0:9b334a45a8ff	2345	#define GPIO_DIRSET_PIN20_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2346	#define GPIO_DIRSET_PIN20_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2347	#define GPIO_DIRSET_PIN20_Set (1UL) /!< Set pin as output. /
bogdanm	0:9b334a45a8ff	2348
bogdanm	0:9b334a45a8ff	2349	/* Bit 19 : Set as output pin 19. */
bogdanm	0:9b334a45a8ff	2350	#define GPIO_DIRSET_PIN19_Pos (19UL) /!< Position of PIN19 field. /
bogdanm	0:9b334a45a8ff	2351	#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /!< Bit mask of PIN19 field. /
bogdanm	0:9b334a45a8ff	2352	#define GPIO_DIRSET_PIN19_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2353	#define GPIO_DIRSET_PIN19_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2354	#define GPIO_DIRSET_PIN19_Set (1UL) /!< Set pin as output. /
bogdanm	0:9b334a45a8ff	2355
bogdanm	0:9b334a45a8ff	2356	/* Bit 18 : Set as output pin 18. */
bogdanm	0:9b334a45a8ff	2357	#define GPIO_DIRSET_PIN18_Pos (18UL) /!< Position of PIN18 field. /
bogdanm	0:9b334a45a8ff	2358	#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /!< Bit mask of PIN18 field. /
bogdanm	0:9b334a45a8ff	2359	#define GPIO_DIRSET_PIN18_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2360	#define GPIO_DIRSET_PIN18_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2361	#define GPIO_DIRSET_PIN18_Set (1UL) /!< Set pin as output. /
bogdanm	0:9b334a45a8ff	2362
bogdanm	0:9b334a45a8ff	2363	/* Bit 17 : Set as output pin 17. */
bogdanm	0:9b334a45a8ff	2364	#define GPIO_DIRSET_PIN17_Pos (17UL) /!< Position of PIN17 field. /
bogdanm	0:9b334a45a8ff	2365	#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /!< Bit mask of PIN17 field. /
bogdanm	0:9b334a45a8ff	2366	#define GPIO_DIRSET_PIN17_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2367	#define GPIO_DIRSET_PIN17_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2368	#define GPIO_DIRSET_PIN17_Set (1UL) /!< Set pin as output. /
bogdanm	0:9b334a45a8ff	2369
bogdanm	0:9b334a45a8ff	2370	/* Bit 16 : Set as output pin 16. */
bogdanm	0:9b334a45a8ff	2371	#define GPIO_DIRSET_PIN16_Pos (16UL) /!< Position of PIN16 field. /
bogdanm	0:9b334a45a8ff	2372	#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /!< Bit mask of PIN16 field. /
bogdanm	0:9b334a45a8ff	2373	#define GPIO_DIRSET_PIN16_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2374	#define GPIO_DIRSET_PIN16_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2375	#define GPIO_DIRSET_PIN16_Set (1UL) /!< Set pin as output. /
bogdanm	0:9b334a45a8ff	2376
bogdanm	0:9b334a45a8ff	2377	/* Bit 15 : Set as output pin 15. */
bogdanm	0:9b334a45a8ff	2378	#define GPIO_DIRSET_PIN15_Pos (15UL) /!< Position of PIN15 field. /
bogdanm	0:9b334a45a8ff	2379	#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /!< Bit mask of PIN15 field. /
bogdanm	0:9b334a45a8ff	2380	#define GPIO_DIRSET_PIN15_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2381	#define GPIO_DIRSET_PIN15_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2382	#define GPIO_DIRSET_PIN15_Set (1UL) /!< Set pin as output. /
bogdanm	0:9b334a45a8ff	2383
bogdanm	0:9b334a45a8ff	2384	/* Bit 14 : Set as output pin 14. */
bogdanm	0:9b334a45a8ff	2385	#define GPIO_DIRSET_PIN14_Pos (14UL) /!< Position of PIN14 field. /
bogdanm	0:9b334a45a8ff	2386	#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /!< Bit mask of PIN14 field. /
bogdanm	0:9b334a45a8ff	2387	#define GPIO_DIRSET_PIN14_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2388	#define GPIO_DIRSET_PIN14_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2389	#define GPIO_DIRSET_PIN14_Set (1UL) /!< Set pin as output. /
bogdanm	0:9b334a45a8ff	2390
bogdanm	0:9b334a45a8ff	2391	/* Bit 13 : Set as output pin 13. */
bogdanm	0:9b334a45a8ff	2392	#define GPIO_DIRSET_PIN13_Pos (13UL) /!< Position of PIN13 field. /
bogdanm	0:9b334a45a8ff	2393	#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /!< Bit mask of PIN13 field. /
bogdanm	0:9b334a45a8ff	2394	#define GPIO_DIRSET_PIN13_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2395	#define GPIO_DIRSET_PIN13_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2396	#define GPIO_DIRSET_PIN13_Set (1UL) /!< Set pin as output. /
bogdanm	0:9b334a45a8ff	2397
bogdanm	0:9b334a45a8ff	2398	/* Bit 12 : Set as output pin 12. */
bogdanm	0:9b334a45a8ff	2399	#define GPIO_DIRSET_PIN12_Pos (12UL) /!< Position of PIN12 field. /
bogdanm	0:9b334a45a8ff	2400	#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /!< Bit mask of PIN12 field. /
bogdanm	0:9b334a45a8ff	2401	#define GPIO_DIRSET_PIN12_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2402	#define GPIO_DIRSET_PIN12_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2403	#define GPIO_DIRSET_PIN12_Set (1UL) /!< Set pin as output. /
bogdanm	0:9b334a45a8ff	2404
bogdanm	0:9b334a45a8ff	2405	/* Bit 11 : Set as output pin 11. */
bogdanm	0:9b334a45a8ff	2406	#define GPIO_DIRSET_PIN11_Pos (11UL) /!< Position of PIN11 field. /
bogdanm	0:9b334a45a8ff	2407	#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /!< Bit mask of PIN11 field. /
bogdanm	0:9b334a45a8ff	2408	#define GPIO_DIRSET_PIN11_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2409	#define GPIO_DIRSET_PIN11_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2410	#define GPIO_DIRSET_PIN11_Set (1UL) /!< Set pin as output. /
bogdanm	0:9b334a45a8ff	2411
bogdanm	0:9b334a45a8ff	2412	/* Bit 10 : Set as output pin 10. */
bogdanm	0:9b334a45a8ff	2413	#define GPIO_DIRSET_PIN10_Pos (10UL) /!< Position of PIN10 field. /
bogdanm	0:9b334a45a8ff	2414	#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /!< Bit mask of PIN10 field. /
bogdanm	0:9b334a45a8ff	2415	#define GPIO_DIRSET_PIN10_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2416	#define GPIO_DIRSET_PIN10_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2417	#define GPIO_DIRSET_PIN10_Set (1UL) /!< Set pin as output. /
bogdanm	0:9b334a45a8ff	2418
bogdanm	0:9b334a45a8ff	2419	/* Bit 9 : Set as output pin 9. */
bogdanm	0:9b334a45a8ff	2420	#define GPIO_DIRSET_PIN9_Pos (9UL) /!< Position of PIN9 field. /
bogdanm	0:9b334a45a8ff	2421	#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /!< Bit mask of PIN9 field. /
bogdanm	0:9b334a45a8ff	2422	#define GPIO_DIRSET_PIN9_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2423	#define GPIO_DIRSET_PIN9_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2424	#define GPIO_DIRSET_PIN9_Set (1UL) /!< Set pin as output. /
bogdanm	0:9b334a45a8ff	2425
bogdanm	0:9b334a45a8ff	2426	/* Bit 8 : Set as output pin 8. */
bogdanm	0:9b334a45a8ff	2427	#define GPIO_DIRSET_PIN8_Pos (8UL) /!< Position of PIN8 field. /
bogdanm	0:9b334a45a8ff	2428	#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /!< Bit mask of PIN8 field. /
bogdanm	0:9b334a45a8ff	2429	#define GPIO_DIRSET_PIN8_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2430	#define GPIO_DIRSET_PIN8_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2431	#define GPIO_DIRSET_PIN8_Set (1UL) /!< Set pin as output. /
bogdanm	0:9b334a45a8ff	2432
bogdanm	0:9b334a45a8ff	2433	/* Bit 7 : Set as output pin 7. */
bogdanm	0:9b334a45a8ff	2434	#define GPIO_DIRSET_PIN7_Pos (7UL) /!< Position of PIN7 field. /
bogdanm	0:9b334a45a8ff	2435	#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /!< Bit mask of PIN7 field. /
bogdanm	0:9b334a45a8ff	2436	#define GPIO_DIRSET_PIN7_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2437	#define GPIO_DIRSET_PIN7_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2438	#define GPIO_DIRSET_PIN7_Set (1UL) /!< Set pin as output. /
bogdanm	0:9b334a45a8ff	2439
bogdanm	0:9b334a45a8ff	2440	/* Bit 6 : Set as output pin 6. */
bogdanm	0:9b334a45a8ff	2441	#define GPIO_DIRSET_PIN6_Pos (6UL) /!< Position of PIN6 field. /
bogdanm	0:9b334a45a8ff	2442	#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /!< Bit mask of PIN6 field. /
bogdanm	0:9b334a45a8ff	2443	#define GPIO_DIRSET_PIN6_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2444	#define GPIO_DIRSET_PIN6_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2445	#define GPIO_DIRSET_PIN6_Set (1UL) /!< Set pin as output. /
bogdanm	0:9b334a45a8ff	2446
bogdanm	0:9b334a45a8ff	2447	/* Bit 5 : Set as output pin 5. */
bogdanm	0:9b334a45a8ff	2448	#define GPIO_DIRSET_PIN5_Pos (5UL) /!< Position of PIN5 field. /
bogdanm	0:9b334a45a8ff	2449	#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /!< Bit mask of PIN5 field. /
bogdanm	0:9b334a45a8ff	2450	#define GPIO_DIRSET_PIN5_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2451	#define GPIO_DIRSET_PIN5_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2452	#define GPIO_DIRSET_PIN5_Set (1UL) /!< Set pin as output. /
bogdanm	0:9b334a45a8ff	2453
bogdanm	0:9b334a45a8ff	2454	/* Bit 4 : Set as output pin 4. */
bogdanm	0:9b334a45a8ff	2455	#define GPIO_DIRSET_PIN4_Pos (4UL) /!< Position of PIN4 field. /
bogdanm	0:9b334a45a8ff	2456	#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /!< Bit mask of PIN4 field. /
bogdanm	0:9b334a45a8ff	2457	#define GPIO_DIRSET_PIN4_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2458	#define GPIO_DIRSET_PIN4_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2459	#define GPIO_DIRSET_PIN4_Set (1UL) /!< Set pin as output. /
bogdanm	0:9b334a45a8ff	2460
bogdanm	0:9b334a45a8ff	2461	/* Bit 3 : Set as output pin 3. */
bogdanm	0:9b334a45a8ff	2462	#define GPIO_DIRSET_PIN3_Pos (3UL) /!< Position of PIN3 field. /
bogdanm	0:9b334a45a8ff	2463	#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /!< Bit mask of PIN3 field. /
bogdanm	0:9b334a45a8ff	2464	#define GPIO_DIRSET_PIN3_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2465	#define GPIO_DIRSET_PIN3_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2466	#define GPIO_DIRSET_PIN3_Set (1UL) /!< Set pin as output. /
bogdanm	0:9b334a45a8ff	2467
bogdanm	0:9b334a45a8ff	2468	/* Bit 2 : Set as output pin 2. */
bogdanm	0:9b334a45a8ff	2469	#define GPIO_DIRSET_PIN2_Pos (2UL) /!< Position of PIN2 field. /
bogdanm	0:9b334a45a8ff	2470	#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /!< Bit mask of PIN2 field. /
bogdanm	0:9b334a45a8ff	2471	#define GPIO_DIRSET_PIN2_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2472	#define GPIO_DIRSET_PIN2_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2473	#define GPIO_DIRSET_PIN2_Set (1UL) /!< Set pin as output. /
bogdanm	0:9b334a45a8ff	2474
bogdanm	0:9b334a45a8ff	2475	/* Bit 1 : Set as output pin 1. */
bogdanm	0:9b334a45a8ff	2476	#define GPIO_DIRSET_PIN1_Pos (1UL) /!< Position of PIN1 field. /
bogdanm	0:9b334a45a8ff	2477	#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /!< Bit mask of PIN1 field. /
bogdanm	0:9b334a45a8ff	2478	#define GPIO_DIRSET_PIN1_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2479	#define GPIO_DIRSET_PIN1_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2480	#define GPIO_DIRSET_PIN1_Set (1UL) /!< Set pin as output. /
bogdanm	0:9b334a45a8ff	2481
bogdanm	0:9b334a45a8ff	2482	/* Bit 0 : Set as output pin 0. */
bogdanm	0:9b334a45a8ff	2483	#define GPIO_DIRSET_PIN0_Pos (0UL) /!< Position of PIN0 field. /
bogdanm	0:9b334a45a8ff	2484	#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /!< Bit mask of PIN0 field. /
bogdanm	0:9b334a45a8ff	2485	#define GPIO_DIRSET_PIN0_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2486	#define GPIO_DIRSET_PIN0_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2487	#define GPIO_DIRSET_PIN0_Set (1UL) /!< Set pin as output. /
bogdanm	0:9b334a45a8ff	2488
bogdanm	0:9b334a45a8ff	2489	/* Register: GPIO_DIRCLR */
bogdanm	0:9b334a45a8ff	2490	/* Description: DIR clear register. */
bogdanm	0:9b334a45a8ff	2491
bogdanm	0:9b334a45a8ff	2492	/* Bit 31 : Set as input pin 31. */
bogdanm	0:9b334a45a8ff	2493	#define GPIO_DIRCLR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
bogdanm	0:9b334a45a8ff	2494	#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /!< Bit mask of PIN31 field. /
bogdanm	0:9b334a45a8ff	2495	#define GPIO_DIRCLR_PIN31_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2496	#define GPIO_DIRCLR_PIN31_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2497	#define GPIO_DIRCLR_PIN31_Clear (1UL) /!< Set pin as input. /
bogdanm	0:9b334a45a8ff	2498
bogdanm	0:9b334a45a8ff	2499	/* Bit 30 : Set as input pin 30. */
bogdanm	0:9b334a45a8ff	2500	#define GPIO_DIRCLR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
bogdanm	0:9b334a45a8ff	2501	#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /!< Bit mask of PIN30 field. /
bogdanm	0:9b334a45a8ff	2502	#define GPIO_DIRCLR_PIN30_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2503	#define GPIO_DIRCLR_PIN30_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2504	#define GPIO_DIRCLR_PIN30_Clear (1UL) /!< Set pin as input. /
bogdanm	0:9b334a45a8ff	2505
bogdanm	0:9b334a45a8ff	2506	/* Bit 29 : Set as input pin 29. */
bogdanm	0:9b334a45a8ff	2507	#define GPIO_DIRCLR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
bogdanm	0:9b334a45a8ff	2508	#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /!< Bit mask of PIN29 field. /
bogdanm	0:9b334a45a8ff	2509	#define GPIO_DIRCLR_PIN29_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2510	#define GPIO_DIRCLR_PIN29_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2511	#define GPIO_DIRCLR_PIN29_Clear (1UL) /!< Set pin as input. /
bogdanm	0:9b334a45a8ff	2512
bogdanm	0:9b334a45a8ff	2513	/* Bit 28 : Set as input pin 28. */
bogdanm	0:9b334a45a8ff	2514	#define GPIO_DIRCLR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
bogdanm	0:9b334a45a8ff	2515	#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /!< Bit mask of PIN28 field. /
bogdanm	0:9b334a45a8ff	2516	#define GPIO_DIRCLR_PIN28_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2517	#define GPIO_DIRCLR_PIN28_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2518	#define GPIO_DIRCLR_PIN28_Clear (1UL) /!< Set pin as input. /
bogdanm	0:9b334a45a8ff	2519
bogdanm	0:9b334a45a8ff	2520	/* Bit 27 : Set as input pin 27. */
bogdanm	0:9b334a45a8ff	2521	#define GPIO_DIRCLR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
bogdanm	0:9b334a45a8ff	2522	#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /!< Bit mask of PIN27 field. /
bogdanm	0:9b334a45a8ff	2523	#define GPIO_DIRCLR_PIN27_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2524	#define GPIO_DIRCLR_PIN27_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2525	#define GPIO_DIRCLR_PIN27_Clear (1UL) /!< Set pin as input. /
bogdanm	0:9b334a45a8ff	2526
bogdanm	0:9b334a45a8ff	2527	/* Bit 26 : Set as input pin 26. */
bogdanm	0:9b334a45a8ff	2528	#define GPIO_DIRCLR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
bogdanm	0:9b334a45a8ff	2529	#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /!< Bit mask of PIN26 field. /
bogdanm	0:9b334a45a8ff	2530	#define GPIO_DIRCLR_PIN26_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2531	#define GPIO_DIRCLR_PIN26_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2532	#define GPIO_DIRCLR_PIN26_Clear (1UL) /!< Set pin as input. /
bogdanm	0:9b334a45a8ff	2533
bogdanm	0:9b334a45a8ff	2534	/* Bit 25 : Set as input pin 25. */
bogdanm	0:9b334a45a8ff	2535	#define GPIO_DIRCLR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
bogdanm	0:9b334a45a8ff	2536	#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /!< Bit mask of PIN25 field. /
bogdanm	0:9b334a45a8ff	2537	#define GPIO_DIRCLR_PIN25_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2538	#define GPIO_DIRCLR_PIN25_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2539	#define GPIO_DIRCLR_PIN25_Clear (1UL) /!< Set pin as input. /
bogdanm	0:9b334a45a8ff	2540
bogdanm	0:9b334a45a8ff	2541	/* Bit 24 : Set as input pin 24. */
bogdanm	0:9b334a45a8ff	2542	#define GPIO_DIRCLR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
bogdanm	0:9b334a45a8ff	2543	#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /!< Bit mask of PIN24 field. /
bogdanm	0:9b334a45a8ff	2544	#define GPIO_DIRCLR_PIN24_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2545	#define GPIO_DIRCLR_PIN24_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2546	#define GPIO_DIRCLR_PIN24_Clear (1UL) /!< Set pin as input. /
bogdanm	0:9b334a45a8ff	2547
bogdanm	0:9b334a45a8ff	2548	/* Bit 23 : Set as input pin 23. */
bogdanm	0:9b334a45a8ff	2549	#define GPIO_DIRCLR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
bogdanm	0:9b334a45a8ff	2550	#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /!< Bit mask of PIN23 field. /
bogdanm	0:9b334a45a8ff	2551	#define GPIO_DIRCLR_PIN23_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2552	#define GPIO_DIRCLR_PIN23_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2553	#define GPIO_DIRCLR_PIN23_Clear (1UL) /!< Set pin as input. /
bogdanm	0:9b334a45a8ff	2554
bogdanm	0:9b334a45a8ff	2555	/* Bit 22 : Set as input pin 22. */
bogdanm	0:9b334a45a8ff	2556	#define GPIO_DIRCLR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
bogdanm	0:9b334a45a8ff	2557	#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /!< Bit mask of PIN22 field. /
bogdanm	0:9b334a45a8ff	2558	#define GPIO_DIRCLR_PIN22_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2559	#define GPIO_DIRCLR_PIN22_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2560	#define GPIO_DIRCLR_PIN22_Clear (1UL) /!< Set pin as input. /
bogdanm	0:9b334a45a8ff	2561
bogdanm	0:9b334a45a8ff	2562	/* Bit 21 : Set as input pin 21. */
bogdanm	0:9b334a45a8ff	2563	#define GPIO_DIRCLR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
bogdanm	0:9b334a45a8ff	2564	#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /!< Bit mask of PIN21 field. /
bogdanm	0:9b334a45a8ff	2565	#define GPIO_DIRCLR_PIN21_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2566	#define GPIO_DIRCLR_PIN21_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2567	#define GPIO_DIRCLR_PIN21_Clear (1UL) /!< Set pin as input. /
bogdanm	0:9b334a45a8ff	2568
bogdanm	0:9b334a45a8ff	2569	/* Bit 20 : Set as input pin 20. */
bogdanm	0:9b334a45a8ff	2570	#define GPIO_DIRCLR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
bogdanm	0:9b334a45a8ff	2571	#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /!< Bit mask of PIN20 field. /
bogdanm	0:9b334a45a8ff	2572	#define GPIO_DIRCLR_PIN20_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2573	#define GPIO_DIRCLR_PIN20_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2574	#define GPIO_DIRCLR_PIN20_Clear (1UL) /!< Set pin as input. /
bogdanm	0:9b334a45a8ff	2575
bogdanm	0:9b334a45a8ff	2576	/* Bit 19 : Set as input pin 19. */
bogdanm	0:9b334a45a8ff	2577	#define GPIO_DIRCLR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
bogdanm	0:9b334a45a8ff	2578	#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /!< Bit mask of PIN19 field. /
bogdanm	0:9b334a45a8ff	2579	#define GPIO_DIRCLR_PIN19_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2580	#define GPIO_DIRCLR_PIN19_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2581	#define GPIO_DIRCLR_PIN19_Clear (1UL) /!< Set pin as input. /
bogdanm	0:9b334a45a8ff	2582
bogdanm	0:9b334a45a8ff	2583	/* Bit 18 : Set as input pin 18. */
bogdanm	0:9b334a45a8ff	2584	#define GPIO_DIRCLR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
bogdanm	0:9b334a45a8ff	2585	#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /!< Bit mask of PIN18 field. /
bogdanm	0:9b334a45a8ff	2586	#define GPIO_DIRCLR_PIN18_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2587	#define GPIO_DIRCLR_PIN18_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2588	#define GPIO_DIRCLR_PIN18_Clear (1UL) /!< Set pin as input. /
bogdanm	0:9b334a45a8ff	2589
bogdanm	0:9b334a45a8ff	2590	/* Bit 17 : Set as input pin 17. */
bogdanm	0:9b334a45a8ff	2591	#define GPIO_DIRCLR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
bogdanm	0:9b334a45a8ff	2592	#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /!< Bit mask of PIN17 field. /
bogdanm	0:9b334a45a8ff	2593	#define GPIO_DIRCLR_PIN17_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2594	#define GPIO_DIRCLR_PIN17_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2595	#define GPIO_DIRCLR_PIN17_Clear (1UL) /!< Set pin as input. /
bogdanm	0:9b334a45a8ff	2596
bogdanm	0:9b334a45a8ff	2597	/* Bit 16 : Set as input pin 16. */
bogdanm	0:9b334a45a8ff	2598	#define GPIO_DIRCLR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
bogdanm	0:9b334a45a8ff	2599	#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /!< Bit mask of PIN16 field. /
bogdanm	0:9b334a45a8ff	2600	#define GPIO_DIRCLR_PIN16_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2601	#define GPIO_DIRCLR_PIN16_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2602	#define GPIO_DIRCLR_PIN16_Clear (1UL) /!< Set pin as input. /
bogdanm	0:9b334a45a8ff	2603
bogdanm	0:9b334a45a8ff	2604	/* Bit 15 : Set as input pin 15. */
bogdanm	0:9b334a45a8ff	2605	#define GPIO_DIRCLR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
bogdanm	0:9b334a45a8ff	2606	#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /!< Bit mask of PIN15 field. /
bogdanm	0:9b334a45a8ff	2607	#define GPIO_DIRCLR_PIN15_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2608	#define GPIO_DIRCLR_PIN15_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2609	#define GPIO_DIRCLR_PIN15_Clear (1UL) /!< Set pin as input. /
bogdanm	0:9b334a45a8ff	2610
bogdanm	0:9b334a45a8ff	2611	/* Bit 14 : Set as input pin 14. */
bogdanm	0:9b334a45a8ff	2612	#define GPIO_DIRCLR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
bogdanm	0:9b334a45a8ff	2613	#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /!< Bit mask of PIN14 field. /
bogdanm	0:9b334a45a8ff	2614	#define GPIO_DIRCLR_PIN14_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2615	#define GPIO_DIRCLR_PIN14_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2616	#define GPIO_DIRCLR_PIN14_Clear (1UL) /!< Set pin as input. /
bogdanm	0:9b334a45a8ff	2617
bogdanm	0:9b334a45a8ff	2618	/* Bit 13 : Set as input pin 13. */
bogdanm	0:9b334a45a8ff	2619	#define GPIO_DIRCLR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
bogdanm	0:9b334a45a8ff	2620	#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /!< Bit mask of PIN13 field. /
bogdanm	0:9b334a45a8ff	2621	#define GPIO_DIRCLR_PIN13_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2622	#define GPIO_DIRCLR_PIN13_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2623	#define GPIO_DIRCLR_PIN13_Clear (1UL) /!< Set pin as input. /
bogdanm	0:9b334a45a8ff	2624
bogdanm	0:9b334a45a8ff	2625	/* Bit 12 : Set as input pin 12. */
bogdanm	0:9b334a45a8ff	2626	#define GPIO_DIRCLR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
bogdanm	0:9b334a45a8ff	2627	#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /!< Bit mask of PIN12 field. /
bogdanm	0:9b334a45a8ff	2628	#define GPIO_DIRCLR_PIN12_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2629	#define GPIO_DIRCLR_PIN12_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2630	#define GPIO_DIRCLR_PIN12_Clear (1UL) /!< Set pin as input. /
bogdanm	0:9b334a45a8ff	2631
bogdanm	0:9b334a45a8ff	2632	/* Bit 11 : Set as input pin 11. */
bogdanm	0:9b334a45a8ff	2633	#define GPIO_DIRCLR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
bogdanm	0:9b334a45a8ff	2634	#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /!< Bit mask of PIN11 field. /
bogdanm	0:9b334a45a8ff	2635	#define GPIO_DIRCLR_PIN11_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2636	#define GPIO_DIRCLR_PIN11_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2637	#define GPIO_DIRCLR_PIN11_Clear (1UL) /!< Set pin as input. /
bogdanm	0:9b334a45a8ff	2638
bogdanm	0:9b334a45a8ff	2639	/* Bit 10 : Set as input pin 10. */
bogdanm	0:9b334a45a8ff	2640	#define GPIO_DIRCLR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
bogdanm	0:9b334a45a8ff	2641	#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /!< Bit mask of PIN10 field. /
bogdanm	0:9b334a45a8ff	2642	#define GPIO_DIRCLR_PIN10_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2643	#define GPIO_DIRCLR_PIN10_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2644	#define GPIO_DIRCLR_PIN10_Clear (1UL) /!< Set pin as input. /
bogdanm	0:9b334a45a8ff	2645
bogdanm	0:9b334a45a8ff	2646	/* Bit 9 : Set as input pin 9. */
bogdanm	0:9b334a45a8ff	2647	#define GPIO_DIRCLR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
bogdanm	0:9b334a45a8ff	2648	#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /!< Bit mask of PIN9 field. /
bogdanm	0:9b334a45a8ff	2649	#define GPIO_DIRCLR_PIN9_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2650	#define GPIO_DIRCLR_PIN9_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2651	#define GPIO_DIRCLR_PIN9_Clear (1UL) /!< Set pin as input. /
bogdanm	0:9b334a45a8ff	2652
bogdanm	0:9b334a45a8ff	2653	/* Bit 8 : Set as input pin 8. */
bogdanm	0:9b334a45a8ff	2654	#define GPIO_DIRCLR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
bogdanm	0:9b334a45a8ff	2655	#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /!< Bit mask of PIN8 field. /
bogdanm	0:9b334a45a8ff	2656	#define GPIO_DIRCLR_PIN8_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2657	#define GPIO_DIRCLR_PIN8_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2658	#define GPIO_DIRCLR_PIN8_Clear (1UL) /!< Set pin as input. /
bogdanm	0:9b334a45a8ff	2659
bogdanm	0:9b334a45a8ff	2660	/* Bit 7 : Set as input pin 7. */
bogdanm	0:9b334a45a8ff	2661	#define GPIO_DIRCLR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
bogdanm	0:9b334a45a8ff	2662	#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /!< Bit mask of PIN7 field. /
bogdanm	0:9b334a45a8ff	2663	#define GPIO_DIRCLR_PIN7_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2664	#define GPIO_DIRCLR_PIN7_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2665	#define GPIO_DIRCLR_PIN7_Clear (1UL) /!< Set pin as input. /
bogdanm	0:9b334a45a8ff	2666
bogdanm	0:9b334a45a8ff	2667	/* Bit 6 : Set as input pin 6. */
bogdanm	0:9b334a45a8ff	2668	#define GPIO_DIRCLR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
bogdanm	0:9b334a45a8ff	2669	#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /!< Bit mask of PIN6 field. /
bogdanm	0:9b334a45a8ff	2670	#define GPIO_DIRCLR_PIN6_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2671	#define GPIO_DIRCLR_PIN6_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2672	#define GPIO_DIRCLR_PIN6_Clear (1UL) /!< Set pin as input. /
bogdanm	0:9b334a45a8ff	2673
bogdanm	0:9b334a45a8ff	2674	/* Bit 5 : Set as input pin 5. */
bogdanm	0:9b334a45a8ff	2675	#define GPIO_DIRCLR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
bogdanm	0:9b334a45a8ff	2676	#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /!< Bit mask of PIN5 field. /
bogdanm	0:9b334a45a8ff	2677	#define GPIO_DIRCLR_PIN5_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2678	#define GPIO_DIRCLR_PIN5_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2679	#define GPIO_DIRCLR_PIN5_Clear (1UL) /!< Set pin as input. /
bogdanm	0:9b334a45a8ff	2680
bogdanm	0:9b334a45a8ff	2681	/* Bit 4 : Set as input pin 4. */
bogdanm	0:9b334a45a8ff	2682	#define GPIO_DIRCLR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
bogdanm	0:9b334a45a8ff	2683	#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /!< Bit mask of PIN4 field. /
bogdanm	0:9b334a45a8ff	2684	#define GPIO_DIRCLR_PIN4_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2685	#define GPIO_DIRCLR_PIN4_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2686	#define GPIO_DIRCLR_PIN4_Clear (1UL) /!< Set pin as input. /
bogdanm	0:9b334a45a8ff	2687
bogdanm	0:9b334a45a8ff	2688	/* Bit 3 : Set as input pin 3. */
bogdanm	0:9b334a45a8ff	2689	#define GPIO_DIRCLR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
bogdanm	0:9b334a45a8ff	2690	#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /!< Bit mask of PIN3 field. /
bogdanm	0:9b334a45a8ff	2691	#define GPIO_DIRCLR_PIN3_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2692	#define GPIO_DIRCLR_PIN3_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2693	#define GPIO_DIRCLR_PIN3_Clear (1UL) /!< Set pin as input. /
bogdanm	0:9b334a45a8ff	2694
bogdanm	0:9b334a45a8ff	2695	/* Bit 2 : Set as input pin 2. */
bogdanm	0:9b334a45a8ff	2696	#define GPIO_DIRCLR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
bogdanm	0:9b334a45a8ff	2697	#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /!< Bit mask of PIN2 field. /
bogdanm	0:9b334a45a8ff	2698	#define GPIO_DIRCLR_PIN2_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2699	#define GPIO_DIRCLR_PIN2_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2700	#define GPIO_DIRCLR_PIN2_Clear (1UL) /!< Set pin as input. /
bogdanm	0:9b334a45a8ff	2701
bogdanm	0:9b334a45a8ff	2702	/* Bit 1 : Set as input pin 1. */
bogdanm	0:9b334a45a8ff	2703	#define GPIO_DIRCLR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
bogdanm	0:9b334a45a8ff	2704	#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /!< Bit mask of PIN1 field. /
bogdanm	0:9b334a45a8ff	2705	#define GPIO_DIRCLR_PIN1_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2706	#define GPIO_DIRCLR_PIN1_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2707	#define GPIO_DIRCLR_PIN1_Clear (1UL) /!< Set pin as input. /
bogdanm	0:9b334a45a8ff	2708
bogdanm	0:9b334a45a8ff	2709	/* Bit 0 : Set as input pin 0. */
bogdanm	0:9b334a45a8ff	2710	#define GPIO_DIRCLR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
bogdanm	0:9b334a45a8ff	2711	#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /!< Bit mask of PIN0 field. /
bogdanm	0:9b334a45a8ff	2712	#define GPIO_DIRCLR_PIN0_Input (0UL) /!< Pin set as input. /
bogdanm	0:9b334a45a8ff	2713	#define GPIO_DIRCLR_PIN0_Output (1UL) /!< Pin set as output. /
bogdanm	0:9b334a45a8ff	2714	#define GPIO_DIRCLR_PIN0_Clear (1UL) /!< Set pin as input. /
bogdanm	0:9b334a45a8ff	2715
bogdanm	0:9b334a45a8ff	2716	/* Register: GPIO_PIN_CNF */
bogdanm	0:9b334a45a8ff	2717	/* Description: Configuration of GPIO pins. */
bogdanm	0:9b334a45a8ff	2718
bogdanm	0:9b334a45a8ff	2719	/* Bits 17..16 : Pin sensing mechanism. */
bogdanm	0:9b334a45a8ff	2720	#define GPIO_PIN_CNF_SENSE_Pos (16UL) /!< Position of SENSE field. /
bogdanm	0:9b334a45a8ff	2721	#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /!< Bit mask of SENSE field. /
bogdanm	0:9b334a45a8ff	2722	#define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /!< Disabled. /
bogdanm	0:9b334a45a8ff	2723	#define GPIO_PIN_CNF_SENSE_High (0x02UL) /!< Wakeup on high level. /
bogdanm	0:9b334a45a8ff	2724	#define GPIO_PIN_CNF_SENSE_Low (0x03UL) /!< Wakeup on low level. /
bogdanm	0:9b334a45a8ff	2725
bogdanm	0:9b334a45a8ff	2726	/* Bits 10..8 : Drive configuration. */
bogdanm	0:9b334a45a8ff	2727	#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /!< Position of DRIVE field. /
bogdanm	0:9b334a45a8ff	2728	#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /!< Bit mask of DRIVE field. /
bogdanm	0:9b334a45a8ff	2729	#define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /!< Standard '0', Standard '1'. /
bogdanm	0:9b334a45a8ff	2730	#define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /!< High '0', Standard '1'. /
bogdanm	0:9b334a45a8ff	2731	#define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /!< Standard '0', High '1'. /
bogdanm	0:9b334a45a8ff	2732	#define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /!< High '0', High '1'. /
bogdanm	0:9b334a45a8ff	2733	#define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /!< Disconnected '0', Standard '1'. /
bogdanm	0:9b334a45a8ff	2734	#define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /!< Disconnected '0', High '1'. /
bogdanm	0:9b334a45a8ff	2735	#define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /!< Standard '0', Disconnected '1'. /
bogdanm	0:9b334a45a8ff	2736	#define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /!< High '0', Disconnected '1'. /
bogdanm	0:9b334a45a8ff	2737
bogdanm	0:9b334a45a8ff	2738	/* Bits 3..2 : Pull-up or -down configuration. */
bogdanm	0:9b334a45a8ff	2739	#define GPIO_PIN_CNF_PULL_Pos (2UL) /!< Position of PULL field. /
bogdanm	0:9b334a45a8ff	2740	#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /!< Bit mask of PULL field. /
bogdanm	0:9b334a45a8ff	2741	#define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /!< No pull. /
bogdanm	0:9b334a45a8ff	2742	#define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /!< Pulldown on pin. /
bogdanm	0:9b334a45a8ff	2743	#define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /!< Pullup on pin. /
bogdanm	0:9b334a45a8ff	2744
bogdanm	0:9b334a45a8ff	2745	/* Bit 1 : Connect or disconnect input path. */
bogdanm	0:9b334a45a8ff	2746	#define GPIO_PIN_CNF_INPUT_Pos (1UL) /!< Position of INPUT field. /
bogdanm	0:9b334a45a8ff	2747	#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /!< Bit mask of INPUT field. /
bogdanm	0:9b334a45a8ff	2748	#define GPIO_PIN_CNF_INPUT_Connect (0UL) /!< Connect input pin. /
bogdanm	0:9b334a45a8ff	2749	#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /!< Disconnect input pin. /
bogdanm	0:9b334a45a8ff	2750
bogdanm	0:9b334a45a8ff	2751	/* Bit 0 : Pin direction. */
bogdanm	0:9b334a45a8ff	2752	#define GPIO_PIN_CNF_DIR_Pos (0UL) /!< Position of DIR field. /
bogdanm	0:9b334a45a8ff	2753	#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /!< Bit mask of DIR field. /
bogdanm	0:9b334a45a8ff	2754	#define GPIO_PIN_CNF_DIR_Input (0UL) /!< Configure pin as an input pin. /
bogdanm	0:9b334a45a8ff	2755	#define GPIO_PIN_CNF_DIR_Output (1UL) /!< Configure pin as an output pin. /
bogdanm	0:9b334a45a8ff	2756
bogdanm	0:9b334a45a8ff	2757
bogdanm	0:9b334a45a8ff	2758	/* Peripheral: GPIOTE */
bogdanm	0:9b334a45a8ff	2759	/* Description: GPIO tasks and events. */
bogdanm	0:9b334a45a8ff	2760
bogdanm	0:9b334a45a8ff	2761	/* Register: GPIOTE_INTENSET */
bogdanm	0:9b334a45a8ff	2762	/* Description: Interrupt enable set register. */
bogdanm	0:9b334a45a8ff	2763
bogdanm	0:9b334a45a8ff	2764	/* Bit 31 : Enable interrupt on PORT event. */
bogdanm	0:9b334a45a8ff	2765	#define GPIOTE_INTENSET_PORT_Pos (31UL) /!< Position of PORT field. /
bogdanm	0:9b334a45a8ff	2766	#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /!< Bit mask of PORT field. /
bogdanm	0:9b334a45a8ff	2767	#define GPIOTE_INTENSET_PORT_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	2768	#define GPIOTE_INTENSET_PORT_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	2769	#define GPIOTE_INTENSET_PORT_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	2770
bogdanm	0:9b334a45a8ff	2771	/* Bit 3 : Enable interrupt on IN[3] event. */
bogdanm	0:9b334a45a8ff	2772	#define GPIOTE_INTENSET_IN3_Pos (3UL) /!< Position of IN3 field. /
bogdanm	0:9b334a45a8ff	2773	#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /!< Bit mask of IN3 field. /
bogdanm	0:9b334a45a8ff	2774	#define GPIOTE_INTENSET_IN3_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	2775	#define GPIOTE_INTENSET_IN3_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	2776	#define GPIOTE_INTENSET_IN3_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	2777
bogdanm	0:9b334a45a8ff	2778	/* Bit 2 : Enable interrupt on IN[2] event. */
bogdanm	0:9b334a45a8ff	2779	#define GPIOTE_INTENSET_IN2_Pos (2UL) /!< Position of IN2 field. /
bogdanm	0:9b334a45a8ff	2780	#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /!< Bit mask of IN2 field. /
bogdanm	0:9b334a45a8ff	2781	#define GPIOTE_INTENSET_IN2_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	2782	#define GPIOTE_INTENSET_IN2_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	2783	#define GPIOTE_INTENSET_IN2_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	2784
bogdanm	0:9b334a45a8ff	2785	/* Bit 1 : Enable interrupt on IN[1] event. */
bogdanm	0:9b334a45a8ff	2786	#define GPIOTE_INTENSET_IN1_Pos (1UL) /!< Position of IN1 field. /
bogdanm	0:9b334a45a8ff	2787	#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /!< Bit mask of IN1 field. /
bogdanm	0:9b334a45a8ff	2788	#define GPIOTE_INTENSET_IN1_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	2789	#define GPIOTE_INTENSET_IN1_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	2790	#define GPIOTE_INTENSET_IN1_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	2791
bogdanm	0:9b334a45a8ff	2792	/* Bit 0 : Enable interrupt on IN[0] event. */
bogdanm	0:9b334a45a8ff	2793	#define GPIOTE_INTENSET_IN0_Pos (0UL) /!< Position of IN0 field. /
bogdanm	0:9b334a45a8ff	2794	#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /!< Bit mask of IN0 field. /
bogdanm	0:9b334a45a8ff	2795	#define GPIOTE_INTENSET_IN0_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	2796	#define GPIOTE_INTENSET_IN0_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	2797	#define GPIOTE_INTENSET_IN0_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	2798
bogdanm	0:9b334a45a8ff	2799	/* Register: GPIOTE_INTENCLR */
bogdanm	0:9b334a45a8ff	2800	/* Description: Interrupt enable clear register. */
bogdanm	0:9b334a45a8ff	2801
bogdanm	0:9b334a45a8ff	2802	/* Bit 31 : Disable interrupt on PORT event. */
bogdanm	0:9b334a45a8ff	2803	#define GPIOTE_INTENCLR_PORT_Pos (31UL) /!< Position of PORT field. /
bogdanm	0:9b334a45a8ff	2804	#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /!< Bit mask of PORT field. /
bogdanm	0:9b334a45a8ff	2805	#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	2806	#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	2807	#define GPIOTE_INTENCLR_PORT_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	2808
bogdanm	0:9b334a45a8ff	2809	/* Bit 3 : Disable interrupt on IN[3] event. */
bogdanm	0:9b334a45a8ff	2810	#define GPIOTE_INTENCLR_IN3_Pos (3UL) /!< Position of IN3 field. /
bogdanm	0:9b334a45a8ff	2811	#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /!< Bit mask of IN3 field. /
bogdanm	0:9b334a45a8ff	2812	#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	2813	#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	2814	#define GPIOTE_INTENCLR_IN3_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	2815
bogdanm	0:9b334a45a8ff	2816	/* Bit 2 : Disable interrupt on IN[2] event. */
bogdanm	0:9b334a45a8ff	2817	#define GPIOTE_INTENCLR_IN2_Pos (2UL) /!< Position of IN2 field. /
bogdanm	0:9b334a45a8ff	2818	#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /!< Bit mask of IN2 field. /
bogdanm	0:9b334a45a8ff	2819	#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	2820	#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	2821	#define GPIOTE_INTENCLR_IN2_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	2822
bogdanm	0:9b334a45a8ff	2823	/* Bit 1 : Disable interrupt on IN[1] event. */
bogdanm	0:9b334a45a8ff	2824	#define GPIOTE_INTENCLR_IN1_Pos (1UL) /!< Position of IN1 field. /
bogdanm	0:9b334a45a8ff	2825	#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /!< Bit mask of IN1 field. /
bogdanm	0:9b334a45a8ff	2826	#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	2827	#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	2828	#define GPIOTE_INTENCLR_IN1_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	2829
bogdanm	0:9b334a45a8ff	2830	/* Bit 0 : Disable interrupt on IN[0] event. */
bogdanm	0:9b334a45a8ff	2831	#define GPIOTE_INTENCLR_IN0_Pos (0UL) /!< Position of IN0 field. /
bogdanm	0:9b334a45a8ff	2832	#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /!< Bit mask of IN0 field. /
bogdanm	0:9b334a45a8ff	2833	#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	2834	#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	2835	#define GPIOTE_INTENCLR_IN0_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	2836
bogdanm	0:9b334a45a8ff	2837	/* Register: GPIOTE_CONFIG */
bogdanm	0:9b334a45a8ff	2838	/* Description: Channel configuration registers. */
bogdanm	0:9b334a45a8ff	2839
bogdanm	0:9b334a45a8ff	2840	/* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */
bogdanm	0:9b334a45a8ff	2841	#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /!< Position of OUTINIT field. /
bogdanm	0:9b334a45a8ff	2842	#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /!< Bit mask of OUTINIT field. /
bogdanm	0:9b334a45a8ff	2843	#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /!< Initial low output when in task mode. /
bogdanm	0:9b334a45a8ff	2844	#define GPIOTE_CONFIG_OUTINIT_High (1UL) /!< Initial high output when in task mode. /
bogdanm	0:9b334a45a8ff	2845
bogdanm	0:9b334a45a8ff	2846	/* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */
bogdanm	0:9b334a45a8ff	2847	#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /!< Position of POLARITY field. /
bogdanm	0:9b334a45a8ff	2848	#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /!< Bit mask of POLARITY field. /
bogdanm	0:9b334a45a8ff	2849	#define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /!< Low to high. /
bogdanm	0:9b334a45a8ff	2850	#define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /!< High to low. /
bogdanm	0:9b334a45a8ff	2851	#define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /!< Toggle. /
bogdanm	0:9b334a45a8ff	2852
bogdanm	0:9b334a45a8ff	2853	/* Bits 12..8 : Pin select. */
bogdanm	0:9b334a45a8ff	2854	#define GPIOTE_CONFIG_PSEL_Pos (8UL) /!< Position of PSEL field. /
bogdanm	0:9b334a45a8ff	2855	#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /!< Bit mask of PSEL field. /
bogdanm	0:9b334a45a8ff	2856
bogdanm	0:9b334a45a8ff	2857	/* Bits 1..0 : Mode */
bogdanm	0:9b334a45a8ff	2858	#define GPIOTE_CONFIG_MODE_Pos (0UL) /!< Position of MODE field. /
bogdanm	0:9b334a45a8ff	2859	#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /!< Bit mask of MODE field. /
bogdanm	0:9b334a45a8ff	2860	#define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /!< Disabled. /
bogdanm	0:9b334a45a8ff	2861	#define GPIOTE_CONFIG_MODE_Event (0x01UL) /!< Channel configure in event mode. /
bogdanm	0:9b334a45a8ff	2862	#define GPIOTE_CONFIG_MODE_Task (0x03UL) /!< Channel configure in task mode. /
bogdanm	0:9b334a45a8ff	2863
bogdanm	0:9b334a45a8ff	2864	/* Register: GPIOTE_POWER */
bogdanm	0:9b334a45a8ff	2865	/* Description: Peripheral power control. */
bogdanm	0:9b334a45a8ff	2866
bogdanm	0:9b334a45a8ff	2867	/* Bit 0 : Peripheral power control. */
bogdanm	0:9b334a45a8ff	2868	#define GPIOTE_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	0:9b334a45a8ff	2869	#define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	0:9b334a45a8ff	2870	#define GPIOTE_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	0:9b334a45a8ff	2871	#define GPIOTE_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	0:9b334a45a8ff	2872
bogdanm	0:9b334a45a8ff	2873
bogdanm	0:9b334a45a8ff	2874	/* Peripheral: LPCOMP */
bogdanm	0:9b334a45a8ff	2875	/* Description: Low power comparator. */
bogdanm	0:9b334a45a8ff	2876
bogdanm	0:9b334a45a8ff	2877	/* Register: LPCOMP_SHORTS */
bogdanm	0:9b334a45a8ff	2878	/* Description: Shortcuts for the LPCOMP. */
bogdanm	0:9b334a45a8ff	2879
bogdanm	0:9b334a45a8ff	2880	/* Bit 4 : Shortcut between CROSS event and STOP task. */
bogdanm	0:9b334a45a8ff	2881	#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /!< Position of CROSS_STOP field. /
bogdanm	0:9b334a45a8ff	2882	#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /!< Bit mask of CROSS_STOP field. /
bogdanm	0:9b334a45a8ff	2883	#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	0:9b334a45a8ff	2884	#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	0:9b334a45a8ff	2885
bogdanm	0:9b334a45a8ff	2886	/* Bit 3 : Shortcut between UP event and STOP task. */
bogdanm	0:9b334a45a8ff	2887	#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /!< Position of UP_STOP field. /
bogdanm	0:9b334a45a8ff	2888	#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /!< Bit mask of UP_STOP field. /
bogdanm	0:9b334a45a8ff	2889	#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	0:9b334a45a8ff	2890	#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	0:9b334a45a8ff	2891
bogdanm	0:9b334a45a8ff	2892	/* Bit 2 : Shortcut between DOWN event and STOP task. */
bogdanm	0:9b334a45a8ff	2893	#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /!< Position of DOWN_STOP field. /
bogdanm	0:9b334a45a8ff	2894	#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /!< Bit mask of DOWN_STOP field. /
bogdanm	0:9b334a45a8ff	2895	#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	0:9b334a45a8ff	2896	#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	0:9b334a45a8ff	2897
bogdanm	0:9b334a45a8ff	2898	/* Bit 1 : Shortcut between RADY event and STOP task. */
bogdanm	0:9b334a45a8ff	2899	#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /!< Position of READY_STOP field. /
bogdanm	0:9b334a45a8ff	2900	#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /!< Bit mask of READY_STOP field. /
bogdanm	0:9b334a45a8ff	2901	#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	0:9b334a45a8ff	2902	#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	0:9b334a45a8ff	2903
bogdanm	0:9b334a45a8ff	2904	/* Bit 0 : Shortcut between READY event and SAMPLE task. */
bogdanm	0:9b334a45a8ff	2905	#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /!< Position of READY_SAMPLE field. /
bogdanm	0:9b334a45a8ff	2906	#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /!< Bit mask of READY_SAMPLE field. /
bogdanm	0:9b334a45a8ff	2907	#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	0:9b334a45a8ff	2908	#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	0:9b334a45a8ff	2909
bogdanm	0:9b334a45a8ff	2910	/* Register: LPCOMP_INTENSET */
bogdanm	0:9b334a45a8ff	2911	/* Description: Interrupt enable set register. */
bogdanm	0:9b334a45a8ff	2912
bogdanm	0:9b334a45a8ff	2913	/* Bit 3 : Enable interrupt on CROSS event. */
bogdanm	0:9b334a45a8ff	2914	#define LPCOMP_INTENSET_CROSS_Pos (3UL) /!< Position of CROSS field. /
bogdanm	0:9b334a45a8ff	2915	#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /!< Bit mask of CROSS field. /
bogdanm	0:9b334a45a8ff	2916	#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	2917	#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	2918	#define LPCOMP_INTENSET_CROSS_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	2919
bogdanm	0:9b334a45a8ff	2920	/* Bit 2 : Enable interrupt on UP event. */
bogdanm	0:9b334a45a8ff	2921	#define LPCOMP_INTENSET_UP_Pos (2UL) /!< Position of UP field. /
bogdanm	0:9b334a45a8ff	2922	#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /!< Bit mask of UP field. /
bogdanm	0:9b334a45a8ff	2923	#define LPCOMP_INTENSET_UP_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	2924	#define LPCOMP_INTENSET_UP_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	2925	#define LPCOMP_INTENSET_UP_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	2926
bogdanm	0:9b334a45a8ff	2927	/* Bit 1 : Enable interrupt on DOWN event. */
bogdanm	0:9b334a45a8ff	2928	#define LPCOMP_INTENSET_DOWN_Pos (1UL) /!< Position of DOWN field. /
bogdanm	0:9b334a45a8ff	2929	#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /!< Bit mask of DOWN field. /
bogdanm	0:9b334a45a8ff	2930	#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	2931	#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	2932	#define LPCOMP_INTENSET_DOWN_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	2933
bogdanm	0:9b334a45a8ff	2934	/* Bit 0 : Enable interrupt on READY event. */
bogdanm	0:9b334a45a8ff	2935	#define LPCOMP_INTENSET_READY_Pos (0UL) /!< Position of READY field. /
bogdanm	0:9b334a45a8ff	2936	#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /!< Bit mask of READY field. /
bogdanm	0:9b334a45a8ff	2937	#define LPCOMP_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	2938	#define LPCOMP_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	2939	#define LPCOMP_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	2940
bogdanm	0:9b334a45a8ff	2941	/* Register: LPCOMP_INTENCLR */
bogdanm	0:9b334a45a8ff	2942	/* Description: Interrupt enable clear register. */
bogdanm	0:9b334a45a8ff	2943
bogdanm	0:9b334a45a8ff	2944	/* Bit 3 : Disable interrupt on CROSS event. */
bogdanm	0:9b334a45a8ff	2945	#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /!< Position of CROSS field. /
bogdanm	0:9b334a45a8ff	2946	#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /!< Bit mask of CROSS field. /
bogdanm	0:9b334a45a8ff	2947	#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	2948	#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	2949	#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	2950
bogdanm	0:9b334a45a8ff	2951	/* Bit 2 : Disable interrupt on UP event. */
bogdanm	0:9b334a45a8ff	2952	#define LPCOMP_INTENCLR_UP_Pos (2UL) /!< Position of UP field. /
bogdanm	0:9b334a45a8ff	2953	#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /!< Bit mask of UP field. /
bogdanm	0:9b334a45a8ff	2954	#define LPCOMP_INTENCLR_UP_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	2955	#define LPCOMP_INTENCLR_UP_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	2956	#define LPCOMP_INTENCLR_UP_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	2957
bogdanm	0:9b334a45a8ff	2958	/* Bit 1 : Disable interrupt on DOWN event. */
bogdanm	0:9b334a45a8ff	2959	#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /!< Position of DOWN field. /
bogdanm	0:9b334a45a8ff	2960	#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /!< Bit mask of DOWN field. /
bogdanm	0:9b334a45a8ff	2961	#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	2962	#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	2963	#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	2964
bogdanm	0:9b334a45a8ff	2965	/* Bit 0 : Disable interrupt on READY event. */
bogdanm	0:9b334a45a8ff	2966	#define LPCOMP_INTENCLR_READY_Pos (0UL) /!< Position of READY field. /
bogdanm	0:9b334a45a8ff	2967	#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
bogdanm	0:9b334a45a8ff	2968	#define LPCOMP_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	2969	#define LPCOMP_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	2970	#define LPCOMP_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	2971
bogdanm	0:9b334a45a8ff	2972	/* Register: LPCOMP_RESULT */
bogdanm	0:9b334a45a8ff	2973	/* Description: Result of last compare. */
bogdanm	0:9b334a45a8ff	2974
bogdanm	0:9b334a45a8ff	2975	/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
bogdanm	0:9b334a45a8ff	2976	#define LPCOMP_RESULT_RESULT_Pos (0UL) /!< Position of RESULT field. /
bogdanm	0:9b334a45a8ff	2977	#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /!< Bit mask of RESULT field. /
bogdanm	0:9b334a45a8ff	2978	#define LPCOMP_RESULT_RESULT_Bellow (0UL) /!< Input voltage is bellow the reference threshold. /
bogdanm	0:9b334a45a8ff	2979	#define LPCOMP_RESULT_RESULT_Above (1UL) /!< Input voltage is above the reference threshold. /
bogdanm	0:9b334a45a8ff	2980
bogdanm	0:9b334a45a8ff	2981	/* Register: LPCOMP_ENABLE */
bogdanm	0:9b334a45a8ff	2982	/* Description: Enable the LPCOMP. */
bogdanm	0:9b334a45a8ff	2983
bogdanm	0:9b334a45a8ff	2984	/* Bits 1..0 : Enable or disable LPCOMP. */
bogdanm	0:9b334a45a8ff	2985	#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
bogdanm	0:9b334a45a8ff	2986	#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
bogdanm	0:9b334a45a8ff	2987	#define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled LPCOMP. /
bogdanm	0:9b334a45a8ff	2988	#define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /!< Enable LPCOMP. /
bogdanm	0:9b334a45a8ff	2989
bogdanm	0:9b334a45a8ff	2990	/* Register: LPCOMP_PSEL */
bogdanm	0:9b334a45a8ff	2991	/* Description: Input pin select. */
bogdanm	0:9b334a45a8ff	2992
bogdanm	0:9b334a45a8ff	2993	/* Bits 2..0 : Analog input pin select. */
bogdanm	0:9b334a45a8ff	2994	#define LPCOMP_PSEL_PSEL_Pos (0UL) /!< Position of PSEL field. /
bogdanm	0:9b334a45a8ff	2995	#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /!< Bit mask of PSEL field. /
bogdanm	0:9b334a45a8ff	2996	#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /!< Use analog input 0 as analog input. /
bogdanm	0:9b334a45a8ff	2997	#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /!< Use analog input 1 as analog input. /
bogdanm	0:9b334a45a8ff	2998	#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /!< Use analog input 2 as analog input. /
bogdanm	0:9b334a45a8ff	2999	#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /!< Use analog input 3 as analog input. /
bogdanm	0:9b334a45a8ff	3000	#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /!< Use analog input 4 as analog input. /
bogdanm	0:9b334a45a8ff	3001	#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /!< Use analog input 5 as analog input. /
bogdanm	0:9b334a45a8ff	3002	#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /!< Use analog input 6 as analog input. /
bogdanm	0:9b334a45a8ff	3003	#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /!< Use analog input 7 as analog input. /
bogdanm	0:9b334a45a8ff	3004
bogdanm	0:9b334a45a8ff	3005	/* Register: LPCOMP_REFSEL */
bogdanm	0:9b334a45a8ff	3006	/* Description: Reference select. */
bogdanm	0:9b334a45a8ff	3007
bogdanm	0:9b334a45a8ff	3008	/* Bits 2..0 : Reference select. */
bogdanm	0:9b334a45a8ff	3009	#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /!< Position of REFSEL field. /
bogdanm	0:9b334a45a8ff	3010	#define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /!< Bit mask of REFSEL field. /
bogdanm	0:9b334a45a8ff	3011	#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /!< Use supply with a 1/8 prescaler as reference. /
bogdanm	0:9b334a45a8ff	3012	#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /!< Use supply with a 2/8 prescaler as reference. /
bogdanm	0:9b334a45a8ff	3013	#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /!< Use supply with a 3/8 prescaler as reference. /
bogdanm	0:9b334a45a8ff	3014	#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /!< Use supply with a 4/8 prescaler as reference. /
bogdanm	0:9b334a45a8ff	3015	#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /!< Use supply with a 5/8 prescaler as reference. /
bogdanm	0:9b334a45a8ff	3016	#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /!< Use supply with a 6/8 prescaler as reference. /
bogdanm	0:9b334a45a8ff	3017	#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /!< Use supply with a 7/8 prescaler as reference. /
bogdanm	0:9b334a45a8ff	3018	#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /!< Use external analog reference as reference. /
bogdanm	0:9b334a45a8ff	3019
bogdanm	0:9b334a45a8ff	3020	/* Register: LPCOMP_EXTREFSEL */
bogdanm	0:9b334a45a8ff	3021	/* Description: External reference select. */
bogdanm	0:9b334a45a8ff	3022
bogdanm	0:9b334a45a8ff	3023	/* Bit 0 : External analog reference pin selection. */
bogdanm	0:9b334a45a8ff	3024	#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /!< Position of EXTREFSEL field. /
bogdanm	0:9b334a45a8ff	3025	#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /!< Bit mask of EXTREFSEL field. /
bogdanm	0:9b334a45a8ff	3026	#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /!< Use analog reference 0 as reference. /
bogdanm	0:9b334a45a8ff	3027	#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /!< Use analog reference 1 as reference. /
bogdanm	0:9b334a45a8ff	3028
bogdanm	0:9b334a45a8ff	3029	/* Register: LPCOMP_ANADETECT */
bogdanm	0:9b334a45a8ff	3030	/* Description: Analog detect configuration. */
bogdanm	0:9b334a45a8ff	3031
bogdanm	0:9b334a45a8ff	3032	/* Bits 1..0 : Analog detect configuration. */
bogdanm	0:9b334a45a8ff	3033	#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /!< Position of ANADETECT field. /
bogdanm	0:9b334a45a8ff	3034	#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /!< Bit mask of ANADETECT field. /
bogdanm	0:9b334a45a8ff	3035	#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /!< Generate ANADETEC on crossing, both upwards and downwards crossing. /
bogdanm	0:9b334a45a8ff	3036	#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /!< Generate ANADETEC on upwards crossing only. /
bogdanm	0:9b334a45a8ff	3037	#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /!< Generate ANADETEC on downwards crossing only. /
bogdanm	0:9b334a45a8ff	3038
bogdanm	0:9b334a45a8ff	3039	/* Register: LPCOMP_POWER */
bogdanm	0:9b334a45a8ff	3040	/* Description: Peripheral power control. */
bogdanm	0:9b334a45a8ff	3041
bogdanm	0:9b334a45a8ff	3042	/* Bit 0 : Peripheral power control. */
bogdanm	0:9b334a45a8ff	3043	#define LPCOMP_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	0:9b334a45a8ff	3044	#define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	0:9b334a45a8ff	3045	#define LPCOMP_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	0:9b334a45a8ff	3046	#define LPCOMP_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	0:9b334a45a8ff	3047
bogdanm	0:9b334a45a8ff	3048
bogdanm	0:9b334a45a8ff	3049	/* Peripheral: MPU */
bogdanm	0:9b334a45a8ff	3050	/* Description: Memory Protection Unit. */
bogdanm	0:9b334a45a8ff	3051
bogdanm	0:9b334a45a8ff	3052	/* Register: MPU_PERR0 */
bogdanm	0:9b334a45a8ff	3053	/* Description: Configuration of peripherals in mpu regions. */
bogdanm	0:9b334a45a8ff	3054
bogdanm	0:9b334a45a8ff	3055	/* Bit 31 : PPI region configuration. */
bogdanm	0:9b334a45a8ff	3056	#define MPU_PERR0_PPI_Pos (31UL) /!< Position of PPI field. /
bogdanm	0:9b334a45a8ff	3057	#define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /!< Bit mask of PPI field. /
bogdanm	0:9b334a45a8ff	3058	#define MPU_PERR0_PPI_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	0:9b334a45a8ff	3059	#define MPU_PERR0_PPI_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	0:9b334a45a8ff	3060
bogdanm	0:9b334a45a8ff	3061	/* Bit 30 : NVMC region configuration. */
bogdanm	0:9b334a45a8ff	3062	#define MPU_PERR0_NVMC_Pos (30UL) /!< Position of NVMC field. /
bogdanm	0:9b334a45a8ff	3063	#define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /!< Bit mask of NVMC field. /
bogdanm	0:9b334a45a8ff	3064	#define MPU_PERR0_NVMC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	0:9b334a45a8ff	3065	#define MPU_PERR0_NVMC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	0:9b334a45a8ff	3066
bogdanm	0:9b334a45a8ff	3067	/* Bit 19 : LPCOMP region configuration. */
bogdanm	0:9b334a45a8ff	3068	#define MPU_PERR0_LPCOMP_Pos (19UL) /!< Position of LPCOMP field. /
bogdanm	0:9b334a45a8ff	3069	#define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /!< Bit mask of LPCOMP field. /
bogdanm	0:9b334a45a8ff	3070	#define MPU_PERR0_LPCOMP_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	0:9b334a45a8ff	3071	#define MPU_PERR0_LPCOMP_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	0:9b334a45a8ff	3072
bogdanm	0:9b334a45a8ff	3073	/* Bit 18 : QDEC region configuration. */
bogdanm	0:9b334a45a8ff	3074	#define MPU_PERR0_QDEC_Pos (18UL) /!< Position of QDEC field. /
bogdanm	0:9b334a45a8ff	3075	#define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /!< Bit mask of QDEC field. /
bogdanm	0:9b334a45a8ff	3076	#define MPU_PERR0_QDEC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	0:9b334a45a8ff	3077	#define MPU_PERR0_QDEC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	0:9b334a45a8ff	3078
bogdanm	0:9b334a45a8ff	3079	/* Bit 17 : RTC1 region configuration. */
bogdanm	0:9b334a45a8ff	3080	#define MPU_PERR0_RTC1_Pos (17UL) /!< Position of RTC1 field. /
bogdanm	0:9b334a45a8ff	3081	#define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /!< Bit mask of RTC1 field. /
bogdanm	0:9b334a45a8ff	3082	#define MPU_PERR0_RTC1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	0:9b334a45a8ff	3083	#define MPU_PERR0_RTC1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	0:9b334a45a8ff	3084
bogdanm	0:9b334a45a8ff	3085	/* Bit 16 : WDT region configuration. */
bogdanm	0:9b334a45a8ff	3086	#define MPU_PERR0_WDT_Pos (16UL) /!< Position of WDT field. /
bogdanm	0:9b334a45a8ff	3087	#define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /!< Bit mask of WDT field. /
bogdanm	0:9b334a45a8ff	3088	#define MPU_PERR0_WDT_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	0:9b334a45a8ff	3089	#define MPU_PERR0_WDT_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	0:9b334a45a8ff	3090
bogdanm	0:9b334a45a8ff	3091	/* Bit 15 : CCM and AAR region configuration. */
bogdanm	0:9b334a45a8ff	3092	#define MPU_PERR0_CCM_AAR_Pos (15UL) /!< Position of CCM_AAR field. /
bogdanm	0:9b334a45a8ff	3093	#define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /!< Bit mask of CCM_AAR field. /
bogdanm	0:9b334a45a8ff	3094	#define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	0:9b334a45a8ff	3095	#define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	0:9b334a45a8ff	3096
bogdanm	0:9b334a45a8ff	3097	/* Bit 14 : ECB region configuration. */
bogdanm	0:9b334a45a8ff	3098	#define MPU_PERR0_ECB_Pos (14UL) /!< Position of ECB field. /
bogdanm	0:9b334a45a8ff	3099	#define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /!< Bit mask of ECB field. /
bogdanm	0:9b334a45a8ff	3100	#define MPU_PERR0_ECB_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	0:9b334a45a8ff	3101	#define MPU_PERR0_ECB_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	0:9b334a45a8ff	3102
bogdanm	0:9b334a45a8ff	3103	/* Bit 13 : RNG region configuration. */
bogdanm	0:9b334a45a8ff	3104	#define MPU_PERR0_RNG_Pos (13UL) /!< Position of RNG field. /
bogdanm	0:9b334a45a8ff	3105	#define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /!< Bit mask of RNG field. /
bogdanm	0:9b334a45a8ff	3106	#define MPU_PERR0_RNG_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	0:9b334a45a8ff	3107	#define MPU_PERR0_RNG_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	0:9b334a45a8ff	3108
bogdanm	0:9b334a45a8ff	3109	/* Bit 12 : TEMP region configuration. */
bogdanm	0:9b334a45a8ff	3110	#define MPU_PERR0_TEMP_Pos (12UL) /!< Position of TEMP field. /
bogdanm	0:9b334a45a8ff	3111	#define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /!< Bit mask of TEMP field. /
bogdanm	0:9b334a45a8ff	3112	#define MPU_PERR0_TEMP_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	0:9b334a45a8ff	3113	#define MPU_PERR0_TEMP_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	0:9b334a45a8ff	3114
bogdanm	0:9b334a45a8ff	3115	/* Bit 11 : RTC0 region configuration. */
bogdanm	0:9b334a45a8ff	3116	#define MPU_PERR0_RTC0_Pos (11UL) /!< Position of RTC0 field. /
bogdanm	0:9b334a45a8ff	3117	#define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /!< Bit mask of RTC0 field. /
bogdanm	0:9b334a45a8ff	3118	#define MPU_PERR0_RTC0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	0:9b334a45a8ff	3119	#define MPU_PERR0_RTC0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	0:9b334a45a8ff	3120
bogdanm	0:9b334a45a8ff	3121	/* Bit 10 : TIMER2 region configuration. */
bogdanm	0:9b334a45a8ff	3122	#define MPU_PERR0_TIMER2_Pos (10UL) /!< Position of TIMER2 field. /
bogdanm	0:9b334a45a8ff	3123	#define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /!< Bit mask of TIMER2 field. /
bogdanm	0:9b334a45a8ff	3124	#define MPU_PERR0_TIMER2_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	0:9b334a45a8ff	3125	#define MPU_PERR0_TIMER2_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	0:9b334a45a8ff	3126
bogdanm	0:9b334a45a8ff	3127	/* Bit 9 : TIMER1 region configuration. */
bogdanm	0:9b334a45a8ff	3128	#define MPU_PERR0_TIMER1_Pos (9UL) /!< Position of TIMER1 field. /
bogdanm	0:9b334a45a8ff	3129	#define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /!< Bit mask of TIMER1 field. /
bogdanm	0:9b334a45a8ff	3130	#define MPU_PERR0_TIMER1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	0:9b334a45a8ff	3131	#define MPU_PERR0_TIMER1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	0:9b334a45a8ff	3132
bogdanm	0:9b334a45a8ff	3133	/* Bit 8 : TIMER0 region configuration. */
bogdanm	0:9b334a45a8ff	3134	#define MPU_PERR0_TIMER0_Pos (8UL) /!< Position of TIMER0 field. /
bogdanm	0:9b334a45a8ff	3135	#define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /!< Bit mask of TIMER0 field. /
bogdanm	0:9b334a45a8ff	3136	#define MPU_PERR0_TIMER0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	0:9b334a45a8ff	3137	#define MPU_PERR0_TIMER0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	0:9b334a45a8ff	3138
bogdanm	0:9b334a45a8ff	3139	/* Bit 7 : ADC region configuration. */
bogdanm	0:9b334a45a8ff	3140	#define MPU_PERR0_ADC_Pos (7UL) /!< Position of ADC field. /
bogdanm	0:9b334a45a8ff	3141	#define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /!< Bit mask of ADC field. /
bogdanm	0:9b334a45a8ff	3142	#define MPU_PERR0_ADC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	0:9b334a45a8ff	3143	#define MPU_PERR0_ADC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	0:9b334a45a8ff	3144
bogdanm	0:9b334a45a8ff	3145	/* Bit 6 : GPIOTE region configuration. */
bogdanm	0:9b334a45a8ff	3146	#define MPU_PERR0_GPIOTE_Pos (6UL) /!< Position of GPIOTE field. /
bogdanm	0:9b334a45a8ff	3147	#define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /!< Bit mask of GPIOTE field. /
bogdanm	0:9b334a45a8ff	3148	#define MPU_PERR0_GPIOTE_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	0:9b334a45a8ff	3149	#define MPU_PERR0_GPIOTE_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	0:9b334a45a8ff	3150
bogdanm	0:9b334a45a8ff	3151	/* Bit 4 : SPI1 and TWI1 region configuration. */
bogdanm	0:9b334a45a8ff	3152	#define MPU_PERR0_SPI1_TWI1_Pos (4UL) /!< Position of SPI1_TWI1 field. /
bogdanm	0:9b334a45a8ff	3153	#define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /!< Bit mask of SPI1_TWI1 field. /
bogdanm	0:9b334a45a8ff	3154	#define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	0:9b334a45a8ff	3155	#define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	0:9b334a45a8ff	3156
bogdanm	0:9b334a45a8ff	3157	/* Bit 3 : SPI0 and TWI0 region configuration. */
bogdanm	0:9b334a45a8ff	3158	#define MPU_PERR0_SPI0_TWI0_Pos (3UL) /!< Position of SPI0_TWI0 field. /
bogdanm	0:9b334a45a8ff	3159	#define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /!< Bit mask of SPI0_TWI0 field. /
bogdanm	0:9b334a45a8ff	3160	#define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	0:9b334a45a8ff	3161	#define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	0:9b334a45a8ff	3162
bogdanm	0:9b334a45a8ff	3163	/* Bit 2 : UART0 region configuration. */
bogdanm	0:9b334a45a8ff	3164	#define MPU_PERR0_UART0_Pos (2UL) /!< Position of UART0 field. /
bogdanm	0:9b334a45a8ff	3165	#define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /!< Bit mask of UART0 field. /
bogdanm	0:9b334a45a8ff	3166	#define MPU_PERR0_UART0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	0:9b334a45a8ff	3167	#define MPU_PERR0_UART0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	0:9b334a45a8ff	3168
bogdanm	0:9b334a45a8ff	3169	/* Bit 1 : RADIO region configuration. */
bogdanm	0:9b334a45a8ff	3170	#define MPU_PERR0_RADIO_Pos (1UL) /!< Position of RADIO field. /
bogdanm	0:9b334a45a8ff	3171	#define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /!< Bit mask of RADIO field. /
bogdanm	0:9b334a45a8ff	3172	#define MPU_PERR0_RADIO_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	0:9b334a45a8ff	3173	#define MPU_PERR0_RADIO_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	0:9b334a45a8ff	3174
bogdanm	0:9b334a45a8ff	3175	/* Bit 0 : POWER_CLOCK region configuration. */
bogdanm	0:9b334a45a8ff	3176	#define MPU_PERR0_POWER_CLOCK_Pos (0UL) /!< Position of POWER_CLOCK field. /
bogdanm	0:9b334a45a8ff	3177	#define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /!< Bit mask of POWER_CLOCK field. /
bogdanm	0:9b334a45a8ff	3178	#define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	0:9b334a45a8ff	3179	#define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	0:9b334a45a8ff	3180
bogdanm	0:9b334a45a8ff	3181	/* Register: MPU_PROTENSET0 */
bogdanm	0:9b334a45a8ff	3182	/* Description: Erase and write protection bit enable set register. */
bogdanm	0:9b334a45a8ff	3183
bogdanm	0:9b334a45a8ff	3184	/* Bit 31 : Protection enable for region 31. */
bogdanm	0:9b334a45a8ff	3185	#define MPU_PROTENSET0_PROTREG31_Pos (31UL) /!< Position of PROTREG31 field. /
bogdanm	0:9b334a45a8ff	3186	#define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /!< Bit mask of PROTREG31 field. /
bogdanm	0:9b334a45a8ff	3187	#define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3188	#define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3189	#define MPU_PROTENSET0_PROTREG31_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3190
bogdanm	0:9b334a45a8ff	3191	/* Bit 30 : Protection enable for region 30. */
bogdanm	0:9b334a45a8ff	3192	#define MPU_PROTENSET0_PROTREG30_Pos (30UL) /!< Position of PROTREG30 field. /
bogdanm	0:9b334a45a8ff	3193	#define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /!< Bit mask of PROTREG30 field. /
bogdanm	0:9b334a45a8ff	3194	#define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3195	#define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3196	#define MPU_PROTENSET0_PROTREG30_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3197
bogdanm	0:9b334a45a8ff	3198	/* Bit 29 : Protection enable for region 29. */
bogdanm	0:9b334a45a8ff	3199	#define MPU_PROTENSET0_PROTREG29_Pos (29UL) /!< Position of PROTREG29 field. /
bogdanm	0:9b334a45a8ff	3200	#define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /!< Bit mask of PROTREG29 field. /
bogdanm	0:9b334a45a8ff	3201	#define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3202	#define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3203	#define MPU_PROTENSET0_PROTREG29_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3204
bogdanm	0:9b334a45a8ff	3205	/* Bit 28 : Protection enable for region 28. */
bogdanm	0:9b334a45a8ff	3206	#define MPU_PROTENSET0_PROTREG28_Pos (28UL) /!< Position of PROTREG28 field. /
bogdanm	0:9b334a45a8ff	3207	#define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /!< Bit mask of PROTREG28 field. /
bogdanm	0:9b334a45a8ff	3208	#define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3209	#define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3210	#define MPU_PROTENSET0_PROTREG28_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3211
bogdanm	0:9b334a45a8ff	3212	/* Bit 27 : Protection enable for region 27. */
bogdanm	0:9b334a45a8ff	3213	#define MPU_PROTENSET0_PROTREG27_Pos (27UL) /!< Position of PROTREG27 field. /
bogdanm	0:9b334a45a8ff	3214	#define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /!< Bit mask of PROTREG27 field. /
bogdanm	0:9b334a45a8ff	3215	#define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3216	#define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3217	#define MPU_PROTENSET0_PROTREG27_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3218
bogdanm	0:9b334a45a8ff	3219	/* Bit 26 : Protection enable for region 26. */
bogdanm	0:9b334a45a8ff	3220	#define MPU_PROTENSET0_PROTREG26_Pos (26UL) /!< Position of PROTREG26 field. /
bogdanm	0:9b334a45a8ff	3221	#define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /!< Bit mask of PROTREG26 field. /
bogdanm	0:9b334a45a8ff	3222	#define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3223	#define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3224	#define MPU_PROTENSET0_PROTREG26_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3225
bogdanm	0:9b334a45a8ff	3226	/* Bit 25 : Protection enable for region 25. */
bogdanm	0:9b334a45a8ff	3227	#define MPU_PROTENSET0_PROTREG25_Pos (25UL) /!< Position of PROTREG25 field. /
bogdanm	0:9b334a45a8ff	3228	#define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /!< Bit mask of PROTREG25 field. /
bogdanm	0:9b334a45a8ff	3229	#define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3230	#define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3231	#define MPU_PROTENSET0_PROTREG25_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3232
bogdanm	0:9b334a45a8ff	3233	/* Bit 24 : Protection enable for region 24. */
bogdanm	0:9b334a45a8ff	3234	#define MPU_PROTENSET0_PROTREG24_Pos (24UL) /!< Position of PROTREG24 field. /
bogdanm	0:9b334a45a8ff	3235	#define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /!< Bit mask of PROTREG24 field. /
bogdanm	0:9b334a45a8ff	3236	#define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3237	#define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3238	#define MPU_PROTENSET0_PROTREG24_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3239
bogdanm	0:9b334a45a8ff	3240	/* Bit 23 : Protection enable for region 23. */
bogdanm	0:9b334a45a8ff	3241	#define MPU_PROTENSET0_PROTREG23_Pos (23UL) /!< Position of PROTREG23 field. /
bogdanm	0:9b334a45a8ff	3242	#define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /!< Bit mask of PROTREG23 field. /
bogdanm	0:9b334a45a8ff	3243	#define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3244	#define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3245	#define MPU_PROTENSET0_PROTREG23_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3246
bogdanm	0:9b334a45a8ff	3247	/* Bit 22 : Protection enable for region 22. */
bogdanm	0:9b334a45a8ff	3248	#define MPU_PROTENSET0_PROTREG22_Pos (22UL) /!< Position of PROTREG22 field. /
bogdanm	0:9b334a45a8ff	3249	#define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /!< Bit mask of PROTREG22 field. /
bogdanm	0:9b334a45a8ff	3250	#define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3251	#define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3252	#define MPU_PROTENSET0_PROTREG22_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3253
bogdanm	0:9b334a45a8ff	3254	/* Bit 21 : Protection enable for region 21. */
bogdanm	0:9b334a45a8ff	3255	#define MPU_PROTENSET0_PROTREG21_Pos (21UL) /!< Position of PROTREG21 field. /
bogdanm	0:9b334a45a8ff	3256	#define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /!< Bit mask of PROTREG21 field. /
bogdanm	0:9b334a45a8ff	3257	#define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3258	#define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3259	#define MPU_PROTENSET0_PROTREG21_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3260
bogdanm	0:9b334a45a8ff	3261	/* Bit 20 : Protection enable for region 20. */
bogdanm	0:9b334a45a8ff	3262	#define MPU_PROTENSET0_PROTREG20_Pos (20UL) /!< Position of PROTREG20 field. /
bogdanm	0:9b334a45a8ff	3263	#define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /!< Bit mask of PROTREG20 field. /
bogdanm	0:9b334a45a8ff	3264	#define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3265	#define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3266	#define MPU_PROTENSET0_PROTREG20_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3267
bogdanm	0:9b334a45a8ff	3268	/* Bit 19 : Protection enable for region 19. */
bogdanm	0:9b334a45a8ff	3269	#define MPU_PROTENSET0_PROTREG19_Pos (19UL) /!< Position of PROTREG19 field. /
bogdanm	0:9b334a45a8ff	3270	#define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /!< Bit mask of PROTREG19 field. /
bogdanm	0:9b334a45a8ff	3271	#define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3272	#define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3273	#define MPU_PROTENSET0_PROTREG19_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3274
bogdanm	0:9b334a45a8ff	3275	/* Bit 18 : Protection enable for region 18. */
bogdanm	0:9b334a45a8ff	3276	#define MPU_PROTENSET0_PROTREG18_Pos (18UL) /!< Position of PROTREG18 field. /
bogdanm	0:9b334a45a8ff	3277	#define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /!< Bit mask of PROTREG18 field. /
bogdanm	0:9b334a45a8ff	3278	#define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3279	#define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3280	#define MPU_PROTENSET0_PROTREG18_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3281
bogdanm	0:9b334a45a8ff	3282	/* Bit 17 : Protection enable for region 17. */
bogdanm	0:9b334a45a8ff	3283	#define MPU_PROTENSET0_PROTREG17_Pos (17UL) /!< Position of PROTREG17 field. /
bogdanm	0:9b334a45a8ff	3284	#define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /!< Bit mask of PROTREG17 field. /
bogdanm	0:9b334a45a8ff	3285	#define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3286	#define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3287	#define MPU_PROTENSET0_PROTREG17_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3288
bogdanm	0:9b334a45a8ff	3289	/* Bit 16 : Protection enable for region 16. */
bogdanm	0:9b334a45a8ff	3290	#define MPU_PROTENSET0_PROTREG16_Pos (16UL) /!< Position of PROTREG16 field. /
bogdanm	0:9b334a45a8ff	3291	#define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /!< Bit mask of PROTREG16 field. /
bogdanm	0:9b334a45a8ff	3292	#define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3293	#define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3294	#define MPU_PROTENSET0_PROTREG16_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3295
bogdanm	0:9b334a45a8ff	3296	/* Bit 15 : Protection enable for region 15. */
bogdanm	0:9b334a45a8ff	3297	#define MPU_PROTENSET0_PROTREG15_Pos (15UL) /!< Position of PROTREG15 field. /
bogdanm	0:9b334a45a8ff	3298	#define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /!< Bit mask of PROTREG15 field. /
bogdanm	0:9b334a45a8ff	3299	#define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3300	#define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3301	#define MPU_PROTENSET0_PROTREG15_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3302
bogdanm	0:9b334a45a8ff	3303	/* Bit 14 : Protection enable for region 14. */
bogdanm	0:9b334a45a8ff	3304	#define MPU_PROTENSET0_PROTREG14_Pos (14UL) /!< Position of PROTREG14 field. /
bogdanm	0:9b334a45a8ff	3305	#define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /!< Bit mask of PROTREG14 field. /
bogdanm	0:9b334a45a8ff	3306	#define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3307	#define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3308	#define MPU_PROTENSET0_PROTREG14_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3309
bogdanm	0:9b334a45a8ff	3310	/* Bit 13 : Protection enable for region 13. */
bogdanm	0:9b334a45a8ff	3311	#define MPU_PROTENSET0_PROTREG13_Pos (13UL) /!< Position of PROTREG13 field. /
bogdanm	0:9b334a45a8ff	3312	#define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /!< Bit mask of PROTREG13 field. /
bogdanm	0:9b334a45a8ff	3313	#define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3314	#define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3315	#define MPU_PROTENSET0_PROTREG13_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3316
bogdanm	0:9b334a45a8ff	3317	/* Bit 12 : Protection enable for region 12. */
bogdanm	0:9b334a45a8ff	3318	#define MPU_PROTENSET0_PROTREG12_Pos (12UL) /!< Position of PROTREG12 field. /
bogdanm	0:9b334a45a8ff	3319	#define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /!< Bit mask of PROTREG12 field. /
bogdanm	0:9b334a45a8ff	3320	#define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3321	#define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3322	#define MPU_PROTENSET0_PROTREG12_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3323
bogdanm	0:9b334a45a8ff	3324	/* Bit 11 : Protection enable for region 11. */
bogdanm	0:9b334a45a8ff	3325	#define MPU_PROTENSET0_PROTREG11_Pos (11UL) /!< Position of PROTREG11 field. /
bogdanm	0:9b334a45a8ff	3326	#define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /!< Bit mask of PROTREG11 field. /
bogdanm	0:9b334a45a8ff	3327	#define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3328	#define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3329	#define MPU_PROTENSET0_PROTREG11_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3330
bogdanm	0:9b334a45a8ff	3331	/* Bit 10 : Protection enable for region 10. */
bogdanm	0:9b334a45a8ff	3332	#define MPU_PROTENSET0_PROTREG10_Pos (10UL) /!< Position of PROTREG10 field. /
bogdanm	0:9b334a45a8ff	3333	#define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /!< Bit mask of PROTREG10 field. /
bogdanm	0:9b334a45a8ff	3334	#define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3335	#define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3336	#define MPU_PROTENSET0_PROTREG10_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3337
bogdanm	0:9b334a45a8ff	3338	/* Bit 9 : Protection enable for region 9. */
bogdanm	0:9b334a45a8ff	3339	#define MPU_PROTENSET0_PROTREG9_Pos (9UL) /!< Position of PROTREG9 field. /
bogdanm	0:9b334a45a8ff	3340	#define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /!< Bit mask of PROTREG9 field. /
bogdanm	0:9b334a45a8ff	3341	#define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3342	#define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3343	#define MPU_PROTENSET0_PROTREG9_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3344
bogdanm	0:9b334a45a8ff	3345	/* Bit 8 : Protection enable for region 8. */
bogdanm	0:9b334a45a8ff	3346	#define MPU_PROTENSET0_PROTREG8_Pos (8UL) /!< Position of PROTREG8 field. /
bogdanm	0:9b334a45a8ff	3347	#define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /!< Bit mask of PROTREG8 field. /
bogdanm	0:9b334a45a8ff	3348	#define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3349	#define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3350	#define MPU_PROTENSET0_PROTREG8_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3351
bogdanm	0:9b334a45a8ff	3352	/* Bit 7 : Protection enable for region 7. */
bogdanm	0:9b334a45a8ff	3353	#define MPU_PROTENSET0_PROTREG7_Pos (7UL) /!< Position of PROTREG7 field. /
bogdanm	0:9b334a45a8ff	3354	#define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /!< Bit mask of PROTREG7 field. /
bogdanm	0:9b334a45a8ff	3355	#define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3356	#define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3357	#define MPU_PROTENSET0_PROTREG7_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3358
bogdanm	0:9b334a45a8ff	3359	/* Bit 6 : Protection enable for region 6. */
bogdanm	0:9b334a45a8ff	3360	#define MPU_PROTENSET0_PROTREG6_Pos (6UL) /!< Position of PROTREG6 field. /
bogdanm	0:9b334a45a8ff	3361	#define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /!< Bit mask of PROTREG6 field. /
bogdanm	0:9b334a45a8ff	3362	#define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3363	#define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3364	#define MPU_PROTENSET0_PROTREG6_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3365
bogdanm	0:9b334a45a8ff	3366	/* Bit 5 : Protection enable for region 5. */
bogdanm	0:9b334a45a8ff	3367	#define MPU_PROTENSET0_PROTREG5_Pos (5UL) /!< Position of PROTREG5 field. /
bogdanm	0:9b334a45a8ff	3368	#define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /!< Bit mask of PROTREG5 field. /
bogdanm	0:9b334a45a8ff	3369	#define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3370	#define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3371	#define MPU_PROTENSET0_PROTREG5_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3372
bogdanm	0:9b334a45a8ff	3373	/* Bit 4 : Protection enable for region 4. */
bogdanm	0:9b334a45a8ff	3374	#define MPU_PROTENSET0_PROTREG4_Pos (4UL) /!< Position of PROTREG4 field. /
bogdanm	0:9b334a45a8ff	3375	#define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /!< Bit mask of PROTREG4 field. /
bogdanm	0:9b334a45a8ff	3376	#define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3377	#define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3378	#define MPU_PROTENSET0_PROTREG4_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3379
bogdanm	0:9b334a45a8ff	3380	/* Bit 3 : Protection enable for region 3. */
bogdanm	0:9b334a45a8ff	3381	#define MPU_PROTENSET0_PROTREG3_Pos (3UL) /!< Position of PROTREG3 field. /
bogdanm	0:9b334a45a8ff	3382	#define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /!< Bit mask of PROTREG3 field. /
bogdanm	0:9b334a45a8ff	3383	#define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3384	#define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3385	#define MPU_PROTENSET0_PROTREG3_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3386
bogdanm	0:9b334a45a8ff	3387	/* Bit 2 : Protection enable for region 2. */
bogdanm	0:9b334a45a8ff	3388	#define MPU_PROTENSET0_PROTREG2_Pos (2UL) /!< Position of PROTREG2 field. /
bogdanm	0:9b334a45a8ff	3389	#define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /!< Bit mask of PROTREG2 field. /
bogdanm	0:9b334a45a8ff	3390	#define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3391	#define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3392	#define MPU_PROTENSET0_PROTREG2_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3393
bogdanm	0:9b334a45a8ff	3394	/* Bit 1 : Protection enable for region 1. */
bogdanm	0:9b334a45a8ff	3395	#define MPU_PROTENSET0_PROTREG1_Pos (1UL) /!< Position of PROTREG1 field. /
bogdanm	0:9b334a45a8ff	3396	#define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /!< Bit mask of PROTREG1 field. /
bogdanm	0:9b334a45a8ff	3397	#define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3398	#define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3399	#define MPU_PROTENSET0_PROTREG1_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3400
bogdanm	0:9b334a45a8ff	3401	/* Bit 0 : Protection enable for region 0. */
bogdanm	0:9b334a45a8ff	3402	#define MPU_PROTENSET0_PROTREG0_Pos (0UL) /!< Position of PROTREG0 field. /
bogdanm	0:9b334a45a8ff	3403	#define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /!< Bit mask of PROTREG0 field. /
bogdanm	0:9b334a45a8ff	3404	#define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3405	#define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3406	#define MPU_PROTENSET0_PROTREG0_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3407
bogdanm	0:9b334a45a8ff	3408	/* Register: MPU_PROTENSET1 */
bogdanm	0:9b334a45a8ff	3409	/* Description: Erase and write protection bit enable set register. */
bogdanm	0:9b334a45a8ff	3410
bogdanm	0:9b334a45a8ff	3411	/* Bit 31 : Protection enable for region 63. */
bogdanm	0:9b334a45a8ff	3412	#define MPU_PROTENSET1_PROTREG63_Pos (31UL) /!< Position of PROTREG63 field. /
bogdanm	0:9b334a45a8ff	3413	#define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /!< Bit mask of PROTREG63 field. /
bogdanm	0:9b334a45a8ff	3414	#define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3415	#define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3416	#define MPU_PROTENSET1_PROTREG63_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3417
bogdanm	0:9b334a45a8ff	3418	/* Bit 30 : Protection enable for region 62. */
bogdanm	0:9b334a45a8ff	3419	#define MPU_PROTENSET1_PROTREG62_Pos (30UL) /!< Position of PROTREG62 field. /
bogdanm	0:9b334a45a8ff	3420	#define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /!< Bit mask of PROTREG62 field. /
bogdanm	0:9b334a45a8ff	3421	#define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3422	#define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3423	#define MPU_PROTENSET1_PROTREG62_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3424
bogdanm	0:9b334a45a8ff	3425	/* Bit 29 : Protection enable for region 61. */
bogdanm	0:9b334a45a8ff	3426	#define MPU_PROTENSET1_PROTREG61_Pos (29UL) /!< Position of PROTREG61 field. /
bogdanm	0:9b334a45a8ff	3427	#define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /!< Bit mask of PROTREG61 field. /
bogdanm	0:9b334a45a8ff	3428	#define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3429	#define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3430	#define MPU_PROTENSET1_PROTREG61_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3431
bogdanm	0:9b334a45a8ff	3432	/* Bit 28 : Protection enable for region 60. */
bogdanm	0:9b334a45a8ff	3433	#define MPU_PROTENSET1_PROTREG60_Pos (28UL) /!< Position of PROTREG60 field. /
bogdanm	0:9b334a45a8ff	3434	#define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /!< Bit mask of PROTREG60 field. /
bogdanm	0:9b334a45a8ff	3435	#define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3436	#define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3437	#define MPU_PROTENSET1_PROTREG60_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3438
bogdanm	0:9b334a45a8ff	3439	/* Bit 27 : Protection enable for region 59. */
bogdanm	0:9b334a45a8ff	3440	#define MPU_PROTENSET1_PROTREG59_Pos (27UL) /!< Position of PROTREG59 field. /
bogdanm	0:9b334a45a8ff	3441	#define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /!< Bit mask of PROTREG59 field. /
bogdanm	0:9b334a45a8ff	3442	#define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3443	#define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3444	#define MPU_PROTENSET1_PROTREG59_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3445
bogdanm	0:9b334a45a8ff	3446	/* Bit 26 : Protection enable for region 58. */
bogdanm	0:9b334a45a8ff	3447	#define MPU_PROTENSET1_PROTREG58_Pos (26UL) /!< Position of PROTREG58 field. /
bogdanm	0:9b334a45a8ff	3448	#define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /!< Bit mask of PROTREG58 field. /
bogdanm	0:9b334a45a8ff	3449	#define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3450	#define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3451	#define MPU_PROTENSET1_PROTREG58_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3452
bogdanm	0:9b334a45a8ff	3453	/* Bit 25 : Protection enable for region 57. */
bogdanm	0:9b334a45a8ff	3454	#define MPU_PROTENSET1_PROTREG57_Pos (25UL) /!< Position of PROTREG57 field. /
bogdanm	0:9b334a45a8ff	3455	#define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /!< Bit mask of PROTREG57 field. /
bogdanm	0:9b334a45a8ff	3456	#define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3457	#define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3458	#define MPU_PROTENSET1_PROTREG57_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3459
bogdanm	0:9b334a45a8ff	3460	/* Bit 24 : Protection enable for region 56. */
bogdanm	0:9b334a45a8ff	3461	#define MPU_PROTENSET1_PROTREG56_Pos (24UL) /!< Position of PROTREG56 field. /
bogdanm	0:9b334a45a8ff	3462	#define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /!< Bit mask of PROTREG56 field. /
bogdanm	0:9b334a45a8ff	3463	#define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3464	#define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3465	#define MPU_PROTENSET1_PROTREG56_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3466
bogdanm	0:9b334a45a8ff	3467	/* Bit 23 : Protection enable for region 55. */
bogdanm	0:9b334a45a8ff	3468	#define MPU_PROTENSET1_PROTREG55_Pos (23UL) /!< Position of PROTREG55 field. /
bogdanm	0:9b334a45a8ff	3469	#define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /!< Bit mask of PROTREG55 field. /
bogdanm	0:9b334a45a8ff	3470	#define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3471	#define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3472	#define MPU_PROTENSET1_PROTREG55_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3473
bogdanm	0:9b334a45a8ff	3474	/* Bit 22 : Protection enable for region 54. */
bogdanm	0:9b334a45a8ff	3475	#define MPU_PROTENSET1_PROTREG54_Pos (22UL) /!< Position of PROTREG54 field. /
bogdanm	0:9b334a45a8ff	3476	#define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /!< Bit mask of PROTREG54 field. /
bogdanm	0:9b334a45a8ff	3477	#define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3478	#define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3479	#define MPU_PROTENSET1_PROTREG54_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3480
bogdanm	0:9b334a45a8ff	3481	/* Bit 21 : Protection enable for region 53. */
bogdanm	0:9b334a45a8ff	3482	#define MPU_PROTENSET1_PROTREG53_Pos (21UL) /!< Position of PROTREG53 field. /
bogdanm	0:9b334a45a8ff	3483	#define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /!< Bit mask of PROTREG53 field. /
bogdanm	0:9b334a45a8ff	3484	#define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3485	#define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3486	#define MPU_PROTENSET1_PROTREG53_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3487
bogdanm	0:9b334a45a8ff	3488	/* Bit 20 : Protection enable for region 52. */
bogdanm	0:9b334a45a8ff	3489	#define MPU_PROTENSET1_PROTREG52_Pos (20UL) /!< Position of PROTREG52 field. /
bogdanm	0:9b334a45a8ff	3490	#define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /!< Bit mask of PROTREG52 field. /
bogdanm	0:9b334a45a8ff	3491	#define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3492	#define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3493	#define MPU_PROTENSET1_PROTREG52_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3494
bogdanm	0:9b334a45a8ff	3495	/* Bit 19 : Protection enable for region 51. */
bogdanm	0:9b334a45a8ff	3496	#define MPU_PROTENSET1_PROTREG51_Pos (19UL) /!< Position of PROTREG51 field. /
bogdanm	0:9b334a45a8ff	3497	#define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /!< Bit mask of PROTREG51 field. /
bogdanm	0:9b334a45a8ff	3498	#define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3499	#define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3500	#define MPU_PROTENSET1_PROTREG51_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3501
bogdanm	0:9b334a45a8ff	3502	/* Bit 18 : Protection enable for region 50. */
bogdanm	0:9b334a45a8ff	3503	#define MPU_PROTENSET1_PROTREG50_Pos (18UL) /!< Position of PROTREG50 field. /
bogdanm	0:9b334a45a8ff	3504	#define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /!< Bit mask of PROTREG50 field. /
bogdanm	0:9b334a45a8ff	3505	#define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3506	#define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3507	#define MPU_PROTENSET1_PROTREG50_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3508
bogdanm	0:9b334a45a8ff	3509	/* Bit 17 : Protection enable for region 49. */
bogdanm	0:9b334a45a8ff	3510	#define MPU_PROTENSET1_PROTREG49_Pos (17UL) /!< Position of PROTREG49 field. /
bogdanm	0:9b334a45a8ff	3511	#define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /!< Bit mask of PROTREG49 field. /
bogdanm	0:9b334a45a8ff	3512	#define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3513	#define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3514	#define MPU_PROTENSET1_PROTREG49_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3515
bogdanm	0:9b334a45a8ff	3516	/* Bit 16 : Protection enable for region 48. */
bogdanm	0:9b334a45a8ff	3517	#define MPU_PROTENSET1_PROTREG48_Pos (16UL) /!< Position of PROTREG48 field. /
bogdanm	0:9b334a45a8ff	3518	#define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /!< Bit mask of PROTREG48 field. /
bogdanm	0:9b334a45a8ff	3519	#define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3520	#define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3521	#define MPU_PROTENSET1_PROTREG48_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3522
bogdanm	0:9b334a45a8ff	3523	/* Bit 15 : Protection enable for region 47. */
bogdanm	0:9b334a45a8ff	3524	#define MPU_PROTENSET1_PROTREG47_Pos (15UL) /!< Position of PROTREG47 field. /
bogdanm	0:9b334a45a8ff	3525	#define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /!< Bit mask of PROTREG47 field. /
bogdanm	0:9b334a45a8ff	3526	#define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3527	#define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3528	#define MPU_PROTENSET1_PROTREG47_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3529
bogdanm	0:9b334a45a8ff	3530	/* Bit 14 : Protection enable for region 46. */
bogdanm	0:9b334a45a8ff	3531	#define MPU_PROTENSET1_PROTREG46_Pos (14UL) /!< Position of PROTREG46 field. /
bogdanm	0:9b334a45a8ff	3532	#define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /!< Bit mask of PROTREG46 field. /
bogdanm	0:9b334a45a8ff	3533	#define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3534	#define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3535	#define MPU_PROTENSET1_PROTREG46_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3536
bogdanm	0:9b334a45a8ff	3537	/* Bit 13 : Protection enable for region 45. */
bogdanm	0:9b334a45a8ff	3538	#define MPU_PROTENSET1_PROTREG45_Pos (13UL) /!< Position of PROTREG45 field. /
bogdanm	0:9b334a45a8ff	3539	#define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /!< Bit mask of PROTREG45 field. /
bogdanm	0:9b334a45a8ff	3540	#define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3541	#define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3542	#define MPU_PROTENSET1_PROTREG45_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3543
bogdanm	0:9b334a45a8ff	3544	/* Bit 12 : Protection enable for region 44. */
bogdanm	0:9b334a45a8ff	3545	#define MPU_PROTENSET1_PROTREG44_Pos (12UL) /!< Position of PROTREG44 field. /
bogdanm	0:9b334a45a8ff	3546	#define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /!< Bit mask of PROTREG44 field. /
bogdanm	0:9b334a45a8ff	3547	#define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3548	#define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3549	#define MPU_PROTENSET1_PROTREG44_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3550
bogdanm	0:9b334a45a8ff	3551	/* Bit 11 : Protection enable for region 43. */
bogdanm	0:9b334a45a8ff	3552	#define MPU_PROTENSET1_PROTREG43_Pos (11UL) /!< Position of PROTREG43 field. /
bogdanm	0:9b334a45a8ff	3553	#define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /!< Bit mask of PROTREG43 field. /
bogdanm	0:9b334a45a8ff	3554	#define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3555	#define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3556	#define MPU_PROTENSET1_PROTREG43_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3557
bogdanm	0:9b334a45a8ff	3558	/* Bit 10 : Protection enable for region 42. */
bogdanm	0:9b334a45a8ff	3559	#define MPU_PROTENSET1_PROTREG42_Pos (10UL) /!< Position of PROTREG42 field. /
bogdanm	0:9b334a45a8ff	3560	#define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /!< Bit mask of PROTREG42 field. /
bogdanm	0:9b334a45a8ff	3561	#define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3562	#define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3563	#define MPU_PROTENSET1_PROTREG42_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3564
bogdanm	0:9b334a45a8ff	3565	/* Bit 9 : Protection enable for region 41. */
bogdanm	0:9b334a45a8ff	3566	#define MPU_PROTENSET1_PROTREG41_Pos (9UL) /!< Position of PROTREG41 field. /
bogdanm	0:9b334a45a8ff	3567	#define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /!< Bit mask of PROTREG41 field. /
bogdanm	0:9b334a45a8ff	3568	#define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3569	#define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3570	#define MPU_PROTENSET1_PROTREG41_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3571
bogdanm	0:9b334a45a8ff	3572	/* Bit 8 : Protection enable for region 40. */
bogdanm	0:9b334a45a8ff	3573	#define MPU_PROTENSET1_PROTREG40_Pos (8UL) /!< Position of PROTREG40 field. /
bogdanm	0:9b334a45a8ff	3574	#define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /!< Bit mask of PROTREG40 field. /
bogdanm	0:9b334a45a8ff	3575	#define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3576	#define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3577	#define MPU_PROTENSET1_PROTREG40_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3578
bogdanm	0:9b334a45a8ff	3579	/* Bit 7 : Protection enable for region 39. */
bogdanm	0:9b334a45a8ff	3580	#define MPU_PROTENSET1_PROTREG39_Pos (7UL) /!< Position of PROTREG39 field. /
bogdanm	0:9b334a45a8ff	3581	#define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /!< Bit mask of PROTREG39 field. /
bogdanm	0:9b334a45a8ff	3582	#define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3583	#define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3584	#define MPU_PROTENSET1_PROTREG39_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3585
bogdanm	0:9b334a45a8ff	3586	/* Bit 6 : Protection enable for region 38. */
bogdanm	0:9b334a45a8ff	3587	#define MPU_PROTENSET1_PROTREG38_Pos (6UL) /!< Position of PROTREG38 field. /
bogdanm	0:9b334a45a8ff	3588	#define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /!< Bit mask of PROTREG38 field. /
bogdanm	0:9b334a45a8ff	3589	#define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3590	#define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3591	#define MPU_PROTENSET1_PROTREG38_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3592
bogdanm	0:9b334a45a8ff	3593	/* Bit 5 : Protection enable for region 37. */
bogdanm	0:9b334a45a8ff	3594	#define MPU_PROTENSET1_PROTREG37_Pos (5UL) /!< Position of PROTREG37 field. /
bogdanm	0:9b334a45a8ff	3595	#define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /!< Bit mask of PROTREG37 field. /
bogdanm	0:9b334a45a8ff	3596	#define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3597	#define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3598	#define MPU_PROTENSET1_PROTREG37_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3599
bogdanm	0:9b334a45a8ff	3600	/* Bit 4 : Protection enable for region 36. */
bogdanm	0:9b334a45a8ff	3601	#define MPU_PROTENSET1_PROTREG36_Pos (4UL) /!< Position of PROTREG36 field. /
bogdanm	0:9b334a45a8ff	3602	#define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /!< Bit mask of PROTREG36 field. /
bogdanm	0:9b334a45a8ff	3603	#define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3604	#define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3605	#define MPU_PROTENSET1_PROTREG36_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3606
bogdanm	0:9b334a45a8ff	3607	/* Bit 3 : Protection enable for region 35. */
bogdanm	0:9b334a45a8ff	3608	#define MPU_PROTENSET1_PROTREG35_Pos (3UL) /!< Position of PROTREG35 field. /
bogdanm	0:9b334a45a8ff	3609	#define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /!< Bit mask of PROTREG35 field. /
bogdanm	0:9b334a45a8ff	3610	#define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3611	#define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3612	#define MPU_PROTENSET1_PROTREG35_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3613
bogdanm	0:9b334a45a8ff	3614	/* Bit 2 : Protection enable for region 34. */
bogdanm	0:9b334a45a8ff	3615	#define MPU_PROTENSET1_PROTREG34_Pos (2UL) /!< Position of PROTREG34 field. /
bogdanm	0:9b334a45a8ff	3616	#define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /!< Bit mask of PROTREG34 field. /
bogdanm	0:9b334a45a8ff	3617	#define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3618	#define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3619	#define MPU_PROTENSET1_PROTREG34_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3620
bogdanm	0:9b334a45a8ff	3621	/* Bit 1 : Protection enable for region 33. */
bogdanm	0:9b334a45a8ff	3622	#define MPU_PROTENSET1_PROTREG33_Pos (1UL) /!< Position of PROTREG33 field. /
bogdanm	0:9b334a45a8ff	3623	#define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /!< Bit mask of PROTREG33 field. /
bogdanm	0:9b334a45a8ff	3624	#define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3625	#define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3626	#define MPU_PROTENSET1_PROTREG33_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3627
bogdanm	0:9b334a45a8ff	3628	/* Bit 0 : Protection enable for region 32. */
bogdanm	0:9b334a45a8ff	3629	#define MPU_PROTENSET1_PROTREG32_Pos (0UL) /!< Position of PROTREG32 field. /
bogdanm	0:9b334a45a8ff	3630	#define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /!< Bit mask of PROTREG32 field. /
bogdanm	0:9b334a45a8ff	3631	#define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3632	#define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3633	#define MPU_PROTENSET1_PROTREG32_Set (1UL) /!< Enable protection on write. /
bogdanm	0:9b334a45a8ff	3634
bogdanm	0:9b334a45a8ff	3635	/* Register: MPU_DISABLEINDEBUG */
bogdanm	0:9b334a45a8ff	3636	/* Description: Disable erase and write protection mechanism in debug mode. */
bogdanm	0:9b334a45a8ff	3637
bogdanm	0:9b334a45a8ff	3638	/* Bit 0 : Disable protection mechanism in debug mode. */
bogdanm	0:9b334a45a8ff	3639	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /!< Position of DISABLEINDEBUG field. /
bogdanm	0:9b334a45a8ff	3640	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /!< Bit mask of DISABLEINDEBUG field. /
bogdanm	0:9b334a45a8ff	3641	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /!< Protection enabled. /
bogdanm	0:9b334a45a8ff	3642	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /!< Protection disabled. /
bogdanm	0:9b334a45a8ff	3643
bogdanm	0:9b334a45a8ff	3644	/* Register: MPU_PROTBLOCKSIZE */
bogdanm	0:9b334a45a8ff	3645	/* Description: Erase and write protection block size. */
bogdanm	0:9b334a45a8ff	3646
bogdanm	0:9b334a45a8ff	3647	/* Bits 1..0 : Erase and write protection block size. */
bogdanm	0:9b334a45a8ff	3648	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /!< Position of PROTBLOCKSIZE field. /
bogdanm	0:9b334a45a8ff	3649	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /!< Bit mask of PROTBLOCKSIZE field. /
bogdanm	0:9b334a45a8ff	3650	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /!< Erase and write protection block size is 4k. /
bogdanm	0:9b334a45a8ff	3651
bogdanm	0:9b334a45a8ff	3652
bogdanm	0:9b334a45a8ff	3653	/* Peripheral: NVMC */
bogdanm	0:9b334a45a8ff	3654	/* Description: Non Volatile Memory Controller. */
bogdanm	0:9b334a45a8ff	3655
bogdanm	0:9b334a45a8ff	3656	/* Register: NVMC_READY */
bogdanm	0:9b334a45a8ff	3657	/* Description: Ready flag. */
bogdanm	0:9b334a45a8ff	3658
bogdanm	0:9b334a45a8ff	3659	/* Bit 0 : NVMC ready. */
bogdanm	0:9b334a45a8ff	3660	#define NVMC_READY_READY_Pos (0UL) /!< Position of READY field. /
bogdanm	0:9b334a45a8ff	3661	#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /!< Bit mask of READY field. /
bogdanm	0:9b334a45a8ff	3662	#define NVMC_READY_READY_Busy (0UL) /!< NVMC is busy (on-going write or erase operation). /
bogdanm	0:9b334a45a8ff	3663	#define NVMC_READY_READY_Ready (1UL) /!< NVMC is ready. /
bogdanm	0:9b334a45a8ff	3664
bogdanm	0:9b334a45a8ff	3665	/* Register: NVMC_CONFIG */
bogdanm	0:9b334a45a8ff	3666	/* Description: Configuration register. */
bogdanm	0:9b334a45a8ff	3667
bogdanm	0:9b334a45a8ff	3668	/* Bits 1..0 : Program write enable. */
bogdanm	0:9b334a45a8ff	3669	#define NVMC_CONFIG_WEN_Pos (0UL) /!< Position of WEN field. /
bogdanm	0:9b334a45a8ff	3670	#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /!< Bit mask of WEN field. /
bogdanm	0:9b334a45a8ff	3671	#define NVMC_CONFIG_WEN_Ren (0x00UL) /!< Read only access. /
bogdanm	0:9b334a45a8ff	3672	#define NVMC_CONFIG_WEN_Wen (0x01UL) /!< Write enabled. /
bogdanm	0:9b334a45a8ff	3673	#define NVMC_CONFIG_WEN_Een (0x02UL) /!< Erase enabled. /
bogdanm	0:9b334a45a8ff	3674
bogdanm	0:9b334a45a8ff	3675	/* Register: NVMC_ERASEALL */
bogdanm	0:9b334a45a8ff	3676	/* Description: Register for erasing all non-volatile user memory. */
bogdanm	0:9b334a45a8ff	3677
bogdanm	0:9b334a45a8ff	3678	/* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */
bogdanm	0:9b334a45a8ff	3679	#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /!< Position of ERASEALL field. /
bogdanm	0:9b334a45a8ff	3680	#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /!< Bit mask of ERASEALL field. /
bogdanm	0:9b334a45a8ff	3681	#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /!< No operation. /
bogdanm	0:9b334a45a8ff	3682	#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /!< Start chip erase. /
bogdanm	0:9b334a45a8ff	3683
bogdanm	0:9b334a45a8ff	3684	/* Register: NVMC_ERASEUICR */
bogdanm	0:9b334a45a8ff	3685	/* Description: Register for start erasing User Information Congfiguration Registers. */
bogdanm	0:9b334a45a8ff	3686
bogdanm	0:9b334a45a8ff	3687	/* Bit 0 : It can only be used when all contents of code region 1 are erased. */
bogdanm	0:9b334a45a8ff	3688	#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /!< Position of ERASEUICR field. /
bogdanm	0:9b334a45a8ff	3689	#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /!< Bit mask of ERASEUICR field. /
bogdanm	0:9b334a45a8ff	3690	#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /!< No operation. /
bogdanm	0:9b334a45a8ff	3691	#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /!< Start UICR erase. /
bogdanm	0:9b334a45a8ff	3692
bogdanm	0:9b334a45a8ff	3693
bogdanm	0:9b334a45a8ff	3694	/* Peripheral: POWER */
bogdanm	0:9b334a45a8ff	3695	/* Description: Power Control. */
bogdanm	0:9b334a45a8ff	3696
bogdanm	0:9b334a45a8ff	3697	/* Register: POWER_INTENSET */
bogdanm	0:9b334a45a8ff	3698	/* Description: Interrupt enable set register. */
bogdanm	0:9b334a45a8ff	3699
bogdanm	0:9b334a45a8ff	3700	/* Bit 2 : Enable interrupt on POFWARN event. */
bogdanm	0:9b334a45a8ff	3701	#define POWER_INTENSET_POFWARN_Pos (2UL) /!< Position of POFWARN field. /
bogdanm	0:9b334a45a8ff	3702	#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /!< Bit mask of POFWARN field. /
bogdanm	0:9b334a45a8ff	3703	#define POWER_INTENSET_POFWARN_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	3704	#define POWER_INTENSET_POFWARN_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	3705	#define POWER_INTENSET_POFWARN_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	3706
bogdanm	0:9b334a45a8ff	3707	/* Register: POWER_INTENCLR */
bogdanm	0:9b334a45a8ff	3708	/* Description: Interrupt enable clear register. */
bogdanm	0:9b334a45a8ff	3709
bogdanm	0:9b334a45a8ff	3710	/* Bit 2 : Disable interrupt on POFWARN event. */
bogdanm	0:9b334a45a8ff	3711	#define POWER_INTENCLR_POFWARN_Pos (2UL) /!< Position of POFWARN field. /
bogdanm	0:9b334a45a8ff	3712	#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /!< Bit mask of POFWARN field. /
bogdanm	0:9b334a45a8ff	3713	#define POWER_INTENCLR_POFWARN_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	3714	#define POWER_INTENCLR_POFWARN_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	3715	#define POWER_INTENCLR_POFWARN_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	3716
bogdanm	0:9b334a45a8ff	3717	/* Register: POWER_RESETREAS */
bogdanm	0:9b334a45a8ff	3718	/* Description: Reset reason. */
bogdanm	0:9b334a45a8ff	3719
bogdanm	0:9b334a45a8ff	3720	/* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */
bogdanm	0:9b334a45a8ff	3721	#define POWER_RESETREAS_DIF_Pos (18UL) /!< Position of DIF field. /
bogdanm	0:9b334a45a8ff	3722	#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /!< Bit mask of DIF field. /
bogdanm	0:9b334a45a8ff	3723
bogdanm	0:9b334a45a8ff	3724	/* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */
bogdanm	0:9b334a45a8ff	3725	#define POWER_RESETREAS_LPCOMP_Pos (17UL) /!< Position of LPCOMP field. /
bogdanm	0:9b334a45a8ff	3726	#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /!< Bit mask of LPCOMP field. /
bogdanm	0:9b334a45a8ff	3727
bogdanm	0:9b334a45a8ff	3728	/* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */
bogdanm	0:9b334a45a8ff	3729	#define POWER_RESETREAS_OFF_Pos (16UL) /!< Position of OFF field. /
bogdanm	0:9b334a45a8ff	3730	#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /!< Bit mask of OFF field. /
bogdanm	0:9b334a45a8ff	3731
bogdanm	0:9b334a45a8ff	3732	/* Bit 3 : Reset from CPU lock-up detected. */
bogdanm	0:9b334a45a8ff	3733	#define POWER_RESETREAS_LOCKUP_Pos (3UL) /!< Position of LOCKUP field. /
bogdanm	0:9b334a45a8ff	3734	#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /!< Bit mask of LOCKUP field. /
bogdanm	0:9b334a45a8ff	3735
bogdanm	0:9b334a45a8ff	3736	/* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */
bogdanm	0:9b334a45a8ff	3737	#define POWER_RESETREAS_SREQ_Pos (2UL) /!< Position of SREQ field. /
bogdanm	0:9b334a45a8ff	3738	#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /!< Bit mask of SREQ field. /
bogdanm	0:9b334a45a8ff	3739
bogdanm	0:9b334a45a8ff	3740	/* Bit 1 : Reset from watchdog detected. */
bogdanm	0:9b334a45a8ff	3741	#define POWER_RESETREAS_DOG_Pos (1UL) /!< Position of DOG field. /
bogdanm	0:9b334a45a8ff	3742	#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /!< Bit mask of DOG field. /
bogdanm	0:9b334a45a8ff	3743
bogdanm	0:9b334a45a8ff	3744	/* Bit 0 : Reset from pin-reset detected. */
bogdanm	0:9b334a45a8ff	3745	#define POWER_RESETREAS_RESETPIN_Pos (0UL) /!< Position of RESETPIN field. /
bogdanm	0:9b334a45a8ff	3746	#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /!< Bit mask of RESETPIN field. /
bogdanm	0:9b334a45a8ff	3747
bogdanm	0:9b334a45a8ff	3748	/* Register: POWER_RAMSTATUS */
bogdanm	0:9b334a45a8ff	3749	/* Description: Ram status register. */
bogdanm	0:9b334a45a8ff	3750
bogdanm	0:9b334a45a8ff	3751	/* Bit 3 : RAM block 3 status. */
bogdanm	0:9b334a45a8ff	3752	#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /!< Position of RAMBLOCK3 field. /
bogdanm	0:9b334a45a8ff	3753	#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /!< Bit mask of RAMBLOCK3 field. /
bogdanm	0:9b334a45a8ff	3754	#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /!< RAM block 3 is off or powering up. /
bogdanm	0:9b334a45a8ff	3755	#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /!< RAM block 3 is on. /
bogdanm	0:9b334a45a8ff	3756
bogdanm	0:9b334a45a8ff	3757	/* Bit 2 : RAM block 2 status. */
bogdanm	0:9b334a45a8ff	3758	#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /!< Position of RAMBLOCK2 field. /
bogdanm	0:9b334a45a8ff	3759	#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /!< Bit mask of RAMBLOCK2 field. /
bogdanm	0:9b334a45a8ff	3760	#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /!< RAM block 2 is off or powering up. /
bogdanm	0:9b334a45a8ff	3761	#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /!< RAM block 2 is on. /
bogdanm	0:9b334a45a8ff	3762
bogdanm	0:9b334a45a8ff	3763	/* Bit 1 : RAM block 1 status. */
bogdanm	0:9b334a45a8ff	3764	#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /!< Position of RAMBLOCK1 field. /
bogdanm	0:9b334a45a8ff	3765	#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /!< Bit mask of RAMBLOCK1 field. /
bogdanm	0:9b334a45a8ff	3766	#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /!< RAM block 1 is off or powering up. /
bogdanm	0:9b334a45a8ff	3767	#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /!< RAM block 1 is on. /
bogdanm	0:9b334a45a8ff	3768
bogdanm	0:9b334a45a8ff	3769	/* Bit 0 : RAM block 0 status. */
bogdanm	0:9b334a45a8ff	3770	#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /!< Position of RAMBLOCK0 field. /
bogdanm	0:9b334a45a8ff	3771	#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /!< Bit mask of RAMBLOCK0 field. /
bogdanm	0:9b334a45a8ff	3772	#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /!< RAM block 0 is off or powering up. /
bogdanm	0:9b334a45a8ff	3773	#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /!< RAM block 0 is on. /
bogdanm	0:9b334a45a8ff	3774
bogdanm	0:9b334a45a8ff	3775	/* Register: POWER_SYSTEMOFF */
bogdanm	0:9b334a45a8ff	3776	/* Description: System off register. */
bogdanm	0:9b334a45a8ff	3777
bogdanm	0:9b334a45a8ff	3778	/* Bit 0 : Enter system off mode. */
bogdanm	0:9b334a45a8ff	3779	#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /!< Position of SYSTEMOFF field. /
bogdanm	0:9b334a45a8ff	3780	#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /!< Bit mask of SYSTEMOFF field. /
bogdanm	0:9b334a45a8ff	3781	#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /!< Enter system off mode. /
bogdanm	0:9b334a45a8ff	3782
bogdanm	0:9b334a45a8ff	3783	/* Register: POWER_POFCON */
bogdanm	0:9b334a45a8ff	3784	/* Description: Power failure configuration. */
bogdanm	0:9b334a45a8ff	3785
bogdanm	0:9b334a45a8ff	3786	/* Bits 2..1 : Set threshold level. */
bogdanm	0:9b334a45a8ff	3787	#define POWER_POFCON_THRESHOLD_Pos (1UL) /!< Position of THRESHOLD field. /
bogdanm	0:9b334a45a8ff	3788	#define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /!< Bit mask of THRESHOLD field. /
bogdanm	0:9b334a45a8ff	3789	#define POWER_POFCON_THRESHOLD_V21 (0x00UL) /!< Set threshold to 2.1Volts. /
bogdanm	0:9b334a45a8ff	3790	#define POWER_POFCON_THRESHOLD_V23 (0x01UL) /!< Set threshold to 2.3Volts. /
bogdanm	0:9b334a45a8ff	3791	#define POWER_POFCON_THRESHOLD_V25 (0x02UL) /!< Set threshold to 2.5Volts. /
bogdanm	0:9b334a45a8ff	3792	#define POWER_POFCON_THRESHOLD_V27 (0x03UL) /!< Set threshold to 2.7Volts. /
bogdanm	0:9b334a45a8ff	3793
bogdanm	0:9b334a45a8ff	3794	/* Bit 0 : Power failure comparator enable. */
bogdanm	0:9b334a45a8ff	3795	#define POWER_POFCON_POF_Pos (0UL) /!< Position of POF field. /
bogdanm	0:9b334a45a8ff	3796	#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /!< Bit mask of POF field. /
bogdanm	0:9b334a45a8ff	3797	#define POWER_POFCON_POF_Disabled (0UL) /!< Disabled. /
bogdanm	0:9b334a45a8ff	3798	#define POWER_POFCON_POF_Enabled (1UL) /!< Enabled. /
bogdanm	0:9b334a45a8ff	3799
bogdanm	0:9b334a45a8ff	3800	/* Register: POWER_GPREGRET */
bogdanm	0:9b334a45a8ff	3801	/* Description: General purpose retention register. This register is a retained register. */
bogdanm	0:9b334a45a8ff	3802
bogdanm	0:9b334a45a8ff	3803	/* Bits 7..0 : General purpose retention register. */
bogdanm	0:9b334a45a8ff	3804	#define POWER_GPREGRET_GPREGRET_Pos (0UL) /!< Position of GPREGRET field. /
bogdanm	0:9b334a45a8ff	3805	#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /!< Bit mask of GPREGRET field. /
bogdanm	0:9b334a45a8ff	3806
bogdanm	0:9b334a45a8ff	3807	/* Register: POWER_RAMON */
bogdanm	0:9b334a45a8ff	3808	/* Description: Ram on/off. */
bogdanm	0:9b334a45a8ff	3809
bogdanm	0:9b334a45a8ff	3810	/* Bit 17 : RAM block 1 behaviour in OFF mode. */
bogdanm	0:9b334a45a8ff	3811	#define POWER_RAMON_OFFRAM1_Pos (17UL) /!< Position of OFFRAM1 field. /
bogdanm	0:9b334a45a8ff	3812	#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /!< Bit mask of OFFRAM1 field. /
bogdanm	0:9b334a45a8ff	3813	#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /!< RAM block 1 OFF in OFF mode. /
bogdanm	0:9b334a45a8ff	3814	#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /!< RAM block 1 ON in OFF mode. /
bogdanm	0:9b334a45a8ff	3815
bogdanm	0:9b334a45a8ff	3816	/* Bit 16 : RAM block 0 behaviour in OFF mode. */
bogdanm	0:9b334a45a8ff	3817	#define POWER_RAMON_OFFRAM0_Pos (16UL) /!< Position of OFFRAM0 field. /
bogdanm	0:9b334a45a8ff	3818	#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /!< Bit mask of OFFRAM0 field. /
bogdanm	0:9b334a45a8ff	3819	#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /!< RAM block 0 OFF in OFF mode. /
bogdanm	0:9b334a45a8ff	3820	#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /!< RAM block 0 ON in OFF mode. /
bogdanm	0:9b334a45a8ff	3821
bogdanm	0:9b334a45a8ff	3822	/* Bit 1 : RAM block 1 behaviour in ON mode. */
bogdanm	0:9b334a45a8ff	3823	#define POWER_RAMON_ONRAM1_Pos (1UL) /!< Position of ONRAM1 field. /
bogdanm	0:9b334a45a8ff	3824	#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /!< Bit mask of ONRAM1 field. /
bogdanm	0:9b334a45a8ff	3825	#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /!< RAM block 1 OFF in ON mode. /
bogdanm	0:9b334a45a8ff	3826	#define POWER_RAMON_ONRAM1_RAM1On (1UL) /!< RAM block 1 ON in ON mode. /
bogdanm	0:9b334a45a8ff	3827
bogdanm	0:9b334a45a8ff	3828	/* Bit 0 : RAM block 0 behaviour in ON mode. */
bogdanm	0:9b334a45a8ff	3829	#define POWER_RAMON_ONRAM0_Pos (0UL) /!< Position of ONRAM0 field. /
bogdanm	0:9b334a45a8ff	3830	#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /!< Bit mask of ONRAM0 field. /
bogdanm	0:9b334a45a8ff	3831	#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /!< RAM block 0 OFF in ON mode. /
bogdanm	0:9b334a45a8ff	3832	#define POWER_RAMON_ONRAM0_RAM0On (1UL) /!< RAM block 0 ON in ON mode. /
bogdanm	0:9b334a45a8ff	3833
bogdanm	0:9b334a45a8ff	3834	/* Register: POWER_RESET */
bogdanm	0:9b334a45a8ff	3835	/* Description: Pin reset functionality configuration register. This register is a retained register. */
bogdanm	0:9b334a45a8ff	3836
bogdanm	0:9b334a45a8ff	3837	/* Bit 0 : Enable or disable pin reset in debug interface mode. */
bogdanm	0:9b334a45a8ff	3838	#define POWER_RESET_RESET_Pos (0UL) /!< Position of RESET field. /
bogdanm	0:9b334a45a8ff	3839	#define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /!< Bit mask of RESET field. /
bogdanm	0:9b334a45a8ff	3840	#define POWER_RESET_RESET_Disabled (0UL) /!< Pin reset in debug interface mode disabled. /
bogdanm	0:9b334a45a8ff	3841	#define POWER_RESET_RESET_Enabled (1UL) /!< Pin reset in debug interface mode enabled. /
bogdanm	0:9b334a45a8ff	3842
bogdanm	0:9b334a45a8ff	3843	/* Register: POWER_RAMONB */
bogdanm	0:9b334a45a8ff	3844	/* Description: Ram on/off. */
bogdanm	0:9b334a45a8ff	3845
bogdanm	0:9b334a45a8ff	3846	/* Bit 17 : RAM block 3 behaviour in OFF mode. */
bogdanm	0:9b334a45a8ff	3847	#define POWER_RAMONB_OFFRAM3_Pos (17UL) /!< Position of OFFRAM3 field. /
bogdanm	0:9b334a45a8ff	3848	#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /!< Bit mask of OFFRAM3 field. /
bogdanm	0:9b334a45a8ff	3849	#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /!< RAM block 3 OFF in OFF mode. /
bogdanm	0:9b334a45a8ff	3850	#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /!< RAM block 3 ON in OFF mode. /
bogdanm	0:9b334a45a8ff	3851
bogdanm	0:9b334a45a8ff	3852	/* Bit 16 : RAM block 2 behaviour in OFF mode. */
bogdanm	0:9b334a45a8ff	3853	#define POWER_RAMONB_OFFRAM2_Pos (16UL) /!< Position of OFFRAM2 field. /
bogdanm	0:9b334a45a8ff	3854	#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /!< Bit mask of OFFRAM2 field. /
bogdanm	0:9b334a45a8ff	3855	#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /!< RAM block 2 OFF in OFF mode. /
bogdanm	0:9b334a45a8ff	3856	#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /!< RAM block 2 ON in OFF mode. /
bogdanm	0:9b334a45a8ff	3857
bogdanm	0:9b334a45a8ff	3858	/* Bit 1 : RAM block 3 behaviour in ON mode. */
bogdanm	0:9b334a45a8ff	3859	#define POWER_RAMONB_ONRAM3_Pos (1UL) /!< Position of ONRAM3 field. /
bogdanm	0:9b334a45a8ff	3860	#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /!< Bit mask of ONRAM3 field. /
bogdanm	0:9b334a45a8ff	3861	#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /!< RAM block 33 OFF in ON mode. /
bogdanm	0:9b334a45a8ff	3862	#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /!< RAM block 3 ON in ON mode. /
bogdanm	0:9b334a45a8ff	3863
bogdanm	0:9b334a45a8ff	3864	/* Bit 0 : RAM block 2 behaviour in ON mode. */
bogdanm	0:9b334a45a8ff	3865	#define POWER_RAMONB_ONRAM2_Pos (0UL) /!< Position of ONRAM2 field. /
bogdanm	0:9b334a45a8ff	3866	#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /!< Bit mask of ONRAM2 field. /
bogdanm	0:9b334a45a8ff	3867	#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /!< RAM block 2 OFF in ON mode. /
bogdanm	0:9b334a45a8ff	3868	#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /!< RAM block 2 ON in ON mode. /
bogdanm	0:9b334a45a8ff	3869
bogdanm	0:9b334a45a8ff	3870	/* Register: POWER_DCDCEN */
bogdanm	0:9b334a45a8ff	3871	/* Description: DCDC converter enable configuration register. */
bogdanm	0:9b334a45a8ff	3872
bogdanm	0:9b334a45a8ff	3873	/* Bit 0 : Enable DCDC converter. */
bogdanm	0:9b334a45a8ff	3874	#define POWER_DCDCEN_DCDCEN_Pos (0UL) /!< Position of DCDCEN field. /
bogdanm	0:9b334a45a8ff	3875	#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /!< Bit mask of DCDCEN field. /
bogdanm	0:9b334a45a8ff	3876	#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /!< DCDC converter disabled. /
bogdanm	0:9b334a45a8ff	3877	#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /!< DCDC converter enabled. /
bogdanm	0:9b334a45a8ff	3878
bogdanm	0:9b334a45a8ff	3879	/* Register: POWER_DCDCFORCE */
bogdanm	0:9b334a45a8ff	3880	/* Description: DCDC power-up force register. */
bogdanm	0:9b334a45a8ff	3881
bogdanm	0:9b334a45a8ff	3882	/* Bit 1 : DCDC power-up force on. */
bogdanm	0:9b334a45a8ff	3883	#define POWER_DCDCFORCE_FORCEON_Pos (1UL) /!< Position of FORCEON field. /
bogdanm	0:9b334a45a8ff	3884	#define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /!< Bit mask of FORCEON field. /
bogdanm	0:9b334a45a8ff	3885	#define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /!< No force. /
bogdanm	0:9b334a45a8ff	3886	#define POWER_DCDCFORCE_FORCEON_Force (1UL) /!< Force. /
bogdanm	0:9b334a45a8ff	3887
bogdanm	0:9b334a45a8ff	3888	/* Bit 0 : DCDC power-up force off. */
bogdanm	0:9b334a45a8ff	3889	#define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /!< Position of FORCEOFF field. /
bogdanm	0:9b334a45a8ff	3890	#define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /!< Bit mask of FORCEOFF field. /
bogdanm	0:9b334a45a8ff	3891	#define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /!< No force. /
bogdanm	0:9b334a45a8ff	3892	#define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /!< Force. /
bogdanm	0:9b334a45a8ff	3893
bogdanm	0:9b334a45a8ff	3894
bogdanm	0:9b334a45a8ff	3895	/* Peripheral: PPI */
bogdanm	0:9b334a45a8ff	3896	/* Description: PPI controller. */
bogdanm	0:9b334a45a8ff	3897
bogdanm	0:9b334a45a8ff	3898	/* Register: PPI_CHEN */
bogdanm	0:9b334a45a8ff	3899	/* Description: Channel enable. */
bogdanm	0:9b334a45a8ff	3900
bogdanm	0:9b334a45a8ff	3901	/* Bit 31 : Enable PPI channel 31. */
bogdanm	0:9b334a45a8ff	3902	#define PPI_CHEN_CH31_Pos (31UL) /!< Position of CH31 field. /
bogdanm	0:9b334a45a8ff	3903	#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /!< Bit mask of CH31 field. /
bogdanm	0:9b334a45a8ff	3904	#define PPI_CHEN_CH31_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	3905	#define PPI_CHEN_CH31_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	3906
bogdanm	0:9b334a45a8ff	3907	/* Bit 30 : Enable PPI channel 30. */
bogdanm	0:9b334a45a8ff	3908	#define PPI_CHEN_CH30_Pos (30UL) /!< Position of CH30 field. /
bogdanm	0:9b334a45a8ff	3909	#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /!< Bit mask of CH30 field. /
bogdanm	0:9b334a45a8ff	3910	#define PPI_CHEN_CH30_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	3911	#define PPI_CHEN_CH30_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	3912
bogdanm	0:9b334a45a8ff	3913	/* Bit 29 : Enable PPI channel 29. */
bogdanm	0:9b334a45a8ff	3914	#define PPI_CHEN_CH29_Pos (29UL) /!< Position of CH29 field. /
bogdanm	0:9b334a45a8ff	3915	#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /!< Bit mask of CH29 field. /
bogdanm	0:9b334a45a8ff	3916	#define PPI_CHEN_CH29_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	3917	#define PPI_CHEN_CH29_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	3918
bogdanm	0:9b334a45a8ff	3919	/* Bit 28 : Enable PPI channel 28. */
bogdanm	0:9b334a45a8ff	3920	#define PPI_CHEN_CH28_Pos (28UL) /!< Position of CH28 field. /
bogdanm	0:9b334a45a8ff	3921	#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /!< Bit mask of CH28 field. /
bogdanm	0:9b334a45a8ff	3922	#define PPI_CHEN_CH28_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	3923	#define PPI_CHEN_CH28_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	3924
bogdanm	0:9b334a45a8ff	3925	/* Bit 27 : Enable PPI channel 27. */
bogdanm	0:9b334a45a8ff	3926	#define PPI_CHEN_CH27_Pos (27UL) /!< Position of CH27 field. /
bogdanm	0:9b334a45a8ff	3927	#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /!< Bit mask of CH27 field. /
bogdanm	0:9b334a45a8ff	3928	#define PPI_CHEN_CH27_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	3929	#define PPI_CHEN_CH27_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	3930
bogdanm	0:9b334a45a8ff	3931	/* Bit 26 : Enable PPI channel 26. */
bogdanm	0:9b334a45a8ff	3932	#define PPI_CHEN_CH26_Pos (26UL) /!< Position of CH26 field. /
bogdanm	0:9b334a45a8ff	3933	#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /!< Bit mask of CH26 field. /
bogdanm	0:9b334a45a8ff	3934	#define PPI_CHEN_CH26_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	3935	#define PPI_CHEN_CH26_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	3936
bogdanm	0:9b334a45a8ff	3937	/* Bit 25 : Enable PPI channel 25. */
bogdanm	0:9b334a45a8ff	3938	#define PPI_CHEN_CH25_Pos (25UL) /!< Position of CH25 field. /
bogdanm	0:9b334a45a8ff	3939	#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /!< Bit mask of CH25 field. /
bogdanm	0:9b334a45a8ff	3940	#define PPI_CHEN_CH25_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	3941	#define PPI_CHEN_CH25_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	3942
bogdanm	0:9b334a45a8ff	3943	/* Bit 24 : Enable PPI channel 24. */
bogdanm	0:9b334a45a8ff	3944	#define PPI_CHEN_CH24_Pos (24UL) /!< Position of CH24 field. /
bogdanm	0:9b334a45a8ff	3945	#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /!< Bit mask of CH24 field. /
bogdanm	0:9b334a45a8ff	3946	#define PPI_CHEN_CH24_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	3947	#define PPI_CHEN_CH24_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	3948
bogdanm	0:9b334a45a8ff	3949	/* Bit 23 : Enable PPI channel 23. */
bogdanm	0:9b334a45a8ff	3950	#define PPI_CHEN_CH23_Pos (23UL) /!< Position of CH23 field. /
bogdanm	0:9b334a45a8ff	3951	#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /!< Bit mask of CH23 field. /
bogdanm	0:9b334a45a8ff	3952	#define PPI_CHEN_CH23_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	3953	#define PPI_CHEN_CH23_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	3954
bogdanm	0:9b334a45a8ff	3955	/* Bit 22 : Enable PPI channel 22. */
bogdanm	0:9b334a45a8ff	3956	#define PPI_CHEN_CH22_Pos (22UL) /!< Position of CH22 field. /
bogdanm	0:9b334a45a8ff	3957	#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /!< Bit mask of CH22 field. /
bogdanm	0:9b334a45a8ff	3958	#define PPI_CHEN_CH22_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	3959	#define PPI_CHEN_CH22_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	3960
bogdanm	0:9b334a45a8ff	3961	/* Bit 21 : Enable PPI channel 21. */
bogdanm	0:9b334a45a8ff	3962	#define PPI_CHEN_CH21_Pos (21UL) /!< Position of CH21 field. /
bogdanm	0:9b334a45a8ff	3963	#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /!< Bit mask of CH21 field. /
bogdanm	0:9b334a45a8ff	3964	#define PPI_CHEN_CH21_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	3965	#define PPI_CHEN_CH21_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	3966
bogdanm	0:9b334a45a8ff	3967	/* Bit 20 : Enable PPI channel 20. */
bogdanm	0:9b334a45a8ff	3968	#define PPI_CHEN_CH20_Pos (20UL) /!< Position of CH20 field. /
bogdanm	0:9b334a45a8ff	3969	#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /!< Bit mask of CH20 field. /
bogdanm	0:9b334a45a8ff	3970	#define PPI_CHEN_CH20_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	3971	#define PPI_CHEN_CH20_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	3972
bogdanm	0:9b334a45a8ff	3973	/* Bit 15 : Enable PPI channel 15. */
bogdanm	0:9b334a45a8ff	3974	#define PPI_CHEN_CH15_Pos (15UL) /!< Position of CH15 field. /
bogdanm	0:9b334a45a8ff	3975	#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /!< Bit mask of CH15 field. /
bogdanm	0:9b334a45a8ff	3976	#define PPI_CHEN_CH15_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	3977	#define PPI_CHEN_CH15_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	3978
bogdanm	0:9b334a45a8ff	3979	/* Bit 14 : Enable PPI channel 14. */
bogdanm	0:9b334a45a8ff	3980	#define PPI_CHEN_CH14_Pos (14UL) /!< Position of CH14 field. /
bogdanm	0:9b334a45a8ff	3981	#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /!< Bit mask of CH14 field. /
bogdanm	0:9b334a45a8ff	3982	#define PPI_CHEN_CH14_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	3983	#define PPI_CHEN_CH14_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	3984
bogdanm	0:9b334a45a8ff	3985	/* Bit 13 : Enable PPI channel 13. */
bogdanm	0:9b334a45a8ff	3986	#define PPI_CHEN_CH13_Pos (13UL) /!< Position of CH13 field. /
bogdanm	0:9b334a45a8ff	3987	#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /!< Bit mask of CH13 field. /
bogdanm	0:9b334a45a8ff	3988	#define PPI_CHEN_CH13_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	3989	#define PPI_CHEN_CH13_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	3990
bogdanm	0:9b334a45a8ff	3991	/* Bit 12 : Enable PPI channel 12. */
bogdanm	0:9b334a45a8ff	3992	#define PPI_CHEN_CH12_Pos (12UL) /!< Position of CH12 field. /
bogdanm	0:9b334a45a8ff	3993	#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /!< Bit mask of CH12 field. /
bogdanm	0:9b334a45a8ff	3994	#define PPI_CHEN_CH12_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	3995	#define PPI_CHEN_CH12_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	3996
bogdanm	0:9b334a45a8ff	3997	/* Bit 11 : Enable PPI channel 11. */
bogdanm	0:9b334a45a8ff	3998	#define PPI_CHEN_CH11_Pos (11UL) /!< Position of CH11 field. /
bogdanm	0:9b334a45a8ff	3999	#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /!< Bit mask of CH11 field. /
bogdanm	0:9b334a45a8ff	4000	#define PPI_CHEN_CH11_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4001	#define PPI_CHEN_CH11_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4002
bogdanm	0:9b334a45a8ff	4003	/* Bit 10 : Enable PPI channel 10. */
bogdanm	0:9b334a45a8ff	4004	#define PPI_CHEN_CH10_Pos (10UL) /!< Position of CH10 field. /
bogdanm	0:9b334a45a8ff	4005	#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /!< Bit mask of CH10 field. /
bogdanm	0:9b334a45a8ff	4006	#define PPI_CHEN_CH10_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4007	#define PPI_CHEN_CH10_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4008
bogdanm	0:9b334a45a8ff	4009	/* Bit 9 : Enable PPI channel 9. */
bogdanm	0:9b334a45a8ff	4010	#define PPI_CHEN_CH9_Pos (9UL) /!< Position of CH9 field. /
bogdanm	0:9b334a45a8ff	4011	#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /!< Bit mask of CH9 field. /
bogdanm	0:9b334a45a8ff	4012	#define PPI_CHEN_CH9_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4013	#define PPI_CHEN_CH9_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4014
bogdanm	0:9b334a45a8ff	4015	/* Bit 8 : Enable PPI channel 8. */
bogdanm	0:9b334a45a8ff	4016	#define PPI_CHEN_CH8_Pos (8UL) /!< Position of CH8 field. /
bogdanm	0:9b334a45a8ff	4017	#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /!< Bit mask of CH8 field. /
bogdanm	0:9b334a45a8ff	4018	#define PPI_CHEN_CH8_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4019	#define PPI_CHEN_CH8_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4020
bogdanm	0:9b334a45a8ff	4021	/* Bit 7 : Enable PPI channel 7. */
bogdanm	0:9b334a45a8ff	4022	#define PPI_CHEN_CH7_Pos (7UL) /!< Position of CH7 field. /
bogdanm	0:9b334a45a8ff	4023	#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /!< Bit mask of CH7 field. /
bogdanm	0:9b334a45a8ff	4024	#define PPI_CHEN_CH7_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4025	#define PPI_CHEN_CH7_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4026
bogdanm	0:9b334a45a8ff	4027	/* Bit 6 : Enable PPI channel 6. */
bogdanm	0:9b334a45a8ff	4028	#define PPI_CHEN_CH6_Pos (6UL) /!< Position of CH6 field. /
bogdanm	0:9b334a45a8ff	4029	#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /!< Bit mask of CH6 field. /
bogdanm	0:9b334a45a8ff	4030	#define PPI_CHEN_CH6_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4031	#define PPI_CHEN_CH6_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4032
bogdanm	0:9b334a45a8ff	4033	/* Bit 5 : Enable PPI channel 5. */
bogdanm	0:9b334a45a8ff	4034	#define PPI_CHEN_CH5_Pos (5UL) /!< Position of CH5 field. /
bogdanm	0:9b334a45a8ff	4035	#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /!< Bit mask of CH5 field. /
bogdanm	0:9b334a45a8ff	4036	#define PPI_CHEN_CH5_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4037	#define PPI_CHEN_CH5_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4038
bogdanm	0:9b334a45a8ff	4039	/* Bit 4 : Enable PPI channel 4. */
bogdanm	0:9b334a45a8ff	4040	#define PPI_CHEN_CH4_Pos (4UL) /!< Position of CH4 field. /
bogdanm	0:9b334a45a8ff	4041	#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /!< Bit mask of CH4 field. /
bogdanm	0:9b334a45a8ff	4042	#define PPI_CHEN_CH4_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4043	#define PPI_CHEN_CH4_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4044
bogdanm	0:9b334a45a8ff	4045	/* Bit 3 : Enable PPI channel 3. */
bogdanm	0:9b334a45a8ff	4046	#define PPI_CHEN_CH3_Pos (3UL) /!< Position of CH3 field. /
bogdanm	0:9b334a45a8ff	4047	#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /!< Bit mask of CH3 field. /
bogdanm	0:9b334a45a8ff	4048	#define PPI_CHEN_CH3_Disabled (0UL) /!< Channel disabled /
bogdanm	0:9b334a45a8ff	4049	#define PPI_CHEN_CH3_Enabled (1UL) /!< Channel enabled /
bogdanm	0:9b334a45a8ff	4050
bogdanm	0:9b334a45a8ff	4051	/* Bit 2 : Enable PPI channel 2. */
bogdanm	0:9b334a45a8ff	4052	#define PPI_CHEN_CH2_Pos (2UL) /!< Position of CH2 field. /
bogdanm	0:9b334a45a8ff	4053	#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /!< Bit mask of CH2 field. /
bogdanm	0:9b334a45a8ff	4054	#define PPI_CHEN_CH2_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4055	#define PPI_CHEN_CH2_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4056
bogdanm	0:9b334a45a8ff	4057	/* Bit 1 : Enable PPI channel 1. */
bogdanm	0:9b334a45a8ff	4058	#define PPI_CHEN_CH1_Pos (1UL) /!< Position of CH1 field. /
bogdanm	0:9b334a45a8ff	4059	#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /!< Bit mask of CH1 field. /
bogdanm	0:9b334a45a8ff	4060	#define PPI_CHEN_CH1_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4061	#define PPI_CHEN_CH1_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4062
bogdanm	0:9b334a45a8ff	4063	/* Bit 0 : Enable PPI channel 0. */
bogdanm	0:9b334a45a8ff	4064	#define PPI_CHEN_CH0_Pos (0UL) /!< Position of CH0 field. /
bogdanm	0:9b334a45a8ff	4065	#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /!< Bit mask of CH0 field. /
bogdanm	0:9b334a45a8ff	4066	#define PPI_CHEN_CH0_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4067	#define PPI_CHEN_CH0_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4068
bogdanm	0:9b334a45a8ff	4069	/* Register: PPI_CHENSET */
bogdanm	0:9b334a45a8ff	4070	/* Description: Channel enable set. */
bogdanm	0:9b334a45a8ff	4071
bogdanm	0:9b334a45a8ff	4072	/* Bit 31 : Enable PPI channel 31. */
bogdanm	0:9b334a45a8ff	4073	#define PPI_CHENSET_CH31_Pos (31UL) /!< Position of CH31 field. /
bogdanm	0:9b334a45a8ff	4074	#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /!< Bit mask of CH31 field. /
bogdanm	0:9b334a45a8ff	4075	#define PPI_CHENSET_CH31_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4076	#define PPI_CHENSET_CH31_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4077	#define PPI_CHENSET_CH31_Set (1UL) /!< Enable channel on write. /
bogdanm	0:9b334a45a8ff	4078
bogdanm	0:9b334a45a8ff	4079	/* Bit 30 : Enable PPI channel 30. */
bogdanm	0:9b334a45a8ff	4080	#define PPI_CHENSET_CH30_Pos (30UL) /!< Position of CH30 field. /
bogdanm	0:9b334a45a8ff	4081	#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /!< Bit mask of CH30 field. /
bogdanm	0:9b334a45a8ff	4082	#define PPI_CHENSET_CH30_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4083	#define PPI_CHENSET_CH30_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4084	#define PPI_CHENSET_CH30_Set (1UL) /!< Enable channel on write. /
bogdanm	0:9b334a45a8ff	4085
bogdanm	0:9b334a45a8ff	4086	/* Bit 29 : Enable PPI channel 29. */
bogdanm	0:9b334a45a8ff	4087	#define PPI_CHENSET_CH29_Pos (29UL) /!< Position of CH29 field. /
bogdanm	0:9b334a45a8ff	4088	#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /!< Bit mask of CH29 field. /
bogdanm	0:9b334a45a8ff	4089	#define PPI_CHENSET_CH29_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4090	#define PPI_CHENSET_CH29_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4091	#define PPI_CHENSET_CH29_Set (1UL) /!< Enable channel on write. /
bogdanm	0:9b334a45a8ff	4092
bogdanm	0:9b334a45a8ff	4093	/* Bit 28 : Enable PPI channel 28. */
bogdanm	0:9b334a45a8ff	4094	#define PPI_CHENSET_CH28_Pos (28UL) /!< Position of CH28 field. /
bogdanm	0:9b334a45a8ff	4095	#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /!< Bit mask of CH28 field. /
bogdanm	0:9b334a45a8ff	4096	#define PPI_CHENSET_CH28_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4097	#define PPI_CHENSET_CH28_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4098	#define PPI_CHENSET_CH28_Set (1UL) /!< Enable channel on write. /
bogdanm	0:9b334a45a8ff	4099
bogdanm	0:9b334a45a8ff	4100	/* Bit 27 : Enable PPI channel 27. */
bogdanm	0:9b334a45a8ff	4101	#define PPI_CHENSET_CH27_Pos (27UL) /!< Position of CH27 field. /
bogdanm	0:9b334a45a8ff	4102	#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /!< Bit mask of CH27 field. /
bogdanm	0:9b334a45a8ff	4103	#define PPI_CHENSET_CH27_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4104	#define PPI_CHENSET_CH27_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4105	#define PPI_CHENSET_CH27_Set (1UL) /!< Enable channel on write. /
bogdanm	0:9b334a45a8ff	4106
bogdanm	0:9b334a45a8ff	4107	/* Bit 26 : Enable PPI channel 26. */
bogdanm	0:9b334a45a8ff	4108	#define PPI_CHENSET_CH26_Pos (26UL) /!< Position of CH26 field. /
bogdanm	0:9b334a45a8ff	4109	#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /!< Bit mask of CH26 field. /
bogdanm	0:9b334a45a8ff	4110	#define PPI_CHENSET_CH26_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4111	#define PPI_CHENSET_CH26_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4112	#define PPI_CHENSET_CH26_Set (1UL) /!< Enable channel on write. /
bogdanm	0:9b334a45a8ff	4113
bogdanm	0:9b334a45a8ff	4114	/* Bit 25 : Enable PPI channel 25. */
bogdanm	0:9b334a45a8ff	4115	#define PPI_CHENSET_CH25_Pos (25UL) /!< Position of CH25 field. /
bogdanm	0:9b334a45a8ff	4116	#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /!< Bit mask of CH25 field. /
bogdanm	0:9b334a45a8ff	4117	#define PPI_CHENSET_CH25_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4118	#define PPI_CHENSET_CH25_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4119	#define PPI_CHENSET_CH25_Set (1UL) /!< Enable channel on write. /
bogdanm	0:9b334a45a8ff	4120
bogdanm	0:9b334a45a8ff	4121	/* Bit 24 : Enable PPI channel 24. */
bogdanm	0:9b334a45a8ff	4122	#define PPI_CHENSET_CH24_Pos (24UL) /!< Position of CH24 field. /
bogdanm	0:9b334a45a8ff	4123	#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /!< Bit mask of CH24 field. /
bogdanm	0:9b334a45a8ff	4124	#define PPI_CHENSET_CH24_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4125	#define PPI_CHENSET_CH24_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4126	#define PPI_CHENSET_CH24_Set (1UL) /!< Enable channel on write. /
bogdanm	0:9b334a45a8ff	4127
bogdanm	0:9b334a45a8ff	4128	/* Bit 23 : Enable PPI channel 23. */
bogdanm	0:9b334a45a8ff	4129	#define PPI_CHENSET_CH23_Pos (23UL) /!< Position of CH23 field. /
bogdanm	0:9b334a45a8ff	4130	#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /!< Bit mask of CH23 field. /
bogdanm	0:9b334a45a8ff	4131	#define PPI_CHENSET_CH23_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4132	#define PPI_CHENSET_CH23_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4133	#define PPI_CHENSET_CH23_Set (1UL) /!< Enable channel on write. /
bogdanm	0:9b334a45a8ff	4134
bogdanm	0:9b334a45a8ff	4135	/* Bit 22 : Enable PPI channel 22. */
bogdanm	0:9b334a45a8ff	4136	#define PPI_CHENSET_CH22_Pos (22UL) /!< Position of CH22 field. /
bogdanm	0:9b334a45a8ff	4137	#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /!< Bit mask of CH22 field. /
bogdanm	0:9b334a45a8ff	4138	#define PPI_CHENSET_CH22_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4139	#define PPI_CHENSET_CH22_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4140	#define PPI_CHENSET_CH22_Set (1UL) /!< Enable channel on write. /
bogdanm	0:9b334a45a8ff	4141
bogdanm	0:9b334a45a8ff	4142	/* Bit 21 : Enable PPI channel 21. */
bogdanm	0:9b334a45a8ff	4143	#define PPI_CHENSET_CH21_Pos (21UL) /!< Position of CH21 field. /
bogdanm	0:9b334a45a8ff	4144	#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /!< Bit mask of CH21 field. /
bogdanm	0:9b334a45a8ff	4145	#define PPI_CHENSET_CH21_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4146	#define PPI_CHENSET_CH21_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4147	#define PPI_CHENSET_CH21_Set (1UL) /!< Enable channel on write. /
bogdanm	0:9b334a45a8ff	4148
bogdanm	0:9b334a45a8ff	4149	/* Bit 20 : Enable PPI channel 20. */
bogdanm	0:9b334a45a8ff	4150	#define PPI_CHENSET_CH20_Pos (20UL) /!< Position of CH20 field. /
bogdanm	0:9b334a45a8ff	4151	#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /!< Bit mask of CH20 field. /
bogdanm	0:9b334a45a8ff	4152	#define PPI_CHENSET_CH20_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4153	#define PPI_CHENSET_CH20_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4154	#define PPI_CHENSET_CH20_Set (1UL) /!< Enable channel on write. /
bogdanm	0:9b334a45a8ff	4155
bogdanm	0:9b334a45a8ff	4156	/* Bit 15 : Enable PPI channel 15. */
bogdanm	0:9b334a45a8ff	4157	#define PPI_CHENSET_CH15_Pos (15UL) /!< Position of CH15 field. /
bogdanm	0:9b334a45a8ff	4158	#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /!< Bit mask of CH15 field. /
bogdanm	0:9b334a45a8ff	4159	#define PPI_CHENSET_CH15_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4160	#define PPI_CHENSET_CH15_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4161	#define PPI_CHENSET_CH15_Set (1UL) /!< Enable channel on write. /
bogdanm	0:9b334a45a8ff	4162
bogdanm	0:9b334a45a8ff	4163	/* Bit 14 : Enable PPI channel 14. */
bogdanm	0:9b334a45a8ff	4164	#define PPI_CHENSET_CH14_Pos (14UL) /!< Position of CH14 field. /
bogdanm	0:9b334a45a8ff	4165	#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /!< Bit mask of CH14 field. /
bogdanm	0:9b334a45a8ff	4166	#define PPI_CHENSET_CH14_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4167	#define PPI_CHENSET_CH14_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4168	#define PPI_CHENSET_CH14_Set (1UL) /!< Enable channel on write. /
bogdanm	0:9b334a45a8ff	4169
bogdanm	0:9b334a45a8ff	4170	/* Bit 13 : Enable PPI channel 13. */
bogdanm	0:9b334a45a8ff	4171	#define PPI_CHENSET_CH13_Pos (13UL) /!< Position of CH13 field. /
bogdanm	0:9b334a45a8ff	4172	#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /!< Bit mask of CH13 field. /
bogdanm	0:9b334a45a8ff	4173	#define PPI_CHENSET_CH13_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4174	#define PPI_CHENSET_CH13_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4175	#define PPI_CHENSET_CH13_Set (1UL) /!< Enable channel on write. /
bogdanm	0:9b334a45a8ff	4176
bogdanm	0:9b334a45a8ff	4177	/* Bit 12 : Enable PPI channel 12. */
bogdanm	0:9b334a45a8ff	4178	#define PPI_CHENSET_CH12_Pos (12UL) /!< Position of CH12 field. /
bogdanm	0:9b334a45a8ff	4179	#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /!< Bit mask of CH12 field. /
bogdanm	0:9b334a45a8ff	4180	#define PPI_CHENSET_CH12_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4181	#define PPI_CHENSET_CH12_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4182	#define PPI_CHENSET_CH12_Set (1UL) /!< Enable channel on write. /
bogdanm	0:9b334a45a8ff	4183
bogdanm	0:9b334a45a8ff	4184	/* Bit 11 : Enable PPI channel 11. */
bogdanm	0:9b334a45a8ff	4185	#define PPI_CHENSET_CH11_Pos (11UL) /!< Position of CH11 field. /
bogdanm	0:9b334a45a8ff	4186	#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /!< Bit mask of CH11 field. /
bogdanm	0:9b334a45a8ff	4187	#define PPI_CHENSET_CH11_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4188	#define PPI_CHENSET_CH11_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4189	#define PPI_CHENSET_CH11_Set (1UL) /!< Enable channel on write. /
bogdanm	0:9b334a45a8ff	4190
bogdanm	0:9b334a45a8ff	4191	/* Bit 10 : Enable PPI channel 10. */
bogdanm	0:9b334a45a8ff	4192	#define PPI_CHENSET_CH10_Pos (10UL) /!< Position of CH10 field. /
bogdanm	0:9b334a45a8ff	4193	#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /!< Bit mask of CH10 field. /
bogdanm	0:9b334a45a8ff	4194	#define PPI_CHENSET_CH10_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4195	#define PPI_CHENSET_CH10_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4196	#define PPI_CHENSET_CH10_Set (1UL) /!< Enable channel on write. /
bogdanm	0:9b334a45a8ff	4197
bogdanm	0:9b334a45a8ff	4198	/* Bit 9 : Enable PPI channel 9. */
bogdanm	0:9b334a45a8ff	4199	#define PPI_CHENSET_CH9_Pos (9UL) /!< Position of CH9 field. /
bogdanm	0:9b334a45a8ff	4200	#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /!< Bit mask of CH9 field. /
bogdanm	0:9b334a45a8ff	4201	#define PPI_CHENSET_CH9_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4202	#define PPI_CHENSET_CH9_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4203	#define PPI_CHENSET_CH9_Set (1UL) /!< Enable channel on write. /
bogdanm	0:9b334a45a8ff	4204
bogdanm	0:9b334a45a8ff	4205	/* Bit 8 : Enable PPI channel 8. */
bogdanm	0:9b334a45a8ff	4206	#define PPI_CHENSET_CH8_Pos (8UL) /!< Position of CH8 field. /
bogdanm	0:9b334a45a8ff	4207	#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /!< Bit mask of CH8 field. /
bogdanm	0:9b334a45a8ff	4208	#define PPI_CHENSET_CH8_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4209	#define PPI_CHENSET_CH8_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4210	#define PPI_CHENSET_CH8_Set (1UL) /!< Enable channel on write. /
bogdanm	0:9b334a45a8ff	4211
bogdanm	0:9b334a45a8ff	4212	/* Bit 7 : Enable PPI channel 7. */
bogdanm	0:9b334a45a8ff	4213	#define PPI_CHENSET_CH7_Pos (7UL) /!< Position of CH7 field. /
bogdanm	0:9b334a45a8ff	4214	#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /!< Bit mask of CH7 field. /
bogdanm	0:9b334a45a8ff	4215	#define PPI_CHENSET_CH7_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4216	#define PPI_CHENSET_CH7_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4217	#define PPI_CHENSET_CH7_Set (1UL) /!< Enable channel on write. /
bogdanm	0:9b334a45a8ff	4218
bogdanm	0:9b334a45a8ff	4219	/* Bit 6 : Enable PPI channel 6. */
bogdanm	0:9b334a45a8ff	4220	#define PPI_CHENSET_CH6_Pos (6UL) /!< Position of CH6 field. /
bogdanm	0:9b334a45a8ff	4221	#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /!< Bit mask of CH6 field. /
bogdanm	0:9b334a45a8ff	4222	#define PPI_CHENSET_CH6_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4223	#define PPI_CHENSET_CH6_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4224	#define PPI_CHENSET_CH6_Set (1UL) /!< Enable channel on write. /
bogdanm	0:9b334a45a8ff	4225
bogdanm	0:9b334a45a8ff	4226	/* Bit 5 : Enable PPI channel 5. */
bogdanm	0:9b334a45a8ff	4227	#define PPI_CHENSET_CH5_Pos (5UL) /!< Position of CH5 field. /
bogdanm	0:9b334a45a8ff	4228	#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /!< Bit mask of CH5 field. /
bogdanm	0:9b334a45a8ff	4229	#define PPI_CHENSET_CH5_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4230	#define PPI_CHENSET_CH5_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4231	#define PPI_CHENSET_CH5_Set (1UL) /!< Enable channel on write. /
bogdanm	0:9b334a45a8ff	4232
bogdanm	0:9b334a45a8ff	4233	/* Bit 4 : Enable PPI channel 4. */
bogdanm	0:9b334a45a8ff	4234	#define PPI_CHENSET_CH4_Pos (4UL) /!< Position of CH4 field. /
bogdanm	0:9b334a45a8ff	4235	#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /!< Bit mask of CH4 field. /
bogdanm	0:9b334a45a8ff	4236	#define PPI_CHENSET_CH4_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4237	#define PPI_CHENSET_CH4_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4238	#define PPI_CHENSET_CH4_Set (1UL) /!< Enable channel on write. /
bogdanm	0:9b334a45a8ff	4239
bogdanm	0:9b334a45a8ff	4240	/* Bit 3 : Enable PPI channel 3. */
bogdanm	0:9b334a45a8ff	4241	#define PPI_CHENSET_CH3_Pos (3UL) /!< Position of CH3 field. /
bogdanm	0:9b334a45a8ff	4242	#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /!< Bit mask of CH3 field. /
bogdanm	0:9b334a45a8ff	4243	#define PPI_CHENSET_CH3_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4244	#define PPI_CHENSET_CH3_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4245	#define PPI_CHENSET_CH3_Set (1UL) /!< Enable channel on write. /
bogdanm	0:9b334a45a8ff	4246
bogdanm	0:9b334a45a8ff	4247	/* Bit 2 : Enable PPI channel 2. */
bogdanm	0:9b334a45a8ff	4248	#define PPI_CHENSET_CH2_Pos (2UL) /!< Position of CH2 field. /
bogdanm	0:9b334a45a8ff	4249	#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /!< Bit mask of CH2 field. /
bogdanm	0:9b334a45a8ff	4250	#define PPI_CHENSET_CH2_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4251	#define PPI_CHENSET_CH2_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4252	#define PPI_CHENSET_CH2_Set (1UL) /!< Enable channel on write. /
bogdanm	0:9b334a45a8ff	4253
bogdanm	0:9b334a45a8ff	4254	/* Bit 1 : Enable PPI channel 1. */
bogdanm	0:9b334a45a8ff	4255	#define PPI_CHENSET_CH1_Pos (1UL) /!< Position of CH1 field. /
bogdanm	0:9b334a45a8ff	4256	#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /!< Bit mask of CH1 field. /
bogdanm	0:9b334a45a8ff	4257	#define PPI_CHENSET_CH1_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4258	#define PPI_CHENSET_CH1_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4259	#define PPI_CHENSET_CH1_Set (1UL) /!< Enable channel on write. /
bogdanm	0:9b334a45a8ff	4260
bogdanm	0:9b334a45a8ff	4261	/* Bit 0 : Enable PPI channel 0. */
bogdanm	0:9b334a45a8ff	4262	#define PPI_CHENSET_CH0_Pos (0UL) /!< Position of CH0 field. /
bogdanm	0:9b334a45a8ff	4263	#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /!< Bit mask of CH0 field. /
bogdanm	0:9b334a45a8ff	4264	#define PPI_CHENSET_CH0_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4265	#define PPI_CHENSET_CH0_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4266	#define PPI_CHENSET_CH0_Set (1UL) /!< Enable channel on write. /
bogdanm	0:9b334a45a8ff	4267
bogdanm	0:9b334a45a8ff	4268	/* Register: PPI_CHENCLR */
bogdanm	0:9b334a45a8ff	4269	/* Description: Channel enable clear. */
bogdanm	0:9b334a45a8ff	4270
bogdanm	0:9b334a45a8ff	4271	/* Bit 31 : Disable PPI channel 31. */
bogdanm	0:9b334a45a8ff	4272	#define PPI_CHENCLR_CH31_Pos (31UL) /!< Position of CH31 field. /
bogdanm	0:9b334a45a8ff	4273	#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /!< Bit mask of CH31 field. /
bogdanm	0:9b334a45a8ff	4274	#define PPI_CHENCLR_CH31_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4275	#define PPI_CHENCLR_CH31_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4276	#define PPI_CHENCLR_CH31_Clear (1UL) /!< Disable channel on write. /
bogdanm	0:9b334a45a8ff	4277
bogdanm	0:9b334a45a8ff	4278	/* Bit 30 : Disable PPI channel 30. */
bogdanm	0:9b334a45a8ff	4279	#define PPI_CHENCLR_CH30_Pos (30UL) /!< Position of CH30 field. /
bogdanm	0:9b334a45a8ff	4280	#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /!< Bit mask of CH30 field. /
bogdanm	0:9b334a45a8ff	4281	#define PPI_CHENCLR_CH30_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4282	#define PPI_CHENCLR_CH30_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4283	#define PPI_CHENCLR_CH30_Clear (1UL) /!< Disable channel on write. /
bogdanm	0:9b334a45a8ff	4284
bogdanm	0:9b334a45a8ff	4285	/* Bit 29 : Disable PPI channel 29. */
bogdanm	0:9b334a45a8ff	4286	#define PPI_CHENCLR_CH29_Pos (29UL) /!< Position of CH29 field. /
bogdanm	0:9b334a45a8ff	4287	#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /!< Bit mask of CH29 field. /
bogdanm	0:9b334a45a8ff	4288	#define PPI_CHENCLR_CH29_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4289	#define PPI_CHENCLR_CH29_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4290	#define PPI_CHENCLR_CH29_Clear (1UL) /!< Disable channel on write. /
bogdanm	0:9b334a45a8ff	4291
bogdanm	0:9b334a45a8ff	4292	/* Bit 28 : Disable PPI channel 28. */
bogdanm	0:9b334a45a8ff	4293	#define PPI_CHENCLR_CH28_Pos (28UL) /!< Position of CH28 field. /
bogdanm	0:9b334a45a8ff	4294	#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /!< Bit mask of CH28 field. /
bogdanm	0:9b334a45a8ff	4295	#define PPI_CHENCLR_CH28_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4296	#define PPI_CHENCLR_CH28_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4297	#define PPI_CHENCLR_CH28_Clear (1UL) /!< Disable channel on write. /
bogdanm	0:9b334a45a8ff	4298
bogdanm	0:9b334a45a8ff	4299	/* Bit 27 : Disable PPI channel 27. */
bogdanm	0:9b334a45a8ff	4300	#define PPI_CHENCLR_CH27_Pos (27UL) /!< Position of CH27 field. /
bogdanm	0:9b334a45a8ff	4301	#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /!< Bit mask of CH27 field. /
bogdanm	0:9b334a45a8ff	4302	#define PPI_CHENCLR_CH27_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4303	#define PPI_CHENCLR_CH27_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4304	#define PPI_CHENCLR_CH27_Clear (1UL) /!< Disable channel on write. /
bogdanm	0:9b334a45a8ff	4305
bogdanm	0:9b334a45a8ff	4306	/* Bit 26 : Disable PPI channel 26. */
bogdanm	0:9b334a45a8ff	4307	#define PPI_CHENCLR_CH26_Pos (26UL) /!< Position of CH26 field. /
bogdanm	0:9b334a45a8ff	4308	#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /!< Bit mask of CH26 field. /
bogdanm	0:9b334a45a8ff	4309	#define PPI_CHENCLR_CH26_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4310	#define PPI_CHENCLR_CH26_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4311	#define PPI_CHENCLR_CH26_Clear (1UL) /!< Disable channel on write. /
bogdanm	0:9b334a45a8ff	4312
bogdanm	0:9b334a45a8ff	4313	/* Bit 25 : Disable PPI channel 25. */
bogdanm	0:9b334a45a8ff	4314	#define PPI_CHENCLR_CH25_Pos (25UL) /!< Position of CH25 field. /
bogdanm	0:9b334a45a8ff	4315	#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /!< Bit mask of CH25 field. /
bogdanm	0:9b334a45a8ff	4316	#define PPI_CHENCLR_CH25_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4317	#define PPI_CHENCLR_CH25_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4318	#define PPI_CHENCLR_CH25_Clear (1UL) /!< Disable channel on write. /
bogdanm	0:9b334a45a8ff	4319
bogdanm	0:9b334a45a8ff	4320	/* Bit 24 : Disable PPI channel 24. */
bogdanm	0:9b334a45a8ff	4321	#define PPI_CHENCLR_CH24_Pos (24UL) /!< Position of CH24 field. /
bogdanm	0:9b334a45a8ff	4322	#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /!< Bit mask of CH24 field. /
bogdanm	0:9b334a45a8ff	4323	#define PPI_CHENCLR_CH24_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4324	#define PPI_CHENCLR_CH24_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4325	#define PPI_CHENCLR_CH24_Clear (1UL) /!< Disable channel on write. /
bogdanm	0:9b334a45a8ff	4326
bogdanm	0:9b334a45a8ff	4327	/* Bit 23 : Disable PPI channel 23. */
bogdanm	0:9b334a45a8ff	4328	#define PPI_CHENCLR_CH23_Pos (23UL) /!< Position of CH23 field. /
bogdanm	0:9b334a45a8ff	4329	#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /!< Bit mask of CH23 field. /
bogdanm	0:9b334a45a8ff	4330	#define PPI_CHENCLR_CH23_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4331	#define PPI_CHENCLR_CH23_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4332	#define PPI_CHENCLR_CH23_Clear (1UL) /!< Disable channel on write. /
bogdanm	0:9b334a45a8ff	4333
bogdanm	0:9b334a45a8ff	4334	/* Bit 22 : Disable PPI channel 22. */
bogdanm	0:9b334a45a8ff	4335	#define PPI_CHENCLR_CH22_Pos (22UL) /!< Position of CH22 field. /
bogdanm	0:9b334a45a8ff	4336	#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /!< Bit mask of CH22 field. /
bogdanm	0:9b334a45a8ff	4337	#define PPI_CHENCLR_CH22_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4338	#define PPI_CHENCLR_CH22_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4339	#define PPI_CHENCLR_CH22_Clear (1UL) /!< Disable channel on write. /
bogdanm	0:9b334a45a8ff	4340
bogdanm	0:9b334a45a8ff	4341	/* Bit 21 : Disable PPI channel 21. */
bogdanm	0:9b334a45a8ff	4342	#define PPI_CHENCLR_CH21_Pos (21UL) /!< Position of CH21 field. /
bogdanm	0:9b334a45a8ff	4343	#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /!< Bit mask of CH21 field. /
bogdanm	0:9b334a45a8ff	4344	#define PPI_CHENCLR_CH21_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4345	#define PPI_CHENCLR_CH21_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4346	#define PPI_CHENCLR_CH21_Clear (1UL) /!< Disable channel on write. /
bogdanm	0:9b334a45a8ff	4347
bogdanm	0:9b334a45a8ff	4348	/* Bit 20 : Disable PPI channel 20. */
bogdanm	0:9b334a45a8ff	4349	#define PPI_CHENCLR_CH20_Pos (20UL) /!< Position of CH20 field. /
bogdanm	0:9b334a45a8ff	4350	#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /!< Bit mask of CH20 field. /
bogdanm	0:9b334a45a8ff	4351	#define PPI_CHENCLR_CH20_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4352	#define PPI_CHENCLR_CH20_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4353	#define PPI_CHENCLR_CH20_Clear (1UL) /!< Disable channel on write. /
bogdanm	0:9b334a45a8ff	4354
bogdanm	0:9b334a45a8ff	4355	/* Bit 15 : Disable PPI channel 15. */
bogdanm	0:9b334a45a8ff	4356	#define PPI_CHENCLR_CH15_Pos (15UL) /!< Position of CH15 field. /
bogdanm	0:9b334a45a8ff	4357	#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /!< Bit mask of CH15 field. /
bogdanm	0:9b334a45a8ff	4358	#define PPI_CHENCLR_CH15_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4359	#define PPI_CHENCLR_CH15_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4360	#define PPI_CHENCLR_CH15_Clear (1UL) /!< Disable channel on write. /
bogdanm	0:9b334a45a8ff	4361
bogdanm	0:9b334a45a8ff	4362	/* Bit 14 : Disable PPI channel 14. */
bogdanm	0:9b334a45a8ff	4363	#define PPI_CHENCLR_CH14_Pos (14UL) /!< Position of CH14 field. /
bogdanm	0:9b334a45a8ff	4364	#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /!< Bit mask of CH14 field. /
bogdanm	0:9b334a45a8ff	4365	#define PPI_CHENCLR_CH14_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4366	#define PPI_CHENCLR_CH14_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4367	#define PPI_CHENCLR_CH14_Clear (1UL) /!< Disable channel on write. /
bogdanm	0:9b334a45a8ff	4368
bogdanm	0:9b334a45a8ff	4369	/* Bit 13 : Disable PPI channel 13. */
bogdanm	0:9b334a45a8ff	4370	#define PPI_CHENCLR_CH13_Pos (13UL) /!< Position of CH13 field. /
bogdanm	0:9b334a45a8ff	4371	#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /!< Bit mask of CH13 field. /
bogdanm	0:9b334a45a8ff	4372	#define PPI_CHENCLR_CH13_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4373	#define PPI_CHENCLR_CH13_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4374	#define PPI_CHENCLR_CH13_Clear (1UL) /!< Disable channel on write. /
bogdanm	0:9b334a45a8ff	4375
bogdanm	0:9b334a45a8ff	4376	/* Bit 12 : Disable PPI channel 12. */
bogdanm	0:9b334a45a8ff	4377	#define PPI_CHENCLR_CH12_Pos (12UL) /!< Position of CH12 field. /
bogdanm	0:9b334a45a8ff	4378	#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /!< Bit mask of CH12 field. /
bogdanm	0:9b334a45a8ff	4379	#define PPI_CHENCLR_CH12_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4380	#define PPI_CHENCLR_CH12_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4381	#define PPI_CHENCLR_CH12_Clear (1UL) /!< Disable channel on write. /
bogdanm	0:9b334a45a8ff	4382
bogdanm	0:9b334a45a8ff	4383	/* Bit 11 : Disable PPI channel 11. */
bogdanm	0:9b334a45a8ff	4384	#define PPI_CHENCLR_CH11_Pos (11UL) /!< Position of CH11 field. /
bogdanm	0:9b334a45a8ff	4385	#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /!< Bit mask of CH11 field. /
bogdanm	0:9b334a45a8ff	4386	#define PPI_CHENCLR_CH11_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4387	#define PPI_CHENCLR_CH11_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4388	#define PPI_CHENCLR_CH11_Clear (1UL) /!< Disable channel on write. /
bogdanm	0:9b334a45a8ff	4389
bogdanm	0:9b334a45a8ff	4390	/* Bit 10 : Disable PPI channel 10. */
bogdanm	0:9b334a45a8ff	4391	#define PPI_CHENCLR_CH10_Pos (10UL) /!< Position of CH10 field. /
bogdanm	0:9b334a45a8ff	4392	#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /!< Bit mask of CH10 field. /
bogdanm	0:9b334a45a8ff	4393	#define PPI_CHENCLR_CH10_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4394	#define PPI_CHENCLR_CH10_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4395	#define PPI_CHENCLR_CH10_Clear (1UL) /!< Disable channel on write. /
bogdanm	0:9b334a45a8ff	4396
bogdanm	0:9b334a45a8ff	4397	/* Bit 9 : Disable PPI channel 9. */
bogdanm	0:9b334a45a8ff	4398	#define PPI_CHENCLR_CH9_Pos (9UL) /!< Position of CH9 field. /
bogdanm	0:9b334a45a8ff	4399	#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /!< Bit mask of CH9 field. /
bogdanm	0:9b334a45a8ff	4400	#define PPI_CHENCLR_CH9_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4401	#define PPI_CHENCLR_CH9_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4402	#define PPI_CHENCLR_CH9_Clear (1UL) /!< Disable channel on write. /
bogdanm	0:9b334a45a8ff	4403
bogdanm	0:9b334a45a8ff	4404	/* Bit 8 : Disable PPI channel 8. */
bogdanm	0:9b334a45a8ff	4405	#define PPI_CHENCLR_CH8_Pos (8UL) /!< Position of CH8 field. /
bogdanm	0:9b334a45a8ff	4406	#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /!< Bit mask of CH8 field. /
bogdanm	0:9b334a45a8ff	4407	#define PPI_CHENCLR_CH8_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4408	#define PPI_CHENCLR_CH8_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4409	#define PPI_CHENCLR_CH8_Clear (1UL) /!< Disable channel on write. /
bogdanm	0:9b334a45a8ff	4410
bogdanm	0:9b334a45a8ff	4411	/* Bit 7 : Disable PPI channel 7. */
bogdanm	0:9b334a45a8ff	4412	#define PPI_CHENCLR_CH7_Pos (7UL) /!< Position of CH7 field. /
bogdanm	0:9b334a45a8ff	4413	#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /!< Bit mask of CH7 field. /
bogdanm	0:9b334a45a8ff	4414	#define PPI_CHENCLR_CH7_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4415	#define PPI_CHENCLR_CH7_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4416	#define PPI_CHENCLR_CH7_Clear (1UL) /!< Disable channel on write. /
bogdanm	0:9b334a45a8ff	4417
bogdanm	0:9b334a45a8ff	4418	/* Bit 6 : Disable PPI channel 6. */
bogdanm	0:9b334a45a8ff	4419	#define PPI_CHENCLR_CH6_Pos (6UL) /!< Position of CH6 field. /
bogdanm	0:9b334a45a8ff	4420	#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /!< Bit mask of CH6 field. /
bogdanm	0:9b334a45a8ff	4421	#define PPI_CHENCLR_CH6_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4422	#define PPI_CHENCLR_CH6_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4423	#define PPI_CHENCLR_CH6_Clear (1UL) /!< Disable channel on write. /
bogdanm	0:9b334a45a8ff	4424
bogdanm	0:9b334a45a8ff	4425	/* Bit 5 : Disable PPI channel 5. */
bogdanm	0:9b334a45a8ff	4426	#define PPI_CHENCLR_CH5_Pos (5UL) /!< Position of CH5 field. /
bogdanm	0:9b334a45a8ff	4427	#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /!< Bit mask of CH5 field. /
bogdanm	0:9b334a45a8ff	4428	#define PPI_CHENCLR_CH5_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4429	#define PPI_CHENCLR_CH5_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4430	#define PPI_CHENCLR_CH5_Clear (1UL) /!< Disable channel on write. /
bogdanm	0:9b334a45a8ff	4431
bogdanm	0:9b334a45a8ff	4432	/* Bit 4 : Disable PPI channel 4. */
bogdanm	0:9b334a45a8ff	4433	#define PPI_CHENCLR_CH4_Pos (4UL) /!< Position of CH4 field. /
bogdanm	0:9b334a45a8ff	4434	#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /!< Bit mask of CH4 field. /
bogdanm	0:9b334a45a8ff	4435	#define PPI_CHENCLR_CH4_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4436	#define PPI_CHENCLR_CH4_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4437	#define PPI_CHENCLR_CH4_Clear (1UL) /!< Disable channel on write. /
bogdanm	0:9b334a45a8ff	4438
bogdanm	0:9b334a45a8ff	4439	/* Bit 3 : Disable PPI channel 3. */
bogdanm	0:9b334a45a8ff	4440	#define PPI_CHENCLR_CH3_Pos (3UL) /!< Position of CH3 field. /
bogdanm	0:9b334a45a8ff	4441	#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /!< Bit mask of CH3 field. /
bogdanm	0:9b334a45a8ff	4442	#define PPI_CHENCLR_CH3_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4443	#define PPI_CHENCLR_CH3_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4444	#define PPI_CHENCLR_CH3_Clear (1UL) /!< Disable channel on write. /
bogdanm	0:9b334a45a8ff	4445
bogdanm	0:9b334a45a8ff	4446	/* Bit 2 : Disable PPI channel 2. */
bogdanm	0:9b334a45a8ff	4447	#define PPI_CHENCLR_CH2_Pos (2UL) /!< Position of CH2 field. /
bogdanm	0:9b334a45a8ff	4448	#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /!< Bit mask of CH2 field. /
bogdanm	0:9b334a45a8ff	4449	#define PPI_CHENCLR_CH2_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4450	#define PPI_CHENCLR_CH2_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4451	#define PPI_CHENCLR_CH2_Clear (1UL) /!< Disable channel on write. /
bogdanm	0:9b334a45a8ff	4452
bogdanm	0:9b334a45a8ff	4453	/* Bit 1 : Disable PPI channel 1. */
bogdanm	0:9b334a45a8ff	4454	#define PPI_CHENCLR_CH1_Pos (1UL) /!< Position of CH1 field. /
bogdanm	0:9b334a45a8ff	4455	#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /!< Bit mask of CH1 field. /
bogdanm	0:9b334a45a8ff	4456	#define PPI_CHENCLR_CH1_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4457	#define PPI_CHENCLR_CH1_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4458	#define PPI_CHENCLR_CH1_Clear (1UL) /!< Disable channel on write. /
bogdanm	0:9b334a45a8ff	4459
bogdanm	0:9b334a45a8ff	4460	/* Bit 0 : Disable PPI channel 0. */
bogdanm	0:9b334a45a8ff	4461	#define PPI_CHENCLR_CH0_Pos (0UL) /!< Position of CH0 field. /
bogdanm	0:9b334a45a8ff	4462	#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /!< Bit mask of CH0 field. /
bogdanm	0:9b334a45a8ff	4463	#define PPI_CHENCLR_CH0_Disabled (0UL) /!< Channel disabled. /
bogdanm	0:9b334a45a8ff	4464	#define PPI_CHENCLR_CH0_Enabled (1UL) /!< Channel enabled. /
bogdanm	0:9b334a45a8ff	4465	#define PPI_CHENCLR_CH0_Clear (1UL) /!< Disable channel on write. /
bogdanm	0:9b334a45a8ff	4466
bogdanm	0:9b334a45a8ff	4467	/* Register: PPI_CHG */
bogdanm	0:9b334a45a8ff	4468	/* Description: Channel group configuration. */
bogdanm	0:9b334a45a8ff	4469
bogdanm	0:9b334a45a8ff	4470	/* Bit 31 : Include CH31 in channel group. */
bogdanm	0:9b334a45a8ff	4471	#define PPI_CHG_CH31_Pos (31UL) /!< Position of CH31 field. /
bogdanm	0:9b334a45a8ff	4472	#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /!< Bit mask of CH31 field. /
bogdanm	0:9b334a45a8ff	4473	#define PPI_CHG_CH31_Excluded (0UL) /!< Channel excluded. /
bogdanm	0:9b334a45a8ff	4474	#define PPI_CHG_CH31_Included (1UL) /!< Channel included. /
bogdanm	0:9b334a45a8ff	4475
bogdanm	0:9b334a45a8ff	4476	/* Bit 30 : Include CH30 in channel group. */
bogdanm	0:9b334a45a8ff	4477	#define PPI_CHG_CH30_Pos (30UL) /!< Position of CH30 field. /
bogdanm	0:9b334a45a8ff	4478	#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /!< Bit mask of CH30 field. /
bogdanm	0:9b334a45a8ff	4479	#define PPI_CHG_CH30_Excluded (0UL) /!< Channel excluded. /
bogdanm	0:9b334a45a8ff	4480	#define PPI_CHG_CH30_Included (1UL) /!< Channel included. /
bogdanm	0:9b334a45a8ff	4481
bogdanm	0:9b334a45a8ff	4482	/* Bit 29 : Include CH29 in channel group. */
bogdanm	0:9b334a45a8ff	4483	#define PPI_CHG_CH29_Pos (29UL) /!< Position of CH29 field. /
bogdanm	0:9b334a45a8ff	4484	#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /!< Bit mask of CH29 field. /
bogdanm	0:9b334a45a8ff	4485	#define PPI_CHG_CH29_Excluded (0UL) /!< Channel excluded. /
bogdanm	0:9b334a45a8ff	4486	#define PPI_CHG_CH29_Included (1UL) /!< Channel included. /
bogdanm	0:9b334a45a8ff	4487
bogdanm	0:9b334a45a8ff	4488	/* Bit 28 : Include CH28 in channel group. */
bogdanm	0:9b334a45a8ff	4489	#define PPI_CHG_CH28_Pos (28UL) /!< Position of CH28 field. /
bogdanm	0:9b334a45a8ff	4490	#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /!< Bit mask of CH28 field. /
bogdanm	0:9b334a45a8ff	4491	#define PPI_CHG_CH28_Excluded (0UL) /!< Channel excluded. /
bogdanm	0:9b334a45a8ff	4492	#define PPI_CHG_CH28_Included (1UL) /!< Channel included. /
bogdanm	0:9b334a45a8ff	4493
bogdanm	0:9b334a45a8ff	4494	/* Bit 27 : Include CH27 in channel group. */
bogdanm	0:9b334a45a8ff	4495	#define PPI_CHG_CH27_Pos (27UL) /!< Position of CH27 field. /
bogdanm	0:9b334a45a8ff	4496	#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /!< Bit mask of CH27 field. /
bogdanm	0:9b334a45a8ff	4497	#define PPI_CHG_CH27_Excluded (0UL) /!< Channel excluded. /
bogdanm	0:9b334a45a8ff	4498	#define PPI_CHG_CH27_Included (1UL) /!< Channel included. /
bogdanm	0:9b334a45a8ff	4499
bogdanm	0:9b334a45a8ff	4500	/* Bit 26 : Include CH26 in channel group. */
bogdanm	0:9b334a45a8ff	4501	#define PPI_CHG_CH26_Pos (26UL) /!< Position of CH26 field. /
bogdanm	0:9b334a45a8ff	4502	#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /!< Bit mask of CH26 field. /
bogdanm	0:9b334a45a8ff	4503	#define PPI_CHG_CH26_Excluded (0UL) /!< Channel excluded. /
bogdanm	0:9b334a45a8ff	4504	#define PPI_CHG_CH26_Included (1UL) /!< Channel included. /
bogdanm	0:9b334a45a8ff	4505
bogdanm	0:9b334a45a8ff	4506	/* Bit 25 : Include CH25 in channel group. */
bogdanm	0:9b334a45a8ff	4507	#define PPI_CHG_CH25_Pos (25UL) /!< Position of CH25 field. /
bogdanm	0:9b334a45a8ff	4508	#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /!< Bit mask of CH25 field. /
bogdanm	0:9b334a45a8ff	4509	#define PPI_CHG_CH25_Excluded (0UL) /!< Channel excluded. /
bogdanm	0:9b334a45a8ff	4510	#define PPI_CHG_CH25_Included (1UL) /!< Channel included. /
bogdanm	0:9b334a45a8ff	4511
bogdanm	0:9b334a45a8ff	4512	/* Bit 24 : Include CH24 in channel group. */
bogdanm	0:9b334a45a8ff	4513	#define PPI_CHG_CH24_Pos (24UL) /!< Position of CH24 field. /
bogdanm	0:9b334a45a8ff	4514	#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /!< Bit mask of CH24 field. /
bogdanm	0:9b334a45a8ff	4515	#define PPI_CHG_CH24_Excluded (0UL) /!< Channel excluded. /
bogdanm	0:9b334a45a8ff	4516	#define PPI_CHG_CH24_Included (1UL) /!< Channel included. /
bogdanm	0:9b334a45a8ff	4517
bogdanm	0:9b334a45a8ff	4518	/* Bit 23 : Include CH23 in channel group. */
bogdanm	0:9b334a45a8ff	4519	#define PPI_CHG_CH23_Pos (23UL) /!< Position of CH23 field. /
bogdanm	0:9b334a45a8ff	4520	#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /!< Bit mask of CH23 field. /
bogdanm	0:9b334a45a8ff	4521	#define PPI_CHG_CH23_Excluded (0UL) /!< Channel excluded. /
bogdanm	0:9b334a45a8ff	4522	#define PPI_CHG_CH23_Included (1UL) /!< Channel included. /
bogdanm	0:9b334a45a8ff	4523
bogdanm	0:9b334a45a8ff	4524	/* Bit 22 : Include CH22 in channel group. */
bogdanm	0:9b334a45a8ff	4525	#define PPI_CHG_CH22_Pos (22UL) /!< Position of CH22 field. /
bogdanm	0:9b334a45a8ff	4526	#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /!< Bit mask of CH22 field. /
bogdanm	0:9b334a45a8ff	4527	#define PPI_CHG_CH22_Excluded (0UL) /!< Channel excluded. /
bogdanm	0:9b334a45a8ff	4528	#define PPI_CHG_CH22_Included (1UL) /!< Channel included. /
bogdanm	0:9b334a45a8ff	4529
bogdanm	0:9b334a45a8ff	4530	/* Bit 21 : Include CH21 in channel group. */
bogdanm	0:9b334a45a8ff	4531	#define PPI_CHG_CH21_Pos (21UL) /!< Position of CH21 field. /
bogdanm	0:9b334a45a8ff	4532	#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /!< Bit mask of CH21 field. /
bogdanm	0:9b334a45a8ff	4533	#define PPI_CHG_CH21_Excluded (0UL) /!< Channel excluded. /
bogdanm	0:9b334a45a8ff	4534	#define PPI_CHG_CH21_Included (1UL) /!< Channel included. /
bogdanm	0:9b334a45a8ff	4535
bogdanm	0:9b334a45a8ff	4536	/* Bit 20 : Include CH20 in channel group. */
bogdanm	0:9b334a45a8ff	4537	#define PPI_CHG_CH20_Pos (20UL) /!< Position of CH20 field. /
bogdanm	0:9b334a45a8ff	4538	#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /!< Bit mask of CH20 field. /
bogdanm	0:9b334a45a8ff	4539	#define PPI_CHG_CH20_Excluded (0UL) /!< Channel excluded. /
bogdanm	0:9b334a45a8ff	4540	#define PPI_CHG_CH20_Included (1UL) /!< Channel included. /
bogdanm	0:9b334a45a8ff	4541
bogdanm	0:9b334a45a8ff	4542	/* Bit 15 : Include CH15 in channel group. */
bogdanm	0:9b334a45a8ff	4543	#define PPI_CHG_CH15_Pos (15UL) /!< Position of CH15 field. /
bogdanm	0:9b334a45a8ff	4544	#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /!< Bit mask of CH15 field. /
bogdanm	0:9b334a45a8ff	4545	#define PPI_CHG_CH15_Excluded (0UL) /!< Channel excluded. /
bogdanm	0:9b334a45a8ff	4546	#define PPI_CHG_CH15_Included (1UL) /!< Channel included. /
bogdanm	0:9b334a45a8ff	4547
bogdanm	0:9b334a45a8ff	4548	/* Bit 14 : Include CH14 in channel group. */
bogdanm	0:9b334a45a8ff	4549	#define PPI_CHG_CH14_Pos (14UL) /!< Position of CH14 field. /
bogdanm	0:9b334a45a8ff	4550	#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /!< Bit mask of CH14 field. /
bogdanm	0:9b334a45a8ff	4551	#define PPI_CHG_CH14_Excluded (0UL) /!< Channel excluded. /
bogdanm	0:9b334a45a8ff	4552	#define PPI_CHG_CH14_Included (1UL) /!< Channel included. /
bogdanm	0:9b334a45a8ff	4553
bogdanm	0:9b334a45a8ff	4554	/* Bit 13 : Include CH13 in channel group. */
bogdanm	0:9b334a45a8ff	4555	#define PPI_CHG_CH13_Pos (13UL) /!< Position of CH13 field. /
bogdanm	0:9b334a45a8ff	4556	#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /!< Bit mask of CH13 field. /
bogdanm	0:9b334a45a8ff	4557	#define PPI_CHG_CH13_Excluded (0UL) /!< Channel excluded. /
bogdanm	0:9b334a45a8ff	4558	#define PPI_CHG_CH13_Included (1UL) /!< Channel included. /
bogdanm	0:9b334a45a8ff	4559
bogdanm	0:9b334a45a8ff	4560	/* Bit 12 : Include CH12 in channel group. */
bogdanm	0:9b334a45a8ff	4561	#define PPI_CHG_CH12_Pos (12UL) /!< Position of CH12 field. /
bogdanm	0:9b334a45a8ff	4562	#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /!< Bit mask of CH12 field. /
bogdanm	0:9b334a45a8ff	4563	#define PPI_CHG_CH12_Excluded (0UL) /!< Channel excluded. /
bogdanm	0:9b334a45a8ff	4564	#define PPI_CHG_CH12_Included (1UL) /!< Channel included. /
bogdanm	0:9b334a45a8ff	4565
bogdanm	0:9b334a45a8ff	4566	/* Bit 11 : Include CH11 in channel group. */
bogdanm	0:9b334a45a8ff	4567	#define PPI_CHG_CH11_Pos (11UL) /!< Position of CH11 field. /
bogdanm	0:9b334a45a8ff	4568	#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /!< Bit mask of CH11 field. /
bogdanm	0:9b334a45a8ff	4569	#define PPI_CHG_CH11_Excluded (0UL) /!< Channel excluded. /
bogdanm	0:9b334a45a8ff	4570	#define PPI_CHG_CH11_Included (1UL) /!< Channel included. /
bogdanm	0:9b334a45a8ff	4571
bogdanm	0:9b334a45a8ff	4572	/* Bit 10 : Include CH10 in channel group. */
bogdanm	0:9b334a45a8ff	4573	#define PPI_CHG_CH10_Pos (10UL) /!< Position of CH10 field. /
bogdanm	0:9b334a45a8ff	4574	#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /!< Bit mask of CH10 field. /
bogdanm	0:9b334a45a8ff	4575	#define PPI_CHG_CH10_Excluded (0UL) /!< Channel excluded. /
bogdanm	0:9b334a45a8ff	4576	#define PPI_CHG_CH10_Included (1UL) /!< Channel included. /
bogdanm	0:9b334a45a8ff	4577
bogdanm	0:9b334a45a8ff	4578	/* Bit 9 : Include CH9 in channel group. */
bogdanm	0:9b334a45a8ff	4579	#define PPI_CHG_CH9_Pos (9UL) /!< Position of CH9 field. /
bogdanm	0:9b334a45a8ff	4580	#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /!< Bit mask of CH9 field. /
bogdanm	0:9b334a45a8ff	4581	#define PPI_CHG_CH9_Excluded (0UL) /!< Channel excluded. /
bogdanm	0:9b334a45a8ff	4582	#define PPI_CHG_CH9_Included (1UL) /!< Channel included. /
bogdanm	0:9b334a45a8ff	4583
bogdanm	0:9b334a45a8ff	4584	/* Bit 8 : Include CH8 in channel group. */
bogdanm	0:9b334a45a8ff	4585	#define PPI_CHG_CH8_Pos (8UL) /!< Position of CH8 field. /
bogdanm	0:9b334a45a8ff	4586	#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /!< Bit mask of CH8 field. /
bogdanm	0:9b334a45a8ff	4587	#define PPI_CHG_CH8_Excluded (0UL) /!< Channel excluded. /
bogdanm	0:9b334a45a8ff	4588	#define PPI_CHG_CH8_Included (1UL) /!< Channel included. /
bogdanm	0:9b334a45a8ff	4589
bogdanm	0:9b334a45a8ff	4590	/* Bit 7 : Include CH7 in channel group. */
bogdanm	0:9b334a45a8ff	4591	#define PPI_CHG_CH7_Pos (7UL) /!< Position of CH7 field. /
bogdanm	0:9b334a45a8ff	4592	#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /!< Bit mask of CH7 field. /
bogdanm	0:9b334a45a8ff	4593	#define PPI_CHG_CH7_Excluded (0UL) /!< Channel excluded. /
bogdanm	0:9b334a45a8ff	4594	#define PPI_CHG_CH7_Included (1UL) /!< Channel included. /
bogdanm	0:9b334a45a8ff	4595
bogdanm	0:9b334a45a8ff	4596	/* Bit 6 : Include CH6 in channel group. */
bogdanm	0:9b334a45a8ff	4597	#define PPI_CHG_CH6_Pos (6UL) /!< Position of CH6 field. /
bogdanm	0:9b334a45a8ff	4598	#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /!< Bit mask of CH6 field. /
bogdanm	0:9b334a45a8ff	4599	#define PPI_CHG_CH6_Excluded (0UL) /!< Channel excluded. /
bogdanm	0:9b334a45a8ff	4600	#define PPI_CHG_CH6_Included (1UL) /!< Channel included. /
bogdanm	0:9b334a45a8ff	4601
bogdanm	0:9b334a45a8ff	4602	/* Bit 5 : Include CH5 in channel group. */
bogdanm	0:9b334a45a8ff	4603	#define PPI_CHG_CH5_Pos (5UL) /!< Position of CH5 field. /
bogdanm	0:9b334a45a8ff	4604	#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /!< Bit mask of CH5 field. /
bogdanm	0:9b334a45a8ff	4605	#define PPI_CHG_CH5_Excluded (0UL) /!< Channel excluded. /
bogdanm	0:9b334a45a8ff	4606	#define PPI_CHG_CH5_Included (1UL) /!< Channel included. /
bogdanm	0:9b334a45a8ff	4607
bogdanm	0:9b334a45a8ff	4608	/* Bit 4 : Include CH4 in channel group. */
bogdanm	0:9b334a45a8ff	4609	#define PPI_CHG_CH4_Pos (4UL) /!< Position of CH4 field. /
bogdanm	0:9b334a45a8ff	4610	#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /!< Bit mask of CH4 field. /
bogdanm	0:9b334a45a8ff	4611	#define PPI_CHG_CH4_Excluded (0UL) /!< Channel excluded. /
bogdanm	0:9b334a45a8ff	4612	#define PPI_CHG_CH4_Included (1UL) /!< Channel included. /
bogdanm	0:9b334a45a8ff	4613
bogdanm	0:9b334a45a8ff	4614	/* Bit 3 : Include CH3 in channel group. */
bogdanm	0:9b334a45a8ff	4615	#define PPI_CHG_CH3_Pos (3UL) /!< Position of CH3 field. /
bogdanm	0:9b334a45a8ff	4616	#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /!< Bit mask of CH3 field. /
bogdanm	0:9b334a45a8ff	4617	#define PPI_CHG_CH3_Excluded (0UL) /!< Channel excluded. /
bogdanm	0:9b334a45a8ff	4618	#define PPI_CHG_CH3_Included (1UL) /!< Channel included. /
bogdanm	0:9b334a45a8ff	4619
bogdanm	0:9b334a45a8ff	4620	/* Bit 2 : Include CH2 in channel group. */
bogdanm	0:9b334a45a8ff	4621	#define PPI_CHG_CH2_Pos (2UL) /!< Position of CH2 field. /
bogdanm	0:9b334a45a8ff	4622	#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /!< Bit mask of CH2 field. /
bogdanm	0:9b334a45a8ff	4623	#define PPI_CHG_CH2_Excluded (0UL) /!< Channel excluded. /
bogdanm	0:9b334a45a8ff	4624	#define PPI_CHG_CH2_Included (1UL) /!< Channel included. /
bogdanm	0:9b334a45a8ff	4625
bogdanm	0:9b334a45a8ff	4626	/* Bit 1 : Include CH1 in channel group. */
bogdanm	0:9b334a45a8ff	4627	#define PPI_CHG_CH1_Pos (1UL) /!< Position of CH1 field. /
bogdanm	0:9b334a45a8ff	4628	#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /!< Bit mask of CH1 field. /
bogdanm	0:9b334a45a8ff	4629	#define PPI_CHG_CH1_Excluded (0UL) /!< Channel excluded. /
bogdanm	0:9b334a45a8ff	4630	#define PPI_CHG_CH1_Included (1UL) /!< Channel included. /
bogdanm	0:9b334a45a8ff	4631
bogdanm	0:9b334a45a8ff	4632	/* Bit 0 : Include CH0 in channel group. */
bogdanm	0:9b334a45a8ff	4633	#define PPI_CHG_CH0_Pos (0UL) /!< Position of CH0 field. /
bogdanm	0:9b334a45a8ff	4634	#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /!< Bit mask of CH0 field. /
bogdanm	0:9b334a45a8ff	4635	#define PPI_CHG_CH0_Excluded (0UL) /!< Channel excluded. /
bogdanm	0:9b334a45a8ff	4636	#define PPI_CHG_CH0_Included (1UL) /!< Channel included. /
bogdanm	0:9b334a45a8ff	4637
bogdanm	0:9b334a45a8ff	4638
bogdanm	0:9b334a45a8ff	4639	/* Peripheral: PU */
bogdanm	0:9b334a45a8ff	4640	/* Description: Patch unit. */
bogdanm	0:9b334a45a8ff	4641
bogdanm	0:9b334a45a8ff	4642	/* Register: PU_PATCHADDR */
bogdanm	0:9b334a45a8ff	4643	/* Description: Relative address of patch instructions. */
bogdanm	0:9b334a45a8ff	4644
bogdanm	0:9b334a45a8ff	4645	/* Bits 24..0 : Relative address of patch instructions. */
bogdanm	0:9b334a45a8ff	4646	#define PU_PATCHADDR_PATCHADDR_Pos (0UL) /!< Position of PATCHADDR field. /
bogdanm	0:9b334a45a8ff	4647	#define PU_PATCHADDR_PATCHADDR_Msk (0x1FFFFFFUL << PU_PATCHADDR_PATCHADDR_Pos) /!< Bit mask of PATCHADDR field. /
bogdanm	0:9b334a45a8ff	4648
bogdanm	0:9b334a45a8ff	4649	/* Register: PU_PATCHEN */
bogdanm	0:9b334a45a8ff	4650	/* Description: Patch enable register. */
bogdanm	0:9b334a45a8ff	4651
bogdanm	0:9b334a45a8ff	4652	/* Bit 7 : Patch 7 enabled. */
bogdanm	0:9b334a45a8ff	4653	#define PU_PATCHEN_PATCH7_Pos (7UL) /!< Position of PATCH7 field. /
bogdanm	0:9b334a45a8ff	4654	#define PU_PATCHEN_PATCH7_Msk (0x1UL << PU_PATCHEN_PATCH7_Pos) /!< Bit mask of PATCH7 field. /
bogdanm	0:9b334a45a8ff	4655	#define PU_PATCHEN_PATCH7_Disabled (0UL) /!< Patch disabled. /
bogdanm	0:9b334a45a8ff	4656	#define PU_PATCHEN_PATCH7_Enabled (1UL) /!< Patch enabled. /
bogdanm	0:9b334a45a8ff	4657
bogdanm	0:9b334a45a8ff	4658	/* Bit 6 : Patch 6 enabled. */
bogdanm	0:9b334a45a8ff	4659	#define PU_PATCHEN_PATCH6_Pos (6UL) /!< Position of PATCH6 field. /
bogdanm	0:9b334a45a8ff	4660	#define PU_PATCHEN_PATCH6_Msk (0x1UL << PU_PATCHEN_PATCH6_Pos) /!< Bit mask of PATCH6 field. /
bogdanm	0:9b334a45a8ff	4661	#define PU_PATCHEN_PATCH6_Disabled (0UL) /!< Patch disabled. /
bogdanm	0:9b334a45a8ff	4662	#define PU_PATCHEN_PATCH6_Enabled (1UL) /!< Patch enabled. /
bogdanm	0:9b334a45a8ff	4663
bogdanm	0:9b334a45a8ff	4664	/* Bit 5 : Patch 5 enabled. */
bogdanm	0:9b334a45a8ff	4665	#define PU_PATCHEN_PATCH5_Pos (5UL) /!< Position of PATCH5 field. /
bogdanm	0:9b334a45a8ff	4666	#define PU_PATCHEN_PATCH5_Msk (0x1UL << PU_PATCHEN_PATCH5_Pos) /!< Bit mask of PATCH5 field. /
bogdanm	0:9b334a45a8ff	4667	#define PU_PATCHEN_PATCH5_Disabled (0UL) /!< Patch disabled. /
bogdanm	0:9b334a45a8ff	4668	#define PU_PATCHEN_PATCH5_Enabled (1UL) /!< Patch enabled. /
bogdanm	0:9b334a45a8ff	4669
bogdanm	0:9b334a45a8ff	4670	/* Bit 4 : Patch 4 enabled. */
bogdanm	0:9b334a45a8ff	4671	#define PU_PATCHEN_PATCH4_Pos (4UL) /!< Position of PATCH4 field. /
bogdanm	0:9b334a45a8ff	4672	#define PU_PATCHEN_PATCH4_Msk (0x1UL << PU_PATCHEN_PATCH4_Pos) /!< Bit mask of PATCH4 field. /
bogdanm	0:9b334a45a8ff	4673	#define PU_PATCHEN_PATCH4_Disabled (0UL) /!< Patch disabled. /
bogdanm	0:9b334a45a8ff	4674	#define PU_PATCHEN_PATCH4_Enabled (1UL) /!< Patch enabled. /
bogdanm	0:9b334a45a8ff	4675
bogdanm	0:9b334a45a8ff	4676	/* Bit 3 : Patch 3 enabled. */
bogdanm	0:9b334a45a8ff	4677	#define PU_PATCHEN_PATCH3_Pos (3UL) /!< Position of PATCH3 field. /
bogdanm	0:9b334a45a8ff	4678	#define PU_PATCHEN_PATCH3_Msk (0x1UL << PU_PATCHEN_PATCH3_Pos) /!< Bit mask of PATCH3 field. /
bogdanm	0:9b334a45a8ff	4679	#define PU_PATCHEN_PATCH3_Disabled (0UL) /!< Patch disabled. /
bogdanm	0:9b334a45a8ff	4680	#define PU_PATCHEN_PATCH3_Enabled (1UL) /!< Patch enabled. /
bogdanm	0:9b334a45a8ff	4681
bogdanm	0:9b334a45a8ff	4682	/* Bit 2 : Patch 2 enabled. */
bogdanm	0:9b334a45a8ff	4683	#define PU_PATCHEN_PATCH2_Pos (2UL) /!< Position of PATCH2 field. /
bogdanm	0:9b334a45a8ff	4684	#define PU_PATCHEN_PATCH2_Msk (0x1UL << PU_PATCHEN_PATCH2_Pos) /!< Bit mask of PATCH2 field. /
bogdanm	0:9b334a45a8ff	4685	#define PU_PATCHEN_PATCH2_Disabled (0UL) /!< Patch disabled. /
bogdanm	0:9b334a45a8ff	4686	#define PU_PATCHEN_PATCH2_Enabled (1UL) /!< Patch enabled. /
bogdanm	0:9b334a45a8ff	4687
bogdanm	0:9b334a45a8ff	4688	/* Bit 1 : Patch 1 enabled. */
bogdanm	0:9b334a45a8ff	4689	#define PU_PATCHEN_PATCH1_Pos (1UL) /!< Position of PATCH1 field. /
bogdanm	0:9b334a45a8ff	4690	#define PU_PATCHEN_PATCH1_Msk (0x1UL << PU_PATCHEN_PATCH1_Pos) /!< Bit mask of PATCH1 field. /
bogdanm	0:9b334a45a8ff	4691	#define PU_PATCHEN_PATCH1_Disabled (0UL) /!< Patch disabled. /
bogdanm	0:9b334a45a8ff	4692	#define PU_PATCHEN_PATCH1_Enabled (1UL) /!< Patch enabled. /
bogdanm	0:9b334a45a8ff	4693
bogdanm	0:9b334a45a8ff	4694	/* Bit 0 : Patch 0 enabled. */
bogdanm	0:9b334a45a8ff	4695	#define PU_PATCHEN_PATCH0_Pos (0UL) /!< Position of PATCH0 field. /
bogdanm	0:9b334a45a8ff	4696	#define PU_PATCHEN_PATCH0_Msk (0x1UL << PU_PATCHEN_PATCH0_Pos) /!< Bit mask of PATCH0 field. /
bogdanm	0:9b334a45a8ff	4697	#define PU_PATCHEN_PATCH0_Disabled (0UL) /!< Patch disabled. /
bogdanm	0:9b334a45a8ff	4698	#define PU_PATCHEN_PATCH0_Enabled (1UL) /!< Patch enabled. /
bogdanm	0:9b334a45a8ff	4699
bogdanm	0:9b334a45a8ff	4700	/* Register: PU_PATCHENSET */
bogdanm	0:9b334a45a8ff	4701	/* Description: Patch enable register. */
bogdanm	0:9b334a45a8ff	4702
bogdanm	0:9b334a45a8ff	4703	/* Bit 7 : Patch 7 enabled. */
bogdanm	0:9b334a45a8ff	4704	#define PU_PATCHENSET_PATCH7_Pos (7UL) /!< Position of PATCH7 field. /
bogdanm	0:9b334a45a8ff	4705	#define PU_PATCHENSET_PATCH7_Msk (0x1UL << PU_PATCHENSET_PATCH7_Pos) /!< Bit mask of PATCH7 field. /
bogdanm	0:9b334a45a8ff	4706	#define PU_PATCHENSET_PATCH7_Disabled (0UL) /!< Patch disabled. /
bogdanm	0:9b334a45a8ff	4707	#define PU_PATCHENSET_PATCH7_Enabled (1UL) /!< Patch enabled. /
bogdanm	0:9b334a45a8ff	4708	#define PU_PATCHENSET_PATCH7_Set (1UL) /!< Enable patch on write. /
bogdanm	0:9b334a45a8ff	4709
bogdanm	0:9b334a45a8ff	4710	/* Bit 6 : Patch 6 enabled. */
bogdanm	0:9b334a45a8ff	4711	#define PU_PATCHENSET_PATCH6_Pos (6UL) /!< Position of PATCH6 field. /
bogdanm	0:9b334a45a8ff	4712	#define PU_PATCHENSET_PATCH6_Msk (0x1UL << PU_PATCHENSET_PATCH6_Pos) /!< Bit mask of PATCH6 field. /
bogdanm	0:9b334a45a8ff	4713	#define PU_PATCHENSET_PATCH6_Disabled (0UL) /!< Patch disabled. /
bogdanm	0:9b334a45a8ff	4714	#define PU_PATCHENSET_PATCH6_Enabled (1UL) /!< Patch enabled. /
bogdanm	0:9b334a45a8ff	4715	#define PU_PATCHENSET_PATCH6_Set (1UL) /!< Enable patch on write. /
bogdanm	0:9b334a45a8ff	4716
bogdanm	0:9b334a45a8ff	4717	/* Bit 5 : Patch 5 enabled. */
bogdanm	0:9b334a45a8ff	4718	#define PU_PATCHENSET_PATCH5_Pos (5UL) /!< Position of PATCH5 field. /
bogdanm	0:9b334a45a8ff	4719	#define PU_PATCHENSET_PATCH5_Msk (0x1UL << PU_PATCHENSET_PATCH5_Pos) /!< Bit mask of PATCH5 field. /
bogdanm	0:9b334a45a8ff	4720	#define PU_PATCHENSET_PATCH5_Disabled (0UL) /!< Patch disabled. /
bogdanm	0:9b334a45a8ff	4721	#define PU_PATCHENSET_PATCH5_Enabled (1UL) /!< Patch enabled. /
bogdanm	0:9b334a45a8ff	4722	#define PU_PATCHENSET_PATCH5_Set (1UL) /!< Enable patch on write. /
bogdanm	0:9b334a45a8ff	4723
bogdanm	0:9b334a45a8ff	4724	/* Bit 4 : Patch 4 enabled. */
bogdanm	0:9b334a45a8ff	4725	#define PU_PATCHENSET_PATCH4_Pos (4UL) /!< Position of PATCH4 field. /
bogdanm	0:9b334a45a8ff	4726	#define PU_PATCHENSET_PATCH4_Msk (0x1UL << PU_PATCHENSET_PATCH4_Pos) /!< Bit mask of PATCH4 field. /
bogdanm	0:9b334a45a8ff	4727	#define PU_PATCHENSET_PATCH4_Disabled (0UL) /!< Patch disabled. /
bogdanm	0:9b334a45a8ff	4728	#define PU_PATCHENSET_PATCH4_Enabled (1UL) /!< Patch enabled. /
bogdanm	0:9b334a45a8ff	4729	#define PU_PATCHENSET_PATCH4_Set (1UL) /!< Enable patch on write. /
bogdanm	0:9b334a45a8ff	4730
bogdanm	0:9b334a45a8ff	4731	/* Bit 3 : Patch 3 enabled. */
bogdanm	0:9b334a45a8ff	4732	#define PU_PATCHENSET_PATCH3_Pos (3UL) /!< Position of PATCH3 field. /
bogdanm	0:9b334a45a8ff	4733	#define PU_PATCHENSET_PATCH3_Msk (0x1UL << PU_PATCHENSET_PATCH3_Pos) /!< Bit mask of PATCH3 field. /
bogdanm	0:9b334a45a8ff	4734	#define PU_PATCHENSET_PATCH3_Disabled (0UL) /!< Patch disabled. /
bogdanm	0:9b334a45a8ff	4735	#define PU_PATCHENSET_PATCH3_Enabled (1UL) /!< Patch enabled. /
bogdanm	0:9b334a45a8ff	4736	#define PU_PATCHENSET_PATCH3_Set (1UL) /!< Enable patch on write. /
bogdanm	0:9b334a45a8ff	4737
bogdanm	0:9b334a45a8ff	4738	/* Bit 2 : Patch 2 enabled. */
bogdanm	0:9b334a45a8ff	4739	#define PU_PATCHENSET_PATCH2_Pos (2UL) /!< Position of PATCH2 field. /
bogdanm	0:9b334a45a8ff	4740	#define PU_PATCHENSET_PATCH2_Msk (0x1UL << PU_PATCHENSET_PATCH2_Pos) /!< Bit mask of PATCH2 field. /
bogdanm	0:9b334a45a8ff	4741	#define PU_PATCHENSET_PATCH2_Disabled (0UL) /!< Patch disabled. /
bogdanm	0:9b334a45a8ff	4742	#define PU_PATCHENSET_PATCH2_Enabled (1UL) /!< Patch enabled. /
bogdanm	0:9b334a45a8ff	4743	#define PU_PATCHENSET_PATCH2_Set (1UL) /!< Enable patch on write. /
bogdanm	0:9b334a45a8ff	4744
bogdanm	0:9b334a45a8ff	4745	/* Bit 1 : Patch 1 enabled. */
bogdanm	0:9b334a45a8ff	4746	#define PU_PATCHENSET_PATCH1_Pos (1UL) /!< Position of PATCH1 field. /
bogdanm	0:9b334a45a8ff	4747	#define PU_PATCHENSET_PATCH1_Msk (0x1UL << PU_PATCHENSET_PATCH1_Pos) /!< Bit mask of PATCH1 field. /
bogdanm	0:9b334a45a8ff	4748	#define PU_PATCHENSET_PATCH1_Disabled (0UL) /!< Patch disabled. /
bogdanm	0:9b334a45a8ff	4749	#define PU_PATCHENSET_PATCH1_Enabled (1UL) /!< Patch enabled. /
bogdanm	0:9b334a45a8ff	4750	#define PU_PATCHENSET_PATCH1_Set (1UL) /!< Enable patch on write. /
bogdanm	0:9b334a45a8ff	4751
bogdanm	0:9b334a45a8ff	4752	/* Bit 0 : Patch 0 enabled. */
bogdanm	0:9b334a45a8ff	4753	#define PU_PATCHENSET_PATCH0_Pos (0UL) /!< Position of PATCH0 field. /
bogdanm	0:9b334a45a8ff	4754	#define PU_PATCHENSET_PATCH0_Msk (0x1UL << PU_PATCHENSET_PATCH0_Pos) /!< Bit mask of PATCH0 field. /
bogdanm	0:9b334a45a8ff	4755	#define PU_PATCHENSET_PATCH0_Disabled (0UL) /!< Patch disabled. /
bogdanm	0:9b334a45a8ff	4756	#define PU_PATCHENSET_PATCH0_Enabled (1UL) /!< Patch enabled. /
bogdanm	0:9b334a45a8ff	4757	#define PU_PATCHENSET_PATCH0_Set (1UL) /!< Enable patch on write. /
bogdanm	0:9b334a45a8ff	4758
bogdanm	0:9b334a45a8ff	4759	/* Register: PU_PATCHENCLR */
bogdanm	0:9b334a45a8ff	4760	/* Description: Patch disable register. */
bogdanm	0:9b334a45a8ff	4761
bogdanm	0:9b334a45a8ff	4762	/* Bit 7 : Patch 7 enabled. */
bogdanm	0:9b334a45a8ff	4763	#define PU_PATCHENCLR_PATCH7_Pos (7UL) /!< Position of PATCH7 field. /
bogdanm	0:9b334a45a8ff	4764	#define PU_PATCHENCLR_PATCH7_Msk (0x1UL << PU_PATCHENCLR_PATCH7_Pos) /!< Bit mask of PATCH7 field. /
bogdanm	0:9b334a45a8ff	4765	#define PU_PATCHENCLR_PATCH7_Disabled (0UL) /!< Patch disabled. /
bogdanm	0:9b334a45a8ff	4766	#define PU_PATCHENCLR_PATCH7_Enabled (1UL) /!< Patch enabled. /
bogdanm	0:9b334a45a8ff	4767	#define PU_PATCHENCLR_PATCH7_Clear (1UL) /!< Disable patch on write. /
bogdanm	0:9b334a45a8ff	4768
bogdanm	0:9b334a45a8ff	4769	/* Bit 6 : Patch 6 enabled. */
bogdanm	0:9b334a45a8ff	4770	#define PU_PATCHENCLR_PATCH6_Pos (6UL) /!< Position of PATCH6 field. /
bogdanm	0:9b334a45a8ff	4771	#define PU_PATCHENCLR_PATCH6_Msk (0x1UL << PU_PATCHENCLR_PATCH6_Pos) /!< Bit mask of PATCH6 field. /
bogdanm	0:9b334a45a8ff	4772	#define PU_PATCHENCLR_PATCH6_Disabled (0UL) /!< Patch disabled. /
bogdanm	0:9b334a45a8ff	4773	#define PU_PATCHENCLR_PATCH6_Enabled (1UL) /!< Patch enabled. /
bogdanm	0:9b334a45a8ff	4774	#define PU_PATCHENCLR_PATCH6_Clear (1UL) /!< Disable patch on write. /
bogdanm	0:9b334a45a8ff	4775
bogdanm	0:9b334a45a8ff	4776	/* Bit 5 : Patch 5 enabled. */
bogdanm	0:9b334a45a8ff	4777	#define PU_PATCHENCLR_PATCH5_Pos (5UL) /!< Position of PATCH5 field. /
bogdanm	0:9b334a45a8ff	4778	#define PU_PATCHENCLR_PATCH5_Msk (0x1UL << PU_PATCHENCLR_PATCH5_Pos) /!< Bit mask of PATCH5 field. /
bogdanm	0:9b334a45a8ff	4779	#define PU_PATCHENCLR_PATCH5_Disabled (0UL) /!< Patch disabled. /
bogdanm	0:9b334a45a8ff	4780	#define PU_PATCHENCLR_PATCH5_Enabled (1UL) /!< Patch enabled. /
bogdanm	0:9b334a45a8ff	4781	#define PU_PATCHENCLR_PATCH5_Clear (1UL) /!< Disable patch on write. /
bogdanm	0:9b334a45a8ff	4782
bogdanm	0:9b334a45a8ff	4783	/* Bit 4 : Patch 4 enabled. */
bogdanm	0:9b334a45a8ff	4784	#define PU_PATCHENCLR_PATCH4_Pos (4UL) /!< Position of PATCH4 field. /
bogdanm	0:9b334a45a8ff	4785	#define PU_PATCHENCLR_PATCH4_Msk (0x1UL << PU_PATCHENCLR_PATCH4_Pos) /!< Bit mask of PATCH4 field. /
bogdanm	0:9b334a45a8ff	4786	#define PU_PATCHENCLR_PATCH4_Disabled (0UL) /!< Patch disabled. /
bogdanm	0:9b334a45a8ff	4787	#define PU_PATCHENCLR_PATCH4_Enabled (1UL) /!< Patch enabled. /
bogdanm	0:9b334a45a8ff	4788	#define PU_PATCHENCLR_PATCH4_Clear (1UL) /!< Disable patch on write. /
bogdanm	0:9b334a45a8ff	4789
bogdanm	0:9b334a45a8ff	4790	/* Bit 3 : Patch 3 enabled. */
bogdanm	0:9b334a45a8ff	4791	#define PU_PATCHENCLR_PATCH3_Pos (3UL) /!< Position of PATCH3 field. /
bogdanm	0:9b334a45a8ff	4792	#define PU_PATCHENCLR_PATCH3_Msk (0x1UL << PU_PATCHENCLR_PATCH3_Pos) /!< Bit mask of PATCH3 field. /
bogdanm	0:9b334a45a8ff	4793	#define PU_PATCHENCLR_PATCH3_Disabled (0UL) /!< Patch disabled. /
bogdanm	0:9b334a45a8ff	4794	#define PU_PATCHENCLR_PATCH3_Enabled (1UL) /!< Patch enabled. /
bogdanm	0:9b334a45a8ff	4795	#define PU_PATCHENCLR_PATCH3_Clear (1UL) /!< Disable patch on write. /
bogdanm	0:9b334a45a8ff	4796
bogdanm	0:9b334a45a8ff	4797	/* Bit 2 : Patch 2 enabled. */
bogdanm	0:9b334a45a8ff	4798	#define PU_PATCHENCLR_PATCH2_Pos (2UL) /!< Position of PATCH2 field. /
bogdanm	0:9b334a45a8ff	4799	#define PU_PATCHENCLR_PATCH2_Msk (0x1UL << PU_PATCHENCLR_PATCH2_Pos) /!< Bit mask of PATCH2 field. /
bogdanm	0:9b334a45a8ff	4800	#define PU_PATCHENCLR_PATCH2_Disabled (0UL) /!< Patch disabled. /
bogdanm	0:9b334a45a8ff	4801	#define PU_PATCHENCLR_PATCH2_Enabled (1UL) /!< Patch enabled. /
bogdanm	0:9b334a45a8ff	4802	#define PU_PATCHENCLR_PATCH2_Clear (1UL) /!< Disable patch on write. /
bogdanm	0:9b334a45a8ff	4803
bogdanm	0:9b334a45a8ff	4804	/* Bit 1 : Patch 1 enabled. */
bogdanm	0:9b334a45a8ff	4805	#define PU_PATCHENCLR_PATCH1_Pos (1UL) /!< Position of PATCH1 field. /
bogdanm	0:9b334a45a8ff	4806	#define PU_PATCHENCLR_PATCH1_Msk (0x1UL << PU_PATCHENCLR_PATCH1_Pos) /!< Bit mask of PATCH1 field. /
bogdanm	0:9b334a45a8ff	4807	#define PU_PATCHENCLR_PATCH1_Disabled (0UL) /!< Patch disabled. /
bogdanm	0:9b334a45a8ff	4808	#define PU_PATCHENCLR_PATCH1_Enabled (1UL) /!< Patch enabled. /
bogdanm	0:9b334a45a8ff	4809	#define PU_PATCHENCLR_PATCH1_Clear (1UL) /!< Disable patch on write. /
bogdanm	0:9b334a45a8ff	4810
bogdanm	0:9b334a45a8ff	4811	/* Bit 0 : Patch 0 enabled. */
bogdanm	0:9b334a45a8ff	4812	#define PU_PATCHENCLR_PATCH0_Pos (0UL) /!< Position of PATCH0 field. /
bogdanm	0:9b334a45a8ff	4813	#define PU_PATCHENCLR_PATCH0_Msk (0x1UL << PU_PATCHENCLR_PATCH0_Pos) /!< Bit mask of PATCH0 field. /
bogdanm	0:9b334a45a8ff	4814	#define PU_PATCHENCLR_PATCH0_Disabled (0UL) /!< Patch disabled. /
bogdanm	0:9b334a45a8ff	4815	#define PU_PATCHENCLR_PATCH0_Enabled (1UL) /!< Patch enabled. /
bogdanm	0:9b334a45a8ff	4816	#define PU_PATCHENCLR_PATCH0_Clear (1UL) /!< Disable patch on write. /
bogdanm	0:9b334a45a8ff	4817
bogdanm	0:9b334a45a8ff	4818
bogdanm	0:9b334a45a8ff	4819	/* Peripheral: QDEC */
bogdanm	0:9b334a45a8ff	4820	/* Description: Rotary decoder. */
bogdanm	0:9b334a45a8ff	4821
bogdanm	0:9b334a45a8ff	4822	/* Register: QDEC_SHORTS */
bogdanm	0:9b334a45a8ff	4823	/* Description: Shortcuts for the QDEC. */
bogdanm	0:9b334a45a8ff	4824
bogdanm	0:9b334a45a8ff	4825	/* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */
bogdanm	0:9b334a45a8ff	4826	#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /!< Position of SAMPLERDY_STOP field. /
bogdanm	0:9b334a45a8ff	4827	#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /!< Bit mask of SAMPLERDY_STOP field. /
bogdanm	0:9b334a45a8ff	4828	#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	0:9b334a45a8ff	4829	#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	0:9b334a45a8ff	4830
bogdanm	0:9b334a45a8ff	4831	/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */
bogdanm	0:9b334a45a8ff	4832	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /!< Position of REPORTRDY_READCLRACC field. /
bogdanm	0:9b334a45a8ff	4833	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /!< Bit mask of REPORTRDY_READCLRACC field. /
bogdanm	0:9b334a45a8ff	4834	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	0:9b334a45a8ff	4835	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	0:9b334a45a8ff	4836
bogdanm	0:9b334a45a8ff	4837	/* Register: QDEC_INTENSET */
bogdanm	0:9b334a45a8ff	4838	/* Description: Interrupt enable set register. */
bogdanm	0:9b334a45a8ff	4839
bogdanm	0:9b334a45a8ff	4840	/* Bit 2 : Enable interrupt on ACCOF event. */
bogdanm	0:9b334a45a8ff	4841	#define QDEC_INTENSET_ACCOF_Pos (2UL) /!< Position of ACCOF field. /
bogdanm	0:9b334a45a8ff	4842	#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /!< Bit mask of ACCOF field. /
bogdanm	0:9b334a45a8ff	4843	#define QDEC_INTENSET_ACCOF_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	4844	#define QDEC_INTENSET_ACCOF_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	4845	#define QDEC_INTENSET_ACCOF_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	4846
bogdanm	0:9b334a45a8ff	4847	/* Bit 1 : Enable interrupt on REPORTRDY event. */
bogdanm	0:9b334a45a8ff	4848	#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /!< Position of REPORTRDY field. /
bogdanm	0:9b334a45a8ff	4849	#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /!< Bit mask of REPORTRDY field. /
bogdanm	0:9b334a45a8ff	4850	#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	4851	#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	4852	#define QDEC_INTENSET_REPORTRDY_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	4853
bogdanm	0:9b334a45a8ff	4854	/* Bit 0 : Enable interrupt on SAMPLERDY event. */
bogdanm	0:9b334a45a8ff	4855	#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /!< Position of SAMPLERDY field. /
bogdanm	0:9b334a45a8ff	4856	#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /!< Bit mask of SAMPLERDY field. /
bogdanm	0:9b334a45a8ff	4857	#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	4858	#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	4859	#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	4860
bogdanm	0:9b334a45a8ff	4861	/* Register: QDEC_INTENCLR */
bogdanm	0:9b334a45a8ff	4862	/* Description: Interrupt enable clear register. */
bogdanm	0:9b334a45a8ff	4863
bogdanm	0:9b334a45a8ff	4864	/* Bit 2 : Disable interrupt on ACCOF event. */
bogdanm	0:9b334a45a8ff	4865	#define QDEC_INTENCLR_ACCOF_Pos (2UL) /!< Position of ACCOF field. /
bogdanm	0:9b334a45a8ff	4866	#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /!< Bit mask of ACCOF field. /
bogdanm	0:9b334a45a8ff	4867	#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	4868	#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	4869	#define QDEC_INTENCLR_ACCOF_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	4870
bogdanm	0:9b334a45a8ff	4871	/* Bit 1 : Disable interrupt on REPORTRDY event. */
bogdanm	0:9b334a45a8ff	4872	#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /!< Position of REPORTRDY field. /
bogdanm	0:9b334a45a8ff	4873	#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /!< Bit mask of REPORTRDY field. /
bogdanm	0:9b334a45a8ff	4874	#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	4875	#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	4876	#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	4877
bogdanm	0:9b334a45a8ff	4878	/* Bit 0 : Disable interrupt on SAMPLERDY event. */
bogdanm	0:9b334a45a8ff	4879	#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /!< Position of SAMPLERDY field. /
bogdanm	0:9b334a45a8ff	4880	#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /!< Bit mask of SAMPLERDY field. /
bogdanm	0:9b334a45a8ff	4881	#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	4882	#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	4883	#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	4884
bogdanm	0:9b334a45a8ff	4885	/* Register: QDEC_ENABLE */
bogdanm	0:9b334a45a8ff	4886	/* Description: Enable the QDEC. */
bogdanm	0:9b334a45a8ff	4887
bogdanm	0:9b334a45a8ff	4888	/* Bit 0 : Enable or disable QDEC. */
bogdanm	0:9b334a45a8ff	4889	#define QDEC_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
bogdanm	0:9b334a45a8ff	4890	#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
bogdanm	0:9b334a45a8ff	4891	#define QDEC_ENABLE_ENABLE_Disabled (0UL) /!< Disabled QDEC. /
bogdanm	0:9b334a45a8ff	4892	#define QDEC_ENABLE_ENABLE_Enabled (1UL) /!< Enable QDEC. /
bogdanm	0:9b334a45a8ff	4893
bogdanm	0:9b334a45a8ff	4894	/* Register: QDEC_LEDPOL */
bogdanm	0:9b334a45a8ff	4895	/* Description: LED output pin polarity. */
bogdanm	0:9b334a45a8ff	4896
bogdanm	0:9b334a45a8ff	4897	/* Bit 0 : LED output pin polarity. */
bogdanm	0:9b334a45a8ff	4898	#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /!< Position of LEDPOL field. /
bogdanm	0:9b334a45a8ff	4899	#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /!< Bit mask of LEDPOL field. /
bogdanm	0:9b334a45a8ff	4900	#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /!< LED output is active low. /
bogdanm	0:9b334a45a8ff	4901	#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /!< LED output is active high. /
bogdanm	0:9b334a45a8ff	4902
bogdanm	0:9b334a45a8ff	4903	/* Register: QDEC_SAMPLEPER */
bogdanm	0:9b334a45a8ff	4904	/* Description: Sample period. */
bogdanm	0:9b334a45a8ff	4905
bogdanm	0:9b334a45a8ff	4906	/* Bits 2..0 : Sample period. */
bogdanm	0:9b334a45a8ff	4907	#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /!< Position of SAMPLEPER field. /
bogdanm	0:9b334a45a8ff	4908	#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /!< Bit mask of SAMPLEPER field. /
bogdanm	0:9b334a45a8ff	4909	#define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /!< 128us sample period. /
bogdanm	0:9b334a45a8ff	4910	#define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /!< 256us sample period. /
bogdanm	0:9b334a45a8ff	4911	#define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /!< 512us sample period. /
bogdanm	0:9b334a45a8ff	4912	#define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /!< 1024us sample period. /
bogdanm	0:9b334a45a8ff	4913	#define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /!< 2048us sample period. /
bogdanm	0:9b334a45a8ff	4914	#define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /!< 4096us sample period. /
bogdanm	0:9b334a45a8ff	4915	#define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /!< 8192us sample period. /
bogdanm	0:9b334a45a8ff	4916	#define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /!< 16384us sample period. /
bogdanm	0:9b334a45a8ff	4917
bogdanm	0:9b334a45a8ff	4918	/* Register: QDEC_SAMPLE */
bogdanm	0:9b334a45a8ff	4919	/* Description: Motion sample value. */
bogdanm	0:9b334a45a8ff	4920
bogdanm	0:9b334a45a8ff	4921	/* Bits 31..0 : Last sample taken in compliment to 2. */
bogdanm	0:9b334a45a8ff	4922	#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /!< Position of SAMPLE field. /
bogdanm	0:9b334a45a8ff	4923	#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /!< Bit mask of SAMPLE field. /
bogdanm	0:9b334a45a8ff	4924
bogdanm	0:9b334a45a8ff	4925	/* Register: QDEC_REPORTPER */
bogdanm	0:9b334a45a8ff	4926	/* Description: Number of samples to generate an EVENT_REPORTRDY. */
bogdanm	0:9b334a45a8ff	4927
bogdanm	0:9b334a45a8ff	4928	/* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */
bogdanm	0:9b334a45a8ff	4929	#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /!< Position of REPORTPER field. /
bogdanm	0:9b334a45a8ff	4930	#define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /!< Bit mask of REPORTPER field. /
bogdanm	0:9b334a45a8ff	4931	#define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /!< 10 samples per report. /
bogdanm	0:9b334a45a8ff	4932	#define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /!< 40 samples per report. /
bogdanm	0:9b334a45a8ff	4933	#define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /!< 80 samples per report. /
bogdanm	0:9b334a45a8ff	4934	#define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /!< 120 samples per report. /
bogdanm	0:9b334a45a8ff	4935	#define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /!< 160 samples per report. /
bogdanm	0:9b334a45a8ff	4936	#define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /!< 200 samples per report. /
bogdanm	0:9b334a45a8ff	4937	#define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /!< 240 samples per report. /
bogdanm	0:9b334a45a8ff	4938	#define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /!< 280 samples per report. /
bogdanm	0:9b334a45a8ff	4939
bogdanm	0:9b334a45a8ff	4940	/* Register: QDEC_DBFEN */
bogdanm	0:9b334a45a8ff	4941	/* Description: Enable debouncer input filters. */
bogdanm	0:9b334a45a8ff	4942
bogdanm	0:9b334a45a8ff	4943	/* Bit 0 : Enable debounce input filters. */
bogdanm	0:9b334a45a8ff	4944	#define QDEC_DBFEN_DBFEN_Pos (0UL) /!< Position of DBFEN field. /
bogdanm	0:9b334a45a8ff	4945	#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /!< Bit mask of DBFEN field. /
bogdanm	0:9b334a45a8ff	4946	#define QDEC_DBFEN_DBFEN_Disabled (0UL) /!< Debounce input filters disabled. /
bogdanm	0:9b334a45a8ff	4947	#define QDEC_DBFEN_DBFEN_Enabled (1UL) /!< Debounce input filters enabled. /
bogdanm	0:9b334a45a8ff	4948
bogdanm	0:9b334a45a8ff	4949	/* Register: QDEC_LEDPRE */
bogdanm	0:9b334a45a8ff	4950	/* Description: Time LED is switched ON before the sample. */
bogdanm	0:9b334a45a8ff	4951
bogdanm	0:9b334a45a8ff	4952	/* Bits 8..0 : Period in us the LED in switched on prior to sampling. */
bogdanm	0:9b334a45a8ff	4953	#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /!< Position of LEDPRE field. /
bogdanm	0:9b334a45a8ff	4954	#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /!< Bit mask of LEDPRE field. /
bogdanm	0:9b334a45a8ff	4955
bogdanm	0:9b334a45a8ff	4956	/* Register: QDEC_ACCDBL */
bogdanm	0:9b334a45a8ff	4957	/* Description: Accumulated double (error) transitions register. */
bogdanm	0:9b334a45a8ff	4958
bogdanm	0:9b334a45a8ff	4959	/* Bits 3..0 : Accumulated double (error) transitions. */
bogdanm	0:9b334a45a8ff	4960	#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /!< Position of ACCDBL field. /
bogdanm	0:9b334a45a8ff	4961	#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /!< Bit mask of ACCDBL field. /
bogdanm	0:9b334a45a8ff	4962
bogdanm	0:9b334a45a8ff	4963	/* Register: QDEC_ACCDBLREAD */
bogdanm	0:9b334a45a8ff	4964	/* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */
bogdanm	0:9b334a45a8ff	4965
bogdanm	0:9b334a45a8ff	4966	/* Bits 3..0 : Snapshot of accumulated double (error) transitions. */
bogdanm	0:9b334a45a8ff	4967	#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /!< Position of ACCDBLREAD field. /
bogdanm	0:9b334a45a8ff	4968	#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /!< Bit mask of ACCDBLREAD field. /
bogdanm	0:9b334a45a8ff	4969
bogdanm	0:9b334a45a8ff	4970	/* Register: QDEC_POWER */
bogdanm	0:9b334a45a8ff	4971	/* Description: Peripheral power control. */
bogdanm	0:9b334a45a8ff	4972
bogdanm	0:9b334a45a8ff	4973	/* Bit 0 : Peripheral power control. */
bogdanm	0:9b334a45a8ff	4974	#define QDEC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	0:9b334a45a8ff	4975	#define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	0:9b334a45a8ff	4976	#define QDEC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	0:9b334a45a8ff	4977	#define QDEC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	0:9b334a45a8ff	4978
bogdanm	0:9b334a45a8ff	4979
bogdanm	0:9b334a45a8ff	4980	/* Peripheral: RADIO */
bogdanm	0:9b334a45a8ff	4981	/* Description: The radio. */
bogdanm	0:9b334a45a8ff	4982
bogdanm	0:9b334a45a8ff	4983	/* Register: RADIO_SHORTS */
bogdanm	0:9b334a45a8ff	4984	/* Description: Shortcuts for the radio. */
bogdanm	0:9b334a45a8ff	4985
bogdanm	0:9b334a45a8ff	4986	/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */
bogdanm	0:9b334a45a8ff	4987	#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /!< Position of DISABLED_RSSISTOP field. /
bogdanm	0:9b334a45a8ff	4988	#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /!< Bit mask of DISABLED_RSSISTOP field. /
bogdanm	0:9b334a45a8ff	4989	#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	0:9b334a45a8ff	4990	#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	0:9b334a45a8ff	4991
bogdanm	0:9b334a45a8ff	4992	/* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */
bogdanm	0:9b334a45a8ff	4993	#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /!< Position of ADDRESS_BCSTART field. /
bogdanm	0:9b334a45a8ff	4994	#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /!< Bit mask of ADDRESS_BCSTART field. /
bogdanm	0:9b334a45a8ff	4995	#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	0:9b334a45a8ff	4996	#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	0:9b334a45a8ff	4997
bogdanm	0:9b334a45a8ff	4998	/* Bit 5 : Shortcut between END event and START task. */
bogdanm	0:9b334a45a8ff	4999	#define RADIO_SHORTS_END_START_Pos (5UL) /!< Position of END_START field. /
bogdanm	0:9b334a45a8ff	5000	#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /!< Bit mask of END_START field. /
bogdanm	0:9b334a45a8ff	5001	#define RADIO_SHORTS_END_START_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	0:9b334a45a8ff	5002	#define RADIO_SHORTS_END_START_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	0:9b334a45a8ff	5003
bogdanm	0:9b334a45a8ff	5004	/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */
bogdanm	0:9b334a45a8ff	5005	#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /!< Position of ADDRESS_RSSISTART field. /
bogdanm	0:9b334a45a8ff	5006	#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /!< Bit mask of ADDRESS_RSSISTART field. /
bogdanm	0:9b334a45a8ff	5007	#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	0:9b334a45a8ff	5008	#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	0:9b334a45a8ff	5009
bogdanm	0:9b334a45a8ff	5010	/* Bit 3 : Shortcut between DISABLED event and RXEN task. */
bogdanm	0:9b334a45a8ff	5011	#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /!< Position of DISABLED_RXEN field. /
bogdanm	0:9b334a45a8ff	5012	#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /!< Bit mask of DISABLED_RXEN field. /
bogdanm	0:9b334a45a8ff	5013	#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	0:9b334a45a8ff	5014	#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	0:9b334a45a8ff	5015
bogdanm	0:9b334a45a8ff	5016	/* Bit 2 : Shortcut between DISABLED event and TXEN task. */
bogdanm	0:9b334a45a8ff	5017	#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /!< Position of DISABLED_TXEN field. /
bogdanm	0:9b334a45a8ff	5018	#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /!< Bit mask of DISABLED_TXEN field. /
bogdanm	0:9b334a45a8ff	5019	#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	0:9b334a45a8ff	5020	#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	0:9b334a45a8ff	5021
bogdanm	0:9b334a45a8ff	5022	/* Bit 1 : Shortcut between END event and DISABLE task. */
bogdanm	0:9b334a45a8ff	5023	#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /!< Position of END_DISABLE field. /
bogdanm	0:9b334a45a8ff	5024	#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /!< Bit mask of END_DISABLE field. /
bogdanm	0:9b334a45a8ff	5025	#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	0:9b334a45a8ff	5026	#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	0:9b334a45a8ff	5027
bogdanm	0:9b334a45a8ff	5028	/* Bit 0 : Shortcut between READY event and START task. */
bogdanm	0:9b334a45a8ff	5029	#define RADIO_SHORTS_READY_START_Pos (0UL) /!< Position of READY_START field. /
bogdanm	0:9b334a45a8ff	5030	#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /!< Bit mask of READY_START field. /
bogdanm	0:9b334a45a8ff	5031	#define RADIO_SHORTS_READY_START_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	0:9b334a45a8ff	5032	#define RADIO_SHORTS_READY_START_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	0:9b334a45a8ff	5033
bogdanm	0:9b334a45a8ff	5034	/* Register: RADIO_INTENSET */
bogdanm	0:9b334a45a8ff	5035	/* Description: Interrupt enable set register. */
bogdanm	0:9b334a45a8ff	5036
bogdanm	0:9b334a45a8ff	5037	/* Bit 10 : Enable interrupt on BCMATCH event. */
bogdanm	0:9b334a45a8ff	5038	#define RADIO_INTENSET_BCMATCH_Pos (10UL) /!< Position of BCMATCH field. /
bogdanm	0:9b334a45a8ff	5039	#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /!< Bit mask of BCMATCH field. /
bogdanm	0:9b334a45a8ff	5040	#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	5041	#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	5042	#define RADIO_INTENSET_BCMATCH_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	5043
bogdanm	0:9b334a45a8ff	5044	/* Bit 7 : Enable interrupt on RSSIEND event. */
bogdanm	0:9b334a45a8ff	5045	#define RADIO_INTENSET_RSSIEND_Pos (7UL) /!< Position of RSSIEND field. /
bogdanm	0:9b334a45a8ff	5046	#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /!< Bit mask of RSSIEND field. /
bogdanm	0:9b334a45a8ff	5047	#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	5048	#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	5049	#define RADIO_INTENSET_RSSIEND_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	5050
bogdanm	0:9b334a45a8ff	5051	/* Bit 6 : Enable interrupt on DEVMISS event. */
bogdanm	0:9b334a45a8ff	5052	#define RADIO_INTENSET_DEVMISS_Pos (6UL) /!< Position of DEVMISS field. /
bogdanm	0:9b334a45a8ff	5053	#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /!< Bit mask of DEVMISS field. /
bogdanm	0:9b334a45a8ff	5054	#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	5055	#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	5056	#define RADIO_INTENSET_DEVMISS_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	5057
bogdanm	0:9b334a45a8ff	5058	/* Bit 5 : Enable interrupt on DEVMATCH event. */
bogdanm	0:9b334a45a8ff	5059	#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /!< Position of DEVMATCH field. /
bogdanm	0:9b334a45a8ff	5060	#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /!< Bit mask of DEVMATCH field. /
bogdanm	0:9b334a45a8ff	5061	#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	5062	#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	5063	#define RADIO_INTENSET_DEVMATCH_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	5064
bogdanm	0:9b334a45a8ff	5065	/* Bit 4 : Enable interrupt on DISABLED event. */
bogdanm	0:9b334a45a8ff	5066	#define RADIO_INTENSET_DISABLED_Pos (4UL) /!< Position of DISABLED field. /
bogdanm	0:9b334a45a8ff	5067	#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /!< Bit mask of DISABLED field. /
bogdanm	0:9b334a45a8ff	5068	#define RADIO_INTENSET_DISABLED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	5069	#define RADIO_INTENSET_DISABLED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	5070	#define RADIO_INTENSET_DISABLED_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	5071
bogdanm	0:9b334a45a8ff	5072	/* Bit 3 : Enable interrupt on END event. */
bogdanm	0:9b334a45a8ff	5073	#define RADIO_INTENSET_END_Pos (3UL) /!< Position of END field. /
bogdanm	0:9b334a45a8ff	5074	#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /!< Bit mask of END field. /
bogdanm	0:9b334a45a8ff	5075	#define RADIO_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	5076	#define RADIO_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	5077	#define RADIO_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	5078
bogdanm	0:9b334a45a8ff	5079	/* Bit 2 : Enable interrupt on PAYLOAD event. */
bogdanm	0:9b334a45a8ff	5080	#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /!< Position of PAYLOAD field. /
bogdanm	0:9b334a45a8ff	5081	#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /!< Bit mask of PAYLOAD field. /
bogdanm	0:9b334a45a8ff	5082	#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	5083	#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	5084	#define RADIO_INTENSET_PAYLOAD_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	5085
bogdanm	0:9b334a45a8ff	5086	/* Bit 1 : Enable interrupt on ADDRESS event. */
bogdanm	0:9b334a45a8ff	5087	#define RADIO_INTENSET_ADDRESS_Pos (1UL) /!< Position of ADDRESS field. /
bogdanm	0:9b334a45a8ff	5088	#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
bogdanm	0:9b334a45a8ff	5089	#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	5090	#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	5091	#define RADIO_INTENSET_ADDRESS_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	5092
bogdanm	0:9b334a45a8ff	5093	/* Bit 0 : Enable interrupt on READY event. */
bogdanm	0:9b334a45a8ff	5094	#define RADIO_INTENSET_READY_Pos (0UL) /!< Position of READY field. /
bogdanm	0:9b334a45a8ff	5095	#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /!< Bit mask of READY field. /
bogdanm	0:9b334a45a8ff	5096	#define RADIO_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	5097	#define RADIO_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	5098	#define RADIO_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	5099
bogdanm	0:9b334a45a8ff	5100	/* Register: RADIO_INTENCLR */
bogdanm	0:9b334a45a8ff	5101	/* Description: Interrupt enable clear register. */
bogdanm	0:9b334a45a8ff	5102
bogdanm	0:9b334a45a8ff	5103	/* Bit 10 : Disable interrupt on BCMATCH event. */
bogdanm	0:9b334a45a8ff	5104	#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /!< Position of BCMATCH field. /
bogdanm	0:9b334a45a8ff	5105	#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /!< Bit mask of BCMATCH field. /
bogdanm	0:9b334a45a8ff	5106	#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	5107	#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	5108	#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	5109
bogdanm	0:9b334a45a8ff	5110	/* Bit 7 : Disable interrupt on RSSIEND event. */
bogdanm	0:9b334a45a8ff	5111	#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /!< Position of RSSIEND field. /
bogdanm	0:9b334a45a8ff	5112	#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /!< Bit mask of RSSIEND field. /
bogdanm	0:9b334a45a8ff	5113	#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	5114	#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	5115	#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	5116
bogdanm	0:9b334a45a8ff	5117	/* Bit 6 : Disable interrupt on DEVMISS event. */
bogdanm	0:9b334a45a8ff	5118	#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /!< Position of DEVMISS field. /
bogdanm	0:9b334a45a8ff	5119	#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /!< Bit mask of DEVMISS field. /
bogdanm	0:9b334a45a8ff	5120	#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	5121	#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	5122	#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	5123
bogdanm	0:9b334a45a8ff	5124	/* Bit 5 : Disable interrupt on DEVMATCH event. */
bogdanm	0:9b334a45a8ff	5125	#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /!< Position of DEVMATCH field. /
bogdanm	0:9b334a45a8ff	5126	#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /!< Bit mask of DEVMATCH field. /
bogdanm	0:9b334a45a8ff	5127	#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	5128	#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	5129	#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	5130
bogdanm	0:9b334a45a8ff	5131	/* Bit 4 : Disable interrupt on DISABLED event. */
bogdanm	0:9b334a45a8ff	5132	#define RADIO_INTENCLR_DISABLED_Pos (4UL) /!< Position of DISABLED field. /
bogdanm	0:9b334a45a8ff	5133	#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /!< Bit mask of DISABLED field. /
bogdanm	0:9b334a45a8ff	5134	#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	5135	#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	5136	#define RADIO_INTENCLR_DISABLED_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	5137
bogdanm	0:9b334a45a8ff	5138	/* Bit 3 : Disable interrupt on END event. */
bogdanm	0:9b334a45a8ff	5139	#define RADIO_INTENCLR_END_Pos (3UL) /!< Position of END field. /
bogdanm	0:9b334a45a8ff	5140	#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /!< Bit mask of END field. /
bogdanm	0:9b334a45a8ff	5141	#define RADIO_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	5142	#define RADIO_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	5143	#define RADIO_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	5144
bogdanm	0:9b334a45a8ff	5145	/* Bit 2 : Disable interrupt on PAYLOAD event. */
bogdanm	0:9b334a45a8ff	5146	#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /!< Position of PAYLOAD field. /
bogdanm	0:9b334a45a8ff	5147	#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /!< Bit mask of PAYLOAD field. /
bogdanm	0:9b334a45a8ff	5148	#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	5149	#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	5150	#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	5151
bogdanm	0:9b334a45a8ff	5152	/* Bit 1 : Disable interrupt on ADDRESS event. */
bogdanm	0:9b334a45a8ff	5153	#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /!< Position of ADDRESS field. /
bogdanm	0:9b334a45a8ff	5154	#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
bogdanm	0:9b334a45a8ff	5155	#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	5156	#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	5157	#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	5158
bogdanm	0:9b334a45a8ff	5159	/* Bit 0 : Disable interrupt on READY event. */
bogdanm	0:9b334a45a8ff	5160	#define RADIO_INTENCLR_READY_Pos (0UL) /!< Position of READY field. /
bogdanm	0:9b334a45a8ff	5161	#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
bogdanm	0:9b334a45a8ff	5162	#define RADIO_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	5163	#define RADIO_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	5164	#define RADIO_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	5165
bogdanm	0:9b334a45a8ff	5166	/* Register: RADIO_CRCSTATUS */
bogdanm	0:9b334a45a8ff	5167	/* Description: CRC status of received packet. */
bogdanm	0:9b334a45a8ff	5168
bogdanm	0:9b334a45a8ff	5169	/* Bit 0 : CRC status of received packet. */
bogdanm	0:9b334a45a8ff	5170	#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /!< Position of CRCSTATUS field. /
bogdanm	0:9b334a45a8ff	5171	#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /!< Bit mask of CRCSTATUS field. /
bogdanm	0:9b334a45a8ff	5172	#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /!< Packet received with CRC error. /
bogdanm	0:9b334a45a8ff	5173	#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /!< Packet received with CRC ok. /
bogdanm	0:9b334a45a8ff	5174
bogdanm	0:9b334a45a8ff	5175	/* Register: RADIO_CD */
bogdanm	0:9b334a45a8ff	5176	/* Description: Carrier detect. */
bogdanm	0:9b334a45a8ff	5177
bogdanm	0:9b334a45a8ff	5178	/* Bit 0 : Carrier detect. */
bogdanm	0:9b334a45a8ff	5179	#define RADIO_CD_CD_Pos (0UL) /!< Position of CD field. /
bogdanm	0:9b334a45a8ff	5180	#define RADIO_CD_CD_Msk (0x1UL << RADIO_CD_CD_Pos) /!< Bit mask of CD field. /
bogdanm	0:9b334a45a8ff	5181
bogdanm	0:9b334a45a8ff	5182	/* Register: RADIO_RXMATCH */
bogdanm	0:9b334a45a8ff	5183	/* Description: Received address. */
bogdanm	0:9b334a45a8ff	5184
bogdanm	0:9b334a45a8ff	5185	/* Bits 2..0 : Logical address in which previous packet was received. */
bogdanm	0:9b334a45a8ff	5186	#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /!< Position of RXMATCH field. /
bogdanm	0:9b334a45a8ff	5187	#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /!< Bit mask of RXMATCH field. /
bogdanm	0:9b334a45a8ff	5188
bogdanm	0:9b334a45a8ff	5189	/* Register: RADIO_RXCRC */
bogdanm	0:9b334a45a8ff	5190	/* Description: Received CRC. */
bogdanm	0:9b334a45a8ff	5191
bogdanm	0:9b334a45a8ff	5192	/* Bits 23..0 : CRC field of previously received packet. */
bogdanm	0:9b334a45a8ff	5193	#define RADIO_RXCRC_RXCRC_Pos (0UL) /!< Position of RXCRC field. /
bogdanm	0:9b334a45a8ff	5194	#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /!< Bit mask of RXCRC field. /
bogdanm	0:9b334a45a8ff	5195
bogdanm	0:9b334a45a8ff	5196	/* Register: RADIO_DAI */
bogdanm	0:9b334a45a8ff	5197	/* Description: Device address match index. */
bogdanm	0:9b334a45a8ff	5198
bogdanm	0:9b334a45a8ff	5199	/* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */
bogdanm	0:9b334a45a8ff	5200	#define RADIO_DAI_DAI_Pos (0UL) /!< Position of DAI field. /
bogdanm	0:9b334a45a8ff	5201	#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /!< Bit mask of DAI field. /
bogdanm	0:9b334a45a8ff	5202
bogdanm	0:9b334a45a8ff	5203	/* Register: RADIO_FREQUENCY */
bogdanm	0:9b334a45a8ff	5204	/* Description: Frequency. */
bogdanm	0:9b334a45a8ff	5205
bogdanm	0:9b334a45a8ff	5206	/* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task. */
bogdanm	0:9b334a45a8ff	5207	#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
bogdanm	0:9b334a45a8ff	5208	#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
bogdanm	0:9b334a45a8ff	5209
bogdanm	0:9b334a45a8ff	5210	/* Register: RADIO_TXPOWER */
bogdanm	0:9b334a45a8ff	5211	/* Description: Output power. */
bogdanm	0:9b334a45a8ff	5212
bogdanm	0:9b334a45a8ff	5213	/* Bits 7..0 : Radio output power. Decision point: TXEN task. */
bogdanm	0:9b334a45a8ff	5214	#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /!< Position of TXPOWER field. /
bogdanm	0:9b334a45a8ff	5215	#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /!< Bit mask of TXPOWER field. /
bogdanm	0:9b334a45a8ff	5216	#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /!< +4dBm. /
bogdanm	0:9b334a45a8ff	5217	#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /!< 0dBm. /
bogdanm	0:9b334a45a8ff	5218	#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /!< -4dBm. /
bogdanm	0:9b334a45a8ff	5219	#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /!< -8dBm. /
bogdanm	0:9b334a45a8ff	5220	#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /!< -12dBm. /
bogdanm	0:9b334a45a8ff	5221	#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /!< -16dBm. /
bogdanm	0:9b334a45a8ff	5222	#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /!< -20dBm. /
bogdanm	0:9b334a45a8ff	5223	#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /!< -30dBm. /
bogdanm	0:9b334a45a8ff	5224
bogdanm	0:9b334a45a8ff	5225	/* Register: RADIO_MODE */
bogdanm	0:9b334a45a8ff	5226	/* Description: Data rate and modulation. */
bogdanm	0:9b334a45a8ff	5227
bogdanm	0:9b334a45a8ff	5228	/* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */
bogdanm	0:9b334a45a8ff	5229	#define RADIO_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
bogdanm	0:9b334a45a8ff	5230	#define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /!< Bit mask of MODE field. /
bogdanm	0:9b334a45a8ff	5231	#define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /!< 1Mbit/s Nordic propietary radio mode. /
bogdanm	0:9b334a45a8ff	5232	#define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /!< 2Mbit/s Nordic propietary radio mode. /
bogdanm	0:9b334a45a8ff	5233	#define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /!< 250kbit/s Nordic propietary radio mode. /
bogdanm	0:9b334a45a8ff	5234	#define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /!< 1Mbit/s Bluetooth Low Energy /
bogdanm	0:9b334a45a8ff	5235
bogdanm	0:9b334a45a8ff	5236	/* Register: RADIO_PCNF0 */
bogdanm	0:9b334a45a8ff	5237	/* Description: Packet configuration 0. */
bogdanm	0:9b334a45a8ff	5238
bogdanm	0:9b334a45a8ff	5239	/* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */
bogdanm	0:9b334a45a8ff	5240	#define RADIO_PCNF0_S1LEN_Pos (16UL) /!< Position of S1LEN field. /
bogdanm	0:9b334a45a8ff	5241	#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /!< Bit mask of S1LEN field. /
bogdanm	0:9b334a45a8ff	5242
bogdanm	0:9b334a45a8ff	5243	/* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */
bogdanm	0:9b334a45a8ff	5244	#define RADIO_PCNF0_S0LEN_Pos (8UL) /!< Position of S0LEN field. /
bogdanm	0:9b334a45a8ff	5245	#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /!< Bit mask of S0LEN field. /
bogdanm	0:9b334a45a8ff	5246
bogdanm	0:9b334a45a8ff	5247	/* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */
bogdanm	0:9b334a45a8ff	5248	#define RADIO_PCNF0_LFLEN_Pos (0UL) /!< Position of LFLEN field. /
bogdanm	0:9b334a45a8ff	5249	#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /!< Bit mask of LFLEN field. /
bogdanm	0:9b334a45a8ff	5250
bogdanm	0:9b334a45a8ff	5251	/* Register: RADIO_PCNF1 */
bogdanm	0:9b334a45a8ff	5252	/* Description: Packet configuration 1. */
bogdanm	0:9b334a45a8ff	5253
bogdanm	0:9b334a45a8ff	5254	/* Bit 25 : Packet whitening enable. */
bogdanm	0:9b334a45a8ff	5255	#define RADIO_PCNF1_WHITEEN_Pos (25UL) /!< Position of WHITEEN field. /
bogdanm	0:9b334a45a8ff	5256	#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /!< Bit mask of WHITEEN field. /
bogdanm	0:9b334a45a8ff	5257	#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /!< Whitening disabled. /
bogdanm	0:9b334a45a8ff	5258	#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /!< Whitening enabled. /
bogdanm	0:9b334a45a8ff	5259
bogdanm	0:9b334a45a8ff	5260	/* Bit 24 : On air endianness of packet length field. Decision point: START task. */
bogdanm	0:9b334a45a8ff	5261	#define RADIO_PCNF1_ENDIAN_Pos (24UL) /!< Position of ENDIAN field. /
bogdanm	0:9b334a45a8ff	5262	#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /!< Bit mask of ENDIAN field. /
bogdanm	0:9b334a45a8ff	5263	#define RADIO_PCNF1_ENDIAN_Little (0UL) /!< Least significant bit on air first /
bogdanm	0:9b334a45a8ff	5264	#define RADIO_PCNF1_ENDIAN_Big (1UL) /!< Most significant bit on air first /
bogdanm	0:9b334a45a8ff	5265
bogdanm	0:9b334a45a8ff	5266	/* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */
bogdanm	0:9b334a45a8ff	5267	#define RADIO_PCNF1_BALEN_Pos (16UL) /!< Position of BALEN field. /
bogdanm	0:9b334a45a8ff	5268	#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /!< Bit mask of BALEN field. /
bogdanm	0:9b334a45a8ff	5269
bogdanm	0:9b334a45a8ff	5270	/* Bits 15..8 : Static length in number of bytes. Decision point: START task. */
bogdanm	0:9b334a45a8ff	5271	#define RADIO_PCNF1_STATLEN_Pos (8UL) /!< Position of STATLEN field. /
bogdanm	0:9b334a45a8ff	5272	#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /!< Bit mask of STATLEN field. /
bogdanm	0:9b334a45a8ff	5273
bogdanm	0:9b334a45a8ff	5274	/* Bits 7..0 : Maximum length of packet payload in number of bytes. */
bogdanm	0:9b334a45a8ff	5275	#define RADIO_PCNF1_MAXLEN_Pos (0UL) /!< Position of MAXLEN field. /
bogdanm	0:9b334a45a8ff	5276	#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /!< Bit mask of MAXLEN field. /
bogdanm	0:9b334a45a8ff	5277
bogdanm	0:9b334a45a8ff	5278	/* Register: RADIO_PREFIX0 */
bogdanm	0:9b334a45a8ff	5279	/* Description: Prefixes bytes for logical addresses 0 to 3. */
bogdanm	0:9b334a45a8ff	5280
bogdanm	0:9b334a45a8ff	5281	/* Bits 31..24 : Address prefix 3. Decision point: START task. */
bogdanm	0:9b334a45a8ff	5282	#define RADIO_PREFIX0_AP3_Pos (24UL) /!< Position of AP3 field. /
bogdanm	0:9b334a45a8ff	5283	#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /!< Bit mask of AP3 field. /
bogdanm	0:9b334a45a8ff	5284
bogdanm	0:9b334a45a8ff	5285	/* Bits 23..16 : Address prefix 2. Decision point: START task. */
bogdanm	0:9b334a45a8ff	5286	#define RADIO_PREFIX0_AP2_Pos (16UL) /!< Position of AP2 field. /
bogdanm	0:9b334a45a8ff	5287	#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /!< Bit mask of AP2 field. /
bogdanm	0:9b334a45a8ff	5288
bogdanm	0:9b334a45a8ff	5289	/* Bits 15..8 : Address prefix 1. Decision point: START task. */
bogdanm	0:9b334a45a8ff	5290	#define RADIO_PREFIX0_AP1_Pos (8UL) /!< Position of AP1 field. /
bogdanm	0:9b334a45a8ff	5291	#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /!< Bit mask of AP1 field. /
bogdanm	0:9b334a45a8ff	5292
bogdanm	0:9b334a45a8ff	5293	/* Bits 7..0 : Address prefix 0. Decision point: START task. */
bogdanm	0:9b334a45a8ff	5294	#define RADIO_PREFIX0_AP0_Pos (0UL) /!< Position of AP0 field. /
bogdanm	0:9b334a45a8ff	5295	#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /!< Bit mask of AP0 field. /
bogdanm	0:9b334a45a8ff	5296
bogdanm	0:9b334a45a8ff	5297	/* Register: RADIO_PREFIX1 */
bogdanm	0:9b334a45a8ff	5298	/* Description: Prefixes bytes for logical addresses 4 to 7. */
bogdanm	0:9b334a45a8ff	5299
bogdanm	0:9b334a45a8ff	5300	/* Bits 31..24 : Address prefix 7. Decision point: START task. */
bogdanm	0:9b334a45a8ff	5301	#define RADIO_PREFIX1_AP7_Pos (24UL) /!< Position of AP7 field. /
bogdanm	0:9b334a45a8ff	5302	#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /!< Bit mask of AP7 field. /
bogdanm	0:9b334a45a8ff	5303
bogdanm	0:9b334a45a8ff	5304	/* Bits 23..16 : Address prefix 6. Decision point: START task. */
bogdanm	0:9b334a45a8ff	5305	#define RADIO_PREFIX1_AP6_Pos (16UL) /!< Position of AP6 field. /
bogdanm	0:9b334a45a8ff	5306	#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /!< Bit mask of AP6 field. /
bogdanm	0:9b334a45a8ff	5307
bogdanm	0:9b334a45a8ff	5308	/* Bits 15..8 : Address prefix 5. Decision point: START task. */
bogdanm	0:9b334a45a8ff	5309	#define RADIO_PREFIX1_AP5_Pos (8UL) /!< Position of AP5 field. /
bogdanm	0:9b334a45a8ff	5310	#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /!< Bit mask of AP5 field. /
bogdanm	0:9b334a45a8ff	5311
bogdanm	0:9b334a45a8ff	5312	/* Bits 7..0 : Address prefix 4. Decision point: START task. */
bogdanm	0:9b334a45a8ff	5313	#define RADIO_PREFIX1_AP4_Pos (0UL) /!< Position of AP4 field. /
bogdanm	0:9b334a45a8ff	5314	#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /!< Bit mask of AP4 field. /
bogdanm	0:9b334a45a8ff	5315
bogdanm	0:9b334a45a8ff	5316	/* Register: RADIO_TXADDRESS */
bogdanm	0:9b334a45a8ff	5317	/* Description: Transmit address select. */
bogdanm	0:9b334a45a8ff	5318
bogdanm	0:9b334a45a8ff	5319	/* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */
bogdanm	0:9b334a45a8ff	5320	#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /!< Position of TXADDRESS field. /
bogdanm	0:9b334a45a8ff	5321	#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /!< Bit mask of TXADDRESS field. /
bogdanm	0:9b334a45a8ff	5322
bogdanm	0:9b334a45a8ff	5323	/* Register: RADIO_RXADDRESSES */
bogdanm	0:9b334a45a8ff	5324	/* Description: Receive address select. */
bogdanm	0:9b334a45a8ff	5325
bogdanm	0:9b334a45a8ff	5326	/* Bit 7 : Enable reception on logical address 7. Decision point: START task. */
bogdanm	0:9b334a45a8ff	5327	#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /!< Position of ADDR7 field. /
bogdanm	0:9b334a45a8ff	5328	#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /!< Bit mask of ADDR7 field. /
bogdanm	0:9b334a45a8ff	5329	#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /!< Reception disabled. /
bogdanm	0:9b334a45a8ff	5330	#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /!< Reception enabled. /
bogdanm	0:9b334a45a8ff	5331
bogdanm	0:9b334a45a8ff	5332	/* Bit 6 : Enable reception on logical address 6. Decision point: START task. */
bogdanm	0:9b334a45a8ff	5333	#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /!< Position of ADDR6 field. /
bogdanm	0:9b334a45a8ff	5334	#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /!< Bit mask of ADDR6 field. /
bogdanm	0:9b334a45a8ff	5335	#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /!< Reception disabled. /
bogdanm	0:9b334a45a8ff	5336	#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /!< Reception enabled. /
bogdanm	0:9b334a45a8ff	5337
bogdanm	0:9b334a45a8ff	5338	/* Bit 5 : Enable reception on logical address 5. Decision point: START task. */
bogdanm	0:9b334a45a8ff	5339	#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /!< Position of ADDR5 field. /
bogdanm	0:9b334a45a8ff	5340	#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /!< Bit mask of ADDR5 field. /
bogdanm	0:9b334a45a8ff	5341	#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /!< Reception disabled. /
bogdanm	0:9b334a45a8ff	5342	#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /!< Reception enabled. /
bogdanm	0:9b334a45a8ff	5343
bogdanm	0:9b334a45a8ff	5344	/* Bit 4 : Enable reception on logical address 4. Decision point: START task. */
bogdanm	0:9b334a45a8ff	5345	#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /!< Position of ADDR4 field. /
bogdanm	0:9b334a45a8ff	5346	#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /!< Bit mask of ADDR4 field. /
bogdanm	0:9b334a45a8ff	5347	#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /!< Reception disabled. /
bogdanm	0:9b334a45a8ff	5348	#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /!< Reception enabled. /
bogdanm	0:9b334a45a8ff	5349
bogdanm	0:9b334a45a8ff	5350	/* Bit 3 : Enable reception on logical address 3. Decision point: START task. */
bogdanm	0:9b334a45a8ff	5351	#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /!< Position of ADDR3 field. /
bogdanm	0:9b334a45a8ff	5352	#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /!< Bit mask of ADDR3 field. /
bogdanm	0:9b334a45a8ff	5353	#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /!< Reception disabled. /
bogdanm	0:9b334a45a8ff	5354	#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /!< Reception enabled. /
bogdanm	0:9b334a45a8ff	5355
bogdanm	0:9b334a45a8ff	5356	/* Bit 2 : Enable reception on logical address 2. Decision point: START task. */
bogdanm	0:9b334a45a8ff	5357	#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /!< Position of ADDR2 field. /
bogdanm	0:9b334a45a8ff	5358	#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /!< Bit mask of ADDR2 field. /
bogdanm	0:9b334a45a8ff	5359	#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /!< Reception disabled. /
bogdanm	0:9b334a45a8ff	5360	#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /!< Reception enabled. /
bogdanm	0:9b334a45a8ff	5361
bogdanm	0:9b334a45a8ff	5362	/* Bit 1 : Enable reception on logical address 1. Decision point: START task. */
bogdanm	0:9b334a45a8ff	5363	#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /!< Position of ADDR1 field. /
bogdanm	0:9b334a45a8ff	5364	#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /!< Bit mask of ADDR1 field. /
bogdanm	0:9b334a45a8ff	5365	#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /!< Reception disabled. /
bogdanm	0:9b334a45a8ff	5366	#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /!< Reception enabled. /
bogdanm	0:9b334a45a8ff	5367
bogdanm	0:9b334a45a8ff	5368	/* Bit 0 : Enable reception on logical address 0. Decision point: START task. */
bogdanm	0:9b334a45a8ff	5369	#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /!< Position of ADDR0 field. /
bogdanm	0:9b334a45a8ff	5370	#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /!< Bit mask of ADDR0 field. /
bogdanm	0:9b334a45a8ff	5371	#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /!< Reception disabled. /
bogdanm	0:9b334a45a8ff	5372	#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /!< Reception enabled. /
bogdanm	0:9b334a45a8ff	5373
bogdanm	0:9b334a45a8ff	5374	/* Register: RADIO_CRCCNF */
bogdanm	0:9b334a45a8ff	5375	/* Description: CRC configuration. */
bogdanm	0:9b334a45a8ff	5376
bogdanm	0:9b334a45a8ff	5377	/* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */
bogdanm	0:9b334a45a8ff	5378	#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /!< Position of SKIPADDR field. /
bogdanm	0:9b334a45a8ff	5379	#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /!< Bit mask of SKIPADDR field. /
bogdanm	0:9b334a45a8ff	5380	#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /!< Include packet address in CRC calculation. /
bogdanm	0:9b334a45a8ff	5381	#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. /
bogdanm	0:9b334a45a8ff	5382
bogdanm	0:9b334a45a8ff	5383	/* Bits 1..0 : CRC length. Decision point: START task. */
bogdanm	0:9b334a45a8ff	5384	#define RADIO_CRCCNF_LEN_Pos (0UL) /!< Position of LEN field. /
bogdanm	0:9b334a45a8ff	5385	#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /!< Bit mask of LEN field. /
bogdanm	0:9b334a45a8ff	5386	#define RADIO_CRCCNF_LEN_Disabled (0UL) /!< CRC calculation disabled. /
bogdanm	0:9b334a45a8ff	5387	#define RADIO_CRCCNF_LEN_One (1UL) /!< One byte long CRC. /
bogdanm	0:9b334a45a8ff	5388	#define RADIO_CRCCNF_LEN_Two (2UL) /!< Two bytes long CRC. /
bogdanm	0:9b334a45a8ff	5389	#define RADIO_CRCCNF_LEN_Three (3UL) /!< Three bytes long CRC. /
bogdanm	0:9b334a45a8ff	5390
bogdanm	0:9b334a45a8ff	5391	/* Register: RADIO_CRCPOLY */
bogdanm	0:9b334a45a8ff	5392	/* Description: CRC polynomial. */
bogdanm	0:9b334a45a8ff	5393
bogdanm	0:9b334a45a8ff	5394	/* Bits 23..0 : CRC polynomial. Decision point: START task. */
bogdanm	0:9b334a45a8ff	5395	#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /!< Position of CRCPOLY field. /
bogdanm	0:9b334a45a8ff	5396	#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /!< Bit mask of CRCPOLY field. /
bogdanm	0:9b334a45a8ff	5397
bogdanm	0:9b334a45a8ff	5398	/* Register: RADIO_CRCINIT */
bogdanm	0:9b334a45a8ff	5399	/* Description: CRC initial value. */
bogdanm	0:9b334a45a8ff	5400
bogdanm	0:9b334a45a8ff	5401	/* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */
bogdanm	0:9b334a45a8ff	5402	#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /!< Position of CRCINIT field. /
bogdanm	0:9b334a45a8ff	5403	#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /!< Bit mask of CRCINIT field. /
bogdanm	0:9b334a45a8ff	5404
bogdanm	0:9b334a45a8ff	5405	/* Register: RADIO_TEST */
bogdanm	0:9b334a45a8ff	5406	/* Description: Test features enable register. */
bogdanm	0:9b334a45a8ff	5407
bogdanm	0:9b334a45a8ff	5408	/* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */
bogdanm	0:9b334a45a8ff	5409	#define RADIO_TEST_PLLLOCK_Pos (1UL) /!< Position of PLLLOCK field. /
bogdanm	0:9b334a45a8ff	5410	#define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /!< Bit mask of PLLLOCK field. /
bogdanm	0:9b334a45a8ff	5411	#define RADIO_TEST_PLLLOCK_Disabled (0UL) /!< PLL lock disabled. /
bogdanm	0:9b334a45a8ff	5412	#define RADIO_TEST_PLLLOCK_Enabled (1UL) /!< PLL lock enabled. /
bogdanm	0:9b334a45a8ff	5413
bogdanm	0:9b334a45a8ff	5414	/* Bit 0 : Constant carrier. Decision point: TXEN task. */
bogdanm	0:9b334a45a8ff	5415	#define RADIO_TEST_CONSTCARRIER_Pos (0UL) /!< Position of CONSTCARRIER field. /
bogdanm	0:9b334a45a8ff	5416	#define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /!< Bit mask of CONSTCARRIER field. /
bogdanm	0:9b334a45a8ff	5417	#define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /!< Constant carrier disabled. /
bogdanm	0:9b334a45a8ff	5418	#define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /!< Constant carrier enabled. /
bogdanm	0:9b334a45a8ff	5419
bogdanm	0:9b334a45a8ff	5420	/* Register: RADIO_TIFS */
bogdanm	0:9b334a45a8ff	5421	/* Description: Inter Frame Spacing in microseconds. */
bogdanm	0:9b334a45a8ff	5422
bogdanm	0:9b334a45a8ff	5423	/* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */
bogdanm	0:9b334a45a8ff	5424	#define RADIO_TIFS_TIFS_Pos (0UL) /!< Position of TIFS field. /
bogdanm	0:9b334a45a8ff	5425	#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /!< Bit mask of TIFS field. /
bogdanm	0:9b334a45a8ff	5426
bogdanm	0:9b334a45a8ff	5427	/* Register: RADIO_RSSISAMPLE */
bogdanm	0:9b334a45a8ff	5428	/* Description: RSSI sample. */
bogdanm	0:9b334a45a8ff	5429
bogdanm	0:9b334a45a8ff	5430	/* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */
bogdanm	0:9b334a45a8ff	5431	#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /!< Position of RSSISAMPLE field. /
bogdanm	0:9b334a45a8ff	5432	#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /!< Bit mask of RSSISAMPLE field. /
bogdanm	0:9b334a45a8ff	5433
bogdanm	0:9b334a45a8ff	5434	/* Register: RADIO_STATE */
bogdanm	0:9b334a45a8ff	5435	/* Description: Current radio state. */
bogdanm	0:9b334a45a8ff	5436
bogdanm	0:9b334a45a8ff	5437	/* Bits 3..0 : Current radio state. */
bogdanm	0:9b334a45a8ff	5438	#define RADIO_STATE_STATE_Pos (0UL) /!< Position of STATE field. /
bogdanm	0:9b334a45a8ff	5439	#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /!< Bit mask of STATE field. /
bogdanm	0:9b334a45a8ff	5440	#define RADIO_STATE_STATE_Disabled (0x00UL) /!< Radio is in the Disabled state. /
bogdanm	0:9b334a45a8ff	5441	#define RADIO_STATE_STATE_RxRu (0x01UL) /!< Radio is in the Rx Ramp Up state. /
bogdanm	0:9b334a45a8ff	5442	#define RADIO_STATE_STATE_RxIdle (0x02UL) /!< Radio is in the Rx Idle state. /
bogdanm	0:9b334a45a8ff	5443	#define RADIO_STATE_STATE_Rx (0x03UL) /!< Radio is in the Rx state. /
bogdanm	0:9b334a45a8ff	5444	#define RADIO_STATE_STATE_RxDisable (0x04UL) /!< Radio is in the Rx Disable state. /
bogdanm	0:9b334a45a8ff	5445	#define RADIO_STATE_STATE_TxRu (0x09UL) /!< Radio is in the Tx Ramp Up state. /
bogdanm	0:9b334a45a8ff	5446	#define RADIO_STATE_STATE_TxIdle (0x0AUL) /!< Radio is in the Tx Idle state. /
bogdanm	0:9b334a45a8ff	5447	#define RADIO_STATE_STATE_Tx (0x0BUL) /!< Radio is in the Tx state. /
bogdanm	0:9b334a45a8ff	5448	#define RADIO_STATE_STATE_TxDisable (0x0CUL) /!< Radio is in the Tx Disable state. /
bogdanm	0:9b334a45a8ff	5449
bogdanm	0:9b334a45a8ff	5450	/* Register: RADIO_DATAWHITEIV */
bogdanm	0:9b334a45a8ff	5451	/* Description: Data whitening initial value. */
bogdanm	0:9b334a45a8ff	5452
bogdanm	0:9b334a45a8ff	5453	/* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */
bogdanm	0:9b334a45a8ff	5454	#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /!< Position of DATAWHITEIV field. /
bogdanm	0:9b334a45a8ff	5455	#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /!< Bit mask of DATAWHITEIV field. /
bogdanm	0:9b334a45a8ff	5456
bogdanm	0:9b334a45a8ff	5457	/* Register: RADIO_DAP */
bogdanm	0:9b334a45a8ff	5458	/* Description: Device address prefix. */
bogdanm	0:9b334a45a8ff	5459
bogdanm	0:9b334a45a8ff	5460	/* Bits 15..0 : Device address prefix. */
bogdanm	0:9b334a45a8ff	5461	#define RADIO_DAP_DAP_Pos (0UL) /!< Position of DAP field. /
bogdanm	0:9b334a45a8ff	5462	#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /!< Bit mask of DAP field. /
bogdanm	0:9b334a45a8ff	5463
bogdanm	0:9b334a45a8ff	5464	/* Register: RADIO_DACNF */
bogdanm	0:9b334a45a8ff	5465	/* Description: Device address match configuration. */
bogdanm	0:9b334a45a8ff	5466
bogdanm	0:9b334a45a8ff	5467	/* Bit 15 : TxAdd for device address 7. */
bogdanm	0:9b334a45a8ff	5468	#define RADIO_DACNF_TXADD7_Pos (15UL) /!< Position of TXADD7 field. /
bogdanm	0:9b334a45a8ff	5469	#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /!< Bit mask of TXADD7 field. /
bogdanm	0:9b334a45a8ff	5470
bogdanm	0:9b334a45a8ff	5471	/* Bit 14 : TxAdd for device address 6. */
bogdanm	0:9b334a45a8ff	5472	#define RADIO_DACNF_TXADD6_Pos (14UL) /!< Position of TXADD6 field. /
bogdanm	0:9b334a45a8ff	5473	#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /!< Bit mask of TXADD6 field. /
bogdanm	0:9b334a45a8ff	5474
bogdanm	0:9b334a45a8ff	5475	/* Bit 13 : TxAdd for device address 5. */
bogdanm	0:9b334a45a8ff	5476	#define RADIO_DACNF_TXADD5_Pos (13UL) /!< Position of TXADD5 field. /
bogdanm	0:9b334a45a8ff	5477	#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /!< Bit mask of TXADD5 field. /
bogdanm	0:9b334a45a8ff	5478
bogdanm	0:9b334a45a8ff	5479	/* Bit 12 : TxAdd for device address 4. */
bogdanm	0:9b334a45a8ff	5480	#define RADIO_DACNF_TXADD4_Pos (12UL) /!< Position of TXADD4 field. /
bogdanm	0:9b334a45a8ff	5481	#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /!< Bit mask of TXADD4 field. /
bogdanm	0:9b334a45a8ff	5482
bogdanm	0:9b334a45a8ff	5483	/* Bit 11 : TxAdd for device address 3. */
bogdanm	0:9b334a45a8ff	5484	#define RADIO_DACNF_TXADD3_Pos (11UL) /!< Position of TXADD3 field. /
bogdanm	0:9b334a45a8ff	5485	#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /!< Bit mask of TXADD3 field. /
bogdanm	0:9b334a45a8ff	5486
bogdanm	0:9b334a45a8ff	5487	/* Bit 10 : TxAdd for device address 2. */
bogdanm	0:9b334a45a8ff	5488	#define RADIO_DACNF_TXADD2_Pos (10UL) /!< Position of TXADD2 field. /
bogdanm	0:9b334a45a8ff	5489	#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /!< Bit mask of TXADD2 field. /
bogdanm	0:9b334a45a8ff	5490
bogdanm	0:9b334a45a8ff	5491	/* Bit 9 : TxAdd for device address 1. */
bogdanm	0:9b334a45a8ff	5492	#define RADIO_DACNF_TXADD1_Pos (9UL) /!< Position of TXADD1 field. /
bogdanm	0:9b334a45a8ff	5493	#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /!< Bit mask of TXADD1 field. /
bogdanm	0:9b334a45a8ff	5494
bogdanm	0:9b334a45a8ff	5495	/* Bit 8 : TxAdd for device address 0. */
bogdanm	0:9b334a45a8ff	5496	#define RADIO_DACNF_TXADD0_Pos (8UL) /!< Position of TXADD0 field. /
bogdanm	0:9b334a45a8ff	5497	#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /!< Bit mask of TXADD0 field. /
bogdanm	0:9b334a45a8ff	5498
bogdanm	0:9b334a45a8ff	5499	/* Bit 7 : Enable or disable device address matching using device address 7. */
bogdanm	0:9b334a45a8ff	5500	#define RADIO_DACNF_ENA7_Pos (7UL) /!< Position of ENA7 field. /
bogdanm	0:9b334a45a8ff	5501	#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /!< Bit mask of ENA7 field. /
bogdanm	0:9b334a45a8ff	5502	#define RADIO_DACNF_ENA7_Disabled (0UL) /!< Disabled. /
bogdanm	0:9b334a45a8ff	5503	#define RADIO_DACNF_ENA7_Enabled (1UL) /!< Enabled. /
bogdanm	0:9b334a45a8ff	5504
bogdanm	0:9b334a45a8ff	5505	/* Bit 6 : Enable or disable device address matching using device address 6. */
bogdanm	0:9b334a45a8ff	5506	#define RADIO_DACNF_ENA6_Pos (6UL) /!< Position of ENA6 field. /
bogdanm	0:9b334a45a8ff	5507	#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /!< Bit mask of ENA6 field. /
bogdanm	0:9b334a45a8ff	5508	#define RADIO_DACNF_ENA6_Disabled (0UL) /!< Disabled. /
bogdanm	0:9b334a45a8ff	5509	#define RADIO_DACNF_ENA6_Enabled (1UL) /!< Enabled. /
bogdanm	0:9b334a45a8ff	5510
bogdanm	0:9b334a45a8ff	5511	/* Bit 5 : Enable or disable device address matching using device address 5. */
bogdanm	0:9b334a45a8ff	5512	#define RADIO_DACNF_ENA5_Pos (5UL) /!< Position of ENA5 field. /
bogdanm	0:9b334a45a8ff	5513	#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /!< Bit mask of ENA5 field. /
bogdanm	0:9b334a45a8ff	5514	#define RADIO_DACNF_ENA5_Disabled (0UL) /!< Disabled. /
bogdanm	0:9b334a45a8ff	5515	#define RADIO_DACNF_ENA5_Enabled (1UL) /!< Enabled. /
bogdanm	0:9b334a45a8ff	5516
bogdanm	0:9b334a45a8ff	5517	/* Bit 4 : Enable or disable device address matching using device address 4. */
bogdanm	0:9b334a45a8ff	5518	#define RADIO_DACNF_ENA4_Pos (4UL) /!< Position of ENA4 field. /
bogdanm	0:9b334a45a8ff	5519	#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /!< Bit mask of ENA4 field. /
bogdanm	0:9b334a45a8ff	5520	#define RADIO_DACNF_ENA4_Disabled (0UL) /!< Disabled. /
bogdanm	0:9b334a45a8ff	5521	#define RADIO_DACNF_ENA4_Enabled (1UL) /!< Enabled. /
bogdanm	0:9b334a45a8ff	5522
bogdanm	0:9b334a45a8ff	5523	/* Bit 3 : Enable or disable device address matching using device address 3. */
bogdanm	0:9b334a45a8ff	5524	#define RADIO_DACNF_ENA3_Pos (3UL) /!< Position of ENA3 field. /
bogdanm	0:9b334a45a8ff	5525	#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /!< Bit mask of ENA3 field. /
bogdanm	0:9b334a45a8ff	5526	#define RADIO_DACNF_ENA3_Disabled (0UL) /!< Disabled. /
bogdanm	0:9b334a45a8ff	5527	#define RADIO_DACNF_ENA3_Enabled (1UL) /!< Enabled. /
bogdanm	0:9b334a45a8ff	5528
bogdanm	0:9b334a45a8ff	5529	/* Bit 2 : Enable or disable device address matching using device address 2. */
bogdanm	0:9b334a45a8ff	5530	#define RADIO_DACNF_ENA2_Pos (2UL) /!< Position of ENA2 field. /
bogdanm	0:9b334a45a8ff	5531	#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /!< Bit mask of ENA2 field. /
bogdanm	0:9b334a45a8ff	5532	#define RADIO_DACNF_ENA2_Disabled (0UL) /!< Disabled. /
bogdanm	0:9b334a45a8ff	5533	#define RADIO_DACNF_ENA2_Enabled (1UL) /!< Enabled. /
bogdanm	0:9b334a45a8ff	5534
bogdanm	0:9b334a45a8ff	5535	/* Bit 1 : Enable or disable device address matching using device address 1. */
bogdanm	0:9b334a45a8ff	5536	#define RADIO_DACNF_ENA1_Pos (1UL) /!< Position of ENA1 field. /
bogdanm	0:9b334a45a8ff	5537	#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /!< Bit mask of ENA1 field. /
bogdanm	0:9b334a45a8ff	5538	#define RADIO_DACNF_ENA1_Disabled (0UL) /!< Disabled. /
bogdanm	0:9b334a45a8ff	5539	#define RADIO_DACNF_ENA1_Enabled (1UL) /!< Enabled. /
bogdanm	0:9b334a45a8ff	5540
bogdanm	0:9b334a45a8ff	5541	/* Bit 0 : Enable or disable device address matching using device address 0. */
bogdanm	0:9b334a45a8ff	5542	#define RADIO_DACNF_ENA0_Pos (0UL) /!< Position of ENA0 field. /
bogdanm	0:9b334a45a8ff	5543	#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /!< Bit mask of ENA0 field. /
bogdanm	0:9b334a45a8ff	5544	#define RADIO_DACNF_ENA0_Disabled (0UL) /!< Disabled. /
bogdanm	0:9b334a45a8ff	5545	#define RADIO_DACNF_ENA0_Enabled (1UL) /!< Enabled. /
bogdanm	0:9b334a45a8ff	5546
bogdanm	0:9b334a45a8ff	5547	/* Register: RADIO_OVERRIDE0 */
bogdanm	0:9b334a45a8ff	5548	/* Description: Trim value override register 0. */
bogdanm	0:9b334a45a8ff	5549
bogdanm	0:9b334a45a8ff	5550	/* Bits 31..0 : Trim value override 0. */
bogdanm	0:9b334a45a8ff	5551	#define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /!< Position of OVERRIDE0 field. /
bogdanm	0:9b334a45a8ff	5552	#define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /!< Bit mask of OVERRIDE0 field. /
bogdanm	0:9b334a45a8ff	5553
bogdanm	0:9b334a45a8ff	5554	/* Register: RADIO_OVERRIDE1 */
bogdanm	0:9b334a45a8ff	5555	/* Description: Trim value override register 1. */
bogdanm	0:9b334a45a8ff	5556
bogdanm	0:9b334a45a8ff	5557	/* Bits 31..0 : Trim value override 1. */
bogdanm	0:9b334a45a8ff	5558	#define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /!< Position of OVERRIDE1 field. /
bogdanm	0:9b334a45a8ff	5559	#define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /!< Bit mask of OVERRIDE1 field. /
bogdanm	0:9b334a45a8ff	5560
bogdanm	0:9b334a45a8ff	5561	/* Register: RADIO_OVERRIDE2 */
bogdanm	0:9b334a45a8ff	5562	/* Description: Trim value override register 2. */
bogdanm	0:9b334a45a8ff	5563
bogdanm	0:9b334a45a8ff	5564	/* Bits 31..0 : Trim value override 2. */
bogdanm	0:9b334a45a8ff	5565	#define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /!< Position of OVERRIDE2 field. /
bogdanm	0:9b334a45a8ff	5566	#define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /!< Bit mask of OVERRIDE2 field. /
bogdanm	0:9b334a45a8ff	5567
bogdanm	0:9b334a45a8ff	5568	/* Register: RADIO_OVERRIDE3 */
bogdanm	0:9b334a45a8ff	5569	/* Description: Trim value override register 3. */
bogdanm	0:9b334a45a8ff	5570
bogdanm	0:9b334a45a8ff	5571	/* Bits 31..0 : Trim value override 3. */
bogdanm	0:9b334a45a8ff	5572	#define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /!< Position of OVERRIDE3 field. /
bogdanm	0:9b334a45a8ff	5573	#define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /!< Bit mask of OVERRIDE3 field. /
bogdanm	0:9b334a45a8ff	5574
bogdanm	0:9b334a45a8ff	5575	/* Register: RADIO_OVERRIDE4 */
bogdanm	0:9b334a45a8ff	5576	/* Description: Trim value override register 4. */
bogdanm	0:9b334a45a8ff	5577
bogdanm	0:9b334a45a8ff	5578	/* Bit 31 : Enable or disable override of default trim values. */
bogdanm	0:9b334a45a8ff	5579	#define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /!< Position of ENABLE field. /
bogdanm	0:9b334a45a8ff	5580	#define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /!< Bit mask of ENABLE field. /
bogdanm	0:9b334a45a8ff	5581	#define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /!< Override trim values disabled. /
bogdanm	0:9b334a45a8ff	5582	#define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /!< Override trim values enabled. /
bogdanm	0:9b334a45a8ff	5583
bogdanm	0:9b334a45a8ff	5584	/* Bits 27..0 : Trim value override 4. */
bogdanm	0:9b334a45a8ff	5585	#define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /!< Position of OVERRIDE4 field. /
bogdanm	0:9b334a45a8ff	5586	#define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /!< Bit mask of OVERRIDE4 field. /
bogdanm	0:9b334a45a8ff	5587
bogdanm	0:9b334a45a8ff	5588	/* Register: RADIO_POWER */
bogdanm	0:9b334a45a8ff	5589	/* Description: Peripheral power control. */
bogdanm	0:9b334a45a8ff	5590
bogdanm	0:9b334a45a8ff	5591	/* Bit 0 : Peripheral power control. */
bogdanm	0:9b334a45a8ff	5592	#define RADIO_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	0:9b334a45a8ff	5593	#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	0:9b334a45a8ff	5594	#define RADIO_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	0:9b334a45a8ff	5595	#define RADIO_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	0:9b334a45a8ff	5596
bogdanm	0:9b334a45a8ff	5597
bogdanm	0:9b334a45a8ff	5598	/* Peripheral: RNG */
bogdanm	0:9b334a45a8ff	5599	/* Description: Random Number Generator. */
bogdanm	0:9b334a45a8ff	5600
bogdanm	0:9b334a45a8ff	5601	/* Register: RNG_SHORTS */
bogdanm	0:9b334a45a8ff	5602	/* Description: Shortcuts for the RNG. */
bogdanm	0:9b334a45a8ff	5603
bogdanm	0:9b334a45a8ff	5604	/* Bit 0 : Shortcut between VALRDY event and STOP task. */
bogdanm	0:9b334a45a8ff	5605	#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /!< Position of VALRDY_STOP field. /
bogdanm	0:9b334a45a8ff	5606	#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /!< Bit mask of VALRDY_STOP field. /
bogdanm	0:9b334a45a8ff	5607	#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	0:9b334a45a8ff	5608	#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	0:9b334a45a8ff	5609
bogdanm	0:9b334a45a8ff	5610	/* Register: RNG_INTENSET */
bogdanm	0:9b334a45a8ff	5611	/* Description: Interrupt enable set register */
bogdanm	0:9b334a45a8ff	5612
bogdanm	0:9b334a45a8ff	5613	/* Bit 0 : Enable interrupt on VALRDY event. */
bogdanm	0:9b334a45a8ff	5614	#define RNG_INTENSET_VALRDY_Pos (0UL) /!< Position of VALRDY field. /
bogdanm	0:9b334a45a8ff	5615	#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /!< Bit mask of VALRDY field. /
bogdanm	0:9b334a45a8ff	5616	#define RNG_INTENSET_VALRDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	5617	#define RNG_INTENSET_VALRDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	5618	#define RNG_INTENSET_VALRDY_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	5619
bogdanm	0:9b334a45a8ff	5620	/* Register: RNG_INTENCLR */
bogdanm	0:9b334a45a8ff	5621	/* Description: Interrupt enable clear register */
bogdanm	0:9b334a45a8ff	5622
bogdanm	0:9b334a45a8ff	5623	/* Bit 0 : Disable interrupt on VALRDY event. */
bogdanm	0:9b334a45a8ff	5624	#define RNG_INTENCLR_VALRDY_Pos (0UL) /!< Position of VALRDY field. /
bogdanm	0:9b334a45a8ff	5625	#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /!< Bit mask of VALRDY field. /
bogdanm	0:9b334a45a8ff	5626	#define RNG_INTENCLR_VALRDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	5627	#define RNG_INTENCLR_VALRDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	5628	#define RNG_INTENCLR_VALRDY_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	5629
bogdanm	0:9b334a45a8ff	5630	/* Register: RNG_CONFIG */
bogdanm	0:9b334a45a8ff	5631	/* Description: Configuration register. */
bogdanm	0:9b334a45a8ff	5632
bogdanm	0:9b334a45a8ff	5633	/* Bit 0 : Digital error correction enable. */
bogdanm	0:9b334a45a8ff	5634	#define RNG_CONFIG_DERCEN_Pos (0UL) /!< Position of DERCEN field. /
bogdanm	0:9b334a45a8ff	5635	#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /!< Bit mask of DERCEN field. /
bogdanm	0:9b334a45a8ff	5636	#define RNG_CONFIG_DERCEN_Disabled (0UL) /!< Digital error correction disabled. /
bogdanm	0:9b334a45a8ff	5637	#define RNG_CONFIG_DERCEN_Enabled (1UL) /!< Digital error correction enabled. /
bogdanm	0:9b334a45a8ff	5638
bogdanm	0:9b334a45a8ff	5639	/* Register: RNG_VALUE */
bogdanm	0:9b334a45a8ff	5640	/* Description: RNG random number. */
bogdanm	0:9b334a45a8ff	5641
bogdanm	0:9b334a45a8ff	5642	/* Bits 7..0 : Generated random number. */
bogdanm	0:9b334a45a8ff	5643	#define RNG_VALUE_VALUE_Pos (0UL) /!< Position of VALUE field. /
bogdanm	0:9b334a45a8ff	5644	#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /!< Bit mask of VALUE field. /
bogdanm	0:9b334a45a8ff	5645
bogdanm	0:9b334a45a8ff	5646	/* Register: RNG_POWER */
bogdanm	0:9b334a45a8ff	5647	/* Description: Peripheral power control. */
bogdanm	0:9b334a45a8ff	5648
bogdanm	0:9b334a45a8ff	5649	/* Bit 0 : Peripheral power control. */
bogdanm	0:9b334a45a8ff	5650	#define RNG_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	0:9b334a45a8ff	5651	#define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	0:9b334a45a8ff	5652	#define RNG_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	0:9b334a45a8ff	5653	#define RNG_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	0:9b334a45a8ff	5654
bogdanm	0:9b334a45a8ff	5655
bogdanm	0:9b334a45a8ff	5656	/* Peripheral: RTC */
bogdanm	0:9b334a45a8ff	5657	/* Description: Real time counter 0. */
bogdanm	0:9b334a45a8ff	5658
bogdanm	0:9b334a45a8ff	5659	/* Register: RTC_INTENSET */
bogdanm	0:9b334a45a8ff	5660	/* Description: Interrupt enable set register. */
bogdanm	0:9b334a45a8ff	5661
bogdanm	0:9b334a45a8ff	5662	/* Bit 19 : Enable interrupt on COMPARE[3] event. */
bogdanm	0:9b334a45a8ff	5663	#define RTC_INTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
bogdanm	0:9b334a45a8ff	5664	#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
bogdanm	0:9b334a45a8ff	5665	#define RTC_INTENSET_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	5666	#define RTC_INTENSET_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	5667	#define RTC_INTENSET_COMPARE3_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	5668
bogdanm	0:9b334a45a8ff	5669	/* Bit 18 : Enable interrupt on COMPARE[2] event. */
bogdanm	0:9b334a45a8ff	5670	#define RTC_INTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
bogdanm	0:9b334a45a8ff	5671	#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
bogdanm	0:9b334a45a8ff	5672	#define RTC_INTENSET_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	5673	#define RTC_INTENSET_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	5674	#define RTC_INTENSET_COMPARE2_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	5675
bogdanm	0:9b334a45a8ff	5676	/* Bit 17 : Enable interrupt on COMPARE[1] event. */
bogdanm	0:9b334a45a8ff	5677	#define RTC_INTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
bogdanm	0:9b334a45a8ff	5678	#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
bogdanm	0:9b334a45a8ff	5679	#define RTC_INTENSET_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	5680	#define RTC_INTENSET_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	5681	#define RTC_INTENSET_COMPARE1_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	5682
bogdanm	0:9b334a45a8ff	5683	/* Bit 16 : Enable interrupt on COMPARE[0] event. */
bogdanm	0:9b334a45a8ff	5684	#define RTC_INTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
bogdanm	0:9b334a45a8ff	5685	#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
bogdanm	0:9b334a45a8ff	5686	#define RTC_INTENSET_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	5687	#define RTC_INTENSET_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	5688	#define RTC_INTENSET_COMPARE0_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	5689
bogdanm	0:9b334a45a8ff	5690	/* Bit 1 : Enable interrupt on OVRFLW event. */
bogdanm	0:9b334a45a8ff	5691	#define RTC_INTENSET_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
bogdanm	0:9b334a45a8ff	5692	#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
bogdanm	0:9b334a45a8ff	5693	#define RTC_INTENSET_OVRFLW_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	5694	#define RTC_INTENSET_OVRFLW_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	5695	#define RTC_INTENSET_OVRFLW_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	5696
bogdanm	0:9b334a45a8ff	5697	/* Bit 0 : Enable interrupt on TICK event. */
bogdanm	0:9b334a45a8ff	5698	#define RTC_INTENSET_TICK_Pos (0UL) /!< Position of TICK field. /
bogdanm	0:9b334a45a8ff	5699	#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /!< Bit mask of TICK field. /
bogdanm	0:9b334a45a8ff	5700	#define RTC_INTENSET_TICK_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	5701	#define RTC_INTENSET_TICK_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	5702	#define RTC_INTENSET_TICK_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	5703
bogdanm	0:9b334a45a8ff	5704	/* Register: RTC_INTENCLR */
bogdanm	0:9b334a45a8ff	5705	/* Description: Interrupt enable clear register. */
bogdanm	0:9b334a45a8ff	5706
bogdanm	0:9b334a45a8ff	5707	/* Bit 19 : Disable interrupt on COMPARE[3] event. */
bogdanm	0:9b334a45a8ff	5708	#define RTC_INTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
bogdanm	0:9b334a45a8ff	5709	#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
bogdanm	0:9b334a45a8ff	5710	#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	5711	#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	5712	#define RTC_INTENCLR_COMPARE3_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	5713
bogdanm	0:9b334a45a8ff	5714	/* Bit 18 : Disable interrupt on COMPARE[2] event. */
bogdanm	0:9b334a45a8ff	5715	#define RTC_INTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
bogdanm	0:9b334a45a8ff	5716	#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
bogdanm	0:9b334a45a8ff	5717	#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	5718	#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	5719	#define RTC_INTENCLR_COMPARE2_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	5720
bogdanm	0:9b334a45a8ff	5721	/* Bit 17 : Disable interrupt on COMPARE[1] event. */
bogdanm	0:9b334a45a8ff	5722	#define RTC_INTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
bogdanm	0:9b334a45a8ff	5723	#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
bogdanm	0:9b334a45a8ff	5724	#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	5725	#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	5726	#define RTC_INTENCLR_COMPARE1_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	5727
bogdanm	0:9b334a45a8ff	5728	/* Bit 16 : Disable interrupt on COMPARE[0] event. */
bogdanm	0:9b334a45a8ff	5729	#define RTC_INTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
bogdanm	0:9b334a45a8ff	5730	#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
bogdanm	0:9b334a45a8ff	5731	#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	5732	#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	5733	#define RTC_INTENCLR_COMPARE0_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	5734
bogdanm	0:9b334a45a8ff	5735	/* Bit 1 : Disable interrupt on OVRFLW event. */
bogdanm	0:9b334a45a8ff	5736	#define RTC_INTENCLR_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
bogdanm	0:9b334a45a8ff	5737	#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
bogdanm	0:9b334a45a8ff	5738	#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	5739	#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	5740	#define RTC_INTENCLR_OVRFLW_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	5741
bogdanm	0:9b334a45a8ff	5742	/* Bit 0 : Disable interrupt on TICK event. */
bogdanm	0:9b334a45a8ff	5743	#define RTC_INTENCLR_TICK_Pos (0UL) /!< Position of TICK field. /
bogdanm	0:9b334a45a8ff	5744	#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /!< Bit mask of TICK field. /
bogdanm	0:9b334a45a8ff	5745	#define RTC_INTENCLR_TICK_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	5746	#define RTC_INTENCLR_TICK_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	5747	#define RTC_INTENCLR_TICK_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	5748
bogdanm	0:9b334a45a8ff	5749	/* Register: RTC_EVTEN */
bogdanm	0:9b334a45a8ff	5750	/* Description: Configures event enable routing to PPI for each RTC event. */
bogdanm	0:9b334a45a8ff	5751
bogdanm	0:9b334a45a8ff	5752	/* Bit 19 : COMPARE[3] event enable. */
bogdanm	0:9b334a45a8ff	5753	#define RTC_EVTEN_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
bogdanm	0:9b334a45a8ff	5754	#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
bogdanm	0:9b334a45a8ff	5755	#define RTC_EVTEN_COMPARE3_Disabled (0UL) /!< Event disabled. /
bogdanm	0:9b334a45a8ff	5756	#define RTC_EVTEN_COMPARE3_Enabled (1UL) /!< Event enabled. /
bogdanm	0:9b334a45a8ff	5757
bogdanm	0:9b334a45a8ff	5758	/* Bit 18 : COMPARE[2] event enable. */
bogdanm	0:9b334a45a8ff	5759	#define RTC_EVTEN_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
bogdanm	0:9b334a45a8ff	5760	#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
bogdanm	0:9b334a45a8ff	5761	#define RTC_EVTEN_COMPARE2_Disabled (0UL) /!< Event disabled. /
bogdanm	0:9b334a45a8ff	5762	#define RTC_EVTEN_COMPARE2_Enabled (1UL) /!< Event enabled. /
bogdanm	0:9b334a45a8ff	5763
bogdanm	0:9b334a45a8ff	5764	/* Bit 17 : COMPARE[1] event enable. */
bogdanm	0:9b334a45a8ff	5765	#define RTC_EVTEN_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
bogdanm	0:9b334a45a8ff	5766	#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
bogdanm	0:9b334a45a8ff	5767	#define RTC_EVTEN_COMPARE1_Disabled (0UL) /!< Event disabled. /
bogdanm	0:9b334a45a8ff	5768	#define RTC_EVTEN_COMPARE1_Enabled (1UL) /!< Event enabled. /
bogdanm	0:9b334a45a8ff	5769
bogdanm	0:9b334a45a8ff	5770	/* Bit 16 : COMPARE[0] event enable. */
bogdanm	0:9b334a45a8ff	5771	#define RTC_EVTEN_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
bogdanm	0:9b334a45a8ff	5772	#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
bogdanm	0:9b334a45a8ff	5773	#define RTC_EVTEN_COMPARE0_Disabled (0UL) /!< Event disabled. /
bogdanm	0:9b334a45a8ff	5774	#define RTC_EVTEN_COMPARE0_Enabled (1UL) /!< Event enabled. /
bogdanm	0:9b334a45a8ff	5775
bogdanm	0:9b334a45a8ff	5776	/* Bit 1 : OVRFLW event enable. */
bogdanm	0:9b334a45a8ff	5777	#define RTC_EVTEN_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
bogdanm	0:9b334a45a8ff	5778	#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
bogdanm	0:9b334a45a8ff	5779	#define RTC_EVTEN_OVRFLW_Disabled (0UL) /!< Event disabled. /
bogdanm	0:9b334a45a8ff	5780	#define RTC_EVTEN_OVRFLW_Enabled (1UL) /!< Event enabled. /
bogdanm	0:9b334a45a8ff	5781
bogdanm	0:9b334a45a8ff	5782	/* Bit 0 : TICK event enable. */
bogdanm	0:9b334a45a8ff	5783	#define RTC_EVTEN_TICK_Pos (0UL) /!< Position of TICK field. /
bogdanm	0:9b334a45a8ff	5784	#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /!< Bit mask of TICK field. /
bogdanm	0:9b334a45a8ff	5785	#define RTC_EVTEN_TICK_Disabled (0UL) /!< Event disabled. /
bogdanm	0:9b334a45a8ff	5786	#define RTC_EVTEN_TICK_Enabled (1UL) /!< Event enabled. /
bogdanm	0:9b334a45a8ff	5787
bogdanm	0:9b334a45a8ff	5788	/* Register: RTC_EVTENSET */
bogdanm	0:9b334a45a8ff	5789	/* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */
bogdanm	0:9b334a45a8ff	5790
bogdanm	0:9b334a45a8ff	5791	/* Bit 19 : Enable routing to PPI of COMPARE[3] event. */
bogdanm	0:9b334a45a8ff	5792	#define RTC_EVTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
bogdanm	0:9b334a45a8ff	5793	#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
bogdanm	0:9b334a45a8ff	5794	#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /!< Event disabled. /
bogdanm	0:9b334a45a8ff	5795	#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /!< Event enabled. /
bogdanm	0:9b334a45a8ff	5796	#define RTC_EVTENSET_COMPARE3_Set (1UL) /!< Enable event on write. /
bogdanm	0:9b334a45a8ff	5797
bogdanm	0:9b334a45a8ff	5798	/* Bit 18 : Enable routing to PPI of COMPARE[2] event. */
bogdanm	0:9b334a45a8ff	5799	#define RTC_EVTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
bogdanm	0:9b334a45a8ff	5800	#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
bogdanm	0:9b334a45a8ff	5801	#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /!< Event disabled. /
bogdanm	0:9b334a45a8ff	5802	#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /!< Event enabled. /
bogdanm	0:9b334a45a8ff	5803	#define RTC_EVTENSET_COMPARE2_Set (1UL) /!< Enable event on write. /
bogdanm	0:9b334a45a8ff	5804
bogdanm	0:9b334a45a8ff	5805	/* Bit 17 : Enable routing to PPI of COMPARE[1] event. */
bogdanm	0:9b334a45a8ff	5806	#define RTC_EVTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
bogdanm	0:9b334a45a8ff	5807	#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
bogdanm	0:9b334a45a8ff	5808	#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /!< Event disabled. /
bogdanm	0:9b334a45a8ff	5809	#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /!< Event enabled. /
bogdanm	0:9b334a45a8ff	5810	#define RTC_EVTENSET_COMPARE1_Set (1UL) /!< Enable event on write. /
bogdanm	0:9b334a45a8ff	5811
bogdanm	0:9b334a45a8ff	5812	/* Bit 16 : Enable routing to PPI of COMPARE[0] event. */
bogdanm	0:9b334a45a8ff	5813	#define RTC_EVTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
bogdanm	0:9b334a45a8ff	5814	#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
bogdanm	0:9b334a45a8ff	5815	#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /!< Event disabled. /
bogdanm	0:9b334a45a8ff	5816	#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /!< Event enabled. /
bogdanm	0:9b334a45a8ff	5817	#define RTC_EVTENSET_COMPARE0_Set (1UL) /!< Enable event on write. /
bogdanm	0:9b334a45a8ff	5818
bogdanm	0:9b334a45a8ff	5819	/* Bit 1 : Enable routing to PPI of OVRFLW event. */
bogdanm	0:9b334a45a8ff	5820	#define RTC_EVTENSET_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
bogdanm	0:9b334a45a8ff	5821	#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
bogdanm	0:9b334a45a8ff	5822	#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /!< Event disabled. /
bogdanm	0:9b334a45a8ff	5823	#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /!< Event enabled. /
bogdanm	0:9b334a45a8ff	5824	#define RTC_EVTENSET_OVRFLW_Set (1UL) /!< Enable event on write. /
bogdanm	0:9b334a45a8ff	5825
bogdanm	0:9b334a45a8ff	5826	/* Bit 0 : Enable routing to PPI of TICK event. */
bogdanm	0:9b334a45a8ff	5827	#define RTC_EVTENSET_TICK_Pos (0UL) /!< Position of TICK field. /
bogdanm	0:9b334a45a8ff	5828	#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /!< Bit mask of TICK field. /
bogdanm	0:9b334a45a8ff	5829	#define RTC_EVTENSET_TICK_Disabled (0UL) /!< Event disabled. /
bogdanm	0:9b334a45a8ff	5830	#define RTC_EVTENSET_TICK_Enabled (1UL) /!< Event enabled. /
bogdanm	0:9b334a45a8ff	5831	#define RTC_EVTENSET_TICK_Set (1UL) /!< Enable event on write. /
bogdanm	0:9b334a45a8ff	5832
bogdanm	0:9b334a45a8ff	5833	/* Register: RTC_EVTENCLR */
bogdanm	0:9b334a45a8ff	5834	/* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */
bogdanm	0:9b334a45a8ff	5835
bogdanm	0:9b334a45a8ff	5836	/* Bit 19 : Disable routing to PPI of COMPARE[3] event. */
bogdanm	0:9b334a45a8ff	5837	#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
bogdanm	0:9b334a45a8ff	5838	#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
bogdanm	0:9b334a45a8ff	5839	#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /!< Event disabled. /
bogdanm	0:9b334a45a8ff	5840	#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /!< Event enabled. /
bogdanm	0:9b334a45a8ff	5841	#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /!< Disable event on write. /
bogdanm	0:9b334a45a8ff	5842
bogdanm	0:9b334a45a8ff	5843	/* Bit 18 : Disable routing to PPI of COMPARE[2] event. */
bogdanm	0:9b334a45a8ff	5844	#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
bogdanm	0:9b334a45a8ff	5845	#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
bogdanm	0:9b334a45a8ff	5846	#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /!< Event disabled. /
bogdanm	0:9b334a45a8ff	5847	#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /!< Event enabled. /
bogdanm	0:9b334a45a8ff	5848	#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /!< Disable event on write. /
bogdanm	0:9b334a45a8ff	5849
bogdanm	0:9b334a45a8ff	5850	/* Bit 17 : Disable routing to PPI of COMPARE[1] event. */
bogdanm	0:9b334a45a8ff	5851	#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
bogdanm	0:9b334a45a8ff	5852	#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
bogdanm	0:9b334a45a8ff	5853	#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /!< Event disabled. /
bogdanm	0:9b334a45a8ff	5854	#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /!< Event enabled. /
bogdanm	0:9b334a45a8ff	5855	#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /!< Disable event on write. /
bogdanm	0:9b334a45a8ff	5856
bogdanm	0:9b334a45a8ff	5857	/* Bit 16 : Disable routing to PPI of COMPARE[0] event. */
bogdanm	0:9b334a45a8ff	5858	#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
bogdanm	0:9b334a45a8ff	5859	#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
bogdanm	0:9b334a45a8ff	5860	#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /!< Event disabled. /
bogdanm	0:9b334a45a8ff	5861	#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /!< Event enabled. /
bogdanm	0:9b334a45a8ff	5862	#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /!< Disable event on write. /
bogdanm	0:9b334a45a8ff	5863
bogdanm	0:9b334a45a8ff	5864	/* Bit 1 : Disable routing to PPI of OVRFLW event. */
bogdanm	0:9b334a45a8ff	5865	#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
bogdanm	0:9b334a45a8ff	5866	#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
bogdanm	0:9b334a45a8ff	5867	#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /!< Event disabled. /
bogdanm	0:9b334a45a8ff	5868	#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /!< Event enabled. /
bogdanm	0:9b334a45a8ff	5869	#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /!< Disable event on write. /
bogdanm	0:9b334a45a8ff	5870
bogdanm	0:9b334a45a8ff	5871	/* Bit 0 : Disable routing to PPI of TICK event. */
bogdanm	0:9b334a45a8ff	5872	#define RTC_EVTENCLR_TICK_Pos (0UL) /!< Position of TICK field. /
bogdanm	0:9b334a45a8ff	5873	#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /!< Bit mask of TICK field. /
bogdanm	0:9b334a45a8ff	5874	#define RTC_EVTENCLR_TICK_Disabled (0UL) /!< Event disabled. /
bogdanm	0:9b334a45a8ff	5875	#define RTC_EVTENCLR_TICK_Enabled (1UL) /!< Event enabled. /
bogdanm	0:9b334a45a8ff	5876	#define RTC_EVTENCLR_TICK_Clear (1UL) /!< Disable event on write. /
bogdanm	0:9b334a45a8ff	5877
bogdanm	0:9b334a45a8ff	5878	/* Register: RTC_COUNTER */
bogdanm	0:9b334a45a8ff	5879	/* Description: Current COUNTER value. */
bogdanm	0:9b334a45a8ff	5880
bogdanm	0:9b334a45a8ff	5881	/* Bits 23..0 : Counter value. */
bogdanm	0:9b334a45a8ff	5882	#define RTC_COUNTER_COUNTER_Pos (0UL) /!< Position of COUNTER field. /
bogdanm	0:9b334a45a8ff	5883	#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /!< Bit mask of COUNTER field. /
bogdanm	0:9b334a45a8ff	5884
bogdanm	0:9b334a45a8ff	5885	/* Register: RTC_PRESCALER */
bogdanm	0:9b334a45a8ff	5886	/* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */
bogdanm	0:9b334a45a8ff	5887
bogdanm	0:9b334a45a8ff	5888	/* Bits 11..0 : RTC PRESCALER value. */
bogdanm	0:9b334a45a8ff	5889	#define RTC_PRESCALER_PRESCALER_Pos (0UL) /!< Position of PRESCALER field. /
bogdanm	0:9b334a45a8ff	5890	#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /!< Bit mask of PRESCALER field. /
bogdanm	0:9b334a45a8ff	5891
bogdanm	0:9b334a45a8ff	5892	/* Register: RTC_CC */
bogdanm	0:9b334a45a8ff	5893	/* Description: Capture/compare registers. */
bogdanm	0:9b334a45a8ff	5894
bogdanm	0:9b334a45a8ff	5895	/* Bits 23..0 : Compare value. */
bogdanm	0:9b334a45a8ff	5896	#define RTC_CC_COMPARE_Pos (0UL) /!< Position of COMPARE field. /
bogdanm	0:9b334a45a8ff	5897	#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /!< Bit mask of COMPARE field. /
bogdanm	0:9b334a45a8ff	5898
bogdanm	0:9b334a45a8ff	5899	/* Register: RTC_POWER */
bogdanm	0:9b334a45a8ff	5900	/* Description: Peripheral power control. */
bogdanm	0:9b334a45a8ff	5901
bogdanm	0:9b334a45a8ff	5902	/* Bit 0 : Peripheral power control. */
bogdanm	0:9b334a45a8ff	5903	#define RTC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	0:9b334a45a8ff	5904	#define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	0:9b334a45a8ff	5905	#define RTC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	0:9b334a45a8ff	5906	#define RTC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	0:9b334a45a8ff	5907
bogdanm	0:9b334a45a8ff	5908
bogdanm	0:9b334a45a8ff	5909	/* Peripheral: SPI */
bogdanm	0:9b334a45a8ff	5910	/* Description: SPI master 0. */
bogdanm	0:9b334a45a8ff	5911
bogdanm	0:9b334a45a8ff	5912	/* Register: SPI_INTENSET */
bogdanm	0:9b334a45a8ff	5913	/* Description: Interrupt enable set register. */
bogdanm	0:9b334a45a8ff	5914
bogdanm	0:9b334a45a8ff	5915	/* Bit 2 : Enable interrupt on READY event. */
bogdanm	0:9b334a45a8ff	5916	#define SPI_INTENSET_READY_Pos (2UL) /!< Position of READY field. /
bogdanm	0:9b334a45a8ff	5917	#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /!< Bit mask of READY field. /
bogdanm	0:9b334a45a8ff	5918	#define SPI_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	5919	#define SPI_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	5920	#define SPI_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	5921
bogdanm	0:9b334a45a8ff	5922	/* Register: SPI_INTENCLR */
bogdanm	0:9b334a45a8ff	5923	/* Description: Interrupt enable clear register. */
bogdanm	0:9b334a45a8ff	5924
bogdanm	0:9b334a45a8ff	5925	/* Bit 2 : Disable interrupt on READY event. */
bogdanm	0:9b334a45a8ff	5926	#define SPI_INTENCLR_READY_Pos (2UL) /!< Position of READY field. /
bogdanm	0:9b334a45a8ff	5927	#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
bogdanm	0:9b334a45a8ff	5928	#define SPI_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	5929	#define SPI_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	5930	#define SPI_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	5931
bogdanm	0:9b334a45a8ff	5932	/* Register: SPI_ENABLE */
bogdanm	0:9b334a45a8ff	5933	/* Description: Enable SPI. */
bogdanm	0:9b334a45a8ff	5934
bogdanm	0:9b334a45a8ff	5935	/* Bits 2..0 : Enable or disable SPI. */
bogdanm	0:9b334a45a8ff	5936	#define SPI_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
bogdanm	0:9b334a45a8ff	5937	#define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
bogdanm	0:9b334a45a8ff	5938	#define SPI_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPI. /
bogdanm	0:9b334a45a8ff	5939	#define SPI_ENABLE_ENABLE_Enabled (0x01UL) /!< Enable SPI. /
bogdanm	0:9b334a45a8ff	5940
bogdanm	0:9b334a45a8ff	5941	/* Register: SPI_RXD */
bogdanm	0:9b334a45a8ff	5942	/* Description: RX data. */
bogdanm	0:9b334a45a8ff	5943
bogdanm	0:9b334a45a8ff	5944	/* Bits 7..0 : RX data from last transfer. */
bogdanm	0:9b334a45a8ff	5945	#define SPI_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
bogdanm	0:9b334a45a8ff	5946	#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /!< Bit mask of RXD field. /
bogdanm	0:9b334a45a8ff	5947
bogdanm	0:9b334a45a8ff	5948	/* Register: SPI_TXD */
bogdanm	0:9b334a45a8ff	5949	/* Description: TX data. */
bogdanm	0:9b334a45a8ff	5950
bogdanm	0:9b334a45a8ff	5951	/* Bits 7..0 : TX data for next transfer. */
bogdanm	0:9b334a45a8ff	5952	#define SPI_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
bogdanm	0:9b334a45a8ff	5953	#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /!< Bit mask of TXD field. /
bogdanm	0:9b334a45a8ff	5954
bogdanm	0:9b334a45a8ff	5955	/* Register: SPI_FREQUENCY */
bogdanm	0:9b334a45a8ff	5956	/* Description: SPI frequency */
bogdanm	0:9b334a45a8ff	5957
bogdanm	0:9b334a45a8ff	5958	/* Bits 31..0 : SPI data rate. */
bogdanm	0:9b334a45a8ff	5959	#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
bogdanm	0:9b334a45a8ff	5960	#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
bogdanm	0:9b334a45a8ff	5961	#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /!< 125kbps. /
bogdanm	0:9b334a45a8ff	5962	#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250kbps. /
bogdanm	0:9b334a45a8ff	5963	#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /!< 500kbps. /
bogdanm	0:9b334a45a8ff	5964	#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /!< 1Mbps. /
bogdanm	0:9b334a45a8ff	5965	#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /!< 2Mbps. /
bogdanm	0:9b334a45a8ff	5966	#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /!< 4Mbps. /
bogdanm	0:9b334a45a8ff	5967	#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /!< 8Mbps. /
bogdanm	0:9b334a45a8ff	5968
bogdanm	0:9b334a45a8ff	5969	/* Register: SPI_CONFIG */
bogdanm	0:9b334a45a8ff	5970	/* Description: Configuration register. */
bogdanm	0:9b334a45a8ff	5971
bogdanm	0:9b334a45a8ff	5972	/* Bit 2 : Serial clock (SCK) polarity. */
bogdanm	0:9b334a45a8ff	5973	#define SPI_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
bogdanm	0:9b334a45a8ff	5974	#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
bogdanm	0:9b334a45a8ff	5975	#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
bogdanm	0:9b334a45a8ff	5976	#define SPI_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
bogdanm	0:9b334a45a8ff	5977
bogdanm	0:9b334a45a8ff	5978	/* Bit 1 : Serial clock (SCK) phase. */
bogdanm	0:9b334a45a8ff	5979	#define SPI_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
bogdanm	0:9b334a45a8ff	5980	#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
bogdanm	0:9b334a45a8ff	5981	#define SPI_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
bogdanm	0:9b334a45a8ff	5982	#define SPI_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
bogdanm	0:9b334a45a8ff	5983
bogdanm	0:9b334a45a8ff	5984	/* Bit 0 : Bit order. */
bogdanm	0:9b334a45a8ff	5985	#define SPI_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
bogdanm	0:9b334a45a8ff	5986	#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
bogdanm	0:9b334a45a8ff	5987	#define SPI_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
bogdanm	0:9b334a45a8ff	5988	#define SPI_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
bogdanm	0:9b334a45a8ff	5989
bogdanm	0:9b334a45a8ff	5990	/* Register: SPI_POWER */
bogdanm	0:9b334a45a8ff	5991	/* Description: Peripheral power control. */
bogdanm	0:9b334a45a8ff	5992
bogdanm	0:9b334a45a8ff	5993	/* Bit 0 : Peripheral power control. */
bogdanm	0:9b334a45a8ff	5994	#define SPI_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	0:9b334a45a8ff	5995	#define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	0:9b334a45a8ff	5996	#define SPI_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	0:9b334a45a8ff	5997	#define SPI_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	0:9b334a45a8ff	5998
bogdanm	0:9b334a45a8ff	5999
bogdanm	0:9b334a45a8ff	6000	/* Peripheral: SPIM */
bogdanm	0:9b334a45a8ff	6001	/* Description: SPI master with easyDMA 1. */
bogdanm	0:9b334a45a8ff	6002
bogdanm	0:9b334a45a8ff	6003	/* Register: SPIM_SHORTS */
bogdanm	0:9b334a45a8ff	6004	/* Description: Shortcuts for SPIM. */
bogdanm	0:9b334a45a8ff	6005
bogdanm	0:9b334a45a8ff	6006	/* Bit 17 : Shortcut between END event and START task. */
bogdanm	0:9b334a45a8ff	6007	#define SPIM_SHORTS_END_START_Pos (17UL) /!< Position of END_START field. /
bogdanm	0:9b334a45a8ff	6008	#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /!< Bit mask of END_START field. /
bogdanm	0:9b334a45a8ff	6009	#define SPIM_SHORTS_END_START_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	0:9b334a45a8ff	6010	#define SPIM_SHORTS_END_START_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	0:9b334a45a8ff	6011
bogdanm	0:9b334a45a8ff	6012	/* Register: SPIM_INTENSET */
bogdanm	0:9b334a45a8ff	6013	/* Description: Interrupt enable set register. */
bogdanm	0:9b334a45a8ff	6014
bogdanm	0:9b334a45a8ff	6015	/* Bit 19 : Enable interrupt on STARTED event. */
bogdanm	0:9b334a45a8ff	6016	#define SPIM_INTENSET_STARTED_Pos (19UL) /!< Position of STARTED field. /
bogdanm	0:9b334a45a8ff	6017	#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /!< Bit mask of STARTED field. /
bogdanm	0:9b334a45a8ff	6018	#define SPIM_INTENSET_STARTED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6019	#define SPIM_INTENSET_STARTED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6020	#define SPIM_INTENSET_STARTED_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	6021
bogdanm	0:9b334a45a8ff	6022	/* Bit 8 : Enable interrupt on ENDTX event. */
bogdanm	0:9b334a45a8ff	6023	#define SPIM_INTENSET_ENDTX_Pos (8UL) /!< Position of ENDTX field. /
bogdanm	0:9b334a45a8ff	6024	#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /!< Bit mask of ENDTX field. /
bogdanm	0:9b334a45a8ff	6025	#define SPIM_INTENSET_ENDTX_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6026	#define SPIM_INTENSET_ENDTX_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6027	#define SPIM_INTENSET_ENDTX_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	6028
bogdanm	0:9b334a45a8ff	6029	/* Bit 6 : Enable interrupt on END event. */
bogdanm	0:9b334a45a8ff	6030	#define SPIM_INTENSET_END_Pos (6UL) /!< Position of END field. /
bogdanm	0:9b334a45a8ff	6031	#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /!< Bit mask of END field. /
bogdanm	0:9b334a45a8ff	6032	#define SPIM_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6033	#define SPIM_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6034	#define SPIM_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	6035
bogdanm	0:9b334a45a8ff	6036	/* Bit 4 : Enable interrupt on ENDRX event. */
bogdanm	0:9b334a45a8ff	6037	#define SPIM_INTENSET_ENDRX_Pos (4UL) /!< Position of ENDRX field. /
bogdanm	0:9b334a45a8ff	6038	#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /!< Bit mask of ENDRX field. /
bogdanm	0:9b334a45a8ff	6039	#define SPIM_INTENSET_ENDRX_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6040	#define SPIM_INTENSET_ENDRX_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6041	#define SPIM_INTENSET_ENDRX_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	6042
bogdanm	0:9b334a45a8ff	6043	/* Bit 1 : Enable interrupt on STOPPED event. */
bogdanm	0:9b334a45a8ff	6044	#define SPIM_INTENSET_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
bogdanm	0:9b334a45a8ff	6045	#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /!< Bit mask of STOPPED field. /
bogdanm	0:9b334a45a8ff	6046	#define SPIM_INTENSET_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6047	#define SPIM_INTENSET_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6048	#define SPIM_INTENSET_STOPPED_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	6049
bogdanm	0:9b334a45a8ff	6050	/* Register: SPIM_INTENCLR */
bogdanm	0:9b334a45a8ff	6051	/* Description: Interrupt enable clear register. */
bogdanm	0:9b334a45a8ff	6052
bogdanm	0:9b334a45a8ff	6053	/* Bit 19 : Disable interrupt on STARTED event. */
bogdanm	0:9b334a45a8ff	6054	#define SPIM_INTENCLR_STARTED_Pos (19UL) /!< Position of STARTED field. /
bogdanm	0:9b334a45a8ff	6055	#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /!< Bit mask of STARTED field. /
bogdanm	0:9b334a45a8ff	6056	#define SPIM_INTENCLR_STARTED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6057	#define SPIM_INTENCLR_STARTED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6058	#define SPIM_INTENCLR_STARTED_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	6059
bogdanm	0:9b334a45a8ff	6060	/* Bit 8 : Disable interrupt on ENDTX event. */
bogdanm	0:9b334a45a8ff	6061	#define SPIM_INTENCLR_ENDTX_Pos (8UL) /!< Position of ENDTX field. /
bogdanm	0:9b334a45a8ff	6062	#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /!< Bit mask of ENDTX field. /
bogdanm	0:9b334a45a8ff	6063	#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6064	#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6065	#define SPIM_INTENCLR_ENDTX_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	6066
bogdanm	0:9b334a45a8ff	6067	/* Bit 6 : Disable interrupt on END event. */
bogdanm	0:9b334a45a8ff	6068	#define SPIM_INTENCLR_END_Pos (6UL) /!< Position of END field. /
bogdanm	0:9b334a45a8ff	6069	#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /!< Bit mask of END field. /
bogdanm	0:9b334a45a8ff	6070	#define SPIM_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6071	#define SPIM_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6072	#define SPIM_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	6073
bogdanm	0:9b334a45a8ff	6074	/* Bit 4 : Disable interrupt on ENDRX event. */
bogdanm	0:9b334a45a8ff	6075	#define SPIM_INTENCLR_ENDRX_Pos (4UL) /!< Position of ENDRX field. /
bogdanm	0:9b334a45a8ff	6076	#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /!< Bit mask of ENDRX field. /
bogdanm	0:9b334a45a8ff	6077	#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6078	#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6079	#define SPIM_INTENCLR_ENDRX_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	6080
bogdanm	0:9b334a45a8ff	6081	/* Bit 1 : Disable interrupt on STOPPED event. */
bogdanm	0:9b334a45a8ff	6082	#define SPIM_INTENCLR_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
bogdanm	0:9b334a45a8ff	6083	#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /!< Bit mask of STOPPED field. /
bogdanm	0:9b334a45a8ff	6084	#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6085	#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6086	#define SPIM_INTENCLR_STOPPED_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	6087
bogdanm	0:9b334a45a8ff	6088	/* Register: SPIM_ENABLE */
bogdanm	0:9b334a45a8ff	6089	/* Description: Enable SPIM. */
bogdanm	0:9b334a45a8ff	6090
bogdanm	0:9b334a45a8ff	6091	/* Bits 3..0 : Enable or disable SPIM. */
bogdanm	0:9b334a45a8ff	6092	#define SPIM_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
bogdanm	0:9b334a45a8ff	6093	#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
bogdanm	0:9b334a45a8ff	6094	#define SPIM_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPIM. /
bogdanm	0:9b334a45a8ff	6095	#define SPIM_ENABLE_ENABLE_Enabled (0x07UL) /!< Enable SPIM. /
bogdanm	0:9b334a45a8ff	6096
bogdanm	0:9b334a45a8ff	6097	/* Register: SPIM_RXDDATA */
bogdanm	0:9b334a45a8ff	6098	/* Description: RXD register. */
bogdanm	0:9b334a45a8ff	6099
bogdanm	0:9b334a45a8ff	6100	/* Bits 7..0 : RX data received. Double buffered. */
bogdanm	0:9b334a45a8ff	6101	#define SPIM_RXDDATA_RXD_Pos (0UL) /!< Position of RXD field. /
bogdanm	0:9b334a45a8ff	6102	#define SPIM_RXDDATA_RXD_Msk (0xFFUL << SPIM_RXDDATA_RXD_Pos) /!< Bit mask of RXD field. /
bogdanm	0:9b334a45a8ff	6103
bogdanm	0:9b334a45a8ff	6104	/* Register: SPIM_TXDDATA */
bogdanm	0:9b334a45a8ff	6105	/* Description: TXD register. */
bogdanm	0:9b334a45a8ff	6106
bogdanm	0:9b334a45a8ff	6107	/* Bits 7..0 : TX data to send. Double buffered. */
bogdanm	0:9b334a45a8ff	6108	#define SPIM_TXDDATA_TXD_Pos (0UL) /!< Position of TXD field. /
bogdanm	0:9b334a45a8ff	6109	#define SPIM_TXDDATA_TXD_Msk (0xFFUL << SPIM_TXDDATA_TXD_Pos) /!< Bit mask of TXD field. /
bogdanm	0:9b334a45a8ff	6110
bogdanm	0:9b334a45a8ff	6111	/* Register: SPIM_FREQUENCY */
bogdanm	0:9b334a45a8ff	6112	/* Description: SPI frequency. */
bogdanm	0:9b334a45a8ff	6113
bogdanm	0:9b334a45a8ff	6114	/* Bits 31..0 : SPI master data rate. */
bogdanm	0:9b334a45a8ff	6115	#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
bogdanm	0:9b334a45a8ff	6116	#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
bogdanm	0:9b334a45a8ff	6117	#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /!< 125 kbps. /
bogdanm	0:9b334a45a8ff	6118	#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250 kbps. /
bogdanm	0:9b334a45a8ff	6119	#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /!< 500 kbps. /
bogdanm	0:9b334a45a8ff	6120	#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /!< 1 Mbps. /
bogdanm	0:9b334a45a8ff	6121	#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /!< 2 Mbps. /
bogdanm	0:9b334a45a8ff	6122	#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /!< 4 Mbps. /
bogdanm	0:9b334a45a8ff	6123	#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /!< 8 Mbps. /
bogdanm	0:9b334a45a8ff	6124
bogdanm	0:9b334a45a8ff	6125	/* Register: SPIM_CONFIG */
bogdanm	0:9b334a45a8ff	6126	/* Description: Configuration register. */
bogdanm	0:9b334a45a8ff	6127
bogdanm	0:9b334a45a8ff	6128	/* Bit 2 : Serial clock (SCK) polarity. */
bogdanm	0:9b334a45a8ff	6129	#define SPIM_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
bogdanm	0:9b334a45a8ff	6130	#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
bogdanm	0:9b334a45a8ff	6131	#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
bogdanm	0:9b334a45a8ff	6132	#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
bogdanm	0:9b334a45a8ff	6133
bogdanm	0:9b334a45a8ff	6134	/* Bit 1 : Serial clock (SCK) phase. */
bogdanm	0:9b334a45a8ff	6135	#define SPIM_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
bogdanm	0:9b334a45a8ff	6136	#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
bogdanm	0:9b334a45a8ff	6137	#define SPIM_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
bogdanm	0:9b334a45a8ff	6138	#define SPIM_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
bogdanm	0:9b334a45a8ff	6139
bogdanm	0:9b334a45a8ff	6140	/* Bit 0 : Bit order. */
bogdanm	0:9b334a45a8ff	6141	#define SPIM_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
bogdanm	0:9b334a45a8ff	6142	#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
bogdanm	0:9b334a45a8ff	6143	#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
bogdanm	0:9b334a45a8ff	6144	#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
bogdanm	0:9b334a45a8ff	6145
bogdanm	0:9b334a45a8ff	6146	/* Register: SPIM_ORC */
bogdanm	0:9b334a45a8ff	6147	/* Description: Over-read character. */
bogdanm	0:9b334a45a8ff	6148
bogdanm	0:9b334a45a8ff	6149	/* Bits 7..0 : Over-read character. */
bogdanm	0:9b334a45a8ff	6150	#define SPIM_ORC_ORC_Pos (0UL) /!< Position of ORC field. /
bogdanm	0:9b334a45a8ff	6151	#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /!< Bit mask of ORC field. /
bogdanm	0:9b334a45a8ff	6152
bogdanm	0:9b334a45a8ff	6153	/* Register: SPIM_POWER */
bogdanm	0:9b334a45a8ff	6154	/* Description: Peripheral power control. */
bogdanm	0:9b334a45a8ff	6155
bogdanm	0:9b334a45a8ff	6156	/* Bit 0 : Peripheral power control. */
bogdanm	0:9b334a45a8ff	6157	#define SPIM_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	0:9b334a45a8ff	6158	#define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	0:9b334a45a8ff	6159	#define SPIM_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	0:9b334a45a8ff	6160	#define SPIM_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	0:9b334a45a8ff	6161
bogdanm	0:9b334a45a8ff	6162	/* Register: SPIM_RXD_PTR */
bogdanm	0:9b334a45a8ff	6163	/* Description: Data pointer. */
bogdanm	0:9b334a45a8ff	6164
bogdanm	0:9b334a45a8ff	6165	/* Bits 31..0 : Data pointer. */
bogdanm	0:9b334a45a8ff	6166	#define SPIM_RXD_PTR_PTR_Pos (0UL) /!< Position of PTR field. /
bogdanm	0:9b334a45a8ff	6167	#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /!< Bit mask of PTR field. /
bogdanm	0:9b334a45a8ff	6168
bogdanm	0:9b334a45a8ff	6169	/* Register: SPIM_RXD_MAXCNT */
bogdanm	0:9b334a45a8ff	6170	/* Description: Maximum number of buffer bytes to receive. */
bogdanm	0:9b334a45a8ff	6171
bogdanm	0:9b334a45a8ff	6172	/* Bits 7..0 : Maximum number of buffer bytes to receive. */
bogdanm	0:9b334a45a8ff	6173	#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /!< Position of MAXCNT field. /
bogdanm	0:9b334a45a8ff	6174	#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /!< Bit mask of MAXCNT field. /
bogdanm	0:9b334a45a8ff	6175
bogdanm	0:9b334a45a8ff	6176	/* Register: SPIM_RXD_AMOUNT */
bogdanm	0:9b334a45a8ff	6177	/* Description: Number of bytes received in the last transaction. */
bogdanm	0:9b334a45a8ff	6178
bogdanm	0:9b334a45a8ff	6179	/* Bits 7..0 : Number of bytes received in the last transaction. */
bogdanm	0:9b334a45a8ff	6180	#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /!< Position of AMOUNT field. /
bogdanm	0:9b334a45a8ff	6181	#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /!< Bit mask of AMOUNT field. /
bogdanm	0:9b334a45a8ff	6182
bogdanm	0:9b334a45a8ff	6183	/* Register: SPIM_TXD_PTR */
bogdanm	0:9b334a45a8ff	6184	/* Description: Data pointer. */
bogdanm	0:9b334a45a8ff	6185
bogdanm	0:9b334a45a8ff	6186	/* Bits 31..0 : Data pointer. */
bogdanm	0:9b334a45a8ff	6187	#define SPIM_TXD_PTR_PTR_Pos (0UL) /!< Position of PTR field. /
bogdanm	0:9b334a45a8ff	6188	#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /!< Bit mask of PTR field. /
bogdanm	0:9b334a45a8ff	6189
bogdanm	0:9b334a45a8ff	6190	/* Register: SPIM_TXD_MAXCNT */
bogdanm	0:9b334a45a8ff	6191	/* Description: Maximum number of buffer bytes to send. */
bogdanm	0:9b334a45a8ff	6192
bogdanm	0:9b334a45a8ff	6193	/* Bits 7..0 : Maximum number of buffer bytes to send. */
bogdanm	0:9b334a45a8ff	6194	#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /!< Position of MAXCNT field. /
bogdanm	0:9b334a45a8ff	6195	#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /!< Bit mask of MAXCNT field. /
bogdanm	0:9b334a45a8ff	6196
bogdanm	0:9b334a45a8ff	6197	/* Register: SPIM_TXD_AMOUNT */
bogdanm	0:9b334a45a8ff	6198	/* Description: Number of bytes sent in the last transaction. */
bogdanm	0:9b334a45a8ff	6199
bogdanm	0:9b334a45a8ff	6200	/* Bits 7..0 : Number of bytes sent in the last transaction. */
bogdanm	0:9b334a45a8ff	6201	#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /!< Position of AMOUNT field. /
bogdanm	0:9b334a45a8ff	6202	#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /!< Bit mask of AMOUNT field. /
bogdanm	0:9b334a45a8ff	6203
bogdanm	0:9b334a45a8ff	6204
bogdanm	0:9b334a45a8ff	6205	/* Peripheral: SPIS */
bogdanm	0:9b334a45a8ff	6206	/* Description: SPI slave 1. */
bogdanm	0:9b334a45a8ff	6207
bogdanm	0:9b334a45a8ff	6208	/* Register: SPIS_SHORTS */
bogdanm	0:9b334a45a8ff	6209	/* Description: Shortcuts for SPIS. */
bogdanm	0:9b334a45a8ff	6210
bogdanm	0:9b334a45a8ff	6211	/* Bit 2 : Shortcut between END event and the ACQUIRE task. */
bogdanm	0:9b334a45a8ff	6212	#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /!< Position of END_ACQUIRE field. /
bogdanm	0:9b334a45a8ff	6213	#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /!< Bit mask of END_ACQUIRE field. /
bogdanm	0:9b334a45a8ff	6214	#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	0:9b334a45a8ff	6215	#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	0:9b334a45a8ff	6216
bogdanm	0:9b334a45a8ff	6217	/* Register: SPIS_INTENSET */
bogdanm	0:9b334a45a8ff	6218	/* Description: Interrupt enable set register. */
bogdanm	0:9b334a45a8ff	6219
bogdanm	0:9b334a45a8ff	6220	/* Bit 10 : Enable interrupt on ACQUIRED event. */
bogdanm	0:9b334a45a8ff	6221	#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /!< Position of ACQUIRED field. /
bogdanm	0:9b334a45a8ff	6222	#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /!< Bit mask of ACQUIRED field. /
bogdanm	0:9b334a45a8ff	6223	#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6224	#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6225	#define SPIS_INTENSET_ACQUIRED_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	6226
bogdanm	0:9b334a45a8ff	6227	/* Bit 1 : Enable interrupt on END event. */
bogdanm	0:9b334a45a8ff	6228	#define SPIS_INTENSET_END_Pos (1UL) /!< Position of END field. /
bogdanm	0:9b334a45a8ff	6229	#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /!< Bit mask of END field. /
bogdanm	0:9b334a45a8ff	6230	#define SPIS_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6231	#define SPIS_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6232	#define SPIS_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	6233
bogdanm	0:9b334a45a8ff	6234	/* Register: SPIS_INTENCLR */
bogdanm	0:9b334a45a8ff	6235	/* Description: Interrupt enable clear register. */
bogdanm	0:9b334a45a8ff	6236
bogdanm	0:9b334a45a8ff	6237	/* Bit 10 : Disable interrupt on ACQUIRED event. */
bogdanm	0:9b334a45a8ff	6238	#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /!< Position of ACQUIRED field. /
bogdanm	0:9b334a45a8ff	6239	#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /!< Bit mask of ACQUIRED field. /
bogdanm	0:9b334a45a8ff	6240	#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6241	#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6242	#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	6243
bogdanm	0:9b334a45a8ff	6244	/* Bit 1 : Disable interrupt on END event. */
bogdanm	0:9b334a45a8ff	6245	#define SPIS_INTENCLR_END_Pos (1UL) /!< Position of END field. /
bogdanm	0:9b334a45a8ff	6246	#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /!< Bit mask of END field. /
bogdanm	0:9b334a45a8ff	6247	#define SPIS_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6248	#define SPIS_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6249	#define SPIS_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	6250
bogdanm	0:9b334a45a8ff	6251	/* Register: SPIS_SEMSTAT */
bogdanm	0:9b334a45a8ff	6252	/* Description: Semaphore status. */
bogdanm	0:9b334a45a8ff	6253
bogdanm	0:9b334a45a8ff	6254	/* Bits 1..0 : Semaphore status. */
bogdanm	0:9b334a45a8ff	6255	#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /!< Position of SEMSTAT field. /
bogdanm	0:9b334a45a8ff	6256	#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /!< Bit mask of SEMSTAT field. /
bogdanm	0:9b334a45a8ff	6257	#define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /!< Semaphore is free. /
bogdanm	0:9b334a45a8ff	6258	#define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /!< Semaphore is assigned to the CPU. /
bogdanm	0:9b334a45a8ff	6259	#define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /!< Semaphore is assigned to the SPIS. /
bogdanm	0:9b334a45a8ff	6260	#define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. /
bogdanm	0:9b334a45a8ff	6261
bogdanm	0:9b334a45a8ff	6262	/* Register: SPIS_STATUS */
bogdanm	0:9b334a45a8ff	6263	/* Description: Status from last transaction. */
bogdanm	0:9b334a45a8ff	6264
bogdanm	0:9b334a45a8ff	6265	/* Bit 1 : RX buffer overflow detected, and prevented. */
bogdanm	0:9b334a45a8ff	6266	#define SPIS_STATUS_OVERFLOW_Pos (1UL) /!< Position of OVERFLOW field. /
bogdanm	0:9b334a45a8ff	6267	#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /!< Bit mask of OVERFLOW field. /
bogdanm	0:9b334a45a8ff	6268	#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /!< Error not present. /
bogdanm	0:9b334a45a8ff	6269	#define SPIS_STATUS_OVERFLOW_Present (1UL) /!< Error present. /
bogdanm	0:9b334a45a8ff	6270	#define SPIS_STATUS_OVERFLOW_Clear (1UL) /!< Clear on write. /
bogdanm	0:9b334a45a8ff	6271
bogdanm	0:9b334a45a8ff	6272	/* Bit 0 : TX buffer overread detected, and prevented. */
bogdanm	0:9b334a45a8ff	6273	#define SPIS_STATUS_OVERREAD_Pos (0UL) /!< Position of OVERREAD field. /
bogdanm	0:9b334a45a8ff	6274	#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /!< Bit mask of OVERREAD field. /
bogdanm	0:9b334a45a8ff	6275	#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /!< Error not present. /
bogdanm	0:9b334a45a8ff	6276	#define SPIS_STATUS_OVERREAD_Present (1UL) /!< Error present. /
bogdanm	0:9b334a45a8ff	6277	#define SPIS_STATUS_OVERREAD_Clear (1UL) /!< Clear on write. /
bogdanm	0:9b334a45a8ff	6278
bogdanm	0:9b334a45a8ff	6279	/* Register: SPIS_ENABLE */
bogdanm	0:9b334a45a8ff	6280	/* Description: Enable SPIS. */
bogdanm	0:9b334a45a8ff	6281
bogdanm	0:9b334a45a8ff	6282	/* Bits 2..0 : Enable or disable SPIS. */
bogdanm	0:9b334a45a8ff	6283	#define SPIS_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
bogdanm	0:9b334a45a8ff	6284	#define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
bogdanm	0:9b334a45a8ff	6285	#define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPIS. /
bogdanm	0:9b334a45a8ff	6286	#define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /!< Enable SPIS. /
bogdanm	0:9b334a45a8ff	6287
bogdanm	0:9b334a45a8ff	6288	/* Register: SPIS_MAXRX */
bogdanm	0:9b334a45a8ff	6289	/* Description: Maximum number of bytes in the receive buffer. */
bogdanm	0:9b334a45a8ff	6290
bogdanm	0:9b334a45a8ff	6291	/* Bits 7..0 : Maximum number of bytes in the receive buffer. */
bogdanm	0:9b334a45a8ff	6292	#define SPIS_MAXRX_MAXRX_Pos (0UL) /!< Position of MAXRX field. /
bogdanm	0:9b334a45a8ff	6293	#define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /!< Bit mask of MAXRX field. /
bogdanm	0:9b334a45a8ff	6294
bogdanm	0:9b334a45a8ff	6295	/* Register: SPIS_AMOUNTRX */
bogdanm	0:9b334a45a8ff	6296	/* Description: Number of bytes received in last granted transaction. */
bogdanm	0:9b334a45a8ff	6297
bogdanm	0:9b334a45a8ff	6298	/* Bits 7..0 : Number of bytes received in last granted transaction. */
bogdanm	0:9b334a45a8ff	6299	#define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /!< Position of AMOUNTRX field. /
bogdanm	0:9b334a45a8ff	6300	#define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /!< Bit mask of AMOUNTRX field. /
bogdanm	0:9b334a45a8ff	6301
bogdanm	0:9b334a45a8ff	6302	/* Register: SPIS_MAXTX */
bogdanm	0:9b334a45a8ff	6303	/* Description: Maximum number of bytes in the transmit buffer. */
bogdanm	0:9b334a45a8ff	6304
bogdanm	0:9b334a45a8ff	6305	/* Bits 7..0 : Maximum number of bytes in the transmit buffer. */
bogdanm	0:9b334a45a8ff	6306	#define SPIS_MAXTX_MAXTX_Pos (0UL) /!< Position of MAXTX field. /
bogdanm	0:9b334a45a8ff	6307	#define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /!< Bit mask of MAXTX field. /
bogdanm	0:9b334a45a8ff	6308
bogdanm	0:9b334a45a8ff	6309	/* Register: SPIS_AMOUNTTX */
bogdanm	0:9b334a45a8ff	6310	/* Description: Number of bytes transmitted in last granted transaction. */
bogdanm	0:9b334a45a8ff	6311
bogdanm	0:9b334a45a8ff	6312	/* Bits 7..0 : Number of bytes transmitted in last granted transaction. */
bogdanm	0:9b334a45a8ff	6313	#define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /!< Position of AMOUNTTX field. /
bogdanm	0:9b334a45a8ff	6314	#define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /!< Bit mask of AMOUNTTX field. /
bogdanm	0:9b334a45a8ff	6315
bogdanm	0:9b334a45a8ff	6316	/* Register: SPIS_CONFIG */
bogdanm	0:9b334a45a8ff	6317	/* Description: Configuration register. */
bogdanm	0:9b334a45a8ff	6318
bogdanm	0:9b334a45a8ff	6319	/* Bit 2 : Serial clock (SCK) polarity. */
bogdanm	0:9b334a45a8ff	6320	#define SPIS_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
bogdanm	0:9b334a45a8ff	6321	#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
bogdanm	0:9b334a45a8ff	6322	#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
bogdanm	0:9b334a45a8ff	6323	#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
bogdanm	0:9b334a45a8ff	6324
bogdanm	0:9b334a45a8ff	6325	/* Bit 1 : Serial clock (SCK) phase. */
bogdanm	0:9b334a45a8ff	6326	#define SPIS_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
bogdanm	0:9b334a45a8ff	6327	#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
bogdanm	0:9b334a45a8ff	6328	#define SPIS_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
bogdanm	0:9b334a45a8ff	6329	#define SPIS_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
bogdanm	0:9b334a45a8ff	6330
bogdanm	0:9b334a45a8ff	6331	/* Bit 0 : Bit order. */
bogdanm	0:9b334a45a8ff	6332	#define SPIS_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
bogdanm	0:9b334a45a8ff	6333	#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
bogdanm	0:9b334a45a8ff	6334	#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
bogdanm	0:9b334a45a8ff	6335	#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
bogdanm	0:9b334a45a8ff	6336
bogdanm	0:9b334a45a8ff	6337	/* Register: SPIS_DEF */
bogdanm	0:9b334a45a8ff	6338	/* Description: Default character. */
bogdanm	0:9b334a45a8ff	6339
bogdanm	0:9b334a45a8ff	6340	/* Bits 7..0 : Default character. */
bogdanm	0:9b334a45a8ff	6341	#define SPIS_DEF_DEF_Pos (0UL) /!< Position of DEF field. /
bogdanm	0:9b334a45a8ff	6342	#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /!< Bit mask of DEF field. /
bogdanm	0:9b334a45a8ff	6343
bogdanm	0:9b334a45a8ff	6344	/* Register: SPIS_ORC */
bogdanm	0:9b334a45a8ff	6345	/* Description: Over-read character. */
bogdanm	0:9b334a45a8ff	6346
bogdanm	0:9b334a45a8ff	6347	/* Bits 7..0 : Over-read character. */
bogdanm	0:9b334a45a8ff	6348	#define SPIS_ORC_ORC_Pos (0UL) /!< Position of ORC field. /
bogdanm	0:9b334a45a8ff	6349	#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /!< Bit mask of ORC field. /
bogdanm	0:9b334a45a8ff	6350
bogdanm	0:9b334a45a8ff	6351	/* Register: SPIS_POWER */
bogdanm	0:9b334a45a8ff	6352	/* Description: Peripheral power control. */
bogdanm	0:9b334a45a8ff	6353
bogdanm	0:9b334a45a8ff	6354	/* Bit 0 : Peripheral power control. */
bogdanm	0:9b334a45a8ff	6355	#define SPIS_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	0:9b334a45a8ff	6356	#define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	0:9b334a45a8ff	6357	#define SPIS_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	0:9b334a45a8ff	6358	#define SPIS_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	0:9b334a45a8ff	6359
bogdanm	0:9b334a45a8ff	6360
bogdanm	0:9b334a45a8ff	6361	/* Peripheral: TEMP */
bogdanm	0:9b334a45a8ff	6362	/* Description: Temperature Sensor. */
bogdanm	0:9b334a45a8ff	6363
bogdanm	0:9b334a45a8ff	6364	/* Register: TEMP_INTENSET */
bogdanm	0:9b334a45a8ff	6365	/* Description: Interrupt enable set register. */
bogdanm	0:9b334a45a8ff	6366
bogdanm	0:9b334a45a8ff	6367	/* Bit 0 : Enable interrupt on DATARDY event. */
bogdanm	0:9b334a45a8ff	6368	#define TEMP_INTENSET_DATARDY_Pos (0UL) /!< Position of DATARDY field. /
bogdanm	0:9b334a45a8ff	6369	#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /!< Bit mask of DATARDY field. /
bogdanm	0:9b334a45a8ff	6370	#define TEMP_INTENSET_DATARDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6371	#define TEMP_INTENSET_DATARDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6372	#define TEMP_INTENSET_DATARDY_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	6373
bogdanm	0:9b334a45a8ff	6374	/* Register: TEMP_INTENCLR */
bogdanm	0:9b334a45a8ff	6375	/* Description: Interrupt enable clear register. */
bogdanm	0:9b334a45a8ff	6376
bogdanm	0:9b334a45a8ff	6377	/* Bit 0 : Disable interrupt on DATARDY event. */
bogdanm	0:9b334a45a8ff	6378	#define TEMP_INTENCLR_DATARDY_Pos (0UL) /!< Position of DATARDY field. /
bogdanm	0:9b334a45a8ff	6379	#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /!< Bit mask of DATARDY field. /
bogdanm	0:9b334a45a8ff	6380	#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6381	#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6382	#define TEMP_INTENCLR_DATARDY_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	6383
bogdanm	0:9b334a45a8ff	6384	/* Register: TEMP_POWER */
bogdanm	0:9b334a45a8ff	6385	/* Description: Peripheral power control. */
bogdanm	0:9b334a45a8ff	6386
bogdanm	0:9b334a45a8ff	6387	/* Bit 0 : Peripheral power control. */
bogdanm	0:9b334a45a8ff	6388	#define TEMP_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	0:9b334a45a8ff	6389	#define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	0:9b334a45a8ff	6390	#define TEMP_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	0:9b334a45a8ff	6391	#define TEMP_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	0:9b334a45a8ff	6392
bogdanm	0:9b334a45a8ff	6393
bogdanm	0:9b334a45a8ff	6394	/* Peripheral: TIMER */
bogdanm	0:9b334a45a8ff	6395	/* Description: Timer 0. */
bogdanm	0:9b334a45a8ff	6396
bogdanm	0:9b334a45a8ff	6397	/* Register: TIMER_SHORTS */
bogdanm	0:9b334a45a8ff	6398	/* Description: Shortcuts for Timer. */
bogdanm	0:9b334a45a8ff	6399
bogdanm	0:9b334a45a8ff	6400	/* Bit 11 : Shortcut between CC[3] event and the STOP task. */
bogdanm	0:9b334a45a8ff	6401	#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /!< Position of COMPARE3_STOP field. /
bogdanm	0:9b334a45a8ff	6402	#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /!< Bit mask of COMPARE3_STOP field. /
bogdanm	0:9b334a45a8ff	6403	#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	0:9b334a45a8ff	6404	#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	0:9b334a45a8ff	6405
bogdanm	0:9b334a45a8ff	6406	/* Bit 10 : Shortcut between CC[2] event and the STOP task. */
bogdanm	0:9b334a45a8ff	6407	#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /!< Position of COMPARE2_STOP field. /
bogdanm	0:9b334a45a8ff	6408	#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /!< Bit mask of COMPARE2_STOP field. /
bogdanm	0:9b334a45a8ff	6409	#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	0:9b334a45a8ff	6410	#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	0:9b334a45a8ff	6411
bogdanm	0:9b334a45a8ff	6412	/* Bit 9 : Shortcut between CC[1] event and the STOP task. */
bogdanm	0:9b334a45a8ff	6413	#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /!< Position of COMPARE1_STOP field. /
bogdanm	0:9b334a45a8ff	6414	#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /!< Bit mask of COMPARE1_STOP field. /
bogdanm	0:9b334a45a8ff	6415	#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	0:9b334a45a8ff	6416	#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	0:9b334a45a8ff	6417
bogdanm	0:9b334a45a8ff	6418	/* Bit 8 : Shortcut between CC[0] event and the STOP task. */
bogdanm	0:9b334a45a8ff	6419	#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /!< Position of COMPARE0_STOP field. /
bogdanm	0:9b334a45a8ff	6420	#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /!< Bit mask of COMPARE0_STOP field. /
bogdanm	0:9b334a45a8ff	6421	#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	0:9b334a45a8ff	6422	#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	0:9b334a45a8ff	6423
bogdanm	0:9b334a45a8ff	6424	/* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */
bogdanm	0:9b334a45a8ff	6425	#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /!< Position of COMPARE3_CLEAR field. /
bogdanm	0:9b334a45a8ff	6426	#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /!< Bit mask of COMPARE3_CLEAR field. /
bogdanm	0:9b334a45a8ff	6427	#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	0:9b334a45a8ff	6428	#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	0:9b334a45a8ff	6429
bogdanm	0:9b334a45a8ff	6430	/* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */
bogdanm	0:9b334a45a8ff	6431	#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /!< Position of COMPARE2_CLEAR field. /
bogdanm	0:9b334a45a8ff	6432	#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /!< Bit mask of COMPARE2_CLEAR field. /
bogdanm	0:9b334a45a8ff	6433	#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	0:9b334a45a8ff	6434	#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	0:9b334a45a8ff	6435
bogdanm	0:9b334a45a8ff	6436	/* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */
bogdanm	0:9b334a45a8ff	6437	#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /!< Position of COMPARE1_CLEAR field. /
bogdanm	0:9b334a45a8ff	6438	#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /!< Bit mask of COMPARE1_CLEAR field. /
bogdanm	0:9b334a45a8ff	6439	#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	0:9b334a45a8ff	6440	#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	0:9b334a45a8ff	6441
bogdanm	0:9b334a45a8ff	6442	/* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */
bogdanm	0:9b334a45a8ff	6443	#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /!< Position of COMPARE0_CLEAR field. /
bogdanm	0:9b334a45a8ff	6444	#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /!< Bit mask of COMPARE0_CLEAR field. /
bogdanm	0:9b334a45a8ff	6445	#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	0:9b334a45a8ff	6446	#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	0:9b334a45a8ff	6447
bogdanm	0:9b334a45a8ff	6448	/* Register: TIMER_INTENSET */
bogdanm	0:9b334a45a8ff	6449	/* Description: Interrupt enable set register. */
bogdanm	0:9b334a45a8ff	6450
bogdanm	0:9b334a45a8ff	6451	/* Bit 19 : Enable interrupt on COMPARE[3] */
bogdanm	0:9b334a45a8ff	6452	#define TIMER_INTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
bogdanm	0:9b334a45a8ff	6453	#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
bogdanm	0:9b334a45a8ff	6454	#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6455	#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6456	#define TIMER_INTENSET_COMPARE3_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	6457
bogdanm	0:9b334a45a8ff	6458	/* Bit 18 : Enable interrupt on COMPARE[2] */
bogdanm	0:9b334a45a8ff	6459	#define TIMER_INTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
bogdanm	0:9b334a45a8ff	6460	#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
bogdanm	0:9b334a45a8ff	6461	#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6462	#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6463	#define TIMER_INTENSET_COMPARE2_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	6464
bogdanm	0:9b334a45a8ff	6465	/* Bit 17 : Enable interrupt on COMPARE[1] */
bogdanm	0:9b334a45a8ff	6466	#define TIMER_INTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
bogdanm	0:9b334a45a8ff	6467	#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
bogdanm	0:9b334a45a8ff	6468	#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6469	#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6470	#define TIMER_INTENSET_COMPARE1_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	6471
bogdanm	0:9b334a45a8ff	6472	/* Bit 16 : Enable interrupt on COMPARE[0] */
bogdanm	0:9b334a45a8ff	6473	#define TIMER_INTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
bogdanm	0:9b334a45a8ff	6474	#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
bogdanm	0:9b334a45a8ff	6475	#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6476	#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6477	#define TIMER_INTENSET_COMPARE0_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	6478
bogdanm	0:9b334a45a8ff	6479	/* Register: TIMER_INTENCLR */
bogdanm	0:9b334a45a8ff	6480	/* Description: Interrupt enable clear register. */
bogdanm	0:9b334a45a8ff	6481
bogdanm	0:9b334a45a8ff	6482	/* Bit 19 : Disable interrupt on COMPARE[3] */
bogdanm	0:9b334a45a8ff	6483	#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
bogdanm	0:9b334a45a8ff	6484	#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
bogdanm	0:9b334a45a8ff	6485	#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6486	#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6487	#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	6488
bogdanm	0:9b334a45a8ff	6489	/* Bit 18 : Disable interrupt on COMPARE[2] */
bogdanm	0:9b334a45a8ff	6490	#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
bogdanm	0:9b334a45a8ff	6491	#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
bogdanm	0:9b334a45a8ff	6492	#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6493	#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6494	#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	6495
bogdanm	0:9b334a45a8ff	6496	/* Bit 17 : Disable interrupt on COMPARE[1] */
bogdanm	0:9b334a45a8ff	6497	#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
bogdanm	0:9b334a45a8ff	6498	#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
bogdanm	0:9b334a45a8ff	6499	#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6500	#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6501	#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	6502
bogdanm	0:9b334a45a8ff	6503	/* Bit 16 : Disable interrupt on COMPARE[0] */
bogdanm	0:9b334a45a8ff	6504	#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
bogdanm	0:9b334a45a8ff	6505	#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
bogdanm	0:9b334a45a8ff	6506	#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6507	#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6508	#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	6509
bogdanm	0:9b334a45a8ff	6510	/* Register: TIMER_MODE */
bogdanm	0:9b334a45a8ff	6511	/* Description: Timer Mode selection. */
bogdanm	0:9b334a45a8ff	6512
bogdanm	0:9b334a45a8ff	6513	/* Bit 0 : Select Normal or Counter mode. */
bogdanm	0:9b334a45a8ff	6514	#define TIMER_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
bogdanm	0:9b334a45a8ff	6515	#define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /!< Bit mask of MODE field. /
bogdanm	0:9b334a45a8ff	6516	#define TIMER_MODE_MODE_Timer (0UL) /!< Timer in Normal mode. /
bogdanm	0:9b334a45a8ff	6517	#define TIMER_MODE_MODE_Counter (1UL) /!< Timer in Counter mode. /
bogdanm	0:9b334a45a8ff	6518
bogdanm	0:9b334a45a8ff	6519	/* Register: TIMER_BITMODE */
bogdanm	0:9b334a45a8ff	6520	/* Description: Sets timer behaviour. */
bogdanm	0:9b334a45a8ff	6521
bogdanm	0:9b334a45a8ff	6522	/* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */
bogdanm	0:9b334a45a8ff	6523	#define TIMER_BITMODE_BITMODE_Pos (0UL) /!< Position of BITMODE field. /
bogdanm	0:9b334a45a8ff	6524	#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /!< Bit mask of BITMODE field. /
bogdanm	0:9b334a45a8ff	6525	#define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /!< 16-bit timer behaviour. /
bogdanm	0:9b334a45a8ff	6526	#define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /!< 8-bit timer behaviour. /
bogdanm	0:9b334a45a8ff	6527	#define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /!< 24-bit timer behaviour. /
bogdanm	0:9b334a45a8ff	6528	#define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /!< 32-bit timer behaviour. /
bogdanm	0:9b334a45a8ff	6529
bogdanm	0:9b334a45a8ff	6530	/* Register: TIMER_PRESCALER */
bogdanm	0:9b334a45a8ff	6531	/* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */
bogdanm	0:9b334a45a8ff	6532
bogdanm	0:9b334a45a8ff	6533	/* Bits 3..0 : Timer PRESCALER value. Max value is 9. */
bogdanm	0:9b334a45a8ff	6534	#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /!< Position of PRESCALER field. /
bogdanm	0:9b334a45a8ff	6535	#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /!< Bit mask of PRESCALER field. /
bogdanm	0:9b334a45a8ff	6536
bogdanm	0:9b334a45a8ff	6537	/* Register: TIMER_POWER */
bogdanm	0:9b334a45a8ff	6538	/* Description: Peripheral power control. */
bogdanm	0:9b334a45a8ff	6539
bogdanm	0:9b334a45a8ff	6540	/* Bit 0 : Peripheral power control. */
bogdanm	0:9b334a45a8ff	6541	#define TIMER_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	0:9b334a45a8ff	6542	#define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	0:9b334a45a8ff	6543	#define TIMER_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	0:9b334a45a8ff	6544	#define TIMER_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	0:9b334a45a8ff	6545
bogdanm	0:9b334a45a8ff	6546
bogdanm	0:9b334a45a8ff	6547	/* Peripheral: TWI */
bogdanm	0:9b334a45a8ff	6548	/* Description: Two-wire interface master 0. */
bogdanm	0:9b334a45a8ff	6549
bogdanm	0:9b334a45a8ff	6550	/* Register: TWI_SHORTS */
bogdanm	0:9b334a45a8ff	6551	/* Description: Shortcuts for TWI. */
bogdanm	0:9b334a45a8ff	6552
bogdanm	0:9b334a45a8ff	6553	/* Bit 1 : Shortcut between BB event and the STOP task. */
bogdanm	0:9b334a45a8ff	6554	#define TWI_SHORTS_BB_STOP_Pos (1UL) /!< Position of BB_STOP field. /
bogdanm	0:9b334a45a8ff	6555	#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /!< Bit mask of BB_STOP field. /
bogdanm	0:9b334a45a8ff	6556	#define TWI_SHORTS_BB_STOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	0:9b334a45a8ff	6557	#define TWI_SHORTS_BB_STOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	0:9b334a45a8ff	6558
bogdanm	0:9b334a45a8ff	6559	/* Bit 0 : Shortcut between BB event and the SUSPEND task. */
bogdanm	0:9b334a45a8ff	6560	#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /!< Position of BB_SUSPEND field. /
bogdanm	0:9b334a45a8ff	6561	#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /!< Bit mask of BB_SUSPEND field. /
bogdanm	0:9b334a45a8ff	6562	#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	0:9b334a45a8ff	6563	#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	0:9b334a45a8ff	6564
bogdanm	0:9b334a45a8ff	6565	/* Register: TWI_INTENSET */
bogdanm	0:9b334a45a8ff	6566	/* Description: Interrupt enable set register. */
bogdanm	0:9b334a45a8ff	6567
bogdanm	0:9b334a45a8ff	6568	/* Bit 18 : Enable interrupt on SUSPENDED event. */
bogdanm	0:9b334a45a8ff	6569	#define TWI_INTENSET_SUSPENDED_Pos (18UL) /!< Position of SUSPENDED field. /
bogdanm	0:9b334a45a8ff	6570	#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /!< Bit mask of SUSPENDED field. /
bogdanm	0:9b334a45a8ff	6571	#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6572	#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6573	#define TWI_INTENSET_SUSPENDED_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	6574
bogdanm	0:9b334a45a8ff	6575	/* Bit 14 : Enable interrupt on BB event. */
bogdanm	0:9b334a45a8ff	6576	#define TWI_INTENSET_BB_Pos (14UL) /!< Position of BB field. /
bogdanm	0:9b334a45a8ff	6577	#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /!< Bit mask of BB field. /
bogdanm	0:9b334a45a8ff	6578	#define TWI_INTENSET_BB_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6579	#define TWI_INTENSET_BB_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6580	#define TWI_INTENSET_BB_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	6581
bogdanm	0:9b334a45a8ff	6582	/* Bit 9 : Enable interrupt on ERROR event. */
bogdanm	0:9b334a45a8ff	6583	#define TWI_INTENSET_ERROR_Pos (9UL) /!< Position of ERROR field. /
bogdanm	0:9b334a45a8ff	6584	#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
bogdanm	0:9b334a45a8ff	6585	#define TWI_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6586	#define TWI_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6587	#define TWI_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	6588
bogdanm	0:9b334a45a8ff	6589	/* Bit 7 : Enable interrupt on TXDSENT event. */
bogdanm	0:9b334a45a8ff	6590	#define TWI_INTENSET_TXDSENT_Pos (7UL) /!< Position of TXDSENT field. /
bogdanm	0:9b334a45a8ff	6591	#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /!< Bit mask of TXDSENT field. /
bogdanm	0:9b334a45a8ff	6592	#define TWI_INTENSET_TXDSENT_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6593	#define TWI_INTENSET_TXDSENT_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6594	#define TWI_INTENSET_TXDSENT_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	6595
bogdanm	0:9b334a45a8ff	6596	/* Bit 2 : Enable interrupt on READY event. */
bogdanm	0:9b334a45a8ff	6597	#define TWI_INTENSET_RXDREADY_Pos (2UL) /!< Position of RXDREADY field. /
bogdanm	0:9b334a45a8ff	6598	#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /!< Bit mask of RXDREADY field. /
bogdanm	0:9b334a45a8ff	6599	#define TWI_INTENSET_RXDREADY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6600	#define TWI_INTENSET_RXDREADY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6601	#define TWI_INTENSET_RXDREADY_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	6602
bogdanm	0:9b334a45a8ff	6603	/* Bit 1 : Enable interrupt on STOPPED event. */
bogdanm	0:9b334a45a8ff	6604	#define TWI_INTENSET_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
bogdanm	0:9b334a45a8ff	6605	#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /!< Bit mask of STOPPED field. /
bogdanm	0:9b334a45a8ff	6606	#define TWI_INTENSET_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6607	#define TWI_INTENSET_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6608	#define TWI_INTENSET_STOPPED_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	6609
bogdanm	0:9b334a45a8ff	6610	/* Register: TWI_INTENCLR */
bogdanm	0:9b334a45a8ff	6611	/* Description: Interrupt enable clear register. */
bogdanm	0:9b334a45a8ff	6612
bogdanm	0:9b334a45a8ff	6613	/* Bit 18 : Disable interrupt on SUSPENDED event. */
bogdanm	0:9b334a45a8ff	6614	#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /!< Position of SUSPENDED field. /
bogdanm	0:9b334a45a8ff	6615	#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /!< Bit mask of SUSPENDED field. /
bogdanm	0:9b334a45a8ff	6616	#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6617	#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6618	#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	6619
bogdanm	0:9b334a45a8ff	6620	/* Bit 14 : Disable interrupt on BB event. */
bogdanm	0:9b334a45a8ff	6621	#define TWI_INTENCLR_BB_Pos (14UL) /!< Position of BB field. /
bogdanm	0:9b334a45a8ff	6622	#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /!< Bit mask of BB field. /
bogdanm	0:9b334a45a8ff	6623	#define TWI_INTENCLR_BB_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6624	#define TWI_INTENCLR_BB_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6625	#define TWI_INTENCLR_BB_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	6626
bogdanm	0:9b334a45a8ff	6627	/* Bit 9 : Disable interrupt on ERROR event. */
bogdanm	0:9b334a45a8ff	6628	#define TWI_INTENCLR_ERROR_Pos (9UL) /!< Position of ERROR field. /
bogdanm	0:9b334a45a8ff	6629	#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
bogdanm	0:9b334a45a8ff	6630	#define TWI_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6631	#define TWI_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6632	#define TWI_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	6633
bogdanm	0:9b334a45a8ff	6634	/* Bit 7 : Disable interrupt on TXDSENT event. */
bogdanm	0:9b334a45a8ff	6635	#define TWI_INTENCLR_TXDSENT_Pos (7UL) /!< Position of TXDSENT field. /
bogdanm	0:9b334a45a8ff	6636	#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /!< Bit mask of TXDSENT field. /
bogdanm	0:9b334a45a8ff	6637	#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6638	#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6639	#define TWI_INTENCLR_TXDSENT_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	6640
bogdanm	0:9b334a45a8ff	6641	/* Bit 2 : Disable interrupt on RXDREADY event. */
bogdanm	0:9b334a45a8ff	6642	#define TWI_INTENCLR_RXDREADY_Pos (2UL) /!< Position of RXDREADY field. /
bogdanm	0:9b334a45a8ff	6643	#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /!< Bit mask of RXDREADY field. /
bogdanm	0:9b334a45a8ff	6644	#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6645	#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6646	#define TWI_INTENCLR_RXDREADY_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	6647
bogdanm	0:9b334a45a8ff	6648	/* Bit 1 : Disable interrupt on STOPPED event. */
bogdanm	0:9b334a45a8ff	6649	#define TWI_INTENCLR_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
bogdanm	0:9b334a45a8ff	6650	#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /!< Bit mask of STOPPED field. /
bogdanm	0:9b334a45a8ff	6651	#define TWI_INTENCLR_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6652	#define TWI_INTENCLR_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6653	#define TWI_INTENCLR_STOPPED_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	6654
bogdanm	0:9b334a45a8ff	6655	/* Register: TWI_ERRORSRC */
bogdanm	0:9b334a45a8ff	6656	/* Description: Two-wire error source. Write error field to 1 to clear error. */
bogdanm	0:9b334a45a8ff	6657
bogdanm	0:9b334a45a8ff	6658	/* Bit 2 : NACK received after sending a data byte. */
bogdanm	0:9b334a45a8ff	6659	#define TWI_ERRORSRC_DNACK_Pos (2UL) /!< Position of DNACK field. /
bogdanm	0:9b334a45a8ff	6660	#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /!< Bit mask of DNACK field. /
bogdanm	0:9b334a45a8ff	6661	#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /!< Error not present. /
bogdanm	0:9b334a45a8ff	6662	#define TWI_ERRORSRC_DNACK_Present (1UL) /!< Error present. /
bogdanm	0:9b334a45a8ff	6663	#define TWI_ERRORSRC_DNACK_Clear (1UL) /!< Clear error on write. /
bogdanm	0:9b334a45a8ff	6664
bogdanm	0:9b334a45a8ff	6665	/* Bit 1 : NACK received after sending the address. */
bogdanm	0:9b334a45a8ff	6666	#define TWI_ERRORSRC_ANACK_Pos (1UL) /!< Position of ANACK field. /
bogdanm	0:9b334a45a8ff	6667	#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /!< Bit mask of ANACK field. /
bogdanm	0:9b334a45a8ff	6668	#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /!< Error not present. /
bogdanm	0:9b334a45a8ff	6669	#define TWI_ERRORSRC_ANACK_Present (1UL) /!< Error present. /
bogdanm	0:9b334a45a8ff	6670	#define TWI_ERRORSRC_ANACK_Clear (1UL) /!< Clear error on write. /
bogdanm	0:9b334a45a8ff	6671
bogdanm	0:9b334a45a8ff	6672	/* Register: TWI_ENABLE */
bogdanm	0:9b334a45a8ff	6673	/* Description: Enable two-wire master. */
bogdanm	0:9b334a45a8ff	6674
bogdanm	0:9b334a45a8ff	6675	/* Bits 2..0 : Enable or disable W2M */
bogdanm	0:9b334a45a8ff	6676	#define TWI_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
bogdanm	0:9b334a45a8ff	6677	#define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
bogdanm	0:9b334a45a8ff	6678	#define TWI_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled. /
bogdanm	0:9b334a45a8ff	6679	#define TWI_ENABLE_ENABLE_Enabled (0x05UL) /!< Enabled. /
bogdanm	0:9b334a45a8ff	6680
bogdanm	0:9b334a45a8ff	6681	/* Register: TWI_RXD */
bogdanm	0:9b334a45a8ff	6682	/* Description: RX data register. */
bogdanm	0:9b334a45a8ff	6683
bogdanm	0:9b334a45a8ff	6684	/* Bits 7..0 : RX data from last transfer. */
bogdanm	0:9b334a45a8ff	6685	#define TWI_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
bogdanm	0:9b334a45a8ff	6686	#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /!< Bit mask of RXD field. /
bogdanm	0:9b334a45a8ff	6687
bogdanm	0:9b334a45a8ff	6688	/* Register: TWI_TXD */
bogdanm	0:9b334a45a8ff	6689	/* Description: TX data register. */
bogdanm	0:9b334a45a8ff	6690
bogdanm	0:9b334a45a8ff	6691	/* Bits 7..0 : TX data for next transfer. */
bogdanm	0:9b334a45a8ff	6692	#define TWI_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
bogdanm	0:9b334a45a8ff	6693	#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /!< Bit mask of TXD field. /
bogdanm	0:9b334a45a8ff	6694
bogdanm	0:9b334a45a8ff	6695	/* Register: TWI_FREQUENCY */
bogdanm	0:9b334a45a8ff	6696	/* Description: Two-wire frequency. */
bogdanm	0:9b334a45a8ff	6697
bogdanm	0:9b334a45a8ff	6698	/* Bits 31..0 : Two-wire master clock frequency. */
bogdanm	0:9b334a45a8ff	6699	#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
bogdanm	0:9b334a45a8ff	6700	#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
bogdanm	0:9b334a45a8ff	6701	#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /!< 100 kbps. /
bogdanm	0:9b334a45a8ff	6702	#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250 kbps. /
bogdanm	0:9b334a45a8ff	6703	#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /!< 400 kbps. /
bogdanm	0:9b334a45a8ff	6704
bogdanm	0:9b334a45a8ff	6705	/* Register: TWI_ADDRESS */
bogdanm	0:9b334a45a8ff	6706	/* Description: Address used in the two-wire transfer. */
bogdanm	0:9b334a45a8ff	6707
bogdanm	0:9b334a45a8ff	6708	/* Bits 6..0 : Two-wire address. */
bogdanm	0:9b334a45a8ff	6709	#define TWI_ADDRESS_ADDRESS_Pos (0UL) /!< Position of ADDRESS field. /
bogdanm	0:9b334a45a8ff	6710	#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
bogdanm	0:9b334a45a8ff	6711
bogdanm	0:9b334a45a8ff	6712	/* Register: TWI_POWER */
bogdanm	0:9b334a45a8ff	6713	/* Description: Peripheral power control. */
bogdanm	0:9b334a45a8ff	6714
bogdanm	0:9b334a45a8ff	6715	/* Bit 0 : Peripheral power control. */
bogdanm	0:9b334a45a8ff	6716	#define TWI_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	0:9b334a45a8ff	6717	#define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	0:9b334a45a8ff	6718	#define TWI_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	0:9b334a45a8ff	6719	#define TWI_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	0:9b334a45a8ff	6720
bogdanm	0:9b334a45a8ff	6721
bogdanm	0:9b334a45a8ff	6722	/* Peripheral: UART */
bogdanm	0:9b334a45a8ff	6723	/* Description: Universal Asynchronous Receiver/Transmitter. */
bogdanm	0:9b334a45a8ff	6724
bogdanm	0:9b334a45a8ff	6725	/* Register: UART_SHORTS */
bogdanm	0:9b334a45a8ff	6726	/* Description: Shortcuts for UART. */
bogdanm	0:9b334a45a8ff	6727
bogdanm	0:9b334a45a8ff	6728	/* Bit 4 : Shortcut between NCTS event and the STOPRX task. */
bogdanm	0:9b334a45a8ff	6729	#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /!< Position of NCTS_STOPRX field. /
bogdanm	0:9b334a45a8ff	6730	#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /!< Bit mask of NCTS_STOPRX field. /
bogdanm	0:9b334a45a8ff	6731	#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	0:9b334a45a8ff	6732	#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	0:9b334a45a8ff	6733
bogdanm	0:9b334a45a8ff	6734	/* Bit 3 : Shortcut between CTS event and the STARTRX task. */
bogdanm	0:9b334a45a8ff	6735	#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /!< Position of CTS_STARTRX field. /
bogdanm	0:9b334a45a8ff	6736	#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /!< Bit mask of CTS_STARTRX field. /
bogdanm	0:9b334a45a8ff	6737	#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	0:9b334a45a8ff	6738	#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	0:9b334a45a8ff	6739
bogdanm	0:9b334a45a8ff	6740	/* Register: UART_INTENSET */
bogdanm	0:9b334a45a8ff	6741	/* Description: Interrupt enable set register. */
bogdanm	0:9b334a45a8ff	6742
bogdanm	0:9b334a45a8ff	6743	/* Bit 17 : Enable interrupt on RXTO event. */
bogdanm	0:9b334a45a8ff	6744	#define UART_INTENSET_RXTO_Pos (17UL) /!< Position of RXTO field. /
bogdanm	0:9b334a45a8ff	6745	#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /!< Bit mask of RXTO field. /
bogdanm	0:9b334a45a8ff	6746	#define UART_INTENSET_RXTO_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6747	#define UART_INTENSET_RXTO_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6748	#define UART_INTENSET_RXTO_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	6749
bogdanm	0:9b334a45a8ff	6750	/* Bit 9 : Enable interrupt on ERROR event. */
bogdanm	0:9b334a45a8ff	6751	#define UART_INTENSET_ERROR_Pos (9UL) /!< Position of ERROR field. /
bogdanm	0:9b334a45a8ff	6752	#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
bogdanm	0:9b334a45a8ff	6753	#define UART_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6754	#define UART_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6755	#define UART_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	6756
bogdanm	0:9b334a45a8ff	6757	/* Bit 7 : Enable interrupt on TXRDY event. */
bogdanm	0:9b334a45a8ff	6758	#define UART_INTENSET_TXDRDY_Pos (7UL) /!< Position of TXDRDY field. /
bogdanm	0:9b334a45a8ff	6759	#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /!< Bit mask of TXDRDY field. /
bogdanm	0:9b334a45a8ff	6760	#define UART_INTENSET_TXDRDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6761	#define UART_INTENSET_TXDRDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6762	#define UART_INTENSET_TXDRDY_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	6763
bogdanm	0:9b334a45a8ff	6764	/* Bit 2 : Enable interrupt on RXRDY event. */
bogdanm	0:9b334a45a8ff	6765	#define UART_INTENSET_RXDRDY_Pos (2UL) /!< Position of RXDRDY field. /
bogdanm	0:9b334a45a8ff	6766	#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /!< Bit mask of RXDRDY field. /
bogdanm	0:9b334a45a8ff	6767	#define UART_INTENSET_RXDRDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6768	#define UART_INTENSET_RXDRDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6769	#define UART_INTENSET_RXDRDY_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	6770
bogdanm	0:9b334a45a8ff	6771	/* Bit 1 : Enable interrupt on NCTS event. */
bogdanm	0:9b334a45a8ff	6772	#define UART_INTENSET_NCTS_Pos (1UL) /!< Position of NCTS field. /
bogdanm	0:9b334a45a8ff	6773	#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /!< Bit mask of NCTS field. /
bogdanm	0:9b334a45a8ff	6774	#define UART_INTENSET_NCTS_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6775	#define UART_INTENSET_NCTS_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6776	#define UART_INTENSET_NCTS_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	6777
bogdanm	0:9b334a45a8ff	6778	/* Bit 0 : Enable interrupt on CTS event. */
bogdanm	0:9b334a45a8ff	6779	#define UART_INTENSET_CTS_Pos (0UL) /!< Position of CTS field. /
bogdanm	0:9b334a45a8ff	6780	#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /!< Bit mask of CTS field. /
bogdanm	0:9b334a45a8ff	6781	#define UART_INTENSET_CTS_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6782	#define UART_INTENSET_CTS_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6783	#define UART_INTENSET_CTS_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	6784
bogdanm	0:9b334a45a8ff	6785	/* Register: UART_INTENCLR */
bogdanm	0:9b334a45a8ff	6786	/* Description: Interrupt enable clear register. */
bogdanm	0:9b334a45a8ff	6787
bogdanm	0:9b334a45a8ff	6788	/* Bit 17 : Disable interrupt on RXTO event. */
bogdanm	0:9b334a45a8ff	6789	#define UART_INTENCLR_RXTO_Pos (17UL) /!< Position of RXTO field. /
bogdanm	0:9b334a45a8ff	6790	#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /!< Bit mask of RXTO field. /
bogdanm	0:9b334a45a8ff	6791	#define UART_INTENCLR_RXTO_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6792	#define UART_INTENCLR_RXTO_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6793	#define UART_INTENCLR_RXTO_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	6794
bogdanm	0:9b334a45a8ff	6795	/* Bit 9 : Disable interrupt on ERROR event. */
bogdanm	0:9b334a45a8ff	6796	#define UART_INTENCLR_ERROR_Pos (9UL) /!< Position of ERROR field. /
bogdanm	0:9b334a45a8ff	6797	#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
bogdanm	0:9b334a45a8ff	6798	#define UART_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6799	#define UART_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6800	#define UART_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	6801
bogdanm	0:9b334a45a8ff	6802	/* Bit 7 : Disable interrupt on TXRDY event. */
bogdanm	0:9b334a45a8ff	6803	#define UART_INTENCLR_TXDRDY_Pos (7UL) /!< Position of TXDRDY field. /
bogdanm	0:9b334a45a8ff	6804	#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /!< Bit mask of TXDRDY field. /
bogdanm	0:9b334a45a8ff	6805	#define UART_INTENCLR_TXDRDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6806	#define UART_INTENCLR_TXDRDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6807	#define UART_INTENCLR_TXDRDY_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	6808
bogdanm	0:9b334a45a8ff	6809	/* Bit 2 : Disable interrupt on RXRDY event. */
bogdanm	0:9b334a45a8ff	6810	#define UART_INTENCLR_RXDRDY_Pos (2UL) /!< Position of RXDRDY field. /
bogdanm	0:9b334a45a8ff	6811	#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /!< Bit mask of RXDRDY field. /
bogdanm	0:9b334a45a8ff	6812	#define UART_INTENCLR_RXDRDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6813	#define UART_INTENCLR_RXDRDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6814	#define UART_INTENCLR_RXDRDY_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	6815
bogdanm	0:9b334a45a8ff	6816	/* Bit 1 : Disable interrupt on NCTS event. */
bogdanm	0:9b334a45a8ff	6817	#define UART_INTENCLR_NCTS_Pos (1UL) /!< Position of NCTS field. /
bogdanm	0:9b334a45a8ff	6818	#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /!< Bit mask of NCTS field. /
bogdanm	0:9b334a45a8ff	6819	#define UART_INTENCLR_NCTS_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6820	#define UART_INTENCLR_NCTS_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6821	#define UART_INTENCLR_NCTS_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	6822
bogdanm	0:9b334a45a8ff	6823	/* Bit 0 : Disable interrupt on CTS event. */
bogdanm	0:9b334a45a8ff	6824	#define UART_INTENCLR_CTS_Pos (0UL) /!< Position of CTS field. /
bogdanm	0:9b334a45a8ff	6825	#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /!< Bit mask of CTS field. /
bogdanm	0:9b334a45a8ff	6826	#define UART_INTENCLR_CTS_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6827	#define UART_INTENCLR_CTS_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6828	#define UART_INTENCLR_CTS_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	6829
bogdanm	0:9b334a45a8ff	6830	/* Register: UART_ERRORSRC */
bogdanm	0:9b334a45a8ff	6831	/* Description: Error source. Write error field to 1 to clear error. */
bogdanm	0:9b334a45a8ff	6832
bogdanm	0:9b334a45a8ff	6833	/* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */
bogdanm	0:9b334a45a8ff	6834	#define UART_ERRORSRC_BREAK_Pos (3UL) /!< Position of BREAK field. /
bogdanm	0:9b334a45a8ff	6835	#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /!< Bit mask of BREAK field. /
bogdanm	0:9b334a45a8ff	6836	#define UART_ERRORSRC_BREAK_NotPresent (0UL) /!< Error not present. /
bogdanm	0:9b334a45a8ff	6837	#define UART_ERRORSRC_BREAK_Present (1UL) /!< Error present. /
bogdanm	0:9b334a45a8ff	6838	#define UART_ERRORSRC_BREAK_Clear (1UL) /!< Clear error on write. /
bogdanm	0:9b334a45a8ff	6839
bogdanm	0:9b334a45a8ff	6840	/* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */
bogdanm	0:9b334a45a8ff	6841	#define UART_ERRORSRC_FRAMING_Pos (2UL) /!< Position of FRAMING field. /
bogdanm	0:9b334a45a8ff	6842	#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /!< Bit mask of FRAMING field. /
bogdanm	0:9b334a45a8ff	6843	#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /!< Error not present. /
bogdanm	0:9b334a45a8ff	6844	#define UART_ERRORSRC_FRAMING_Present (1UL) /!< Error present. /
bogdanm	0:9b334a45a8ff	6845	#define UART_ERRORSRC_FRAMING_Clear (1UL) /!< Clear error on write. /
bogdanm	0:9b334a45a8ff	6846
bogdanm	0:9b334a45a8ff	6847	/* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */
bogdanm	0:9b334a45a8ff	6848	#define UART_ERRORSRC_PARITY_Pos (1UL) /!< Position of PARITY field. /
bogdanm	0:9b334a45a8ff	6849	#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /!< Bit mask of PARITY field. /
bogdanm	0:9b334a45a8ff	6850	#define UART_ERRORSRC_PARITY_NotPresent (0UL) /!< Error not present. /
bogdanm	0:9b334a45a8ff	6851	#define UART_ERRORSRC_PARITY_Present (1UL) /!< Error present. /
bogdanm	0:9b334a45a8ff	6852	#define UART_ERRORSRC_PARITY_Clear (1UL) /!< Clear error on write. /
bogdanm	0:9b334a45a8ff	6853
bogdanm	0:9b334a45a8ff	6854	/* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */
bogdanm	0:9b334a45a8ff	6855	#define UART_ERRORSRC_OVERRUN_Pos (0UL) /!< Position of OVERRUN field. /
bogdanm	0:9b334a45a8ff	6856	#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /!< Bit mask of OVERRUN field. /
bogdanm	0:9b334a45a8ff	6857	#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /!< Error not present. /
bogdanm	0:9b334a45a8ff	6858	#define UART_ERRORSRC_OVERRUN_Present (1UL) /!< Error present. /
bogdanm	0:9b334a45a8ff	6859	#define UART_ERRORSRC_OVERRUN_Clear (1UL) /!< Clear error on write. /
bogdanm	0:9b334a45a8ff	6860
bogdanm	0:9b334a45a8ff	6861	/* Register: UART_ENABLE */
bogdanm	0:9b334a45a8ff	6862	/* Description: Enable UART and acquire IOs. */
bogdanm	0:9b334a45a8ff	6863
bogdanm	0:9b334a45a8ff	6864	/* Bits 2..0 : Enable or disable UART and acquire IOs. */
bogdanm	0:9b334a45a8ff	6865	#define UART_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
bogdanm	0:9b334a45a8ff	6866	#define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
bogdanm	0:9b334a45a8ff	6867	#define UART_ENABLE_ENABLE_Disabled (0x00UL) /!< UART disabled. /
bogdanm	0:9b334a45a8ff	6868	#define UART_ENABLE_ENABLE_Enabled (0x04UL) /!< UART enabled. /
bogdanm	0:9b334a45a8ff	6869
bogdanm	0:9b334a45a8ff	6870	/* Register: UART_RXD */
bogdanm	0:9b334a45a8ff	6871	/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */
bogdanm	0:9b334a45a8ff	6872
bogdanm	0:9b334a45a8ff	6873	/* Bits 7..0 : RX data from previous transfer. Double buffered. */
bogdanm	0:9b334a45a8ff	6874	#define UART_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
bogdanm	0:9b334a45a8ff	6875	#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /!< Bit mask of RXD field. /
bogdanm	0:9b334a45a8ff	6876
bogdanm	0:9b334a45a8ff	6877	/* Register: UART_TXD */
bogdanm	0:9b334a45a8ff	6878	/* Description: TXD register. */
bogdanm	0:9b334a45a8ff	6879
bogdanm	0:9b334a45a8ff	6880	/* Bits 7..0 : TX data for transfer. */
bogdanm	0:9b334a45a8ff	6881	#define UART_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
bogdanm	0:9b334a45a8ff	6882	#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /!< Bit mask of TXD field. /
bogdanm	0:9b334a45a8ff	6883
bogdanm	0:9b334a45a8ff	6884	/* Register: UART_BAUDRATE */
bogdanm	0:9b334a45a8ff	6885	/* Description: UART Baudrate. */
bogdanm	0:9b334a45a8ff	6886
bogdanm	0:9b334a45a8ff	6887	/* Bits 31..0 : UART baudrate. */
bogdanm	0:9b334a45a8ff	6888	#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /!< Position of BAUDRATE field. /
bogdanm	0:9b334a45a8ff	6889	#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /!< Bit mask of BAUDRATE field. /
bogdanm	0:9b334a45a8ff	6890	#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /!< 1200 baud. /
bogdanm	0:9b334a45a8ff	6891	#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /!< 2400 baud. /
bogdanm	0:9b334a45a8ff	6892	#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /!< 4800 baud. /
bogdanm	0:9b334a45a8ff	6893	#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /!< 9600 baud. /
bogdanm	0:9b334a45a8ff	6894	#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /!< 14400 baud. /
bogdanm	0:9b334a45a8ff	6895	#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /!< 19200 baud. /
bogdanm	0:9b334a45a8ff	6896	#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /!< 28800 baud. /
bogdanm	0:9b334a45a8ff	6897	#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /!< 38400 baud. /
bogdanm	0:9b334a45a8ff	6898	#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /!< 57600 baud. /
bogdanm	0:9b334a45a8ff	6899	#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /!< 76800 baud. /
bogdanm	0:9b334a45a8ff	6900	#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /!< 115200 baud. /
bogdanm	0:9b334a45a8ff	6901	#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /!< 230400 baud. /
bogdanm	0:9b334a45a8ff	6902	#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /!< 250000 baud. /
bogdanm	0:9b334a45a8ff	6903	#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /!< 460800 baud. /
bogdanm	0:9b334a45a8ff	6904	#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBEDFA4UL) /!< 921600 baud. /
bogdanm	0:9b334a45a8ff	6905	#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /!< 1M baud. /
bogdanm	0:9b334a45a8ff	6906
bogdanm	0:9b334a45a8ff	6907	/* Register: UART_CONFIG */
bogdanm	0:9b334a45a8ff	6908	/* Description: Configuration of parity and hardware flow control register. */
bogdanm	0:9b334a45a8ff	6909
bogdanm	0:9b334a45a8ff	6910	/* Bits 3..1 : Include parity bit. */
bogdanm	0:9b334a45a8ff	6911	#define UART_CONFIG_PARITY_Pos (1UL) /!< Position of PARITY field. /
bogdanm	0:9b334a45a8ff	6912	#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /!< Bit mask of PARITY field. /
bogdanm	0:9b334a45a8ff	6913	#define UART_CONFIG_PARITY_Excluded (0UL) /!< Parity bit excluded. /
bogdanm	0:9b334a45a8ff	6914	#define UART_CONFIG_PARITY_Included (7UL) /!< Parity bit included. /
bogdanm	0:9b334a45a8ff	6915
bogdanm	0:9b334a45a8ff	6916	/* Bit 0 : Hardware flow control. */
bogdanm	0:9b334a45a8ff	6917	#define UART_CONFIG_HWFC_Pos (0UL) /!< Position of HWFC field. /
bogdanm	0:9b334a45a8ff	6918	#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /!< Bit mask of HWFC field. /
bogdanm	0:9b334a45a8ff	6919	#define UART_CONFIG_HWFC_Disabled (0UL) /!< Hardware flow control disabled. /
bogdanm	0:9b334a45a8ff	6920	#define UART_CONFIG_HWFC_Enabled (1UL) /!< Hardware flow control enabled. /
bogdanm	0:9b334a45a8ff	6921
bogdanm	0:9b334a45a8ff	6922	/* Register: UART_POWER */
bogdanm	0:9b334a45a8ff	6923	/* Description: Peripheral power control. */
bogdanm	0:9b334a45a8ff	6924
bogdanm	0:9b334a45a8ff	6925	/* Bit 0 : Peripheral power control. */
bogdanm	0:9b334a45a8ff	6926	#define UART_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	0:9b334a45a8ff	6927	#define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	0:9b334a45a8ff	6928	#define UART_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	0:9b334a45a8ff	6929	#define UART_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	0:9b334a45a8ff	6930
bogdanm	0:9b334a45a8ff	6931
bogdanm	0:9b334a45a8ff	6932	/* Peripheral: UICR */
bogdanm	0:9b334a45a8ff	6933	/* Description: User Information Configuration. */
bogdanm	0:9b334a45a8ff	6934
bogdanm	0:9b334a45a8ff	6935	/* Register: UICR_RBPCONF */
bogdanm	0:9b334a45a8ff	6936	/* Description: Readback protection configuration. */
bogdanm	0:9b334a45a8ff	6937
bogdanm	0:9b334a45a8ff	6938	/* Bits 15..8 : Readback protect all code in the device. */
bogdanm	0:9b334a45a8ff	6939	#define UICR_RBPCONF_PALL_Pos (8UL) /!< Position of PALL field. /
bogdanm	0:9b334a45a8ff	6940	#define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /!< Bit mask of PALL field. /
bogdanm	0:9b334a45a8ff	6941	#define UICR_RBPCONF_PALL_Disabled (0xFFUL) /!< Disabled. /
bogdanm	0:9b334a45a8ff	6942	#define UICR_RBPCONF_PALL_Enabled (0x00UL) /!< Enabled. /
bogdanm	0:9b334a45a8ff	6943
bogdanm	0:9b334a45a8ff	6944	/* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */
bogdanm	0:9b334a45a8ff	6945	#define UICR_RBPCONF_PR0_Pos (0UL) /!< Position of PR0 field. /
bogdanm	0:9b334a45a8ff	6946	#define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /!< Bit mask of PR0 field. /
bogdanm	0:9b334a45a8ff	6947	#define UICR_RBPCONF_PR0_Disabled (0xFFUL) /!< Disabled. /
bogdanm	0:9b334a45a8ff	6948	#define UICR_RBPCONF_PR0_Enabled (0x00UL) /!< Enabled. /
bogdanm	0:9b334a45a8ff	6949
bogdanm	0:9b334a45a8ff	6950	/* Register: UICR_XTALFREQ */
bogdanm	0:9b334a45a8ff	6951	/* Description: Reset value for CLOCK XTALFREQ register. */
bogdanm	0:9b334a45a8ff	6952
bogdanm	0:9b334a45a8ff	6953	/* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */
bogdanm	0:9b334a45a8ff	6954	#define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /!< Position of XTALFREQ field. /
bogdanm	0:9b334a45a8ff	6955	#define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /!< Bit mask of XTALFREQ field. /
bogdanm	0:9b334a45a8ff	6956	#define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /!< 16MHz Xtal is used. /
bogdanm	0:9b334a45a8ff	6957	#define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /!< 32MHz Xtal is used. /
bogdanm	0:9b334a45a8ff	6958
bogdanm	0:9b334a45a8ff	6959	/* Register: UICR_FWID */
bogdanm	0:9b334a45a8ff	6960	/* Description: Firmware ID. */
bogdanm	0:9b334a45a8ff	6961
bogdanm	0:9b334a45a8ff	6962	/* Bits 15..0 : Identification number for the firmware loaded into the chip. */
bogdanm	0:9b334a45a8ff	6963	#define UICR_FWID_FWID_Pos (0UL) /!< Position of FWID field. /
bogdanm	0:9b334a45a8ff	6964	#define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /!< Bit mask of FWID field. /
bogdanm	0:9b334a45a8ff	6965
bogdanm	0:9b334a45a8ff	6966
bogdanm	0:9b334a45a8ff	6967	/* Peripheral: WDT */
bogdanm	0:9b334a45a8ff	6968	/* Description: Watchdog Timer. */
bogdanm	0:9b334a45a8ff	6969
bogdanm	0:9b334a45a8ff	6970	/* Register: WDT_INTENSET */
bogdanm	0:9b334a45a8ff	6971	/* Description: Interrupt enable set register. */
bogdanm	0:9b334a45a8ff	6972
bogdanm	0:9b334a45a8ff	6973	/* Bit 0 : Enable interrupt on TIMEOUT event. */
bogdanm	0:9b334a45a8ff	6974	#define WDT_INTENSET_TIMEOUT_Pos (0UL) /!< Position of TIMEOUT field. /
bogdanm	0:9b334a45a8ff	6975	#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /!< Bit mask of TIMEOUT field. /
bogdanm	0:9b334a45a8ff	6976	#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6977	#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6978	#define WDT_INTENSET_TIMEOUT_Set (1UL) /!< Enable interrupt on write. /
bogdanm	0:9b334a45a8ff	6979
bogdanm	0:9b334a45a8ff	6980	/* Register: WDT_INTENCLR */
bogdanm	0:9b334a45a8ff	6981	/* Description: Interrupt enable clear register. */
bogdanm	0:9b334a45a8ff	6982
bogdanm	0:9b334a45a8ff	6983	/* Bit 0 : Disable interrupt on TIMEOUT event. */
bogdanm	0:9b334a45a8ff	6984	#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /!< Position of TIMEOUT field. /
bogdanm	0:9b334a45a8ff	6985	#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /!< Bit mask of TIMEOUT field. /
bogdanm	0:9b334a45a8ff	6986	#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	0:9b334a45a8ff	6987	#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	0:9b334a45a8ff	6988	#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	0:9b334a45a8ff	6989
bogdanm	0:9b334a45a8ff	6990	/* Register: WDT_RUNSTATUS */
bogdanm	0:9b334a45a8ff	6991	/* Description: Watchdog running status. */
bogdanm	0:9b334a45a8ff	6992
bogdanm	0:9b334a45a8ff	6993	/* Bit 0 : Watchdog running status. */
bogdanm	0:9b334a45a8ff	6994	#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /!< Position of RUNSTATUS field. /
bogdanm	0:9b334a45a8ff	6995	#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /!< Bit mask of RUNSTATUS field. /
bogdanm	0:9b334a45a8ff	6996	#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /!< Watchdog timer is not running. /
bogdanm	0:9b334a45a8ff	6997	#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /!< Watchdog timer is running. /
bogdanm	0:9b334a45a8ff	6998
bogdanm	0:9b334a45a8ff	6999	/* Register: WDT_REQSTATUS */
bogdanm	0:9b334a45a8ff	7000	/* Description: Request status. */
bogdanm	0:9b334a45a8ff	7001
bogdanm	0:9b334a45a8ff	7002	/* Bit 7 : Request status for RR[7]. */
bogdanm	0:9b334a45a8ff	7003	#define WDT_REQSTATUS_RR7_Pos (7UL) /!< Position of RR7 field. /
bogdanm	0:9b334a45a8ff	7004	#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /!< Bit mask of RR7 field. /
bogdanm	0:9b334a45a8ff	7005	#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /!< RR[7] register is not enabled or has already requested reload. /
bogdanm	0:9b334a45a8ff	7006	#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /!< RR[7] register is enabled and has not jet requested. /
bogdanm	0:9b334a45a8ff	7007
bogdanm	0:9b334a45a8ff	7008	/* Bit 6 : Request status for RR[6]. */
bogdanm	0:9b334a45a8ff	7009	#define WDT_REQSTATUS_RR6_Pos (6UL) /!< Position of RR6 field. /
bogdanm	0:9b334a45a8ff	7010	#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /!< Bit mask of RR6 field. /
bogdanm	0:9b334a45a8ff	7011	#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /!< RR[6] register is not enabled or has already requested reload. /
bogdanm	0:9b334a45a8ff	7012	#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /!< RR[6] register is enabled and has not jet requested. /
bogdanm	0:9b334a45a8ff	7013
bogdanm	0:9b334a45a8ff	7014	/* Bit 5 : Request status for RR[5]. */
bogdanm	0:9b334a45a8ff	7015	#define WDT_REQSTATUS_RR5_Pos (5UL) /!< Position of RR5 field. /
bogdanm	0:9b334a45a8ff	7016	#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /!< Bit mask of RR5 field. /
bogdanm	0:9b334a45a8ff	7017	#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /!< RR[5] register is not enabled or has already requested reload. /
bogdanm	0:9b334a45a8ff	7018	#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /!< RR[5] register is enabled and has not jet requested. /
bogdanm	0:9b334a45a8ff	7019
bogdanm	0:9b334a45a8ff	7020	/* Bit 4 : Request status for RR[4]. */
bogdanm	0:9b334a45a8ff	7021	#define WDT_REQSTATUS_RR4_Pos (4UL) /!< Position of RR4 field. /
bogdanm	0:9b334a45a8ff	7022	#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /!< Bit mask of RR4 field. /
bogdanm	0:9b334a45a8ff	7023	#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /!< RR[4] register is not enabled or has already requested reload. /
bogdanm	0:9b334a45a8ff	7024	#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /!< RR[4] register is enabled and has not jet requested. /
bogdanm	0:9b334a45a8ff	7025
bogdanm	0:9b334a45a8ff	7026	/* Bit 3 : Request status for RR[3]. */
bogdanm	0:9b334a45a8ff	7027	#define WDT_REQSTATUS_RR3_Pos (3UL) /!< Position of RR3 field. /
bogdanm	0:9b334a45a8ff	7028	#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /!< Bit mask of RR3 field. /
bogdanm	0:9b334a45a8ff	7029	#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /!< RR[3] register is not enabled or has already requested reload. /
bogdanm	0:9b334a45a8ff	7030	#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /!< RR[3] register is enabled and has not jet requested. /
bogdanm	0:9b334a45a8ff	7031
bogdanm	0:9b334a45a8ff	7032	/* Bit 2 : Request status for RR[2]. */
bogdanm	0:9b334a45a8ff	7033	#define WDT_REQSTATUS_RR2_Pos (2UL) /!< Position of RR2 field. /
bogdanm	0:9b334a45a8ff	7034	#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /!< Bit mask of RR2 field. /
bogdanm	0:9b334a45a8ff	7035	#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /!< RR[2] register is not enabled or has already requested reload. /
bogdanm	0:9b334a45a8ff	7036	#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /!< RR[2] register is enabled and has not jet requested. /
bogdanm	0:9b334a45a8ff	7037
bogdanm	0:9b334a45a8ff	7038	/* Bit 1 : Request status for RR[1]. */
bogdanm	0:9b334a45a8ff	7039	#define WDT_REQSTATUS_RR1_Pos (1UL) /!< Position of RR1 field. /
bogdanm	0:9b334a45a8ff	7040	#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /!< Bit mask of RR1 field. /
bogdanm	0:9b334a45a8ff	7041	#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /!< RR[1] register is not enabled or has already requested reload. /
bogdanm	0:9b334a45a8ff	7042	#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /!< RR[1] register is enabled and has not jet requested. /
bogdanm	0:9b334a45a8ff	7043
bogdanm	0:9b334a45a8ff	7044	/* Bit 0 : Request status for RR[0]. */
bogdanm	0:9b334a45a8ff	7045	#define WDT_REQSTATUS_RR0_Pos (0UL) /!< Position of RR0 field. /
bogdanm	0:9b334a45a8ff	7046	#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /!< Bit mask of RR0 field. /
bogdanm	0:9b334a45a8ff	7047	#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /!< RR[0] register is not enabled or has already requested reload. /
bogdanm	0:9b334a45a8ff	7048	#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /!< RR[0] register is enabled and has not jet requested. /
bogdanm	0:9b334a45a8ff	7049
bogdanm	0:9b334a45a8ff	7050	/* Register: WDT_RREN */
bogdanm	0:9b334a45a8ff	7051	/* Description: Reload request enable. */
bogdanm	0:9b334a45a8ff	7052
bogdanm	0:9b334a45a8ff	7053	/* Bit 7 : Enable or disable RR[7] register. */
bogdanm	0:9b334a45a8ff	7054	#define WDT_RREN_RR7_Pos (7UL) /!< Position of RR7 field. /
bogdanm	0:9b334a45a8ff	7055	#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /!< Bit mask of RR7 field. /
bogdanm	0:9b334a45a8ff	7056	#define WDT_RREN_RR7_Disabled (0UL) /!< RR[7] register is disabled. /
bogdanm	0:9b334a45a8ff	7057	#define WDT_RREN_RR7_Enabled (1UL) /!< RR[7] register is enabled. /
bogdanm	0:9b334a45a8ff	7058
bogdanm	0:9b334a45a8ff	7059	/* Bit 6 : Enable or disable RR[6] register. */
bogdanm	0:9b334a45a8ff	7060	#define WDT_RREN_RR6_Pos (6UL) /!< Position of RR6 field. /
bogdanm	0:9b334a45a8ff	7061	#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /!< Bit mask of RR6 field. /
bogdanm	0:9b334a45a8ff	7062	#define WDT_RREN_RR6_Disabled (0UL) /!< RR[6] register is disabled. /
bogdanm	0:9b334a45a8ff	7063	#define WDT_RREN_RR6_Enabled (1UL) /!< RR[6] register is enabled. /
bogdanm	0:9b334a45a8ff	7064
bogdanm	0:9b334a45a8ff	7065	/* Bit 5 : Enable or disable RR[5] register. */
bogdanm	0:9b334a45a8ff	7066	#define WDT_RREN_RR5_Pos (5UL) /!< Position of RR5 field. /
bogdanm	0:9b334a45a8ff	7067	#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /!< Bit mask of RR5 field. /
bogdanm	0:9b334a45a8ff	7068	#define WDT_RREN_RR5_Disabled (0UL) /!< RR[5] register is disabled. /
bogdanm	0:9b334a45a8ff	7069	#define WDT_RREN_RR5_Enabled (1UL) /!< RR[5] register is enabled. /
bogdanm	0:9b334a45a8ff	7070
bogdanm	0:9b334a45a8ff	7071	/* Bit 4 : Enable or disable RR[4] register. */
bogdanm	0:9b334a45a8ff	7072	#define WDT_RREN_RR4_Pos (4UL) /!< Position of RR4 field. /
bogdanm	0:9b334a45a8ff	7073	#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /!< Bit mask of RR4 field. /
bogdanm	0:9b334a45a8ff	7074	#define WDT_RREN_RR4_Disabled (0UL) /!< RR[4] register is disabled. /
bogdanm	0:9b334a45a8ff	7075	#define WDT_RREN_RR4_Enabled (1UL) /!< RR[4] register is enabled. /
bogdanm	0:9b334a45a8ff	7076
bogdanm	0:9b334a45a8ff	7077	/* Bit 3 : Enable or disable RR[3] register. */
bogdanm	0:9b334a45a8ff	7078	#define WDT_RREN_RR3_Pos (3UL) /!< Position of RR3 field. /
bogdanm	0:9b334a45a8ff	7079	#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /!< Bit mask of RR3 field. /
bogdanm	0:9b334a45a8ff	7080	#define WDT_RREN_RR3_Disabled (0UL) /!< RR[3] register is disabled. /
bogdanm	0:9b334a45a8ff	7081	#define WDT_RREN_RR3_Enabled (1UL) /!< RR[3] register is enabled. /
bogdanm	0:9b334a45a8ff	7082
bogdanm	0:9b334a45a8ff	7083	/* Bit 2 : Enable or disable RR[2] register. */
bogdanm	0:9b334a45a8ff	7084	#define WDT_RREN_RR2_Pos (2UL) /!< Position of RR2 field. /
bogdanm	0:9b334a45a8ff	7085	#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /!< Bit mask of RR2 field. /
bogdanm	0:9b334a45a8ff	7086	#define WDT_RREN_RR2_Disabled (0UL) /!< RR[2] register is disabled. /
bogdanm	0:9b334a45a8ff	7087	#define WDT_RREN_RR2_Enabled (1UL) /!< RR[2] register is enabled. /
bogdanm	0:9b334a45a8ff	7088
bogdanm	0:9b334a45a8ff	7089	/* Bit 1 : Enable or disable RR[1] register. */
bogdanm	0:9b334a45a8ff	7090	#define WDT_RREN_RR1_Pos (1UL) /!< Position of RR1 field. /
bogdanm	0:9b334a45a8ff	7091	#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /!< Bit mask of RR1 field. /
bogdanm	0:9b334a45a8ff	7092	#define WDT_RREN_RR1_Disabled (0UL) /!< RR[1] register is disabled. /
bogdanm	0:9b334a45a8ff	7093	#define WDT_RREN_RR1_Enabled (1UL) /!< RR[1] register is enabled. /
bogdanm	0:9b334a45a8ff	7094
bogdanm	0:9b334a45a8ff	7095	/* Bit 0 : Enable or disable RR[0] register. */
bogdanm	0:9b334a45a8ff	7096	#define WDT_RREN_RR0_Pos (0UL) /!< Position of RR0 field. /
bogdanm	0:9b334a45a8ff	7097	#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /!< Bit mask of RR0 field. /
bogdanm	0:9b334a45a8ff	7098	#define WDT_RREN_RR0_Disabled (0UL) /!< RR[0] register is disabled. /
bogdanm	0:9b334a45a8ff	7099	#define WDT_RREN_RR0_Enabled (1UL) /!< RR[0] register is enabled. /
bogdanm	0:9b334a45a8ff	7100
bogdanm	0:9b334a45a8ff	7101	/* Register: WDT_CONFIG */
bogdanm	0:9b334a45a8ff	7102	/* Description: Configuration register. */
bogdanm	0:9b334a45a8ff	7103
bogdanm	0:9b334a45a8ff	7104	/* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */
bogdanm	0:9b334a45a8ff	7105	#define WDT_CONFIG_HALT_Pos (3UL) /!< Position of HALT field. /
bogdanm	0:9b334a45a8ff	7106	#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /!< Bit mask of HALT field. /
bogdanm	0:9b334a45a8ff	7107	#define WDT_CONFIG_HALT_Pause (0UL) /!< Pause watchdog while the CPU is halted by the debugger. /
bogdanm	0:9b334a45a8ff	7108	#define WDT_CONFIG_HALT_Run (1UL) /!< Do not pause watchdog while the CPU is halted by the debugger. /
bogdanm	0:9b334a45a8ff	7109
bogdanm	0:9b334a45a8ff	7110	/* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */
bogdanm	0:9b334a45a8ff	7111	#define WDT_CONFIG_SLEEP_Pos (0UL) /!< Position of SLEEP field. /
bogdanm	0:9b334a45a8ff	7112	#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /!< Bit mask of SLEEP field. /
bogdanm	0:9b334a45a8ff	7113	#define WDT_CONFIG_SLEEP_Pause (0UL) /!< Pause watchdog while the CPU is asleep. /
bogdanm	0:9b334a45a8ff	7114	#define WDT_CONFIG_SLEEP_Run (1UL) /!< Do not pause watchdog while the CPU is asleep. /
bogdanm	0:9b334a45a8ff	7115
bogdanm	0:9b334a45a8ff	7116	/* Register: WDT_RR */
bogdanm	0:9b334a45a8ff	7117	/* Description: Reload requests registers. */
bogdanm	0:9b334a45a8ff	7118
bogdanm	0:9b334a45a8ff	7119	/* Bits 31..0 : Reload register. */
bogdanm	0:9b334a45a8ff	7120	#define WDT_RR_RR_Pos (0UL) /!< Position of RR field. /
bogdanm	0:9b334a45a8ff	7121	#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /!< Bit mask of RR field. /
bogdanm	0:9b334a45a8ff	7122	#define WDT_RR_RR_Reload (0x6E524635UL) /!< Value to request a reload of the watchdog timer. /
bogdanm	0:9b334a45a8ff	7123
bogdanm	0:9b334a45a8ff	7124	/* Register: WDT_POWER */
bogdanm	0:9b334a45a8ff	7125	/* Description: Peripheral power control. */
bogdanm	0:9b334a45a8ff	7126
bogdanm	0:9b334a45a8ff	7127	/* Bit 0 : Peripheral power control. */
bogdanm	0:9b334a45a8ff	7128	#define WDT_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	0:9b334a45a8ff	7129	#define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	0:9b334a45a8ff	7130	#define WDT_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	0:9b334a45a8ff	7131	#define WDT_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	0:9b334a45a8ff	7132
bogdanm	0:9b334a45a8ff	7133
bogdanm	0:9b334a45a8ff	7134	/lint --flb "Leave library region" /
bogdanm	0:9b334a45a8ff	7135	#endif

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Type:	Library
Created:	11 Apr 2017
Imports:	0
Forks:	1
Commits:	164
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51_bitfields.h@0:9b334a45a8ff, 2015-10-01 (annotated)

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