Cortney Padua / mbed-dev

fixed drive strength

Dependents:   capstone_i2c

Fork of mbed-dev by mbed official

targets/TARGET_NUVOTON/TARGET_M451/gpio_irq_api.c@163:1d4c9d0af1e9, 2017-04-11 (annotated)

Committer:
cpadua
Date:
Tue Apr 11 20:39:24 2017 +0000
Revision:
163:1d4c9d0af1e9
Parent:
153:fa9ff456f731 
fixed i2c-api.c

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /* mbed Microcontroller Library
<> 149:156823d33999 2 * Copyright (c) 2015-2016 Nuvoton
<> 149:156823d33999 3 *
<> 149:156823d33999 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 149:156823d33999 5 * you may not use this file except in compliance with the License.
<> 149:156823d33999 6 * You may obtain a copy of the License at
<> 149:156823d33999 7 *
<> 149:156823d33999 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 149:156823d33999 9 *
<> 149:156823d33999 10 * Unless required by applicable law or agreed to in writing, software
<> 149:156823d33999 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 149:156823d33999 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 149:156823d33999 13 * See the License for the specific language governing permissions and
<> 149:156823d33999 14 * limitations under the License.
<> 149:156823d33999 15 */
<> 149:156823d33999 16
<> 149:156823d33999 17 #include "gpio_irq_api.h"
<> 149:156823d33999 18
<> 149:156823d33999 19 #if DEVICE_INTERRUPTIN
<> 149:156823d33999 20
<> 149:156823d33999 21 #include "gpio_api.h"
<> 149:156823d33999 22 #include "cmsis.h"
<> 149:156823d33999 23 #include "pinmap.h"
<> 149:156823d33999 24 #include "PeripheralPins.h"
<> 149:156823d33999 25 #include "nu_bitutil.h"
<> 149:156823d33999 26
<> 149:156823d33999 27 #define NU_MAX_PIN_PER_PORT 16
<> 149:156823d33999 28
<> 149:156823d33999 29 struct nu_gpio_irq_var {
<> 149:156823d33999 30 gpio_irq_t * obj_arr[NU_MAX_PIN_PER_PORT];
<> 149:156823d33999 31 IRQn_Type irq_n;
<> 149:156823d33999 32 void (*vec)(void);
<> 149:156823d33999 33 };
<> 149:156823d33999 34
<> 149:156823d33999 35 static void gpio_irq_0_vec(void);
<> 149:156823d33999 36 static void gpio_irq_1_vec(void);
<> 149:156823d33999 37 static void gpio_irq_2_vec(void);
<> 149:156823d33999 38 static void gpio_irq_3_vec(void);
<> 149:156823d33999 39 static void gpio_irq_4_vec(void);
<> 149:156823d33999 40 static void gpio_irq_5_vec(void);
<> 149:156823d33999 41 static void gpio_irq(struct nu_gpio_irq_var *var);
<> 149:156823d33999 42
<> 149:156823d33999 43 //EINT0_IRQn
<> 149:156823d33999 44 static struct nu_gpio_irq_var gpio_irq_var_arr[] = {
<> 149:156823d33999 45 {{NULL}, GPA_IRQn, gpio_irq_0_vec},
<> 149:156823d33999 46 {{NULL}, GPB_IRQn, gpio_irq_1_vec},
<> 149:156823d33999 47 {{NULL}, GPC_IRQn, gpio_irq_2_vec},
<> 149:156823d33999 48 {{NULL}, GPD_IRQn, gpio_irq_3_vec},
<> 149:156823d33999 49 {{NULL}, GPE_IRQn, gpio_irq_4_vec},
<> 149:156823d33999 50 {{NULL}, GPF_IRQn, gpio_irq_5_vec}
<> 149:156823d33999 51 };
<> 149:156823d33999 52
<> 149:156823d33999 53 #define NU_MAX_PORT (sizeof (gpio_irq_var_arr) / sizeof (gpio_irq_var_arr[0]))
<> 149:156823d33999 54
<> 153:fa9ff456f731 55 #ifndef MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE
<> 153:fa9ff456f731 56 #define MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE 0
<> 149:156823d33999 57 #endif
<> 149:156823d33999 58
<> 153:fa9ff456f731 59 #ifndef MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE_LIST
<> 153:fa9ff456f731 60 #define MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE_LIST NC
<> 153:fa9ff456f731 61 #endif
<> 153:fa9ff456f731 62 static PinName gpio_irq_debounce_arr[] = {
<> 153:fa9ff456f731 63 MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE_LIST
<> 153:fa9ff456f731 64 };
<> 153:fa9ff456f731 65
<> 153:fa9ff456f731 66 #ifndef MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
<> 153:fa9ff456f731 67 #define MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE GPIO_DBCTL_DBCLKSRC_LIRC
<> 149:156823d33999 68 #endif
<> 149:156823d33999 69
<> 153:fa9ff456f731 70 #ifndef MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
<> 153:fa9ff456f731 71 #define MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCTL_DBCLKSEL_16
<> 149:156823d33999 72 #endif
<> 149:156823d33999 73
<> 149:156823d33999 74 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
<> 149:156823d33999 75 {
<> 149:156823d33999 76 if (pin == NC) {
<> 149:156823d33999 77 return -1;
<> 149:156823d33999 78 }
<> 149:156823d33999 79
<> 149:156823d33999 80 uint32_t pin_index = NU_PINNAME_TO_PIN(pin);
<> 149:156823d33999 81 uint32_t port_index = NU_PINNAME_TO_PORT(pin);
<> 149:156823d33999 82 if (pin_index >= NU_MAX_PIN_PER_PORT || port_index >= NU_MAX_PORT) {
<> 149:156823d33999 83 return -1;
<> 149:156823d33999 84 }
<> 149:156823d33999 85
<> 149:156823d33999 86 obj->pin = pin;
<> 149:156823d33999 87 obj->irq_handler = (uint32_t) handler;
<> 149:156823d33999 88 obj->irq_id = id;
<> 149:156823d33999 89
<> 149:156823d33999 90 GPIO_T *gpio_base = NU_PORT_BASE(port_index);
<> 149:156823d33999 91 //gpio_set(pin);
<> 149:156823d33999 92
<> 153:fa9ff456f731 93 {
<> 153:fa9ff456f731 94 #if MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE
<> 153:fa9ff456f731 95 // Suppress compiler warning
<> 153:fa9ff456f731 96 (void) gpio_irq_debounce_arr;
<> 153:fa9ff456f731 97
<> 153:fa9ff456f731 98 // Configure de-bounce clock source and sampling cycle time
<> 153:fa9ff456f731 99 GPIO_SET_DEBOUNCE_TIME(MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
<> 153:fa9ff456f731 100 GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
<> 149:156823d33999 101 #else
<> 153:fa9ff456f731 102 // Enable de-bounce if the pin is in the de-bounce enable list
<> 153:fa9ff456f731 103
<> 153:fa9ff456f731 104 // De-bounce defaults to disabled.
<> 153:fa9ff456f731 105 GPIO_DISABLE_DEBOUNCE(gpio_base, 1 << pin_index);
<> 153:fa9ff456f731 106
<> 153:fa9ff456f731 107 PinName *debounce_pos = gpio_irq_debounce_arr;
<> 153:fa9ff456f731 108 PinName *debounce_end = gpio_irq_debounce_arr + sizeof (gpio_irq_debounce_arr) / sizeof (gpio_irq_debounce_arr[0]);
<> 153:fa9ff456f731 109 for (; debounce_pos != debounce_end && *debounce_pos != NC; debounce_pos ++) {
<> 153:fa9ff456f731 110 uint32_t pin_index_debunce = NU_PINNAME_TO_PIN(*debounce_pos);
<> 153:fa9ff456f731 111 uint32_t port_index_debounce = NU_PINNAME_TO_PORT(*debounce_pos);
<> 153:fa9ff456f731 112
<> 153:fa9ff456f731 113 if (pin_index == pin_index_debunce &&
<> 153:fa9ff456f731 114 port_index == port_index_debounce) {
<> 153:fa9ff456f731 115 // Configure de-bounce clock source and sampling cycle time
<> 153:fa9ff456f731 116 GPIO_SET_DEBOUNCE_TIME(MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
<> 153:fa9ff456f731 117 GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
<> 153:fa9ff456f731 118 break;
<> 153:fa9ff456f731 119 }
<> 153:fa9ff456f731 120 }
<> 149:156823d33999 121 #endif
<> 153:fa9ff456f731 122 }
<> 149:156823d33999 123
<> 149:156823d33999 124 struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
<> 149:156823d33999 125
<> 149:156823d33999 126 var->obj_arr[pin_index] = obj;
<> 149:156823d33999 127
<> 149:156823d33999 128 // NOTE: InterruptIn requires IRQ enabled by default.
<> 149:156823d33999 129 gpio_irq_enable(obj);
<> 149:156823d33999 130
<> 149:156823d33999 131 return 0;
<> 149:156823d33999 132 }
<> 149:156823d33999 133
<> 149:156823d33999 134 void gpio_irq_free(gpio_irq_t *obj)
<> 149:156823d33999 135 {
<> 149:156823d33999 136 uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
<> 149:156823d33999 137 uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
<> 149:156823d33999 138 struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
<> 149:156823d33999 139
<> 149:156823d33999 140 NVIC_DisableIRQ(var->irq_n);
<> 149:156823d33999 141 NU_PORT_BASE(port_index)->INTEN = 0;
<> 149:156823d33999 142
<> 149:156823d33999 143 MBED_ASSERT(pin_index < NU_MAX_PIN_PER_PORT);
<> 149:156823d33999 144 var->obj_arr[pin_index] = NULL;
<> 149:156823d33999 145 }
<> 149:156823d33999 146
<> 149:156823d33999 147 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
<> 149:156823d33999 148 {
<> 149:156823d33999 149 uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
<> 149:156823d33999 150 uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
<> 149:156823d33999 151 GPIO_T *gpio_base = NU_PORT_BASE(port_index);
<> 149:156823d33999 152
<> 149:156823d33999 153 switch (event) {
<> 149:156823d33999 154 case IRQ_RISE:
<> 149:156823d33999 155 if (enable) {
<> 149:156823d33999 156 GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_RISING);
<> 149:156823d33999 157 }
<> 149:156823d33999 158 else {
<> 149:156823d33999 159 gpio_base->INTEN &= ~(GPIO_INT_RISING << pin_index);
<> 149:156823d33999 160 }
<> 149:156823d33999 161 break;
<> 149:156823d33999 162
<> 149:156823d33999 163 case IRQ_FALL:
<> 149:156823d33999 164 if (enable) {
<> 149:156823d33999 165 GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_FALLING);
<> 149:156823d33999 166 }
<> 149:156823d33999 167 else {
<> 149:156823d33999 168 gpio_base->INTEN &= ~(GPIO_INT_FALLING << pin_index);
<> 149:156823d33999 169 }
<> 149:156823d33999 170 break;
<> 149:156823d33999 171 }
<> 149:156823d33999 172 }
<> 149:156823d33999 173
<> 149:156823d33999 174 void gpio_irq_enable(gpio_irq_t *obj)
<> 149:156823d33999 175 {
<> 149:156823d33999 176 //uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
<> 149:156823d33999 177 uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
<> 149:156823d33999 178 struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
<> 149:156823d33999 179
<> 149:156823d33999 180 NVIC_SetVector(var->irq_n, (uint32_t) var->vec);
<> 149:156823d33999 181 NVIC_EnableIRQ(var->irq_n);
<> 149:156823d33999 182 }
<> 149:156823d33999 183
<> 149:156823d33999 184 void gpio_irq_disable(gpio_irq_t *obj)
<> 149:156823d33999 185 {
<> 149:156823d33999 186 //uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
<> 149:156823d33999 187 uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
<> 149:156823d33999 188 struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
<> 149:156823d33999 189
<> 149:156823d33999 190 NVIC_DisableIRQ(var->irq_n);
<> 149:156823d33999 191 }
<> 149:156823d33999 192
<> 149:156823d33999 193 static void gpio_irq_0_vec(void)
<> 149:156823d33999 194 {
<> 149:156823d33999 195 gpio_irq(gpio_irq_var_arr + 0);
<> 149:156823d33999 196 }
<> 149:156823d33999 197 static void gpio_irq_1_vec(void)
<> 149:156823d33999 198 {
<> 149:156823d33999 199 gpio_irq(gpio_irq_var_arr + 1);
<> 149:156823d33999 200 }
<> 149:156823d33999 201 static void gpio_irq_2_vec(void)
<> 149:156823d33999 202 {
<> 149:156823d33999 203 gpio_irq(gpio_irq_var_arr + 2);
<> 149:156823d33999 204 }
<> 149:156823d33999 205 static void gpio_irq_3_vec(void)
<> 149:156823d33999 206 {
<> 149:156823d33999 207 gpio_irq(gpio_irq_var_arr + 3);
<> 149:156823d33999 208 }
<> 149:156823d33999 209 static void gpio_irq_4_vec(void)
<> 149:156823d33999 210 {
<> 149:156823d33999 211 gpio_irq(gpio_irq_var_arr + 4);
<> 149:156823d33999 212 }
<> 149:156823d33999 213 static void gpio_irq_5_vec(void)
<> 149:156823d33999 214 {
<> 149:156823d33999 215 gpio_irq(gpio_irq_var_arr + 5);
<> 149:156823d33999 216 }
<> 149:156823d33999 217
<> 149:156823d33999 218 static void gpio_irq(struct nu_gpio_irq_var *var)
<> 149:156823d33999 219 {
<> 149:156823d33999 220 uint32_t port_index = var->irq_n - GPA_IRQn;
<> 149:156823d33999 221 GPIO_T *gpio_base = NU_PORT_BASE(port_index);
<> 149:156823d33999 222
<> 149:156823d33999 223 uint32_t intsrc = gpio_base->INTSRC;
<> 149:156823d33999 224 uint32_t inten = gpio_base->INTEN;
<> 149:156823d33999 225 while (intsrc) {
<> 149:156823d33999 226 int pin_index = nu_ctz(intsrc);
<> 149:156823d33999 227 gpio_irq_t *obj = var->obj_arr[pin_index];
<> 149:156823d33999 228 if (inten & (GPIO_INT_RISING << pin_index)) {
<> 149:156823d33999 229 if (GPIO_PIN_DATA(port_index, pin_index)) {
<> 149:156823d33999 230 if (obj->irq_handler) {
<> 149:156823d33999 231 ((gpio_irq_handler) obj->irq_handler)(obj->irq_id, IRQ_RISE);
<> 149:156823d33999 232 }
<> 149:156823d33999 233 }
<> 149:156823d33999 234 }
<> 149:156823d33999 235
<> 149:156823d33999 236 if (inten & (GPIO_INT_FALLING << pin_index)) {
<> 149:156823d33999 237 if (! GPIO_PIN_DATA(port_index, pin_index)) {
<> 149:156823d33999 238 if (obj->irq_handler) {
<> 149:156823d33999 239 ((gpio_irq_handler) obj->irq_handler)(obj->irq_id, IRQ_FALL);
<> 149:156823d33999 240 }
<> 149:156823d33999 241 }
<> 149:156823d33999 242 }
<> 149:156823d33999 243
<> 149:156823d33999 244 intsrc &= ~(1 << pin_index);
<> 149:156823d33999 245 }
<> 149:156823d33999 246 // Clear all interrupt flags
<> 149:156823d33999 247 gpio_base->INTSRC = gpio_base->INTSRC;
<> 149:156823d33999 248 }
<> 149:156823d33999 249
<> 149:156823d33999 250 #endif