mbed-dev - fixed drive strength

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fixed drive strength

targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/nrf51_bitfields.h@163:1d4c9d0af1e9, 2017-04-11 (annotated)

Committer:: cpadua
Date:: Tue Apr 11 20:39:24 2017 +0000
Revision:: 163:1d4c9d0af1e9
Parent:: 149:156823d33999

fixed i2c-api.c

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/*
<>	144:ef7eb2e8f9f7	2	* Copyright (c) Nordic Semiconductor ASA
<>	144:ef7eb2e8f9f7	3	* All rights reserved.
<>	144:ef7eb2e8f9f7	4	*
<>	144:ef7eb2e8f9f7	5	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	6	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	7	*
<>	144:ef7eb2e8f9f7	8	* 1. Redistributions of source code must retain the above copyright notice, this
<>	144:ef7eb2e8f9f7	9	* list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	10	*
<>	144:ef7eb2e8f9f7	11	* 2. Redistributions in binary form must reproduce the above copyright notice, this
<>	144:ef7eb2e8f9f7	12	* list of conditions and the following disclaimer in the documentation and/or
<>	144:ef7eb2e8f9f7	13	* other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	14	*
<>	144:ef7eb2e8f9f7	15	* 3. Neither the name of Nordic Semiconductor ASA nor the names of other
<>	144:ef7eb2e8f9f7	16	* contributors to this software may be used to endorse or promote products
<>	144:ef7eb2e8f9f7	17	* derived from this software without specific prior written permission.
<>	144:ef7eb2e8f9f7	18	*
<>	144:ef7eb2e8f9f7	19	*
<>	144:ef7eb2e8f9f7	20	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<>	144:ef7eb2e8f9f7	21	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<>	144:ef7eb2e8f9f7	22	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	23	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<>	144:ef7eb2e8f9f7	24	* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<>	144:ef7eb2e8f9f7	25	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<>	144:ef7eb2e8f9f7	26	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<>	144:ef7eb2e8f9f7	27	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<>	144:ef7eb2e8f9f7	28	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<>	144:ef7eb2e8f9f7	29	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	30	*
<>	144:ef7eb2e8f9f7	31	*/
<>	144:ef7eb2e8f9f7	32	#ifndef __NRF51_BITS_H
<>	144:ef7eb2e8f9f7	33	#define __NRF51_BITS_H
<>	144:ef7eb2e8f9f7	34
<>	144:ef7eb2e8f9f7	35	/lint ++flb "Enter library region" /
<>	144:ef7eb2e8f9f7	36
<>	144:ef7eb2e8f9f7	37	/* Peripheral: AAR */
<>	144:ef7eb2e8f9f7	38	/* Description: Accelerated Address Resolver. */
<>	144:ef7eb2e8f9f7	39
<>	144:ef7eb2e8f9f7	40	/* Register: AAR_INTENSET */
<>	144:ef7eb2e8f9f7	41	/* Description: Interrupt enable set register. */
<>	144:ef7eb2e8f9f7	42
<>	144:ef7eb2e8f9f7	43	/* Bit 2 : Enable interrupt on NOTRESOLVED event. */
<>	144:ef7eb2e8f9f7	44	#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /!< Position of NOTRESOLVED field. /
<>	144:ef7eb2e8f9f7	45	#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /!< Bit mask of NOTRESOLVED field. /
<>	144:ef7eb2e8f9f7	46	#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	47	#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	48	#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	49
<>	144:ef7eb2e8f9f7	50	/* Bit 1 : Enable interrupt on RESOLVED event. */
<>	144:ef7eb2e8f9f7	51	#define AAR_INTENSET_RESOLVED_Pos (1UL) /!< Position of RESOLVED field. /
<>	144:ef7eb2e8f9f7	52	#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /!< Bit mask of RESOLVED field. /
<>	144:ef7eb2e8f9f7	53	#define AAR_INTENSET_RESOLVED_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	54	#define AAR_INTENSET_RESOLVED_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	55	#define AAR_INTENSET_RESOLVED_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	56
<>	144:ef7eb2e8f9f7	57	/* Bit 0 : Enable interrupt on END event. */
<>	144:ef7eb2e8f9f7	58	#define AAR_INTENSET_END_Pos (0UL) /!< Position of END field. /
<>	144:ef7eb2e8f9f7	59	#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /!< Bit mask of END field. /
<>	144:ef7eb2e8f9f7	60	#define AAR_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	61	#define AAR_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	62	#define AAR_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	63
<>	144:ef7eb2e8f9f7	64	/* Register: AAR_INTENCLR */
<>	144:ef7eb2e8f9f7	65	/* Description: Interrupt enable clear register. */
<>	144:ef7eb2e8f9f7	66
<>	144:ef7eb2e8f9f7	67	/* Bit 2 : Disable interrupt on NOTRESOLVED event. */
<>	144:ef7eb2e8f9f7	68	#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /!< Position of NOTRESOLVED field. /
<>	144:ef7eb2e8f9f7	69	#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /!< Bit mask of NOTRESOLVED field. /
<>	144:ef7eb2e8f9f7	70	#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	71	#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	72	#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	73
<>	144:ef7eb2e8f9f7	74	/* Bit 1 : Disable interrupt on RESOLVED event. */
<>	144:ef7eb2e8f9f7	75	#define AAR_INTENCLR_RESOLVED_Pos (1UL) /!< Position of RESOLVED field. /
<>	144:ef7eb2e8f9f7	76	#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /!< Bit mask of RESOLVED field. /
<>	144:ef7eb2e8f9f7	77	#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	78	#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	79	#define AAR_INTENCLR_RESOLVED_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	80
<>	144:ef7eb2e8f9f7	81	/* Bit 0 : Disable interrupt on ENDKSGEN event. */
<>	144:ef7eb2e8f9f7	82	#define AAR_INTENCLR_END_Pos (0UL) /!< Position of END field. /
<>	144:ef7eb2e8f9f7	83	#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /!< Bit mask of END field. /
<>	144:ef7eb2e8f9f7	84	#define AAR_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	85	#define AAR_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	86	#define AAR_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	87
<>	144:ef7eb2e8f9f7	88	/* Register: AAR_STATUS */
<>	144:ef7eb2e8f9f7	89	/* Description: Resolution status. */
<>	144:ef7eb2e8f9f7	90
<>	144:ef7eb2e8f9f7	91	/* Bits 3..0 : The IRK used last time an address was resolved. */
<>	144:ef7eb2e8f9f7	92	#define AAR_STATUS_STATUS_Pos (0UL) /!< Position of STATUS field. /
<>	144:ef7eb2e8f9f7	93	#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /!< Bit mask of STATUS field. /
<>	144:ef7eb2e8f9f7	94
<>	144:ef7eb2e8f9f7	95	/* Register: AAR_ENABLE */
<>	144:ef7eb2e8f9f7	96	/* Description: Enable AAR. */
<>	144:ef7eb2e8f9f7	97
<>	144:ef7eb2e8f9f7	98	/* Bits 1..0 : Enable AAR. */
<>	144:ef7eb2e8f9f7	99	#define AAR_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
<>	144:ef7eb2e8f9f7	100	#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
<>	144:ef7eb2e8f9f7	101	#define AAR_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled AAR. /
<>	144:ef7eb2e8f9f7	102	#define AAR_ENABLE_ENABLE_Enabled (0x03UL) /!< Enable AAR. /
<>	144:ef7eb2e8f9f7	103
<>	144:ef7eb2e8f9f7	104	/* Register: AAR_NIRK */
<>	144:ef7eb2e8f9f7	105	/* Description: Number of Identity root Keys in the IRK data structure. */
<>	144:ef7eb2e8f9f7	106
<>	144:ef7eb2e8f9f7	107	/* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */
<>	144:ef7eb2e8f9f7	108	#define AAR_NIRK_NIRK_Pos (0UL) /!< Position of NIRK field. /
<>	144:ef7eb2e8f9f7	109	#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /!< Bit mask of NIRK field. /
<>	144:ef7eb2e8f9f7	110
<>	144:ef7eb2e8f9f7	111	/* Register: AAR_POWER */
<>	144:ef7eb2e8f9f7	112	/* Description: Peripheral power control. */
<>	144:ef7eb2e8f9f7	113
<>	144:ef7eb2e8f9f7	114	/* Bit 0 : Peripheral power control. */
<>	144:ef7eb2e8f9f7	115	#define AAR_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
<>	144:ef7eb2e8f9f7	116	#define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /!< Bit mask of POWER field. /
<>	144:ef7eb2e8f9f7	117	#define AAR_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
<>	144:ef7eb2e8f9f7	118	#define AAR_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
<>	144:ef7eb2e8f9f7	119
<>	144:ef7eb2e8f9f7	120
<>	144:ef7eb2e8f9f7	121	/* Peripheral: ADC */
<>	144:ef7eb2e8f9f7	122	/* Description: Analog to digital converter. */
<>	144:ef7eb2e8f9f7	123
<>	144:ef7eb2e8f9f7	124	/* Register: ADC_INTENSET */
<>	144:ef7eb2e8f9f7	125	/* Description: Interrupt enable set register. */
<>	144:ef7eb2e8f9f7	126
<>	144:ef7eb2e8f9f7	127	/* Bit 0 : Enable interrupt on END event. */
<>	144:ef7eb2e8f9f7	128	#define ADC_INTENSET_END_Pos (0UL) /!< Position of END field. /
<>	144:ef7eb2e8f9f7	129	#define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /!< Bit mask of END field. /
<>	144:ef7eb2e8f9f7	130	#define ADC_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	131	#define ADC_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	132	#define ADC_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	133
<>	144:ef7eb2e8f9f7	134	/* Register: ADC_INTENCLR */
<>	144:ef7eb2e8f9f7	135	/* Description: Interrupt enable clear register. */
<>	144:ef7eb2e8f9f7	136
<>	144:ef7eb2e8f9f7	137	/* Bit 0 : Disable interrupt on END event. */
<>	144:ef7eb2e8f9f7	138	#define ADC_INTENCLR_END_Pos (0UL) /!< Position of END field. /
<>	144:ef7eb2e8f9f7	139	#define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /!< Bit mask of END field. /
<>	144:ef7eb2e8f9f7	140	#define ADC_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	141	#define ADC_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	142	#define ADC_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	143
<>	144:ef7eb2e8f9f7	144	/* Register: ADC_BUSY */
<>	144:ef7eb2e8f9f7	145	/* Description: ADC busy register. */
<>	144:ef7eb2e8f9f7	146
<>	144:ef7eb2e8f9f7	147	/* Bit 0 : ADC busy register. */
<>	144:ef7eb2e8f9f7	148	#define ADC_BUSY_BUSY_Pos (0UL) /!< Position of BUSY field. /
<>	144:ef7eb2e8f9f7	149	#define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /!< Bit mask of BUSY field. /
<>	144:ef7eb2e8f9f7	150	#define ADC_BUSY_BUSY_Ready (0UL) /!< No ongoing ADC conversion is taking place. ADC is ready. /
<>	144:ef7eb2e8f9f7	151	#define ADC_BUSY_BUSY_Busy (1UL) /!< An ADC conversion is taking place. ADC is busy. /
<>	144:ef7eb2e8f9f7	152
<>	144:ef7eb2e8f9f7	153	/* Register: ADC_ENABLE */
<>	144:ef7eb2e8f9f7	154	/* Description: ADC enable. */
<>	144:ef7eb2e8f9f7	155
<>	144:ef7eb2e8f9f7	156	/* Bits 1..0 : ADC enable. */
<>	144:ef7eb2e8f9f7	157	#define ADC_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
<>	144:ef7eb2e8f9f7	158	#define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
<>	144:ef7eb2e8f9f7	159	#define ADC_ENABLE_ENABLE_Disabled (0x00UL) /!< ADC is disabled. /
<>	144:ef7eb2e8f9f7	160	#define ADC_ENABLE_ENABLE_Enabled (0x01UL) /!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. /
<>	144:ef7eb2e8f9f7	161
<>	144:ef7eb2e8f9f7	162	/* Register: ADC_CONFIG */
<>	144:ef7eb2e8f9f7	163	/* Description: ADC configuration register. */
<>	144:ef7eb2e8f9f7	164
<>	144:ef7eb2e8f9f7	165	/* Bits 17..16 : ADC external reference pin selection. */
<>	144:ef7eb2e8f9f7	166	#define ADC_CONFIG_EXTREFSEL_Pos (16UL) /!< Position of EXTREFSEL field. /
<>	144:ef7eb2e8f9f7	167	#define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /!< Bit mask of EXTREFSEL field. /
<>	144:ef7eb2e8f9f7	168	#define ADC_CONFIG_EXTREFSEL_None (0UL) /!< Analog external reference inputs disabled. /
<>	144:ef7eb2e8f9f7	169	#define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /!< Use analog reference 0 as reference. /
<>	144:ef7eb2e8f9f7	170	#define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /!< Use analog reference 1 as reference. /
<>	144:ef7eb2e8f9f7	171
<>	144:ef7eb2e8f9f7	172	/* Bits 15..8 : ADC analog pin selection. */
<>	144:ef7eb2e8f9f7	173	#define ADC_CONFIG_PSEL_Pos (8UL) /!< Position of PSEL field. /
<>	144:ef7eb2e8f9f7	174	#define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /!< Bit mask of PSEL field. /
<>	144:ef7eb2e8f9f7	175	#define ADC_CONFIG_PSEL_Disabled (0UL) /!< Analog input pins disabled. /
<>	144:ef7eb2e8f9f7	176	#define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /!< Use analog input 0 as analog input. /
<>	144:ef7eb2e8f9f7	177	#define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /!< Use analog input 1 as analog input. /
<>	144:ef7eb2e8f9f7	178	#define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /!< Use analog input 2 as analog input. /
<>	144:ef7eb2e8f9f7	179	#define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /!< Use analog input 3 as analog input. /
<>	144:ef7eb2e8f9f7	180	#define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /!< Use analog input 4 as analog input. /
<>	144:ef7eb2e8f9f7	181	#define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /!< Use analog input 5 as analog input. /
<>	144:ef7eb2e8f9f7	182	#define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /!< Use analog input 6 as analog input. /
<>	144:ef7eb2e8f9f7	183	#define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /!< Use analog input 7 as analog input. /
<>	144:ef7eb2e8f9f7	184
<>	144:ef7eb2e8f9f7	185	/* Bits 6..5 : ADC reference selection. */
<>	144:ef7eb2e8f9f7	186	#define ADC_CONFIG_REFSEL_Pos (5UL) /!< Position of REFSEL field. /
<>	144:ef7eb2e8f9f7	187	#define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /!< Bit mask of REFSEL field. /
<>	144:ef7eb2e8f9f7	188	#define ADC_CONFIG_REFSEL_VBG (0x00UL) /!< Use internal 1.2V bandgap voltage as reference for conversion. /
<>	144:ef7eb2e8f9f7	189	#define ADC_CONFIG_REFSEL_External (0x01UL) /!< Use external source configured by EXTREFSEL as reference for conversion. /
<>	144:ef7eb2e8f9f7	190	#define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. /
<>	144:ef7eb2e8f9f7	191	#define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. /
<>	144:ef7eb2e8f9f7	192
<>	144:ef7eb2e8f9f7	193	/* Bits 4..2 : ADC input selection. */
<>	144:ef7eb2e8f9f7	194	#define ADC_CONFIG_INPSEL_Pos (2UL) /!< Position of INPSEL field. /
<>	144:ef7eb2e8f9f7	195	#define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /!< Bit mask of INPSEL field. /
<>	144:ef7eb2e8f9f7	196	#define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /!< Analog input specified by PSEL with no prescaling used as input for the conversion. /
<>	144:ef7eb2e8f9f7	197	#define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. /
<>	144:ef7eb2e8f9f7	198	#define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. /
<>	144:ef7eb2e8f9f7	199	#define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /!< Supply voltage with 2/3 prescaling used as input for the conversion. /
<>	144:ef7eb2e8f9f7	200	#define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /!< Supply voltage with 1/3 prescaling used as input for the conversion. /
<>	144:ef7eb2e8f9f7	201
<>	144:ef7eb2e8f9f7	202	/* Bits 1..0 : ADC resolution. */
<>	144:ef7eb2e8f9f7	203	#define ADC_CONFIG_RES_Pos (0UL) /!< Position of RES field. /
<>	144:ef7eb2e8f9f7	204	#define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /!< Bit mask of RES field. /
<>	144:ef7eb2e8f9f7	205	#define ADC_CONFIG_RES_8bit (0x00UL) /!< 8bit ADC resolution. /
<>	144:ef7eb2e8f9f7	206	#define ADC_CONFIG_RES_9bit (0x01UL) /!< 9bit ADC resolution. /
<>	144:ef7eb2e8f9f7	207	#define ADC_CONFIG_RES_10bit (0x02UL) /!< 10bit ADC resolution. /
<>	144:ef7eb2e8f9f7	208
<>	144:ef7eb2e8f9f7	209	/* Register: ADC_RESULT */
<>	144:ef7eb2e8f9f7	210	/* Description: Result of ADC conversion. */
<>	144:ef7eb2e8f9f7	211
<>	144:ef7eb2e8f9f7	212	/* Bits 9..0 : Result of ADC conversion. */
<>	144:ef7eb2e8f9f7	213	#define ADC_RESULT_RESULT_Pos (0UL) /!< Position of RESULT field. /
<>	144:ef7eb2e8f9f7	214	#define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /!< Bit mask of RESULT field. /
<>	144:ef7eb2e8f9f7	215
<>	144:ef7eb2e8f9f7	216	/* Register: ADC_POWER */
<>	144:ef7eb2e8f9f7	217	/* Description: Peripheral power control. */
<>	144:ef7eb2e8f9f7	218
<>	144:ef7eb2e8f9f7	219	/* Bit 0 : Peripheral power control. */
<>	144:ef7eb2e8f9f7	220	#define ADC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
<>	144:ef7eb2e8f9f7	221	#define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
<>	144:ef7eb2e8f9f7	222	#define ADC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
<>	144:ef7eb2e8f9f7	223	#define ADC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
<>	144:ef7eb2e8f9f7	224
<>	144:ef7eb2e8f9f7	225
<>	144:ef7eb2e8f9f7	226	/* Peripheral: AMLI */
<>	144:ef7eb2e8f9f7	227	/* Description: AHB Multi-Layer Interface. */
<>	144:ef7eb2e8f9f7	228
<>	144:ef7eb2e8f9f7	229	/* Register: AMLI_RAMPRI_CPU0 */
<>	144:ef7eb2e8f9f7	230	/* Description: Configurable priority configuration register for CPU0. */
<>	144:ef7eb2e8f9f7	231
<>	144:ef7eb2e8f9f7	232	/* Bits 31..28 : Configuration field for RAM block 7. */
<>	144:ef7eb2e8f9f7	233	#define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /!< Position of RAM7 field. /
<>	144:ef7eb2e8f9f7	234	#define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /!< Bit mask of RAM7 field. /
<>	144:ef7eb2e8f9f7	235	#define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	236	#define AMLI_RAMPRI_CPU0_RAM7_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	237	#define AMLI_RAMPRI_CPU0_RAM7_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	238	#define AMLI_RAMPRI_CPU0_RAM7_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	239	#define AMLI_RAMPRI_CPU0_RAM7_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	240	#define AMLI_RAMPRI_CPU0_RAM7_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	241	#define AMLI_RAMPRI_CPU0_RAM7_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	242	#define AMLI_RAMPRI_CPU0_RAM7_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	243
<>	144:ef7eb2e8f9f7	244	/* Bits 27..24 : Configuration field for RAM block 6. */
<>	144:ef7eb2e8f9f7	245	#define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /!< Position of RAM6 field. /
<>	144:ef7eb2e8f9f7	246	#define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /!< Bit mask of RAM6 field. /
<>	144:ef7eb2e8f9f7	247	#define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	248	#define AMLI_RAMPRI_CPU0_RAM6_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	249	#define AMLI_RAMPRI_CPU0_RAM6_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	250	#define AMLI_RAMPRI_CPU0_RAM6_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	251	#define AMLI_RAMPRI_CPU0_RAM6_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	252	#define AMLI_RAMPRI_CPU0_RAM6_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	253	#define AMLI_RAMPRI_CPU0_RAM6_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	254	#define AMLI_RAMPRI_CPU0_RAM6_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	255
<>	144:ef7eb2e8f9f7	256	/* Bits 23..20 : Configuration field for RAM block 5. */
<>	144:ef7eb2e8f9f7	257	#define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /!< Position of RAM5 field. /
<>	144:ef7eb2e8f9f7	258	#define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /!< Bit mask of RAM5 field. /
<>	144:ef7eb2e8f9f7	259	#define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	260	#define AMLI_RAMPRI_CPU0_RAM5_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	261	#define AMLI_RAMPRI_CPU0_RAM5_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	262	#define AMLI_RAMPRI_CPU0_RAM5_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	263	#define AMLI_RAMPRI_CPU0_RAM5_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	264	#define AMLI_RAMPRI_CPU0_RAM5_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	265	#define AMLI_RAMPRI_CPU0_RAM5_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	266	#define AMLI_RAMPRI_CPU0_RAM5_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	267
<>	144:ef7eb2e8f9f7	268	/* Bits 19..16 : Configuration field for RAM block 4. */
<>	144:ef7eb2e8f9f7	269	#define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /!< Position of RAM4 field. /
<>	144:ef7eb2e8f9f7	270	#define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /!< Bit mask of RAM4 field. /
<>	144:ef7eb2e8f9f7	271	#define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	272	#define AMLI_RAMPRI_CPU0_RAM4_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	273	#define AMLI_RAMPRI_CPU0_RAM4_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	274	#define AMLI_RAMPRI_CPU0_RAM4_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	275	#define AMLI_RAMPRI_CPU0_RAM4_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	276	#define AMLI_RAMPRI_CPU0_RAM4_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	277	#define AMLI_RAMPRI_CPU0_RAM4_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	278	#define AMLI_RAMPRI_CPU0_RAM4_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	279
<>	144:ef7eb2e8f9f7	280	/* Bits 15..12 : Configuration field for RAM block 3. */
<>	144:ef7eb2e8f9f7	281	#define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /!< Position of RAM3 field. /
<>	144:ef7eb2e8f9f7	282	#define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /!< Bit mask of RAM3 field. /
<>	144:ef7eb2e8f9f7	283	#define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	284	#define AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	285	#define AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	286	#define AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	287	#define AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	288	#define AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	289	#define AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	290	#define AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	291
<>	144:ef7eb2e8f9f7	292	/* Bits 11..8 : Configuration field for RAM block 2. */
<>	144:ef7eb2e8f9f7	293	#define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /!< Position of RAM2 field. /
<>	144:ef7eb2e8f9f7	294	#define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /!< Bit mask of RAM2 field. /
<>	144:ef7eb2e8f9f7	295	#define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	296	#define AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	297	#define AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	298	#define AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	299	#define AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	300	#define AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	301	#define AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	302	#define AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	303
<>	144:ef7eb2e8f9f7	304	/* Bits 7..4 : Configuration field for RAM block 1. */
<>	144:ef7eb2e8f9f7	305	#define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /!< Position of RAM1 field. /
<>	144:ef7eb2e8f9f7	306	#define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /!< Bit mask of RAM1 field. /
<>	144:ef7eb2e8f9f7	307	#define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	308	#define AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	309	#define AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	310	#define AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	311	#define AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	312	#define AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	313	#define AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	314	#define AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	315
<>	144:ef7eb2e8f9f7	316	/* Bits 3..0 : Configuration field for RAM block 0. */
<>	144:ef7eb2e8f9f7	317	#define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /!< Position of RAM0 field. /
<>	144:ef7eb2e8f9f7	318	#define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /!< Bit mask of RAM0 field. /
<>	144:ef7eb2e8f9f7	319	#define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	320	#define AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	321	#define AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	322	#define AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	323	#define AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	324	#define AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	325	#define AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	326	#define AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	327
<>	144:ef7eb2e8f9f7	328	/* Register: AMLI_RAMPRI_SPIS1 */
<>	144:ef7eb2e8f9f7	329	/* Description: Configurable priority configuration register for SPIS1. */
<>	144:ef7eb2e8f9f7	330
<>	144:ef7eb2e8f9f7	331	/* Bits 31..28 : Configuration field for RAM block 7. */
<>	144:ef7eb2e8f9f7	332	#define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /!< Position of RAM7 field. /
<>	144:ef7eb2e8f9f7	333	#define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /!< Bit mask of RAM7 field. /
<>	144:ef7eb2e8f9f7	334	#define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	335	#define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	336	#define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	337	#define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	338	#define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	339	#define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	340	#define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	341	#define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	342
<>	144:ef7eb2e8f9f7	343	/* Bits 27..24 : Configuration field for RAM block 6. */
<>	144:ef7eb2e8f9f7	344	#define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /!< Position of RAM6 field. /
<>	144:ef7eb2e8f9f7	345	#define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /!< Bit mask of RAM6 field. /
<>	144:ef7eb2e8f9f7	346	#define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	347	#define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	348	#define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	349	#define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	350	#define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	351	#define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	352	#define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	353	#define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	354
<>	144:ef7eb2e8f9f7	355	/* Bits 23..20 : Configuration field for RAM block 5. */
<>	144:ef7eb2e8f9f7	356	#define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /!< Position of RAM5 field. /
<>	144:ef7eb2e8f9f7	357	#define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /!< Bit mask of RAM5 field. /
<>	144:ef7eb2e8f9f7	358	#define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	359	#define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	360	#define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	361	#define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	362	#define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	363	#define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	364	#define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	365	#define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	366
<>	144:ef7eb2e8f9f7	367	/* Bits 19..16 : Configuration field for RAM block 4. */
<>	144:ef7eb2e8f9f7	368	#define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /!< Position of RAM4 field. /
<>	144:ef7eb2e8f9f7	369	#define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /!< Bit mask of RAM4 field. /
<>	144:ef7eb2e8f9f7	370	#define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	371	#define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	372	#define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	373	#define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	374	#define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	375	#define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	376	#define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	377	#define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	378
<>	144:ef7eb2e8f9f7	379	/* Bits 15..12 : Configuration field for RAM block 3. */
<>	144:ef7eb2e8f9f7	380	#define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /!< Position of RAM3 field. /
<>	144:ef7eb2e8f9f7	381	#define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /!< Bit mask of RAM3 field. /
<>	144:ef7eb2e8f9f7	382	#define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	383	#define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	384	#define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	385	#define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	386	#define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	387	#define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	388	#define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	389	#define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	390
<>	144:ef7eb2e8f9f7	391	/* Bits 11..8 : Configuration field for RAM block 2. */
<>	144:ef7eb2e8f9f7	392	#define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /!< Position of RAM2 field. /
<>	144:ef7eb2e8f9f7	393	#define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /!< Bit mask of RAM2 field. /
<>	144:ef7eb2e8f9f7	394	#define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	395	#define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	396	#define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	397	#define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	398	#define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	399	#define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	400	#define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	401	#define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	402
<>	144:ef7eb2e8f9f7	403	/* Bits 7..4 : Configuration field for RAM block 1. */
<>	144:ef7eb2e8f9f7	404	#define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /!< Position of RAM1 field. /
<>	144:ef7eb2e8f9f7	405	#define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /!< Bit mask of RAM1 field. /
<>	144:ef7eb2e8f9f7	406	#define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	407	#define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	408	#define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	409	#define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	410	#define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	411	#define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	412	#define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	413	#define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	414
<>	144:ef7eb2e8f9f7	415	/* Bits 3..0 : Configuration field for RAM block 0. */
<>	144:ef7eb2e8f9f7	416	#define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /!< Position of RAM0 field. /
<>	144:ef7eb2e8f9f7	417	#define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /!< Bit mask of RAM0 field. /
<>	144:ef7eb2e8f9f7	418	#define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	419	#define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	420	#define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	421	#define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	422	#define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	423	#define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	424	#define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	425	#define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	426
<>	144:ef7eb2e8f9f7	427	/* Register: AMLI_RAMPRI_RADIO */
<>	144:ef7eb2e8f9f7	428	/* Description: Configurable priority configuration register for RADIO. */
<>	144:ef7eb2e8f9f7	429
<>	144:ef7eb2e8f9f7	430	/* Bits 31..28 : Configuration field for RAM block 7. */
<>	144:ef7eb2e8f9f7	431	#define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /!< Position of RAM7 field. /
<>	144:ef7eb2e8f9f7	432	#define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /!< Bit mask of RAM7 field. /
<>	144:ef7eb2e8f9f7	433	#define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	434	#define AMLI_RAMPRI_RADIO_RAM7_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	435	#define AMLI_RAMPRI_RADIO_RAM7_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	436	#define AMLI_RAMPRI_RADIO_RAM7_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	437	#define AMLI_RAMPRI_RADIO_RAM7_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	438	#define AMLI_RAMPRI_RADIO_RAM7_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	439	#define AMLI_RAMPRI_RADIO_RAM7_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	440	#define AMLI_RAMPRI_RADIO_RAM7_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	441
<>	144:ef7eb2e8f9f7	442	/* Bits 27..24 : Configuration field for RAM block 6. */
<>	144:ef7eb2e8f9f7	443	#define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /!< Position of RAM6 field. /
<>	144:ef7eb2e8f9f7	444	#define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /!< Bit mask of RAM6 field. /
<>	144:ef7eb2e8f9f7	445	#define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	446	#define AMLI_RAMPRI_RADIO_RAM6_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	447	#define AMLI_RAMPRI_RADIO_RAM6_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	448	#define AMLI_RAMPRI_RADIO_RAM6_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	449	#define AMLI_RAMPRI_RADIO_RAM6_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	450	#define AMLI_RAMPRI_RADIO_RAM6_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	451	#define AMLI_RAMPRI_RADIO_RAM6_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	452	#define AMLI_RAMPRI_RADIO_RAM6_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	453
<>	144:ef7eb2e8f9f7	454	/* Bits 23..20 : Configuration field for RAM block 5. */
<>	144:ef7eb2e8f9f7	455	#define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /!< Position of RAM5 field. /
<>	144:ef7eb2e8f9f7	456	#define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /!< Bit mask of RAM5 field. /
<>	144:ef7eb2e8f9f7	457	#define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	458	#define AMLI_RAMPRI_RADIO_RAM5_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	459	#define AMLI_RAMPRI_RADIO_RAM5_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	460	#define AMLI_RAMPRI_RADIO_RAM5_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	461	#define AMLI_RAMPRI_RADIO_RAM5_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	462	#define AMLI_RAMPRI_RADIO_RAM5_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	463	#define AMLI_RAMPRI_RADIO_RAM5_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	464	#define AMLI_RAMPRI_RADIO_RAM5_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	465
<>	144:ef7eb2e8f9f7	466	/* Bits 19..16 : Configuration field for RAM block 4. */
<>	144:ef7eb2e8f9f7	467	#define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /!< Position of RAM4 field. /
<>	144:ef7eb2e8f9f7	468	#define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /!< Bit mask of RAM4 field. /
<>	144:ef7eb2e8f9f7	469	#define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	470	#define AMLI_RAMPRI_RADIO_RAM4_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	471	#define AMLI_RAMPRI_RADIO_RAM4_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	472	#define AMLI_RAMPRI_RADIO_RAM4_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	473	#define AMLI_RAMPRI_RADIO_RAM4_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	474	#define AMLI_RAMPRI_RADIO_RAM4_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	475	#define AMLI_RAMPRI_RADIO_RAM4_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	476	#define AMLI_RAMPRI_RADIO_RAM4_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	477
<>	144:ef7eb2e8f9f7	478	/* Bits 15..12 : Configuration field for RAM block 3. */
<>	144:ef7eb2e8f9f7	479	#define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /!< Position of RAM3 field. /
<>	144:ef7eb2e8f9f7	480	#define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /!< Bit mask of RAM3 field. /
<>	144:ef7eb2e8f9f7	481	#define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	482	#define AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	483	#define AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	484	#define AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	485	#define AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	486	#define AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	487	#define AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	488	#define AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	489
<>	144:ef7eb2e8f9f7	490	/* Bits 11..8 : Configuration field for RAM block 2. */
<>	144:ef7eb2e8f9f7	491	#define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /!< Position of RAM2 field. /
<>	144:ef7eb2e8f9f7	492	#define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /!< Bit mask of RAM2 field. /
<>	144:ef7eb2e8f9f7	493	#define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	494	#define AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	495	#define AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	496	#define AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	497	#define AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	498	#define AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	499	#define AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	500	#define AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	501
<>	144:ef7eb2e8f9f7	502	/* Bits 7..4 : Configuration field for RAM block 1. */
<>	144:ef7eb2e8f9f7	503	#define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /!< Position of RAM1 field. /
<>	144:ef7eb2e8f9f7	504	#define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /!< Bit mask of RAM1 field. /
<>	144:ef7eb2e8f9f7	505	#define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	506	#define AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	507	#define AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	508	#define AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	509	#define AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	510	#define AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	511	#define AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	512	#define AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	513
<>	144:ef7eb2e8f9f7	514	/* Bits 3..0 : Configuration field for RAM block 0. */
<>	144:ef7eb2e8f9f7	515	#define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /!< Position of RAM0 field. /
<>	144:ef7eb2e8f9f7	516	#define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /!< Bit mask of RAM0 field. /
<>	144:ef7eb2e8f9f7	517	#define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	518	#define AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	519	#define AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	520	#define AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	521	#define AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	522	#define AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	523	#define AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	524	#define AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	525
<>	144:ef7eb2e8f9f7	526	/* Register: AMLI_RAMPRI_ECB */
<>	144:ef7eb2e8f9f7	527	/* Description: Configurable priority configuration register for ECB. */
<>	144:ef7eb2e8f9f7	528
<>	144:ef7eb2e8f9f7	529	/* Bits 31..28 : Configuration field for RAM block 7. */
<>	144:ef7eb2e8f9f7	530	#define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /!< Position of RAM7 field. /
<>	144:ef7eb2e8f9f7	531	#define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /!< Bit mask of RAM7 field. /
<>	144:ef7eb2e8f9f7	532	#define AMLI_RAMPRI_ECB_RAM7_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	533	#define AMLI_RAMPRI_ECB_RAM7_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	534	#define AMLI_RAMPRI_ECB_RAM7_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	535	#define AMLI_RAMPRI_ECB_RAM7_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	536	#define AMLI_RAMPRI_ECB_RAM7_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	537	#define AMLI_RAMPRI_ECB_RAM7_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	538	#define AMLI_RAMPRI_ECB_RAM7_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	539	#define AMLI_RAMPRI_ECB_RAM7_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	540
<>	144:ef7eb2e8f9f7	541	/* Bits 27..24 : Configuration field for RAM block 6. */
<>	144:ef7eb2e8f9f7	542	#define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /!< Position of RAM6 field. /
<>	144:ef7eb2e8f9f7	543	#define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /!< Bit mask of RAM6 field. /
<>	144:ef7eb2e8f9f7	544	#define AMLI_RAMPRI_ECB_RAM6_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	545	#define AMLI_RAMPRI_ECB_RAM6_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	546	#define AMLI_RAMPRI_ECB_RAM6_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	547	#define AMLI_RAMPRI_ECB_RAM6_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	548	#define AMLI_RAMPRI_ECB_RAM6_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	549	#define AMLI_RAMPRI_ECB_RAM6_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	550	#define AMLI_RAMPRI_ECB_RAM6_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	551	#define AMLI_RAMPRI_ECB_RAM6_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	552
<>	144:ef7eb2e8f9f7	553	/* Bits 23..20 : Configuration field for RAM block 5. */
<>	144:ef7eb2e8f9f7	554	#define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /!< Position of RAM5 field. /
<>	144:ef7eb2e8f9f7	555	#define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /!< Bit mask of RAM5 field. /
<>	144:ef7eb2e8f9f7	556	#define AMLI_RAMPRI_ECB_RAM5_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	557	#define AMLI_RAMPRI_ECB_RAM5_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	558	#define AMLI_RAMPRI_ECB_RAM5_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	559	#define AMLI_RAMPRI_ECB_RAM5_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	560	#define AMLI_RAMPRI_ECB_RAM5_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	561	#define AMLI_RAMPRI_ECB_RAM5_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	562	#define AMLI_RAMPRI_ECB_RAM5_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	563	#define AMLI_RAMPRI_ECB_RAM5_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	564
<>	144:ef7eb2e8f9f7	565	/* Bits 19..16 : Configuration field for RAM block 4. */
<>	144:ef7eb2e8f9f7	566	#define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /!< Position of RAM4 field. /
<>	144:ef7eb2e8f9f7	567	#define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /!< Bit mask of RAM4 field. /
<>	144:ef7eb2e8f9f7	568	#define AMLI_RAMPRI_ECB_RAM4_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	569	#define AMLI_RAMPRI_ECB_RAM4_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	570	#define AMLI_RAMPRI_ECB_RAM4_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	571	#define AMLI_RAMPRI_ECB_RAM4_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	572	#define AMLI_RAMPRI_ECB_RAM4_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	573	#define AMLI_RAMPRI_ECB_RAM4_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	574	#define AMLI_RAMPRI_ECB_RAM4_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	575	#define AMLI_RAMPRI_ECB_RAM4_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	576
<>	144:ef7eb2e8f9f7	577	/* Bits 15..12 : Configuration field for RAM block 3. */
<>	144:ef7eb2e8f9f7	578	#define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /!< Position of RAM3 field. /
<>	144:ef7eb2e8f9f7	579	#define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /!< Bit mask of RAM3 field. /
<>	144:ef7eb2e8f9f7	580	#define AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	581	#define AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	582	#define AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	583	#define AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	584	#define AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	585	#define AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	586	#define AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	587	#define AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	588
<>	144:ef7eb2e8f9f7	589	/* Bits 11..8 : Configuration field for RAM block 2. */
<>	144:ef7eb2e8f9f7	590	#define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /!< Position of RAM2 field. /
<>	144:ef7eb2e8f9f7	591	#define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /!< Bit mask of RAM2 field. /
<>	144:ef7eb2e8f9f7	592	#define AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	593	#define AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	594	#define AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	595	#define AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	596	#define AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	597	#define AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	598	#define AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	599	#define AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	600
<>	144:ef7eb2e8f9f7	601	/* Bits 7..4 : Configuration field for RAM block 1. */
<>	144:ef7eb2e8f9f7	602	#define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /!< Position of RAM1 field. /
<>	144:ef7eb2e8f9f7	603	#define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /!< Bit mask of RAM1 field. /
<>	144:ef7eb2e8f9f7	604	#define AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	605	#define AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	606	#define AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	607	#define AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	608	#define AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	609	#define AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	610	#define AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	611	#define AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	612
<>	144:ef7eb2e8f9f7	613	/* Bits 3..0 : Configuration field for RAM block 0. */
<>	144:ef7eb2e8f9f7	614	#define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /!< Position of RAM0 field. /
<>	144:ef7eb2e8f9f7	615	#define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /!< Bit mask of RAM0 field. /
<>	144:ef7eb2e8f9f7	616	#define AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	617	#define AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	618	#define AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	619	#define AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	620	#define AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	621	#define AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	622	#define AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	623	#define AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	624
<>	144:ef7eb2e8f9f7	625	/* Register: AMLI_RAMPRI_CCM */
<>	144:ef7eb2e8f9f7	626	/* Description: Configurable priority configuration register for CCM. */
<>	144:ef7eb2e8f9f7	627
<>	144:ef7eb2e8f9f7	628	/* Bits 31..28 : Configuration field for RAM block 7. */
<>	144:ef7eb2e8f9f7	629	#define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /!< Position of RAM7 field. /
<>	144:ef7eb2e8f9f7	630	#define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /!< Bit mask of RAM7 field. /
<>	144:ef7eb2e8f9f7	631	#define AMLI_RAMPRI_CCM_RAM7_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	632	#define AMLI_RAMPRI_CCM_RAM7_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	633	#define AMLI_RAMPRI_CCM_RAM7_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	634	#define AMLI_RAMPRI_CCM_RAM7_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	635	#define AMLI_RAMPRI_CCM_RAM7_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	636	#define AMLI_RAMPRI_CCM_RAM7_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	637	#define AMLI_RAMPRI_CCM_RAM7_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	638	#define AMLI_RAMPRI_CCM_RAM7_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	639
<>	144:ef7eb2e8f9f7	640	/* Bits 27..24 : Configuration field for RAM block 6. */
<>	144:ef7eb2e8f9f7	641	#define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /!< Position of RAM6 field. /
<>	144:ef7eb2e8f9f7	642	#define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /!< Bit mask of RAM6 field. /
<>	144:ef7eb2e8f9f7	643	#define AMLI_RAMPRI_CCM_RAM6_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	644	#define AMLI_RAMPRI_CCM_RAM6_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	645	#define AMLI_RAMPRI_CCM_RAM6_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	646	#define AMLI_RAMPRI_CCM_RAM6_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	647	#define AMLI_RAMPRI_CCM_RAM6_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	648	#define AMLI_RAMPRI_CCM_RAM6_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	649	#define AMLI_RAMPRI_CCM_RAM6_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	650	#define AMLI_RAMPRI_CCM_RAM6_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	651
<>	144:ef7eb2e8f9f7	652	/* Bits 23..20 : Configuration field for RAM block 5. */
<>	144:ef7eb2e8f9f7	653	#define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /!< Position of RAM5 field. /
<>	144:ef7eb2e8f9f7	654	#define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /!< Bit mask of RAM5 field. /
<>	144:ef7eb2e8f9f7	655	#define AMLI_RAMPRI_CCM_RAM5_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	656	#define AMLI_RAMPRI_CCM_RAM5_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	657	#define AMLI_RAMPRI_CCM_RAM5_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	658	#define AMLI_RAMPRI_CCM_RAM5_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	659	#define AMLI_RAMPRI_CCM_RAM5_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	660	#define AMLI_RAMPRI_CCM_RAM5_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	661	#define AMLI_RAMPRI_CCM_RAM5_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	662	#define AMLI_RAMPRI_CCM_RAM5_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	663
<>	144:ef7eb2e8f9f7	664	/* Bits 19..16 : Configuration field for RAM block 4. */
<>	144:ef7eb2e8f9f7	665	#define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /!< Position of RAM4 field. /
<>	144:ef7eb2e8f9f7	666	#define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /!< Bit mask of RAM4 field. /
<>	144:ef7eb2e8f9f7	667	#define AMLI_RAMPRI_CCM_RAM4_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	668	#define AMLI_RAMPRI_CCM_RAM4_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	669	#define AMLI_RAMPRI_CCM_RAM4_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	670	#define AMLI_RAMPRI_CCM_RAM4_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	671	#define AMLI_RAMPRI_CCM_RAM4_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	672	#define AMLI_RAMPRI_CCM_RAM4_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	673	#define AMLI_RAMPRI_CCM_RAM4_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	674	#define AMLI_RAMPRI_CCM_RAM4_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	675
<>	144:ef7eb2e8f9f7	676	/* Bits 15..12 : Configuration field for RAM block 3. */
<>	144:ef7eb2e8f9f7	677	#define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /!< Position of RAM3 field. /
<>	144:ef7eb2e8f9f7	678	#define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /!< Bit mask of RAM3 field. /
<>	144:ef7eb2e8f9f7	679	#define AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	680	#define AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	681	#define AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	682	#define AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	683	#define AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	684	#define AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	685	#define AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	686	#define AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	687
<>	144:ef7eb2e8f9f7	688	/* Bits 11..8 : Configuration field for RAM block 2. */
<>	144:ef7eb2e8f9f7	689	#define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /!< Position of RAM2 field. /
<>	144:ef7eb2e8f9f7	690	#define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /!< Bit mask of RAM2 field. /
<>	144:ef7eb2e8f9f7	691	#define AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	692	#define AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	693	#define AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	694	#define AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	695	#define AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	696	#define AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	697	#define AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	698	#define AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	699
<>	144:ef7eb2e8f9f7	700	/* Bits 7..4 : Configuration field for RAM block 1. */
<>	144:ef7eb2e8f9f7	701	#define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /!< Position of RAM1 field. /
<>	144:ef7eb2e8f9f7	702	#define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /!< Bit mask of RAM1 field. /
<>	144:ef7eb2e8f9f7	703	#define AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	704	#define AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	705	#define AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	706	#define AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	707	#define AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	708	#define AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	709	#define AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	710	#define AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	711
<>	144:ef7eb2e8f9f7	712	/* Bits 3..0 : Configuration field for RAM block 0. */
<>	144:ef7eb2e8f9f7	713	#define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /!< Position of RAM0 field. /
<>	144:ef7eb2e8f9f7	714	#define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /!< Bit mask of RAM0 field. /
<>	144:ef7eb2e8f9f7	715	#define AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	716	#define AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	717	#define AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	718	#define AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	719	#define AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	720	#define AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	721	#define AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	722	#define AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	723
<>	144:ef7eb2e8f9f7	724	/* Register: AMLI_RAMPRI_AAR */
<>	144:ef7eb2e8f9f7	725	/* Description: Configurable priority configuration register for AAR. */
<>	144:ef7eb2e8f9f7	726
<>	144:ef7eb2e8f9f7	727	/* Bits 31..28 : Configuration field for RAM block 7. */
<>	144:ef7eb2e8f9f7	728	#define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /!< Position of RAM7 field. /
<>	144:ef7eb2e8f9f7	729	#define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /!< Bit mask of RAM7 field. /
<>	144:ef7eb2e8f9f7	730	#define AMLI_RAMPRI_AAR_RAM7_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	731	#define AMLI_RAMPRI_AAR_RAM7_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	732	#define AMLI_RAMPRI_AAR_RAM7_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	733	#define AMLI_RAMPRI_AAR_RAM7_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	734	#define AMLI_RAMPRI_AAR_RAM7_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	735	#define AMLI_RAMPRI_AAR_RAM7_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	736	#define AMLI_RAMPRI_AAR_RAM7_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	737	#define AMLI_RAMPRI_AAR_RAM7_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	738
<>	144:ef7eb2e8f9f7	739	/* Bits 27..24 : Configuration field for RAM block 6. */
<>	144:ef7eb2e8f9f7	740	#define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /!< Position of RAM6 field. /
<>	144:ef7eb2e8f9f7	741	#define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /!< Bit mask of RAM6 field. /
<>	144:ef7eb2e8f9f7	742	#define AMLI_RAMPRI_AAR_RAM6_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	743	#define AMLI_RAMPRI_AAR_RAM6_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	744	#define AMLI_RAMPRI_AAR_RAM6_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	745	#define AMLI_RAMPRI_AAR_RAM6_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	746	#define AMLI_RAMPRI_AAR_RAM6_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	747	#define AMLI_RAMPRI_AAR_RAM6_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	748	#define AMLI_RAMPRI_AAR_RAM6_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	749	#define AMLI_RAMPRI_AAR_RAM6_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	750
<>	144:ef7eb2e8f9f7	751	/* Bits 23..20 : Configuration field for RAM block 5. */
<>	144:ef7eb2e8f9f7	752	#define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /!< Position of RAM5 field. /
<>	144:ef7eb2e8f9f7	753	#define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /!< Bit mask of RAM5 field. /
<>	144:ef7eb2e8f9f7	754	#define AMLI_RAMPRI_AAR_RAM5_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	755	#define AMLI_RAMPRI_AAR_RAM5_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	756	#define AMLI_RAMPRI_AAR_RAM5_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	757	#define AMLI_RAMPRI_AAR_RAM5_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	758	#define AMLI_RAMPRI_AAR_RAM5_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	759	#define AMLI_RAMPRI_AAR_RAM5_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	760	#define AMLI_RAMPRI_AAR_RAM5_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	761	#define AMLI_RAMPRI_AAR_RAM5_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	762
<>	144:ef7eb2e8f9f7	763	/* Bits 19..16 : Configuration field for RAM block 4. */
<>	144:ef7eb2e8f9f7	764	#define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /!< Position of RAM4 field. /
<>	144:ef7eb2e8f9f7	765	#define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /!< Bit mask of RAM4 field. /
<>	144:ef7eb2e8f9f7	766	#define AMLI_RAMPRI_AAR_RAM4_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	767	#define AMLI_RAMPRI_AAR_RAM4_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	768	#define AMLI_RAMPRI_AAR_RAM4_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	769	#define AMLI_RAMPRI_AAR_RAM4_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	770	#define AMLI_RAMPRI_AAR_RAM4_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	771	#define AMLI_RAMPRI_AAR_RAM4_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	772	#define AMLI_RAMPRI_AAR_RAM4_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	773	#define AMLI_RAMPRI_AAR_RAM4_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	774
<>	144:ef7eb2e8f9f7	775	/* Bits 15..12 : Configuration field for RAM block 3. */
<>	144:ef7eb2e8f9f7	776	#define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /!< Position of RAM3 field. /
<>	144:ef7eb2e8f9f7	777	#define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /!< Bit mask of RAM3 field. /
<>	144:ef7eb2e8f9f7	778	#define AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	779	#define AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	780	#define AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	781	#define AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	782	#define AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	783	#define AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	784	#define AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	785	#define AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	786
<>	144:ef7eb2e8f9f7	787	/* Bits 11..8 : Configuration field for RAM block 2. */
<>	144:ef7eb2e8f9f7	788	#define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /!< Position of RAM2 field. /
<>	144:ef7eb2e8f9f7	789	#define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /!< Bit mask of RAM2 field. /
<>	144:ef7eb2e8f9f7	790	#define AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	791	#define AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	792	#define AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	793	#define AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	794	#define AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	795	#define AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	796	#define AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	797	#define AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	798
<>	144:ef7eb2e8f9f7	799	/* Bits 7..4 : Configuration field for RAM block 1. */
<>	144:ef7eb2e8f9f7	800	#define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /!< Position of RAM1 field. /
<>	144:ef7eb2e8f9f7	801	#define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /!< Bit mask of RAM1 field. /
<>	144:ef7eb2e8f9f7	802	#define AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	803	#define AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	804	#define AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	805	#define AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	806	#define AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	807	#define AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	808	#define AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	809	#define AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	810
<>	144:ef7eb2e8f9f7	811	/* Bits 3..0 : Configuration field for RAM block 0. */
<>	144:ef7eb2e8f9f7	812	#define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /!< Position of RAM0 field. /
<>	144:ef7eb2e8f9f7	813	#define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /!< Bit mask of RAM0 field. /
<>	144:ef7eb2e8f9f7	814	#define AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL) /!< Priority 0. /
<>	144:ef7eb2e8f9f7	815	#define AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL) /!< Priority 2. /
<>	144:ef7eb2e8f9f7	816	#define AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL) /!< Priority 4. /
<>	144:ef7eb2e8f9f7	817	#define AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL) /!< Priority 6. /
<>	144:ef7eb2e8f9f7	818	#define AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL) /!< Priority 8. /
<>	144:ef7eb2e8f9f7	819	#define AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL) /!< Priority 10. /
<>	144:ef7eb2e8f9f7	820	#define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /!< Priority 12. /
<>	144:ef7eb2e8f9f7	821	#define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /!< Priority 14. /
<>	144:ef7eb2e8f9f7	822
<>	144:ef7eb2e8f9f7	823
<>	144:ef7eb2e8f9f7	824	/* Peripheral: CCM */
<>	144:ef7eb2e8f9f7	825	/* Description: AES CCM Mode Encryption. */
<>	144:ef7eb2e8f9f7	826
<>	144:ef7eb2e8f9f7	827	/* Register: CCM_SHORTS */
<>	144:ef7eb2e8f9f7	828	/* Description: Shortcuts for the CCM. */
<>	144:ef7eb2e8f9f7	829
<>	144:ef7eb2e8f9f7	830	/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */
<>	144:ef7eb2e8f9f7	831	#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /!< Position of ENDKSGEN_CRYPT field. /
<>	144:ef7eb2e8f9f7	832	#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /!< Bit mask of ENDKSGEN_CRYPT field. /
<>	144:ef7eb2e8f9f7	833	#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /!< Shortcut disabled. /
<>	144:ef7eb2e8f9f7	834	#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /!< Shortcut enabled. /
<>	144:ef7eb2e8f9f7	835
<>	144:ef7eb2e8f9f7	836	/* Register: CCM_INTENSET */
<>	144:ef7eb2e8f9f7	837	/* Description: Interrupt enable set register. */
<>	144:ef7eb2e8f9f7	838
<>	144:ef7eb2e8f9f7	839	/* Bit 2 : Enable interrupt on ERROR event. */
<>	144:ef7eb2e8f9f7	840	#define CCM_INTENSET_ERROR_Pos (2UL) /!< Position of ERROR field. /
<>	144:ef7eb2e8f9f7	841	#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
<>	144:ef7eb2e8f9f7	842	#define CCM_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	843	#define CCM_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	844	#define CCM_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	845
<>	144:ef7eb2e8f9f7	846	/* Bit 1 : Enable interrupt on ENDCRYPT event. */
<>	144:ef7eb2e8f9f7	847	#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /!< Position of ENDCRYPT field. /
<>	144:ef7eb2e8f9f7	848	#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /!< Bit mask of ENDCRYPT field. /
<>	144:ef7eb2e8f9f7	849	#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	850	#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	851	#define CCM_INTENSET_ENDCRYPT_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	852
<>	144:ef7eb2e8f9f7	853	/* Bit 0 : Enable interrupt on ENDKSGEN event. */
<>	144:ef7eb2e8f9f7	854	#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /!< Position of ENDKSGEN field. /
<>	144:ef7eb2e8f9f7	855	#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /!< Bit mask of ENDKSGEN field. /
<>	144:ef7eb2e8f9f7	856	#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	857	#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	858	#define CCM_INTENSET_ENDKSGEN_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	859
<>	144:ef7eb2e8f9f7	860	/* Register: CCM_INTENCLR */
<>	144:ef7eb2e8f9f7	861	/* Description: Interrupt enable clear register. */
<>	144:ef7eb2e8f9f7	862
<>	144:ef7eb2e8f9f7	863	/* Bit 2 : Disable interrupt on ERROR event. */
<>	144:ef7eb2e8f9f7	864	#define CCM_INTENCLR_ERROR_Pos (2UL) /!< Position of ERROR field. /
<>	144:ef7eb2e8f9f7	865	#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
<>	144:ef7eb2e8f9f7	866	#define CCM_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	867	#define CCM_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	868	#define CCM_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	869
<>	144:ef7eb2e8f9f7	870	/* Bit 1 : Disable interrupt on ENDCRYPT event. */
<>	144:ef7eb2e8f9f7	871	#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /!< Position of ENDCRYPT field. /
<>	144:ef7eb2e8f9f7	872	#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /!< Bit mask of ENDCRYPT field. /
<>	144:ef7eb2e8f9f7	873	#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	874	#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	875	#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	876
<>	144:ef7eb2e8f9f7	877	/* Bit 0 : Disable interrupt on ENDKSGEN event. */
<>	144:ef7eb2e8f9f7	878	#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /!< Position of ENDKSGEN field. /
<>	144:ef7eb2e8f9f7	879	#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /!< Bit mask of ENDKSGEN field. /
<>	144:ef7eb2e8f9f7	880	#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	881	#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	882	#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	883
<>	144:ef7eb2e8f9f7	884	/* Register: CCM_MICSTATUS */
<>	144:ef7eb2e8f9f7	885	/* Description: CCM RX MIC check result. */
<>	144:ef7eb2e8f9f7	886
<>	144:ef7eb2e8f9f7	887	/* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */
<>	144:ef7eb2e8f9f7	888	#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /!< Position of MICSTATUS field. /
<>	144:ef7eb2e8f9f7	889	#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /!< Bit mask of MICSTATUS field. /
<>	144:ef7eb2e8f9f7	890	#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /!< MIC check failed. /
<>	144:ef7eb2e8f9f7	891	#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /!< MIC check passed. /
<>	144:ef7eb2e8f9f7	892
<>	144:ef7eb2e8f9f7	893	/* Register: CCM_ENABLE */
<>	144:ef7eb2e8f9f7	894	/* Description: CCM enable. */
<>	144:ef7eb2e8f9f7	895
<>	144:ef7eb2e8f9f7	896	/* Bits 1..0 : CCM enable. */
<>	144:ef7eb2e8f9f7	897	#define CCM_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
<>	144:ef7eb2e8f9f7	898	#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
<>	144:ef7eb2e8f9f7	899	#define CCM_ENABLE_ENABLE_Disabled (0x00UL) /!< CCM is disabled. /
<>	144:ef7eb2e8f9f7	900	#define CCM_ENABLE_ENABLE_Enabled (0x02UL) /!< CCM is enabled. /
<>	144:ef7eb2e8f9f7	901
<>	144:ef7eb2e8f9f7	902	/* Register: CCM_MODE */
<>	144:ef7eb2e8f9f7	903	/* Description: Operation mode. */
<>	144:ef7eb2e8f9f7	904
<>	144:ef7eb2e8f9f7	905	/* Bit 0 : CCM mode operation. */
<>	144:ef7eb2e8f9f7	906	#define CCM_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
<>	144:ef7eb2e8f9f7	907	#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /!< Bit mask of MODE field. /
<>	144:ef7eb2e8f9f7	908	#define CCM_MODE_MODE_Encryption (0UL) /!< CCM mode TX /
<>	144:ef7eb2e8f9f7	909	#define CCM_MODE_MODE_Decryption (1UL) /!< CCM mode TX /
<>	144:ef7eb2e8f9f7	910
<>	144:ef7eb2e8f9f7	911	/* Register: CCM_POWER */
<>	144:ef7eb2e8f9f7	912	/* Description: Peripheral power control. */
<>	144:ef7eb2e8f9f7	913
<>	144:ef7eb2e8f9f7	914	/* Bit 0 : Peripheral power control. */
<>	144:ef7eb2e8f9f7	915	#define CCM_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
<>	144:ef7eb2e8f9f7	916	#define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /!< Bit mask of POWER field. /
<>	144:ef7eb2e8f9f7	917	#define CCM_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
<>	144:ef7eb2e8f9f7	918	#define CCM_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
<>	144:ef7eb2e8f9f7	919
<>	144:ef7eb2e8f9f7	920
<>	144:ef7eb2e8f9f7	921	/* Peripheral: CLOCK */
<>	144:ef7eb2e8f9f7	922	/* Description: Clock control. */
<>	144:ef7eb2e8f9f7	923
<>	144:ef7eb2e8f9f7	924	/* Register: CLOCK_INTENSET */
<>	144:ef7eb2e8f9f7	925	/* Description: Interrupt enable set register. */
<>	144:ef7eb2e8f9f7	926
<>	144:ef7eb2e8f9f7	927	/* Bit 4 : Enable interrupt on CTTO event. */
<>	144:ef7eb2e8f9f7	928	#define CLOCK_INTENSET_CTTO_Pos (4UL) /!< Position of CTTO field. /
<>	144:ef7eb2e8f9f7	929	#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /!< Bit mask of CTTO field. /
<>	144:ef7eb2e8f9f7	930	#define CLOCK_INTENSET_CTTO_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	931	#define CLOCK_INTENSET_CTTO_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	932	#define CLOCK_INTENSET_CTTO_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	933
<>	144:ef7eb2e8f9f7	934	/* Bit 3 : Enable interrupt on DONE event. */
<>	144:ef7eb2e8f9f7	935	#define CLOCK_INTENSET_DONE_Pos (3UL) /!< Position of DONE field. /
<>	144:ef7eb2e8f9f7	936	#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /!< Bit mask of DONE field. /
<>	144:ef7eb2e8f9f7	937	#define CLOCK_INTENSET_DONE_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	938	#define CLOCK_INTENSET_DONE_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	939	#define CLOCK_INTENSET_DONE_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	940
<>	144:ef7eb2e8f9f7	941	/* Bit 1 : Enable interrupt on LFCLKSTARTED event. */
<>	144:ef7eb2e8f9f7	942	#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /!< Position of LFCLKSTARTED field. /
<>	144:ef7eb2e8f9f7	943	#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /!< Bit mask of LFCLKSTARTED field. /
<>	144:ef7eb2e8f9f7	944	#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	945	#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	946	#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	947
<>	144:ef7eb2e8f9f7	948	/* Bit 0 : Enable interrupt on HFCLKSTARTED event. */
<>	144:ef7eb2e8f9f7	949	#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /!< Position of HFCLKSTARTED field. /
<>	144:ef7eb2e8f9f7	950	#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /!< Bit mask of HFCLKSTARTED field. /
<>	144:ef7eb2e8f9f7	951	#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	952	#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	953	#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	954
<>	144:ef7eb2e8f9f7	955	/* Register: CLOCK_INTENCLR */
<>	144:ef7eb2e8f9f7	956	/* Description: Interrupt enable clear register. */
<>	144:ef7eb2e8f9f7	957
<>	144:ef7eb2e8f9f7	958	/* Bit 4 : Disable interrupt on CTTO event. */
<>	144:ef7eb2e8f9f7	959	#define CLOCK_INTENCLR_CTTO_Pos (4UL) /!< Position of CTTO field. /
<>	144:ef7eb2e8f9f7	960	#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /!< Bit mask of CTTO field. /
<>	144:ef7eb2e8f9f7	961	#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	962	#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	963	#define CLOCK_INTENCLR_CTTO_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	964
<>	144:ef7eb2e8f9f7	965	/* Bit 3 : Disable interrupt on DONE event. */
<>	144:ef7eb2e8f9f7	966	#define CLOCK_INTENCLR_DONE_Pos (3UL) /!< Position of DONE field. /
<>	144:ef7eb2e8f9f7	967	#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /!< Bit mask of DONE field. /
<>	144:ef7eb2e8f9f7	968	#define CLOCK_INTENCLR_DONE_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	969	#define CLOCK_INTENCLR_DONE_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	970	#define CLOCK_INTENCLR_DONE_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	971
<>	144:ef7eb2e8f9f7	972	/* Bit 1 : Disable interrupt on LFCLKSTARTED event. */
<>	144:ef7eb2e8f9f7	973	#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /!< Position of LFCLKSTARTED field. /
<>	144:ef7eb2e8f9f7	974	#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /!< Bit mask of LFCLKSTARTED field. /
<>	144:ef7eb2e8f9f7	975	#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	976	#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	977	#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	978
<>	144:ef7eb2e8f9f7	979	/* Bit 0 : Disable interrupt on HFCLKSTARTED event. */
<>	144:ef7eb2e8f9f7	980	#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /!< Position of HFCLKSTARTED field. /
<>	144:ef7eb2e8f9f7	981	#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /!< Bit mask of HFCLKSTARTED field. /
<>	144:ef7eb2e8f9f7	982	#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	983	#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	984	#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	985
<>	144:ef7eb2e8f9f7	986	/* Register: CLOCK_HFCLKRUN */
<>	144:ef7eb2e8f9f7	987	/* Description: Task HFCLKSTART trigger status. */
<>	144:ef7eb2e8f9f7	988
<>	144:ef7eb2e8f9f7	989	/* Bit 0 : Task HFCLKSTART trigger status. */
<>	144:ef7eb2e8f9f7	990	#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /!< Position of STATUS field. /
<>	144:ef7eb2e8f9f7	991	#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /!< Bit mask of STATUS field. /
<>	144:ef7eb2e8f9f7	992	#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /!< Task HFCLKSTART has not been triggered. /
<>	144:ef7eb2e8f9f7	993	#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /!< Task HFCLKSTART has been triggered. /
<>	144:ef7eb2e8f9f7	994
<>	144:ef7eb2e8f9f7	995	/* Register: CLOCK_HFCLKSTAT */
<>	144:ef7eb2e8f9f7	996	/* Description: High frequency clock status. */
<>	144:ef7eb2e8f9f7	997
<>	144:ef7eb2e8f9f7	998	/* Bit 16 : State for the HFCLK. */
<>	144:ef7eb2e8f9f7	999	#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /!< Position of STATE field. /
<>	144:ef7eb2e8f9f7	1000	#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /!< Bit mask of STATE field. /
<>	144:ef7eb2e8f9f7	1001	#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /!< HFCLK clock not running. /
<>	144:ef7eb2e8f9f7	1002	#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /!< HFCLK clock running. /
<>	144:ef7eb2e8f9f7	1003
<>	144:ef7eb2e8f9f7	1004	/* Bit 0 : Active clock source for the HF clock. */
<>	144:ef7eb2e8f9f7	1005	#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /!< Position of SRC field. /
<>	144:ef7eb2e8f9f7	1006	#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /!< Bit mask of SRC field. /
<>	144:ef7eb2e8f9f7	1007	#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /!< Internal 16MHz RC oscillator running and generating the HFCLK clock. /
<>	144:ef7eb2e8f9f7	1008	#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. /
<>	144:ef7eb2e8f9f7	1009
<>	144:ef7eb2e8f9f7	1010	/* Register: CLOCK_LFCLKRUN */
<>	144:ef7eb2e8f9f7	1011	/* Description: Task LFCLKSTART triggered status. */
<>	144:ef7eb2e8f9f7	1012
<>	144:ef7eb2e8f9f7	1013	/* Bit 0 : Task LFCLKSTART triggered status. */
<>	144:ef7eb2e8f9f7	1014	#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /!< Position of STATUS field. /
<>	144:ef7eb2e8f9f7	1015	#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /!< Bit mask of STATUS field. /
<>	144:ef7eb2e8f9f7	1016	#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /!< Task LFCLKSTART has not been triggered. /
<>	144:ef7eb2e8f9f7	1017	#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /!< Task LFCLKSTART has been triggered. /
<>	144:ef7eb2e8f9f7	1018
<>	144:ef7eb2e8f9f7	1019	/* Register: CLOCK_LFCLKSTAT */
<>	144:ef7eb2e8f9f7	1020	/* Description: Low frequency clock status. */
<>	144:ef7eb2e8f9f7	1021
<>	144:ef7eb2e8f9f7	1022	/* Bit 16 : State for the LF clock. */
<>	144:ef7eb2e8f9f7	1023	#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /!< Position of STATE field. /
<>	144:ef7eb2e8f9f7	1024	#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /!< Bit mask of STATE field. /
<>	144:ef7eb2e8f9f7	1025	#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /!< LFCLK clock not running. /
<>	144:ef7eb2e8f9f7	1026	#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /!< LFCLK clock running. /
<>	144:ef7eb2e8f9f7	1027
<>	144:ef7eb2e8f9f7	1028	/* Bits 1..0 : Active clock source for the LF clock. */
<>	144:ef7eb2e8f9f7	1029	#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /!< Position of SRC field. /
<>	144:ef7eb2e8f9f7	1030	#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /!< Bit mask of SRC field. /
<>	144:ef7eb2e8f9f7	1031	#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. /
<>	144:ef7eb2e8f9f7	1032	#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /!< External 32KiHz crystal oscillator running and generating the LFCLK clock. /
<>	144:ef7eb2e8f9f7	1033	#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. /
<>	144:ef7eb2e8f9f7	1034
<>	144:ef7eb2e8f9f7	1035	/* Register: CLOCK_LFCLKSRCCOPY */
<>	144:ef7eb2e8f9f7	1036	/* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
<>	144:ef7eb2e8f9f7	1037
<>	144:ef7eb2e8f9f7	1038	/* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
<>	144:ef7eb2e8f9f7	1039	#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /!< Position of SRC field. /
<>	144:ef7eb2e8f9f7	1040	#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /!< Bit mask of SRC field. /
<>	144:ef7eb2e8f9f7	1041	#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator. /
<>	144:ef7eb2e8f9f7	1042	#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /!< External 32KiHz crystal. /
<>	144:ef7eb2e8f9f7	1043	#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from HFCLK system clock. /
<>	144:ef7eb2e8f9f7	1044
<>	144:ef7eb2e8f9f7	1045	/* Register: CLOCK_LFCLKSRC */
<>	144:ef7eb2e8f9f7	1046	/* Description: Clock source for the LFCLK clock. */
<>	144:ef7eb2e8f9f7	1047
<>	144:ef7eb2e8f9f7	1048	/* Bits 1..0 : Clock source. */
<>	144:ef7eb2e8f9f7	1049	#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /!< Position of SRC field. /
<>	144:ef7eb2e8f9f7	1050	#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /!< Bit mask of SRC field. /
<>	144:ef7eb2e8f9f7	1051	#define CLOCK_LFCLKSRC_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator. /
<>	144:ef7eb2e8f9f7	1052	#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /!< External 32KiHz crystal. /
<>	144:ef7eb2e8f9f7	1053	#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from HFCLK system clock. /
<>	144:ef7eb2e8f9f7	1054
<>	144:ef7eb2e8f9f7	1055	/* Register: CLOCK_CTIV */
<>	144:ef7eb2e8f9f7	1056	/* Description: Calibration timer interval. */
<>	144:ef7eb2e8f9f7	1057
<>	144:ef7eb2e8f9f7	1058	/* Bits 6..0 : Calibration timer interval in 0.25s resolution. */
<>	144:ef7eb2e8f9f7	1059	#define CLOCK_CTIV_CTIV_Pos (0UL) /!< Position of CTIV field. /
<>	144:ef7eb2e8f9f7	1060	#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /!< Bit mask of CTIV field. /
<>	144:ef7eb2e8f9f7	1061
<>	144:ef7eb2e8f9f7	1062	/* Register: CLOCK_XTALFREQ */
<>	144:ef7eb2e8f9f7	1063	/* Description: Crystal frequency. */
<>	144:ef7eb2e8f9f7	1064
<>	144:ef7eb2e8f9f7	1065	/* Bits 7..0 : External Xtal frequency selection. */
<>	144:ef7eb2e8f9f7	1066	#define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /!< Position of XTALFREQ field. /
<>	144:ef7eb2e8f9f7	1067	#define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /!< Bit mask of XTALFREQ field. /
<>	144:ef7eb2e8f9f7	1068	#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /!< 32MHz xtal is used as source for the HFCLK oscillator. /
<>	144:ef7eb2e8f9f7	1069	#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /!< 16MHz xtal is used as source for the HFCLK oscillator. /
<>	144:ef7eb2e8f9f7	1070
<>	144:ef7eb2e8f9f7	1071
<>	144:ef7eb2e8f9f7	1072	/* Peripheral: ECB */
<>	144:ef7eb2e8f9f7	1073	/* Description: AES ECB Mode Encryption. */
<>	144:ef7eb2e8f9f7	1074
<>	144:ef7eb2e8f9f7	1075	/* Register: ECB_INTENSET */
<>	144:ef7eb2e8f9f7	1076	/* Description: Interrupt enable set register. */
<>	144:ef7eb2e8f9f7	1077
<>	144:ef7eb2e8f9f7	1078	/* Bit 1 : Enable interrupt on ERRORECB event. */
<>	144:ef7eb2e8f9f7	1079	#define ECB_INTENSET_ERRORECB_Pos (1UL) /!< Position of ERRORECB field. /
<>	144:ef7eb2e8f9f7	1080	#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /!< Bit mask of ERRORECB field. /
<>	144:ef7eb2e8f9f7	1081	#define ECB_INTENSET_ERRORECB_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	1082	#define ECB_INTENSET_ERRORECB_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	1083	#define ECB_INTENSET_ERRORECB_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	1084
<>	144:ef7eb2e8f9f7	1085	/* Bit 0 : Enable interrupt on ENDECB event. */
<>	144:ef7eb2e8f9f7	1086	#define ECB_INTENSET_ENDECB_Pos (0UL) /!< Position of ENDECB field. /
<>	144:ef7eb2e8f9f7	1087	#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /!< Bit mask of ENDECB field. /
<>	144:ef7eb2e8f9f7	1088	#define ECB_INTENSET_ENDECB_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	1089	#define ECB_INTENSET_ENDECB_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	1090	#define ECB_INTENSET_ENDECB_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	1091
<>	144:ef7eb2e8f9f7	1092	/* Register: ECB_INTENCLR */
<>	144:ef7eb2e8f9f7	1093	/* Description: Interrupt enable clear register. */
<>	144:ef7eb2e8f9f7	1094
<>	144:ef7eb2e8f9f7	1095	/* Bit 1 : Disable interrupt on ERRORECB event. */
<>	144:ef7eb2e8f9f7	1096	#define ECB_INTENCLR_ERRORECB_Pos (1UL) /!< Position of ERRORECB field. /
<>	144:ef7eb2e8f9f7	1097	#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /!< Bit mask of ERRORECB field. /
<>	144:ef7eb2e8f9f7	1098	#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	1099	#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	1100	#define ECB_INTENCLR_ERRORECB_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	1101
<>	144:ef7eb2e8f9f7	1102	/* Bit 0 : Disable interrupt on ENDECB event. */
<>	144:ef7eb2e8f9f7	1103	#define ECB_INTENCLR_ENDECB_Pos (0UL) /!< Position of ENDECB field. /
<>	144:ef7eb2e8f9f7	1104	#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /!< Bit mask of ENDECB field. /
<>	144:ef7eb2e8f9f7	1105	#define ECB_INTENCLR_ENDECB_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	1106	#define ECB_INTENCLR_ENDECB_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	1107	#define ECB_INTENCLR_ENDECB_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	1108
<>	144:ef7eb2e8f9f7	1109	/* Register: ECB_POWER */
<>	144:ef7eb2e8f9f7	1110	/* Description: Peripheral power control. */
<>	144:ef7eb2e8f9f7	1111
<>	144:ef7eb2e8f9f7	1112	/* Bit 0 : Peripheral power control. */
<>	144:ef7eb2e8f9f7	1113	#define ECB_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
<>	144:ef7eb2e8f9f7	1114	#define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /!< Bit mask of POWER field. /
<>	144:ef7eb2e8f9f7	1115	#define ECB_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
<>	144:ef7eb2e8f9f7	1116	#define ECB_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
<>	144:ef7eb2e8f9f7	1117
<>	144:ef7eb2e8f9f7	1118
<>	144:ef7eb2e8f9f7	1119	/* Peripheral: FICR */
<>	144:ef7eb2e8f9f7	1120	/* Description: Factory Information Configuration. */
<>	144:ef7eb2e8f9f7	1121
<>	144:ef7eb2e8f9f7	1122	/* Register: FICR_PPFC */
<>	144:ef7eb2e8f9f7	1123	/* Description: Pre-programmed factory code present. */
<>	144:ef7eb2e8f9f7	1124
<>	144:ef7eb2e8f9f7	1125	/* Bits 7..0 : Pre-programmed factory code present. */
<>	144:ef7eb2e8f9f7	1126	#define FICR_PPFC_PPFC_Pos (0UL) /!< Position of PPFC field. /
<>	144:ef7eb2e8f9f7	1127	#define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /!< Bit mask of PPFC field. /
<>	144:ef7eb2e8f9f7	1128	#define FICR_PPFC_PPFC_Present (0x00UL) /!< Present. /
<>	144:ef7eb2e8f9f7	1129	#define FICR_PPFC_PPFC_NotPresent (0xFFUL) /!< Not present. /
<>	144:ef7eb2e8f9f7	1130
<>	144:ef7eb2e8f9f7	1131	/* Register: FICR_CONFIGID */
<>	144:ef7eb2e8f9f7	1132	/* Description: Configuration identifier. */
<>	144:ef7eb2e8f9f7	1133
<>	144:ef7eb2e8f9f7	1134	/* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */
<>	144:ef7eb2e8f9f7	1135	#define FICR_CONFIGID_FWID_Pos (16UL) /!< Position of FWID field. /
<>	144:ef7eb2e8f9f7	1136	#define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /!< Bit mask of FWID field. /
<>	144:ef7eb2e8f9f7	1137
<>	144:ef7eb2e8f9f7	1138	/* Bits 15..0 : Hardware Identification Number. */
<>	144:ef7eb2e8f9f7	1139	#define FICR_CONFIGID_HWID_Pos (0UL) /!< Position of HWID field. /
<>	144:ef7eb2e8f9f7	1140	#define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /!< Bit mask of HWID field. /
<>	144:ef7eb2e8f9f7	1141
<>	144:ef7eb2e8f9f7	1142	/* Register: FICR_DEVICEADDRTYPE */
<>	144:ef7eb2e8f9f7	1143	/* Description: Device address type. */
<>	144:ef7eb2e8f9f7	1144
<>	144:ef7eb2e8f9f7	1145	/* Bit 0 : Device address type. */
<>	144:ef7eb2e8f9f7	1146	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /!< Position of DEVICEADDRTYPE field. /
<>	144:ef7eb2e8f9f7	1147	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /!< Bit mask of DEVICEADDRTYPE field. /
<>	144:ef7eb2e8f9f7	1148	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /!< Public address. /
<>	144:ef7eb2e8f9f7	1149	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /!< Random address. /
<>	144:ef7eb2e8f9f7	1150
<>	144:ef7eb2e8f9f7	1151	/* Register: FICR_OVERRIDEEN */
<>	144:ef7eb2e8f9f7	1152	/* Description: Radio calibration override enable. */
<>	144:ef7eb2e8f9f7	1153
<>	144:ef7eb2e8f9f7	1154	/* Bit 3 : Override default values for BLE_1Mbit mode. */
<>	144:ef7eb2e8f9f7	1155	#define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /!< Position of BLE_1MBIT field. /
<>	144:ef7eb2e8f9f7	1156	#define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /!< Bit mask of BLE_1MBIT field. /
<>	144:ef7eb2e8f9f7	1157	#define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /!< Override the default values for BLE_1Mbit mode. /
<>	144:ef7eb2e8f9f7	1158	#define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /!< Do not override the default values for BLE_1Mbit mode. /
<>	144:ef7eb2e8f9f7	1159
<>	144:ef7eb2e8f9f7	1160	/* Bit 0 : Override default values for NRF_1Mbit mode. */
<>	144:ef7eb2e8f9f7	1161	#define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /!< Position of NRF_1MBIT field. /
<>	144:ef7eb2e8f9f7	1162	#define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /!< Bit mask of NRF_1MBIT field. /
<>	144:ef7eb2e8f9f7	1163	#define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /!< Override the default values for NRF_1Mbit mode. /
<>	144:ef7eb2e8f9f7	1164	#define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /!< Do not override the default values for NRF_1Mbit mode. /
<>	144:ef7eb2e8f9f7	1165
<>	144:ef7eb2e8f9f7	1166
<>	144:ef7eb2e8f9f7	1167	/* Peripheral: GPIO */
<>	144:ef7eb2e8f9f7	1168	/* Description: General purpose input and output. */
<>	144:ef7eb2e8f9f7	1169
<>	144:ef7eb2e8f9f7	1170	/* Register: GPIO_OUT */
<>	144:ef7eb2e8f9f7	1171	/* Description: Write GPIO port. */
<>	144:ef7eb2e8f9f7	1172
<>	144:ef7eb2e8f9f7	1173	/* Bit 31 : Pin 31. */
<>	144:ef7eb2e8f9f7	1174	#define GPIO_OUT_PIN31_Pos (31UL) /!< Position of PIN31 field. /
<>	144:ef7eb2e8f9f7	1175	#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /!< Bit mask of PIN31 field. /
<>	144:ef7eb2e8f9f7	1176	#define GPIO_OUT_PIN31_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1177	#define GPIO_OUT_PIN31_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1178
<>	144:ef7eb2e8f9f7	1179	/* Bit 30 : Pin 30. */
<>	144:ef7eb2e8f9f7	1180	#define GPIO_OUT_PIN30_Pos (30UL) /!< Position of PIN30 field. /
<>	144:ef7eb2e8f9f7	1181	#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /!< Bit mask of PIN30 field. /
<>	144:ef7eb2e8f9f7	1182	#define GPIO_OUT_PIN30_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1183	#define GPIO_OUT_PIN30_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1184
<>	144:ef7eb2e8f9f7	1185	/* Bit 29 : Pin 29. */
<>	144:ef7eb2e8f9f7	1186	#define GPIO_OUT_PIN29_Pos (29UL) /!< Position of PIN29 field. /
<>	144:ef7eb2e8f9f7	1187	#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /!< Bit mask of PIN29 field. /
<>	144:ef7eb2e8f9f7	1188	#define GPIO_OUT_PIN29_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1189	#define GPIO_OUT_PIN29_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1190
<>	144:ef7eb2e8f9f7	1191	/* Bit 28 : Pin 28. */
<>	144:ef7eb2e8f9f7	1192	#define GPIO_OUT_PIN28_Pos (28UL) /!< Position of PIN28 field. /
<>	144:ef7eb2e8f9f7	1193	#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /!< Bit mask of PIN28 field. /
<>	144:ef7eb2e8f9f7	1194	#define GPIO_OUT_PIN28_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1195	#define GPIO_OUT_PIN28_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1196
<>	144:ef7eb2e8f9f7	1197	/* Bit 27 : Pin 27. */
<>	144:ef7eb2e8f9f7	1198	#define GPIO_OUT_PIN27_Pos (27UL) /!< Position of PIN27 field. /
<>	144:ef7eb2e8f9f7	1199	#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /!< Bit mask of PIN27 field. /
<>	144:ef7eb2e8f9f7	1200	#define GPIO_OUT_PIN27_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1201	#define GPIO_OUT_PIN27_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1202
<>	144:ef7eb2e8f9f7	1203	/* Bit 26 : Pin 26. */
<>	144:ef7eb2e8f9f7	1204	#define GPIO_OUT_PIN26_Pos (26UL) /!< Position of PIN26 field. /
<>	144:ef7eb2e8f9f7	1205	#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /!< Bit mask of PIN26 field. /
<>	144:ef7eb2e8f9f7	1206	#define GPIO_OUT_PIN26_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1207	#define GPIO_OUT_PIN26_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1208
<>	144:ef7eb2e8f9f7	1209	/* Bit 25 : Pin 25. */
<>	144:ef7eb2e8f9f7	1210	#define GPIO_OUT_PIN25_Pos (25UL) /!< Position of PIN25 field. /
<>	144:ef7eb2e8f9f7	1211	#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /!< Bit mask of PIN25 field. /
<>	144:ef7eb2e8f9f7	1212	#define GPIO_OUT_PIN25_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1213	#define GPIO_OUT_PIN25_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1214
<>	144:ef7eb2e8f9f7	1215	/* Bit 24 : Pin 24. */
<>	144:ef7eb2e8f9f7	1216	#define GPIO_OUT_PIN24_Pos (24UL) /!< Position of PIN24 field. /
<>	144:ef7eb2e8f9f7	1217	#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /!< Bit mask of PIN24 field. /
<>	144:ef7eb2e8f9f7	1218	#define GPIO_OUT_PIN24_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1219	#define GPIO_OUT_PIN24_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1220
<>	144:ef7eb2e8f9f7	1221	/* Bit 23 : Pin 23. */
<>	144:ef7eb2e8f9f7	1222	#define GPIO_OUT_PIN23_Pos (23UL) /!< Position of PIN23 field. /
<>	144:ef7eb2e8f9f7	1223	#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /!< Bit mask of PIN23 field. /
<>	144:ef7eb2e8f9f7	1224	#define GPIO_OUT_PIN23_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1225	#define GPIO_OUT_PIN23_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1226
<>	144:ef7eb2e8f9f7	1227	/* Bit 22 : Pin 22. */
<>	144:ef7eb2e8f9f7	1228	#define GPIO_OUT_PIN22_Pos (22UL) /!< Position of PIN22 field. /
<>	144:ef7eb2e8f9f7	1229	#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /!< Bit mask of PIN22 field. /
<>	144:ef7eb2e8f9f7	1230	#define GPIO_OUT_PIN22_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1231	#define GPIO_OUT_PIN22_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1232
<>	144:ef7eb2e8f9f7	1233	/* Bit 21 : Pin 21. */
<>	144:ef7eb2e8f9f7	1234	#define GPIO_OUT_PIN21_Pos (21UL) /!< Position of PIN21 field. /
<>	144:ef7eb2e8f9f7	1235	#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /!< Bit mask of PIN21 field. /
<>	144:ef7eb2e8f9f7	1236	#define GPIO_OUT_PIN21_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1237	#define GPIO_OUT_PIN21_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1238
<>	144:ef7eb2e8f9f7	1239	/* Bit 20 : Pin 20. */
<>	144:ef7eb2e8f9f7	1240	#define GPIO_OUT_PIN20_Pos (20UL) /!< Position of PIN20 field. /
<>	144:ef7eb2e8f9f7	1241	#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /!< Bit mask of PIN20 field. /
<>	144:ef7eb2e8f9f7	1242	#define GPIO_OUT_PIN20_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1243	#define GPIO_OUT_PIN20_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1244
<>	144:ef7eb2e8f9f7	1245	/* Bit 19 : Pin 19. */
<>	144:ef7eb2e8f9f7	1246	#define GPIO_OUT_PIN19_Pos (19UL) /!< Position of PIN19 field. /
<>	144:ef7eb2e8f9f7	1247	#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /!< Bit mask of PIN19 field. /
<>	144:ef7eb2e8f9f7	1248	#define GPIO_OUT_PIN19_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1249	#define GPIO_OUT_PIN19_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1250
<>	144:ef7eb2e8f9f7	1251	/* Bit 18 : Pin 18. */
<>	144:ef7eb2e8f9f7	1252	#define GPIO_OUT_PIN18_Pos (18UL) /!< Position of PIN18 field. /
<>	144:ef7eb2e8f9f7	1253	#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /!< Bit mask of PIN18 field. /
<>	144:ef7eb2e8f9f7	1254	#define GPIO_OUT_PIN18_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1255	#define GPIO_OUT_PIN18_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1256
<>	144:ef7eb2e8f9f7	1257	/* Bit 17 : Pin 17. */
<>	144:ef7eb2e8f9f7	1258	#define GPIO_OUT_PIN17_Pos (17UL) /!< Position of PIN17 field. /
<>	144:ef7eb2e8f9f7	1259	#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /!< Bit mask of PIN17 field. /
<>	144:ef7eb2e8f9f7	1260	#define GPIO_OUT_PIN17_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1261	#define GPIO_OUT_PIN17_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1262
<>	144:ef7eb2e8f9f7	1263	/* Bit 16 : Pin 16. */
<>	144:ef7eb2e8f9f7	1264	#define GPIO_OUT_PIN16_Pos (16UL) /!< Position of PIN16 field. /
<>	144:ef7eb2e8f9f7	1265	#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /!< Bit mask of PIN16 field. /
<>	144:ef7eb2e8f9f7	1266	#define GPIO_OUT_PIN16_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1267	#define GPIO_OUT_PIN16_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1268
<>	144:ef7eb2e8f9f7	1269	/* Bit 15 : Pin 15. */
<>	144:ef7eb2e8f9f7	1270	#define GPIO_OUT_PIN15_Pos (15UL) /!< Position of PIN15 field. /
<>	144:ef7eb2e8f9f7	1271	#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /!< Bit mask of PIN15 field. /
<>	144:ef7eb2e8f9f7	1272	#define GPIO_OUT_PIN15_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1273	#define GPIO_OUT_PIN15_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1274
<>	144:ef7eb2e8f9f7	1275	/* Bit 14 : Pin 14. */
<>	144:ef7eb2e8f9f7	1276	#define GPIO_OUT_PIN14_Pos (14UL) /!< Position of PIN14 field. /
<>	144:ef7eb2e8f9f7	1277	#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /!< Bit mask of PIN14 field. /
<>	144:ef7eb2e8f9f7	1278	#define GPIO_OUT_PIN14_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1279	#define GPIO_OUT_PIN14_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1280
<>	144:ef7eb2e8f9f7	1281	/* Bit 13 : Pin 13. */
<>	144:ef7eb2e8f9f7	1282	#define GPIO_OUT_PIN13_Pos (13UL) /!< Position of PIN13 field. /
<>	144:ef7eb2e8f9f7	1283	#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /!< Bit mask of PIN13 field. /
<>	144:ef7eb2e8f9f7	1284	#define GPIO_OUT_PIN13_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1285	#define GPIO_OUT_PIN13_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1286
<>	144:ef7eb2e8f9f7	1287	/* Bit 12 : Pin 12. */
<>	144:ef7eb2e8f9f7	1288	#define GPIO_OUT_PIN12_Pos (12UL) /!< Position of PIN12 field. /
<>	144:ef7eb2e8f9f7	1289	#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /!< Bit mask of PIN12 field. /
<>	144:ef7eb2e8f9f7	1290	#define GPIO_OUT_PIN12_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1291	#define GPIO_OUT_PIN12_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1292
<>	144:ef7eb2e8f9f7	1293	/* Bit 11 : Pin 11. */
<>	144:ef7eb2e8f9f7	1294	#define GPIO_OUT_PIN11_Pos (11UL) /!< Position of PIN11 field. /
<>	144:ef7eb2e8f9f7	1295	#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /!< Bit mask of PIN11 field. /
<>	144:ef7eb2e8f9f7	1296	#define GPIO_OUT_PIN11_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1297	#define GPIO_OUT_PIN11_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1298
<>	144:ef7eb2e8f9f7	1299	/* Bit 10 : Pin 10. */
<>	144:ef7eb2e8f9f7	1300	#define GPIO_OUT_PIN10_Pos (10UL) /!< Position of PIN10 field. /
<>	144:ef7eb2e8f9f7	1301	#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /!< Bit mask of PIN10 field. /
<>	144:ef7eb2e8f9f7	1302	#define GPIO_OUT_PIN10_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1303	#define GPIO_OUT_PIN10_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1304
<>	144:ef7eb2e8f9f7	1305	/* Bit 9 : Pin 9. */
<>	144:ef7eb2e8f9f7	1306	#define GPIO_OUT_PIN9_Pos (9UL) /!< Position of PIN9 field. /
<>	144:ef7eb2e8f9f7	1307	#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /!< Bit mask of PIN9 field. /
<>	144:ef7eb2e8f9f7	1308	#define GPIO_OUT_PIN9_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1309	#define GPIO_OUT_PIN9_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1310
<>	144:ef7eb2e8f9f7	1311	/* Bit 8 : Pin 8. */
<>	144:ef7eb2e8f9f7	1312	#define GPIO_OUT_PIN8_Pos (8UL) /!< Position of PIN8 field. /
<>	144:ef7eb2e8f9f7	1313	#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /!< Bit mask of PIN8 field. /
<>	144:ef7eb2e8f9f7	1314	#define GPIO_OUT_PIN8_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1315	#define GPIO_OUT_PIN8_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1316
<>	144:ef7eb2e8f9f7	1317	/* Bit 7 : Pin 7. */
<>	144:ef7eb2e8f9f7	1318	#define GPIO_OUT_PIN7_Pos (7UL) /!< Position of PIN7 field. /
<>	144:ef7eb2e8f9f7	1319	#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /!< Bit mask of PIN7 field. /
<>	144:ef7eb2e8f9f7	1320	#define GPIO_OUT_PIN7_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1321	#define GPIO_OUT_PIN7_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1322
<>	144:ef7eb2e8f9f7	1323	/* Bit 6 : Pin 6. */
<>	144:ef7eb2e8f9f7	1324	#define GPIO_OUT_PIN6_Pos (6UL) /!< Position of PIN6 field. /
<>	144:ef7eb2e8f9f7	1325	#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /!< Bit mask of PIN6 field. /
<>	144:ef7eb2e8f9f7	1326	#define GPIO_OUT_PIN6_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1327	#define GPIO_OUT_PIN6_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1328
<>	144:ef7eb2e8f9f7	1329	/* Bit 5 : Pin 5. */
<>	144:ef7eb2e8f9f7	1330	#define GPIO_OUT_PIN5_Pos (5UL) /!< Position of PIN5 field. /
<>	144:ef7eb2e8f9f7	1331	#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /!< Bit mask of PIN5 field. /
<>	144:ef7eb2e8f9f7	1332	#define GPIO_OUT_PIN5_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1333	#define GPIO_OUT_PIN5_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1334
<>	144:ef7eb2e8f9f7	1335	/* Bit 4 : Pin 4. */
<>	144:ef7eb2e8f9f7	1336	#define GPIO_OUT_PIN4_Pos (4UL) /!< Position of PIN4 field. /
<>	144:ef7eb2e8f9f7	1337	#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /!< Bit mask of PIN4 field. /
<>	144:ef7eb2e8f9f7	1338	#define GPIO_OUT_PIN4_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1339	#define GPIO_OUT_PIN4_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1340
<>	144:ef7eb2e8f9f7	1341	/* Bit 3 : Pin 3. */
<>	144:ef7eb2e8f9f7	1342	#define GPIO_OUT_PIN3_Pos (3UL) /!< Position of PIN3 field. /
<>	144:ef7eb2e8f9f7	1343	#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /!< Bit mask of PIN3 field. /
<>	144:ef7eb2e8f9f7	1344	#define GPIO_OUT_PIN3_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1345	#define GPIO_OUT_PIN3_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1346
<>	144:ef7eb2e8f9f7	1347	/* Bit 2 : Pin 2. */
<>	144:ef7eb2e8f9f7	1348	#define GPIO_OUT_PIN2_Pos (2UL) /!< Position of PIN2 field. /
<>	144:ef7eb2e8f9f7	1349	#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /!< Bit mask of PIN2 field. /
<>	144:ef7eb2e8f9f7	1350	#define GPIO_OUT_PIN2_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1351	#define GPIO_OUT_PIN2_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1352
<>	144:ef7eb2e8f9f7	1353	/* Bit 1 : Pin 1. */
<>	144:ef7eb2e8f9f7	1354	#define GPIO_OUT_PIN1_Pos (1UL) /!< Position of PIN1 field. /
<>	144:ef7eb2e8f9f7	1355	#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /!< Bit mask of PIN1 field. /
<>	144:ef7eb2e8f9f7	1356	#define GPIO_OUT_PIN1_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1357	#define GPIO_OUT_PIN1_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1358
<>	144:ef7eb2e8f9f7	1359	/* Bit 0 : Pin 0. */
<>	144:ef7eb2e8f9f7	1360	#define GPIO_OUT_PIN0_Pos (0UL) /!< Position of PIN0 field. /
<>	144:ef7eb2e8f9f7	1361	#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /!< Bit mask of PIN0 field. /
<>	144:ef7eb2e8f9f7	1362	#define GPIO_OUT_PIN0_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1363	#define GPIO_OUT_PIN0_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1364
<>	144:ef7eb2e8f9f7	1365	/* Register: GPIO_OUTSET */
<>	144:ef7eb2e8f9f7	1366	/* Description: Set individual bits in GPIO port. */
<>	144:ef7eb2e8f9f7	1367
<>	144:ef7eb2e8f9f7	1368	/* Bit 31 : Pin 31. */
<>	144:ef7eb2e8f9f7	1369	#define GPIO_OUTSET_PIN31_Pos (31UL) /!< Position of PIN31 field. /
<>	144:ef7eb2e8f9f7	1370	#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /!< Bit mask of PIN31 field. /
<>	144:ef7eb2e8f9f7	1371	#define GPIO_OUTSET_PIN31_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1372	#define GPIO_OUTSET_PIN31_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1373	#define GPIO_OUTSET_PIN31_Set (1UL) /!< Set pin driver high. /
<>	144:ef7eb2e8f9f7	1374
<>	144:ef7eb2e8f9f7	1375	/* Bit 30 : Pin 30. */
<>	144:ef7eb2e8f9f7	1376	#define GPIO_OUTSET_PIN30_Pos (30UL) /!< Position of PIN30 field. /
<>	144:ef7eb2e8f9f7	1377	#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /!< Bit mask of PIN30 field. /
<>	144:ef7eb2e8f9f7	1378	#define GPIO_OUTSET_PIN30_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1379	#define GPIO_OUTSET_PIN30_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1380	#define GPIO_OUTSET_PIN30_Set (1UL) /!< Set pin driver high. /
<>	144:ef7eb2e8f9f7	1381
<>	144:ef7eb2e8f9f7	1382	/* Bit 29 : Pin 29. */
<>	144:ef7eb2e8f9f7	1383	#define GPIO_OUTSET_PIN29_Pos (29UL) /!< Position of PIN29 field. /
<>	144:ef7eb2e8f9f7	1384	#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /!< Bit mask of PIN29 field. /
<>	144:ef7eb2e8f9f7	1385	#define GPIO_OUTSET_PIN29_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1386	#define GPIO_OUTSET_PIN29_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1387	#define GPIO_OUTSET_PIN29_Set (1UL) /!< Set pin driver high. /
<>	144:ef7eb2e8f9f7	1388
<>	144:ef7eb2e8f9f7	1389	/* Bit 28 : Pin 28. */
<>	144:ef7eb2e8f9f7	1390	#define GPIO_OUTSET_PIN28_Pos (28UL) /!< Position of PIN28 field. /
<>	144:ef7eb2e8f9f7	1391	#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /!< Bit mask of PIN28 field. /
<>	144:ef7eb2e8f9f7	1392	#define GPIO_OUTSET_PIN28_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1393	#define GPIO_OUTSET_PIN28_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1394	#define GPIO_OUTSET_PIN28_Set (1UL) /!< Set pin driver high. /
<>	144:ef7eb2e8f9f7	1395
<>	144:ef7eb2e8f9f7	1396	/* Bit 27 : Pin 27. */
<>	144:ef7eb2e8f9f7	1397	#define GPIO_OUTSET_PIN27_Pos (27UL) /!< Position of PIN27 field. /
<>	144:ef7eb2e8f9f7	1398	#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /!< Bit mask of PIN27 field. /
<>	144:ef7eb2e8f9f7	1399	#define GPIO_OUTSET_PIN27_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1400	#define GPIO_OUTSET_PIN27_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1401	#define GPIO_OUTSET_PIN27_Set (1UL) /!< Set pin driver high. /
<>	144:ef7eb2e8f9f7	1402
<>	144:ef7eb2e8f9f7	1403	/* Bit 26 : Pin 26. */
<>	144:ef7eb2e8f9f7	1404	#define GPIO_OUTSET_PIN26_Pos (26UL) /!< Position of PIN26 field. /
<>	144:ef7eb2e8f9f7	1405	#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /!< Bit mask of PIN26 field. /
<>	144:ef7eb2e8f9f7	1406	#define GPIO_OUTSET_PIN26_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1407	#define GPIO_OUTSET_PIN26_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1408	#define GPIO_OUTSET_PIN26_Set (1UL) /!< Set pin driver high. /
<>	144:ef7eb2e8f9f7	1409
<>	144:ef7eb2e8f9f7	1410	/* Bit 25 : Pin 25. */
<>	144:ef7eb2e8f9f7	1411	#define GPIO_OUTSET_PIN25_Pos (25UL) /!< Position of PIN25 field. /
<>	144:ef7eb2e8f9f7	1412	#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /!< Bit mask of PIN25 field. /
<>	144:ef7eb2e8f9f7	1413	#define GPIO_OUTSET_PIN25_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1414	#define GPIO_OUTSET_PIN25_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1415	#define GPIO_OUTSET_PIN25_Set (1UL) /!< Set pin driver high. /
<>	144:ef7eb2e8f9f7	1416
<>	144:ef7eb2e8f9f7	1417	/* Bit 24 : Pin 24. */
<>	144:ef7eb2e8f9f7	1418	#define GPIO_OUTSET_PIN24_Pos (24UL) /!< Position of PIN24 field. /
<>	144:ef7eb2e8f9f7	1419	#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /!< Bit mask of PIN24 field. /
<>	144:ef7eb2e8f9f7	1420	#define GPIO_OUTSET_PIN24_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1421	#define GPIO_OUTSET_PIN24_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1422	#define GPIO_OUTSET_PIN24_Set (1UL) /!< Set pin driver high. /
<>	144:ef7eb2e8f9f7	1423
<>	144:ef7eb2e8f9f7	1424	/* Bit 23 : Pin 23. */
<>	144:ef7eb2e8f9f7	1425	#define GPIO_OUTSET_PIN23_Pos (23UL) /!< Position of PIN23 field. /
<>	144:ef7eb2e8f9f7	1426	#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /!< Bit mask of PIN23 field. /
<>	144:ef7eb2e8f9f7	1427	#define GPIO_OUTSET_PIN23_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1428	#define GPIO_OUTSET_PIN23_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1429	#define GPIO_OUTSET_PIN23_Set (1UL) /!< Set pin driver high. /
<>	144:ef7eb2e8f9f7	1430
<>	144:ef7eb2e8f9f7	1431	/* Bit 22 : Pin 22. */
<>	144:ef7eb2e8f9f7	1432	#define GPIO_OUTSET_PIN22_Pos (22UL) /!< Position of PIN22 field. /
<>	144:ef7eb2e8f9f7	1433	#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /!< Bit mask of PIN22 field. /
<>	144:ef7eb2e8f9f7	1434	#define GPIO_OUTSET_PIN22_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1435	#define GPIO_OUTSET_PIN22_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1436	#define GPIO_OUTSET_PIN22_Set (1UL) /!< Set pin driver high. /
<>	144:ef7eb2e8f9f7	1437
<>	144:ef7eb2e8f9f7	1438	/* Bit 21 : Pin 21. */
<>	144:ef7eb2e8f9f7	1439	#define GPIO_OUTSET_PIN21_Pos (21UL) /!< Position of PIN21 field. /
<>	144:ef7eb2e8f9f7	1440	#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /!< Bit mask of PIN21 field. /
<>	144:ef7eb2e8f9f7	1441	#define GPIO_OUTSET_PIN21_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1442	#define GPIO_OUTSET_PIN21_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1443	#define GPIO_OUTSET_PIN21_Set (1UL) /!< Set pin driver high. /
<>	144:ef7eb2e8f9f7	1444
<>	144:ef7eb2e8f9f7	1445	/* Bit 20 : Pin 20. */
<>	144:ef7eb2e8f9f7	1446	#define GPIO_OUTSET_PIN20_Pos (20UL) /!< Position of PIN20 field. /
<>	144:ef7eb2e8f9f7	1447	#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /!< Bit mask of PIN20 field. /
<>	144:ef7eb2e8f9f7	1448	#define GPIO_OUTSET_PIN20_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1449	#define GPIO_OUTSET_PIN20_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1450	#define GPIO_OUTSET_PIN20_Set (1UL) /!< Set pin driver high. /
<>	144:ef7eb2e8f9f7	1451
<>	144:ef7eb2e8f9f7	1452	/* Bit 19 : Pin 19. */
<>	144:ef7eb2e8f9f7	1453	#define GPIO_OUTSET_PIN19_Pos (19UL) /!< Position of PIN19 field. /
<>	144:ef7eb2e8f9f7	1454	#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /!< Bit mask of PIN19 field. /
<>	144:ef7eb2e8f9f7	1455	#define GPIO_OUTSET_PIN19_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1456	#define GPIO_OUTSET_PIN19_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1457	#define GPIO_OUTSET_PIN19_Set (1UL) /!< Set pin driver high. /
<>	144:ef7eb2e8f9f7	1458
<>	144:ef7eb2e8f9f7	1459	/* Bit 18 : Pin 18. */
<>	144:ef7eb2e8f9f7	1460	#define GPIO_OUTSET_PIN18_Pos (18UL) /!< Position of PIN18 field. /
<>	144:ef7eb2e8f9f7	1461	#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /!< Bit mask of PIN18 field. /
<>	144:ef7eb2e8f9f7	1462	#define GPIO_OUTSET_PIN18_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1463	#define GPIO_OUTSET_PIN18_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1464	#define GPIO_OUTSET_PIN18_Set (1UL) /!< Set pin driver high. /
<>	144:ef7eb2e8f9f7	1465
<>	144:ef7eb2e8f9f7	1466	/* Bit 17 : Pin 17. */
<>	144:ef7eb2e8f9f7	1467	#define GPIO_OUTSET_PIN17_Pos (17UL) /!< Position of PIN17 field. /
<>	144:ef7eb2e8f9f7	1468	#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /!< Bit mask of PIN17 field. /
<>	144:ef7eb2e8f9f7	1469	#define GPIO_OUTSET_PIN17_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1470	#define GPIO_OUTSET_PIN17_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1471	#define GPIO_OUTSET_PIN17_Set (1UL) /!< Set pin driver high. /
<>	144:ef7eb2e8f9f7	1472
<>	144:ef7eb2e8f9f7	1473	/* Bit 16 : Pin 16. */
<>	144:ef7eb2e8f9f7	1474	#define GPIO_OUTSET_PIN16_Pos (16UL) /!< Position of PIN16 field. /
<>	144:ef7eb2e8f9f7	1475	#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /!< Bit mask of PIN16 field. /
<>	144:ef7eb2e8f9f7	1476	#define GPIO_OUTSET_PIN16_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1477	#define GPIO_OUTSET_PIN16_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1478	#define GPIO_OUTSET_PIN16_Set (1UL) /!< Set pin driver high. /
<>	144:ef7eb2e8f9f7	1479
<>	144:ef7eb2e8f9f7	1480	/* Bit 15 : Pin 15. */
<>	144:ef7eb2e8f9f7	1481	#define GPIO_OUTSET_PIN15_Pos (15UL) /!< Position of PIN15 field. /
<>	144:ef7eb2e8f9f7	1482	#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /!< Bit mask of PIN15 field. /
<>	144:ef7eb2e8f9f7	1483	#define GPIO_OUTSET_PIN15_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1484	#define GPIO_OUTSET_PIN15_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1485	#define GPIO_OUTSET_PIN15_Set (1UL) /!< Set pin driver high. /
<>	144:ef7eb2e8f9f7	1486
<>	144:ef7eb2e8f9f7	1487	/* Bit 14 : Pin 14. */
<>	144:ef7eb2e8f9f7	1488	#define GPIO_OUTSET_PIN14_Pos (14UL) /!< Position of PIN14 field. /
<>	144:ef7eb2e8f9f7	1489	#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /!< Bit mask of PIN14 field. /
<>	144:ef7eb2e8f9f7	1490	#define GPIO_OUTSET_PIN14_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1491	#define GPIO_OUTSET_PIN14_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1492	#define GPIO_OUTSET_PIN14_Set (1UL) /!< Set pin driver high. /
<>	144:ef7eb2e8f9f7	1493
<>	144:ef7eb2e8f9f7	1494	/* Bit 13 : Pin 13. */
<>	144:ef7eb2e8f9f7	1495	#define GPIO_OUTSET_PIN13_Pos (13UL) /!< Position of PIN13 field. /
<>	144:ef7eb2e8f9f7	1496	#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /!< Bit mask of PIN13 field. /
<>	144:ef7eb2e8f9f7	1497	#define GPIO_OUTSET_PIN13_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1498	#define GPIO_OUTSET_PIN13_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1499	#define GPIO_OUTSET_PIN13_Set (1UL) /!< Set pin driver high. /
<>	144:ef7eb2e8f9f7	1500
<>	144:ef7eb2e8f9f7	1501	/* Bit 12 : Pin 12. */
<>	144:ef7eb2e8f9f7	1502	#define GPIO_OUTSET_PIN12_Pos (12UL) /!< Position of PIN12 field. /
<>	144:ef7eb2e8f9f7	1503	#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /!< Bit mask of PIN12 field. /
<>	144:ef7eb2e8f9f7	1504	#define GPIO_OUTSET_PIN12_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1505	#define GPIO_OUTSET_PIN12_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1506	#define GPIO_OUTSET_PIN12_Set (1UL) /!< Set pin driver high. /
<>	144:ef7eb2e8f9f7	1507
<>	144:ef7eb2e8f9f7	1508	/* Bit 11 : Pin 11. */
<>	144:ef7eb2e8f9f7	1509	#define GPIO_OUTSET_PIN11_Pos (11UL) /!< Position of PIN11 field. /
<>	144:ef7eb2e8f9f7	1510	#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /!< Bit mask of PIN11 field. /
<>	144:ef7eb2e8f9f7	1511	#define GPIO_OUTSET_PIN11_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1512	#define GPIO_OUTSET_PIN11_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1513	#define GPIO_OUTSET_PIN11_Set (1UL) /!< Set pin driver high. /
<>	144:ef7eb2e8f9f7	1514
<>	144:ef7eb2e8f9f7	1515	/* Bit 10 : Pin 10. */
<>	144:ef7eb2e8f9f7	1516	#define GPIO_OUTSET_PIN10_Pos (10UL) /!< Position of PIN10 field. /
<>	144:ef7eb2e8f9f7	1517	#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /!< Bit mask of PIN10 field. /
<>	144:ef7eb2e8f9f7	1518	#define GPIO_OUTSET_PIN10_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1519	#define GPIO_OUTSET_PIN10_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1520	#define GPIO_OUTSET_PIN10_Set (1UL) /!< Set pin driver high. /
<>	144:ef7eb2e8f9f7	1521
<>	144:ef7eb2e8f9f7	1522	/* Bit 9 : Pin 9. */
<>	144:ef7eb2e8f9f7	1523	#define GPIO_OUTSET_PIN9_Pos (9UL) /!< Position of PIN9 field. /
<>	144:ef7eb2e8f9f7	1524	#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /!< Bit mask of PIN9 field. /
<>	144:ef7eb2e8f9f7	1525	#define GPIO_OUTSET_PIN9_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1526	#define GPIO_OUTSET_PIN9_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1527	#define GPIO_OUTSET_PIN9_Set (1UL) /!< Set pin driver high. /
<>	144:ef7eb2e8f9f7	1528
<>	144:ef7eb2e8f9f7	1529	/* Bit 8 : Pin 8. */
<>	144:ef7eb2e8f9f7	1530	#define GPIO_OUTSET_PIN8_Pos (8UL) /!< Position of PIN8 field. /
<>	144:ef7eb2e8f9f7	1531	#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /!< Bit mask of PIN8 field. /
<>	144:ef7eb2e8f9f7	1532	#define GPIO_OUTSET_PIN8_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1533	#define GPIO_OUTSET_PIN8_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1534	#define GPIO_OUTSET_PIN8_Set (1UL) /!< Set pin driver high. /
<>	144:ef7eb2e8f9f7	1535
<>	144:ef7eb2e8f9f7	1536	/* Bit 7 : Pin 7. */
<>	144:ef7eb2e8f9f7	1537	#define GPIO_OUTSET_PIN7_Pos (7UL) /!< Position of PIN7 field. /
<>	144:ef7eb2e8f9f7	1538	#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /!< Bit mask of PIN7 field. /
<>	144:ef7eb2e8f9f7	1539	#define GPIO_OUTSET_PIN7_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1540	#define GPIO_OUTSET_PIN7_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1541	#define GPIO_OUTSET_PIN7_Set (1UL) /!< Set pin driver high. /
<>	144:ef7eb2e8f9f7	1542
<>	144:ef7eb2e8f9f7	1543	/* Bit 6 : Pin 6. */
<>	144:ef7eb2e8f9f7	1544	#define GPIO_OUTSET_PIN6_Pos (6UL) /!< Position of PIN6 field. /
<>	144:ef7eb2e8f9f7	1545	#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /!< Bit mask of PIN6 field. /
<>	144:ef7eb2e8f9f7	1546	#define GPIO_OUTSET_PIN6_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1547	#define GPIO_OUTSET_PIN6_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1548	#define GPIO_OUTSET_PIN6_Set (1UL) /!< Set pin driver high. /
<>	144:ef7eb2e8f9f7	1549
<>	144:ef7eb2e8f9f7	1550	/* Bit 5 : Pin 5. */
<>	144:ef7eb2e8f9f7	1551	#define GPIO_OUTSET_PIN5_Pos (5UL) /!< Position of PIN5 field. /
<>	144:ef7eb2e8f9f7	1552	#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /!< Bit mask of PIN5 field. /
<>	144:ef7eb2e8f9f7	1553	#define GPIO_OUTSET_PIN5_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1554	#define GPIO_OUTSET_PIN5_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1555	#define GPIO_OUTSET_PIN5_Set (1UL) /!< Set pin driver high. /
<>	144:ef7eb2e8f9f7	1556
<>	144:ef7eb2e8f9f7	1557	/* Bit 4 : Pin 4. */
<>	144:ef7eb2e8f9f7	1558	#define GPIO_OUTSET_PIN4_Pos (4UL) /!< Position of PIN4 field. /
<>	144:ef7eb2e8f9f7	1559	#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /!< Bit mask of PIN4 field. /
<>	144:ef7eb2e8f9f7	1560	#define GPIO_OUTSET_PIN4_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1561	#define GPIO_OUTSET_PIN4_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1562	#define GPIO_OUTSET_PIN4_Set (1UL) /!< Set pin driver high. /
<>	144:ef7eb2e8f9f7	1563
<>	144:ef7eb2e8f9f7	1564	/* Bit 3 : Pin 3. */
<>	144:ef7eb2e8f9f7	1565	#define GPIO_OUTSET_PIN3_Pos (3UL) /!< Position of PIN3 field. /
<>	144:ef7eb2e8f9f7	1566	#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /!< Bit mask of PIN3 field. /
<>	144:ef7eb2e8f9f7	1567	#define GPIO_OUTSET_PIN3_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1568	#define GPIO_OUTSET_PIN3_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1569	#define GPIO_OUTSET_PIN3_Set (1UL) /!< Set pin driver high. /
<>	144:ef7eb2e8f9f7	1570
<>	144:ef7eb2e8f9f7	1571	/* Bit 2 : Pin 2. */
<>	144:ef7eb2e8f9f7	1572	#define GPIO_OUTSET_PIN2_Pos (2UL) /!< Position of PIN2 field. /
<>	144:ef7eb2e8f9f7	1573	#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /!< Bit mask of PIN2 field. /
<>	144:ef7eb2e8f9f7	1574	#define GPIO_OUTSET_PIN2_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1575	#define GPIO_OUTSET_PIN2_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1576	#define GPIO_OUTSET_PIN2_Set (1UL) /!< Set pin driver high. /
<>	144:ef7eb2e8f9f7	1577
<>	144:ef7eb2e8f9f7	1578	/* Bit 1 : Pin 1. */
<>	144:ef7eb2e8f9f7	1579	#define GPIO_OUTSET_PIN1_Pos (1UL) /!< Position of PIN1 field. /
<>	144:ef7eb2e8f9f7	1580	#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /!< Bit mask of PIN1 field. /
<>	144:ef7eb2e8f9f7	1581	#define GPIO_OUTSET_PIN1_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1582	#define GPIO_OUTSET_PIN1_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1583	#define GPIO_OUTSET_PIN1_Set (1UL) /!< Set pin driver high. /
<>	144:ef7eb2e8f9f7	1584
<>	144:ef7eb2e8f9f7	1585	/* Bit 0 : Pin 0. */
<>	144:ef7eb2e8f9f7	1586	#define GPIO_OUTSET_PIN0_Pos (0UL) /!< Position of PIN0 field. /
<>	144:ef7eb2e8f9f7	1587	#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /!< Bit mask of PIN0 field. /
<>	144:ef7eb2e8f9f7	1588	#define GPIO_OUTSET_PIN0_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1589	#define GPIO_OUTSET_PIN0_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1590	#define GPIO_OUTSET_PIN0_Set (1UL) /!< Set pin driver high. /
<>	144:ef7eb2e8f9f7	1591
<>	144:ef7eb2e8f9f7	1592	/* Register: GPIO_OUTCLR */
<>	144:ef7eb2e8f9f7	1593	/* Description: Clear individual bits in GPIO port. */
<>	144:ef7eb2e8f9f7	1594
<>	144:ef7eb2e8f9f7	1595	/* Bit 31 : Pin 31. */
<>	144:ef7eb2e8f9f7	1596	#define GPIO_OUTCLR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
<>	144:ef7eb2e8f9f7	1597	#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /!< Bit mask of PIN31 field. /
<>	144:ef7eb2e8f9f7	1598	#define GPIO_OUTCLR_PIN31_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1599	#define GPIO_OUTCLR_PIN31_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1600	#define GPIO_OUTCLR_PIN31_Clear (1UL) /!< Set pin driver low. /
<>	144:ef7eb2e8f9f7	1601
<>	144:ef7eb2e8f9f7	1602	/* Bit 30 : Pin 30. */
<>	144:ef7eb2e8f9f7	1603	#define GPIO_OUTCLR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
<>	144:ef7eb2e8f9f7	1604	#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /!< Bit mask of PIN30 field. /
<>	144:ef7eb2e8f9f7	1605	#define GPIO_OUTCLR_PIN30_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1606	#define GPIO_OUTCLR_PIN30_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1607	#define GPIO_OUTCLR_PIN30_Clear (1UL) /!< Set pin driver low. /
<>	144:ef7eb2e8f9f7	1608
<>	144:ef7eb2e8f9f7	1609	/* Bit 29 : Pin 29. */
<>	144:ef7eb2e8f9f7	1610	#define GPIO_OUTCLR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
<>	144:ef7eb2e8f9f7	1611	#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /!< Bit mask of PIN29 field. /
<>	144:ef7eb2e8f9f7	1612	#define GPIO_OUTCLR_PIN29_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1613	#define GPIO_OUTCLR_PIN29_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1614	#define GPIO_OUTCLR_PIN29_Clear (1UL) /!< Set pin driver low. /
<>	144:ef7eb2e8f9f7	1615
<>	144:ef7eb2e8f9f7	1616	/* Bit 28 : Pin 28. */
<>	144:ef7eb2e8f9f7	1617	#define GPIO_OUTCLR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
<>	144:ef7eb2e8f9f7	1618	#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /!< Bit mask of PIN28 field. /
<>	144:ef7eb2e8f9f7	1619	#define GPIO_OUTCLR_PIN28_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1620	#define GPIO_OUTCLR_PIN28_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1621	#define GPIO_OUTCLR_PIN28_Clear (1UL) /!< Set pin driver low. /
<>	144:ef7eb2e8f9f7	1622
<>	144:ef7eb2e8f9f7	1623	/* Bit 27 : Pin 27. */
<>	144:ef7eb2e8f9f7	1624	#define GPIO_OUTCLR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
<>	144:ef7eb2e8f9f7	1625	#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /!< Bit mask of PIN27 field. /
<>	144:ef7eb2e8f9f7	1626	#define GPIO_OUTCLR_PIN27_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1627	#define GPIO_OUTCLR_PIN27_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1628	#define GPIO_OUTCLR_PIN27_Clear (1UL) /!< Set pin driver low. /
<>	144:ef7eb2e8f9f7	1629
<>	144:ef7eb2e8f9f7	1630	/* Bit 26 : Pin 26. */
<>	144:ef7eb2e8f9f7	1631	#define GPIO_OUTCLR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
<>	144:ef7eb2e8f9f7	1632	#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /!< Bit mask of PIN26 field. /
<>	144:ef7eb2e8f9f7	1633	#define GPIO_OUTCLR_PIN26_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1634	#define GPIO_OUTCLR_PIN26_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1635	#define GPIO_OUTCLR_PIN26_Clear (1UL) /!< Set pin driver low. /
<>	144:ef7eb2e8f9f7	1636
<>	144:ef7eb2e8f9f7	1637	/* Bit 25 : Pin 25. */
<>	144:ef7eb2e8f9f7	1638	#define GPIO_OUTCLR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
<>	144:ef7eb2e8f9f7	1639	#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /!< Bit mask of PIN25 field. /
<>	144:ef7eb2e8f9f7	1640	#define GPIO_OUTCLR_PIN25_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1641	#define GPIO_OUTCLR_PIN25_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1642	#define GPIO_OUTCLR_PIN25_Clear (1UL) /!< Set pin driver low. /
<>	144:ef7eb2e8f9f7	1643
<>	144:ef7eb2e8f9f7	1644	/* Bit 24 : Pin 24. */
<>	144:ef7eb2e8f9f7	1645	#define GPIO_OUTCLR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
<>	144:ef7eb2e8f9f7	1646	#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /!< Bit mask of PIN24 field. /
<>	144:ef7eb2e8f9f7	1647	#define GPIO_OUTCLR_PIN24_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1648	#define GPIO_OUTCLR_PIN24_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1649	#define GPIO_OUTCLR_PIN24_Clear (1UL) /!< Set pin driver low. /
<>	144:ef7eb2e8f9f7	1650
<>	144:ef7eb2e8f9f7	1651	/* Bit 23 : Pin 23. */
<>	144:ef7eb2e8f9f7	1652	#define GPIO_OUTCLR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
<>	144:ef7eb2e8f9f7	1653	#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /!< Bit mask of PIN23 field. /
<>	144:ef7eb2e8f9f7	1654	#define GPIO_OUTCLR_PIN23_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1655	#define GPIO_OUTCLR_PIN23_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1656	#define GPIO_OUTCLR_PIN23_Clear (1UL) /!< Set pin driver low. /
<>	144:ef7eb2e8f9f7	1657
<>	144:ef7eb2e8f9f7	1658	/* Bit 22 : Pin 22. */
<>	144:ef7eb2e8f9f7	1659	#define GPIO_OUTCLR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
<>	144:ef7eb2e8f9f7	1660	#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /!< Bit mask of PIN22 field. /
<>	144:ef7eb2e8f9f7	1661	#define GPIO_OUTCLR_PIN22_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1662	#define GPIO_OUTCLR_PIN22_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1663	#define GPIO_OUTCLR_PIN22_Clear (1UL) /!< Set pin driver low. /
<>	144:ef7eb2e8f9f7	1664
<>	144:ef7eb2e8f9f7	1665	/* Bit 21 : Pin 21. */
<>	144:ef7eb2e8f9f7	1666	#define GPIO_OUTCLR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
<>	144:ef7eb2e8f9f7	1667	#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /!< Bit mask of PIN21 field. /
<>	144:ef7eb2e8f9f7	1668	#define GPIO_OUTCLR_PIN21_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1669	#define GPIO_OUTCLR_PIN21_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1670	#define GPIO_OUTCLR_PIN21_Clear (1UL) /!< Set pin driver low. /
<>	144:ef7eb2e8f9f7	1671
<>	144:ef7eb2e8f9f7	1672	/* Bit 20 : Pin 20. */
<>	144:ef7eb2e8f9f7	1673	#define GPIO_OUTCLR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
<>	144:ef7eb2e8f9f7	1674	#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /!< Bit mask of PIN20 field. /
<>	144:ef7eb2e8f9f7	1675	#define GPIO_OUTCLR_PIN20_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1676	#define GPIO_OUTCLR_PIN20_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1677	#define GPIO_OUTCLR_PIN20_Clear (1UL) /!< Set pin driver low. /
<>	144:ef7eb2e8f9f7	1678
<>	144:ef7eb2e8f9f7	1679	/* Bit 19 : Pin 19. */
<>	144:ef7eb2e8f9f7	1680	#define GPIO_OUTCLR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
<>	144:ef7eb2e8f9f7	1681	#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /!< Bit mask of PIN19 field. /
<>	144:ef7eb2e8f9f7	1682	#define GPIO_OUTCLR_PIN19_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1683	#define GPIO_OUTCLR_PIN19_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1684	#define GPIO_OUTCLR_PIN19_Clear (1UL) /!< Set pin driver low. /
<>	144:ef7eb2e8f9f7	1685
<>	144:ef7eb2e8f9f7	1686	/* Bit 18 : Pin 18. */
<>	144:ef7eb2e8f9f7	1687	#define GPIO_OUTCLR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
<>	144:ef7eb2e8f9f7	1688	#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /!< Bit mask of PIN18 field. /
<>	144:ef7eb2e8f9f7	1689	#define GPIO_OUTCLR_PIN18_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1690	#define GPIO_OUTCLR_PIN18_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1691	#define GPIO_OUTCLR_PIN18_Clear (1UL) /!< Set pin driver low. /
<>	144:ef7eb2e8f9f7	1692
<>	144:ef7eb2e8f9f7	1693	/* Bit 17 : Pin 17. */
<>	144:ef7eb2e8f9f7	1694	#define GPIO_OUTCLR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
<>	144:ef7eb2e8f9f7	1695	#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /!< Bit mask of PIN17 field. /
<>	144:ef7eb2e8f9f7	1696	#define GPIO_OUTCLR_PIN17_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1697	#define GPIO_OUTCLR_PIN17_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1698	#define GPIO_OUTCLR_PIN17_Clear (1UL) /!< Set pin driver low. /
<>	144:ef7eb2e8f9f7	1699
<>	144:ef7eb2e8f9f7	1700	/* Bit 16 : Pin 16. */
<>	144:ef7eb2e8f9f7	1701	#define GPIO_OUTCLR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
<>	144:ef7eb2e8f9f7	1702	#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /!< Bit mask of PIN16 field. /
<>	144:ef7eb2e8f9f7	1703	#define GPIO_OUTCLR_PIN16_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1704	#define GPIO_OUTCLR_PIN16_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1705	#define GPIO_OUTCLR_PIN16_Clear (1UL) /!< Set pin driver low. /
<>	144:ef7eb2e8f9f7	1706
<>	144:ef7eb2e8f9f7	1707	/* Bit 15 : Pin 15. */
<>	144:ef7eb2e8f9f7	1708	#define GPIO_OUTCLR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
<>	144:ef7eb2e8f9f7	1709	#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /!< Bit mask of PIN15 field. /
<>	144:ef7eb2e8f9f7	1710	#define GPIO_OUTCLR_PIN15_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1711	#define GPIO_OUTCLR_PIN15_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1712	#define GPIO_OUTCLR_PIN15_Clear (1UL) /!< Set pin driver low. /
<>	144:ef7eb2e8f9f7	1713
<>	144:ef7eb2e8f9f7	1714	/* Bit 14 : Pin 14. */
<>	144:ef7eb2e8f9f7	1715	#define GPIO_OUTCLR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
<>	144:ef7eb2e8f9f7	1716	#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /!< Bit mask of PIN14 field. /
<>	144:ef7eb2e8f9f7	1717	#define GPIO_OUTCLR_PIN14_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1718	#define GPIO_OUTCLR_PIN14_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1719	#define GPIO_OUTCLR_PIN14_Clear (1UL) /!< Set pin driver low. /
<>	144:ef7eb2e8f9f7	1720
<>	144:ef7eb2e8f9f7	1721	/* Bit 13 : Pin 13. */
<>	144:ef7eb2e8f9f7	1722	#define GPIO_OUTCLR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
<>	144:ef7eb2e8f9f7	1723	#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /!< Bit mask of PIN13 field. /
<>	144:ef7eb2e8f9f7	1724	#define GPIO_OUTCLR_PIN13_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1725	#define GPIO_OUTCLR_PIN13_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1726	#define GPIO_OUTCLR_PIN13_Clear (1UL) /!< Set pin driver low. /
<>	144:ef7eb2e8f9f7	1727
<>	144:ef7eb2e8f9f7	1728	/* Bit 12 : Pin 12. */
<>	144:ef7eb2e8f9f7	1729	#define GPIO_OUTCLR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
<>	144:ef7eb2e8f9f7	1730	#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /!< Bit mask of PIN12 field. /
<>	144:ef7eb2e8f9f7	1731	#define GPIO_OUTCLR_PIN12_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1732	#define GPIO_OUTCLR_PIN12_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1733	#define GPIO_OUTCLR_PIN12_Clear (1UL) /!< Set pin driver low. /
<>	144:ef7eb2e8f9f7	1734
<>	144:ef7eb2e8f9f7	1735	/* Bit 11 : Pin 11. */
<>	144:ef7eb2e8f9f7	1736	#define GPIO_OUTCLR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
<>	144:ef7eb2e8f9f7	1737	#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /!< Bit mask of PIN11 field. /
<>	144:ef7eb2e8f9f7	1738	#define GPIO_OUTCLR_PIN11_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1739	#define GPIO_OUTCLR_PIN11_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1740	#define GPIO_OUTCLR_PIN11_Clear (1UL) /!< Set pin driver low. /
<>	144:ef7eb2e8f9f7	1741
<>	144:ef7eb2e8f9f7	1742	/* Bit 10 : Pin 10. */
<>	144:ef7eb2e8f9f7	1743	#define GPIO_OUTCLR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
<>	144:ef7eb2e8f9f7	1744	#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /!< Bit mask of PIN10 field. /
<>	144:ef7eb2e8f9f7	1745	#define GPIO_OUTCLR_PIN10_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1746	#define GPIO_OUTCLR_PIN10_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1747	#define GPIO_OUTCLR_PIN10_Clear (1UL) /!< Set pin driver low. /
<>	144:ef7eb2e8f9f7	1748
<>	144:ef7eb2e8f9f7	1749	/* Bit 9 : Pin 9. */
<>	144:ef7eb2e8f9f7	1750	#define GPIO_OUTCLR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
<>	144:ef7eb2e8f9f7	1751	#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /!< Bit mask of PIN9 field. /
<>	144:ef7eb2e8f9f7	1752	#define GPIO_OUTCLR_PIN9_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1753	#define GPIO_OUTCLR_PIN9_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1754	#define GPIO_OUTCLR_PIN9_Clear (1UL) /!< Set pin driver low. /
<>	144:ef7eb2e8f9f7	1755
<>	144:ef7eb2e8f9f7	1756	/* Bit 8 : Pin 8. */
<>	144:ef7eb2e8f9f7	1757	#define GPIO_OUTCLR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
<>	144:ef7eb2e8f9f7	1758	#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /!< Bit mask of PIN8 field. /
<>	144:ef7eb2e8f9f7	1759	#define GPIO_OUTCLR_PIN8_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1760	#define GPIO_OUTCLR_PIN8_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1761	#define GPIO_OUTCLR_PIN8_Clear (1UL) /!< Set pin driver low. /
<>	144:ef7eb2e8f9f7	1762
<>	144:ef7eb2e8f9f7	1763	/* Bit 7 : Pin 7. */
<>	144:ef7eb2e8f9f7	1764	#define GPIO_OUTCLR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
<>	144:ef7eb2e8f9f7	1765	#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /!< Bit mask of PIN7 field. /
<>	144:ef7eb2e8f9f7	1766	#define GPIO_OUTCLR_PIN7_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1767	#define GPIO_OUTCLR_PIN7_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1768	#define GPIO_OUTCLR_PIN7_Clear (1UL) /!< Set pin driver low. /
<>	144:ef7eb2e8f9f7	1769
<>	144:ef7eb2e8f9f7	1770	/* Bit 6 : Pin 6. */
<>	144:ef7eb2e8f9f7	1771	#define GPIO_OUTCLR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
<>	144:ef7eb2e8f9f7	1772	#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /!< Bit mask of PIN6 field. /
<>	144:ef7eb2e8f9f7	1773	#define GPIO_OUTCLR_PIN6_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1774	#define GPIO_OUTCLR_PIN6_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1775	#define GPIO_OUTCLR_PIN6_Clear (1UL) /!< Set pin driver low. /
<>	144:ef7eb2e8f9f7	1776
<>	144:ef7eb2e8f9f7	1777	/* Bit 5 : Pin 5. */
<>	144:ef7eb2e8f9f7	1778	#define GPIO_OUTCLR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
<>	144:ef7eb2e8f9f7	1779	#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /!< Bit mask of PIN5 field. /
<>	144:ef7eb2e8f9f7	1780	#define GPIO_OUTCLR_PIN5_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1781	#define GPIO_OUTCLR_PIN5_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1782	#define GPIO_OUTCLR_PIN5_Clear (1UL) /!< Set pin driver low. /
<>	144:ef7eb2e8f9f7	1783
<>	144:ef7eb2e8f9f7	1784	/* Bit 4 : Pin 4. */
<>	144:ef7eb2e8f9f7	1785	#define GPIO_OUTCLR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
<>	144:ef7eb2e8f9f7	1786	#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /!< Bit mask of PIN4 field. /
<>	144:ef7eb2e8f9f7	1787	#define GPIO_OUTCLR_PIN4_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1788	#define GPIO_OUTCLR_PIN4_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1789	#define GPIO_OUTCLR_PIN4_Clear (1UL) /!< Set pin driver low. /
<>	144:ef7eb2e8f9f7	1790
<>	144:ef7eb2e8f9f7	1791	/* Bit 3 : Pin 3. */
<>	144:ef7eb2e8f9f7	1792	#define GPIO_OUTCLR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
<>	144:ef7eb2e8f9f7	1793	#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /!< Bit mask of PIN3 field. /
<>	144:ef7eb2e8f9f7	1794	#define GPIO_OUTCLR_PIN3_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1795	#define GPIO_OUTCLR_PIN3_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1796	#define GPIO_OUTCLR_PIN3_Clear (1UL) /!< Set pin driver low. /
<>	144:ef7eb2e8f9f7	1797
<>	144:ef7eb2e8f9f7	1798	/* Bit 2 : Pin 2. */
<>	144:ef7eb2e8f9f7	1799	#define GPIO_OUTCLR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
<>	144:ef7eb2e8f9f7	1800	#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /!< Bit mask of PIN2 field. /
<>	144:ef7eb2e8f9f7	1801	#define GPIO_OUTCLR_PIN2_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1802	#define GPIO_OUTCLR_PIN2_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1803	#define GPIO_OUTCLR_PIN2_Clear (1UL) /!< Set pin driver low. /
<>	144:ef7eb2e8f9f7	1804
<>	144:ef7eb2e8f9f7	1805	/* Bit 1 : Pin 1. */
<>	144:ef7eb2e8f9f7	1806	#define GPIO_OUTCLR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
<>	144:ef7eb2e8f9f7	1807	#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /!< Bit mask of PIN1 field. /
<>	144:ef7eb2e8f9f7	1808	#define GPIO_OUTCLR_PIN1_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1809	#define GPIO_OUTCLR_PIN1_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1810	#define GPIO_OUTCLR_PIN1_Clear (1UL) /!< Set pin driver low. /
<>	144:ef7eb2e8f9f7	1811
<>	144:ef7eb2e8f9f7	1812	/* Bit 0 : Pin 0. */
<>	144:ef7eb2e8f9f7	1813	#define GPIO_OUTCLR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
<>	144:ef7eb2e8f9f7	1814	#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /!< Bit mask of PIN0 field. /
<>	144:ef7eb2e8f9f7	1815	#define GPIO_OUTCLR_PIN0_Low (0UL) /!< Pin driver is low. /
<>	144:ef7eb2e8f9f7	1816	#define GPIO_OUTCLR_PIN0_High (1UL) /!< Pin driver is high. /
<>	144:ef7eb2e8f9f7	1817	#define GPIO_OUTCLR_PIN0_Clear (1UL) /!< Set pin driver low. /
<>	144:ef7eb2e8f9f7	1818
<>	144:ef7eb2e8f9f7	1819	/* Register: GPIO_IN */
<>	144:ef7eb2e8f9f7	1820	/* Description: Read GPIO port. */
<>	144:ef7eb2e8f9f7	1821
<>	144:ef7eb2e8f9f7	1822	/* Bit 31 : Pin 31. */
<>	144:ef7eb2e8f9f7	1823	#define GPIO_IN_PIN31_Pos (31UL) /!< Position of PIN31 field. /
<>	144:ef7eb2e8f9f7	1824	#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /!< Bit mask of PIN31 field. /
<>	144:ef7eb2e8f9f7	1825	#define GPIO_IN_PIN31_Low (0UL) /!< Pin input is low. /
<>	144:ef7eb2e8f9f7	1826	#define GPIO_IN_PIN31_High (1UL) /!< Pin input is high. /
<>	144:ef7eb2e8f9f7	1827
<>	144:ef7eb2e8f9f7	1828	/* Bit 30 : Pin 30. */
<>	144:ef7eb2e8f9f7	1829	#define GPIO_IN_PIN30_Pos (30UL) /!< Position of PIN30 field. /
<>	144:ef7eb2e8f9f7	1830	#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /!< Bit mask of PIN30 field. /
<>	144:ef7eb2e8f9f7	1831	#define GPIO_IN_PIN30_Low (0UL) /!< Pin input is low. /
<>	144:ef7eb2e8f9f7	1832	#define GPIO_IN_PIN30_High (1UL) /!< Pin input is high. /
<>	144:ef7eb2e8f9f7	1833
<>	144:ef7eb2e8f9f7	1834	/* Bit 29 : Pin 29. */
<>	144:ef7eb2e8f9f7	1835	#define GPIO_IN_PIN29_Pos (29UL) /!< Position of PIN29 field. /
<>	144:ef7eb2e8f9f7	1836	#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /!< Bit mask of PIN29 field. /
<>	144:ef7eb2e8f9f7	1837	#define GPIO_IN_PIN29_Low (0UL) /!< Pin input is low. /
<>	144:ef7eb2e8f9f7	1838	#define GPIO_IN_PIN29_High (1UL) /!< Pin input is high. /
<>	144:ef7eb2e8f9f7	1839
<>	144:ef7eb2e8f9f7	1840	/* Bit 28 : Pin 28. */
<>	144:ef7eb2e8f9f7	1841	#define GPIO_IN_PIN28_Pos (28UL) /!< Position of PIN28 field. /
<>	144:ef7eb2e8f9f7	1842	#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /!< Bit mask of PIN28 field. /
<>	144:ef7eb2e8f9f7	1843	#define GPIO_IN_PIN28_Low (0UL) /!< Pin input is low. /
<>	144:ef7eb2e8f9f7	1844	#define GPIO_IN_PIN28_High (1UL) /!< Pin input is high. /
<>	144:ef7eb2e8f9f7	1845
<>	144:ef7eb2e8f9f7	1846	/* Bit 27 : Pin 27. */
<>	144:ef7eb2e8f9f7	1847	#define GPIO_IN_PIN27_Pos (27UL) /!< Position of PIN27 field. /
<>	144:ef7eb2e8f9f7	1848	#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /!< Bit mask of PIN27 field. /
<>	144:ef7eb2e8f9f7	1849	#define GPIO_IN_PIN27_Low (0UL) /!< Pin input is low. /
<>	144:ef7eb2e8f9f7	1850	#define GPIO_IN_PIN27_High (1UL) /!< Pin input is high. /
<>	144:ef7eb2e8f9f7	1851
<>	144:ef7eb2e8f9f7	1852	/* Bit 26 : Pin 26. */
<>	144:ef7eb2e8f9f7	1853	#define GPIO_IN_PIN26_Pos (26UL) /!< Position of PIN26 field. /
<>	144:ef7eb2e8f9f7	1854	#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /!< Bit mask of PIN26 field. /
<>	144:ef7eb2e8f9f7	1855	#define GPIO_IN_PIN26_Low (0UL) /!< Pin input is low. /
<>	144:ef7eb2e8f9f7	1856	#define GPIO_IN_PIN26_High (1UL) /!< Pin input is high. /
<>	144:ef7eb2e8f9f7	1857
<>	144:ef7eb2e8f9f7	1858	/* Bit 25 : Pin 25. */
<>	144:ef7eb2e8f9f7	1859	#define GPIO_IN_PIN25_Pos (25UL) /!< Position of PIN25 field. /
<>	144:ef7eb2e8f9f7	1860	#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /!< Bit mask of PIN25 field. /
<>	144:ef7eb2e8f9f7	1861	#define GPIO_IN_PIN25_Low (0UL) /!< Pin input is low. /
<>	144:ef7eb2e8f9f7	1862	#define GPIO_IN_PIN25_High (1UL) /!< Pin input is high. /
<>	144:ef7eb2e8f9f7	1863
<>	144:ef7eb2e8f9f7	1864	/* Bit 24 : Pin 24. */
<>	144:ef7eb2e8f9f7	1865	#define GPIO_IN_PIN24_Pos (24UL) /!< Position of PIN24 field. /
<>	144:ef7eb2e8f9f7	1866	#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /!< Bit mask of PIN24 field. /
<>	144:ef7eb2e8f9f7	1867	#define GPIO_IN_PIN24_Low (0UL) /!< Pin input is low. /
<>	144:ef7eb2e8f9f7	1868	#define GPIO_IN_PIN24_High (1UL) /!< Pin input is high. /
<>	144:ef7eb2e8f9f7	1869
<>	144:ef7eb2e8f9f7	1870	/* Bit 23 : Pin 23. */
<>	144:ef7eb2e8f9f7	1871	#define GPIO_IN_PIN23_Pos (23UL) /!< Position of PIN23 field. /
<>	144:ef7eb2e8f9f7	1872	#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /!< Bit mask of PIN23 field. /
<>	144:ef7eb2e8f9f7	1873	#define GPIO_IN_PIN23_Low (0UL) /!< Pin input is low. /
<>	144:ef7eb2e8f9f7	1874	#define GPIO_IN_PIN23_High (1UL) /!< Pin input is high. /
<>	144:ef7eb2e8f9f7	1875
<>	144:ef7eb2e8f9f7	1876	/* Bit 22 : Pin 22. */
<>	144:ef7eb2e8f9f7	1877	#define GPIO_IN_PIN22_Pos (22UL) /!< Position of PIN22 field. /
<>	144:ef7eb2e8f9f7	1878	#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /!< Bit mask of PIN22 field. /
<>	144:ef7eb2e8f9f7	1879	#define GPIO_IN_PIN22_Low (0UL) /!< Pin input is low. /
<>	144:ef7eb2e8f9f7	1880	#define GPIO_IN_PIN22_High (1UL) /!< Pin input is high. /
<>	144:ef7eb2e8f9f7	1881
<>	144:ef7eb2e8f9f7	1882	/* Bit 21 : Pin 21. */
<>	144:ef7eb2e8f9f7	1883	#define GPIO_IN_PIN21_Pos (21UL) /!< Position of PIN21 field. /
<>	144:ef7eb2e8f9f7	1884	#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /!< Bit mask of PIN21 field. /
<>	144:ef7eb2e8f9f7	1885	#define GPIO_IN_PIN21_Low (0UL) /!< Pin input is low. /
<>	144:ef7eb2e8f9f7	1886	#define GPIO_IN_PIN21_High (1UL) /!< Pin input is high. /
<>	144:ef7eb2e8f9f7	1887
<>	144:ef7eb2e8f9f7	1888	/* Bit 20 : Pin 20. */
<>	144:ef7eb2e8f9f7	1889	#define GPIO_IN_PIN20_Pos (20UL) /!< Position of PIN20 field. /
<>	144:ef7eb2e8f9f7	1890	#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /!< Bit mask of PIN20 field. /
<>	144:ef7eb2e8f9f7	1891	#define GPIO_IN_PIN20_Low (0UL) /!< Pin input is low. /
<>	144:ef7eb2e8f9f7	1892	#define GPIO_IN_PIN20_High (1UL) /!< Pin input is high. /
<>	144:ef7eb2e8f9f7	1893
<>	144:ef7eb2e8f9f7	1894	/* Bit 19 : Pin 19. */
<>	144:ef7eb2e8f9f7	1895	#define GPIO_IN_PIN19_Pos (19UL) /!< Position of PIN19 field. /
<>	144:ef7eb2e8f9f7	1896	#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /!< Bit mask of PIN19 field. /
<>	144:ef7eb2e8f9f7	1897	#define GPIO_IN_PIN19_Low (0UL) /!< Pin input is low. /
<>	144:ef7eb2e8f9f7	1898	#define GPIO_IN_PIN19_High (1UL) /!< Pin input is high. /
<>	144:ef7eb2e8f9f7	1899
<>	144:ef7eb2e8f9f7	1900	/* Bit 18 : Pin 18. */
<>	144:ef7eb2e8f9f7	1901	#define GPIO_IN_PIN18_Pos (18UL) /!< Position of PIN18 field. /
<>	144:ef7eb2e8f9f7	1902	#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /!< Bit mask of PIN18 field. /
<>	144:ef7eb2e8f9f7	1903	#define GPIO_IN_PIN18_Low (0UL) /!< Pin input is low. /
<>	144:ef7eb2e8f9f7	1904	#define GPIO_IN_PIN18_High (1UL) /!< Pin input is high. /
<>	144:ef7eb2e8f9f7	1905
<>	144:ef7eb2e8f9f7	1906	/* Bit 17 : Pin 17. */
<>	144:ef7eb2e8f9f7	1907	#define GPIO_IN_PIN17_Pos (17UL) /!< Position of PIN17 field. /
<>	144:ef7eb2e8f9f7	1908	#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /!< Bit mask of PIN17 field. /
<>	144:ef7eb2e8f9f7	1909	#define GPIO_IN_PIN17_Low (0UL) /!< Pin input is low. /
<>	144:ef7eb2e8f9f7	1910	#define GPIO_IN_PIN17_High (1UL) /!< Pin input is high. /
<>	144:ef7eb2e8f9f7	1911
<>	144:ef7eb2e8f9f7	1912	/* Bit 16 : Pin 16. */
<>	144:ef7eb2e8f9f7	1913	#define GPIO_IN_PIN16_Pos (16UL) /!< Position of PIN16 field. /
<>	144:ef7eb2e8f9f7	1914	#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /!< Bit mask of PIN16 field. /
<>	144:ef7eb2e8f9f7	1915	#define GPIO_IN_PIN16_Low (0UL) /!< Pin input is low. /
<>	144:ef7eb2e8f9f7	1916	#define GPIO_IN_PIN16_High (1UL) /!< Pin input is high. /
<>	144:ef7eb2e8f9f7	1917
<>	144:ef7eb2e8f9f7	1918	/* Bit 15 : Pin 15. */
<>	144:ef7eb2e8f9f7	1919	#define GPIO_IN_PIN15_Pos (15UL) /!< Position of PIN15 field. /
<>	144:ef7eb2e8f9f7	1920	#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /!< Bit mask of PIN15 field. /
<>	144:ef7eb2e8f9f7	1921	#define GPIO_IN_PIN15_Low (0UL) /!< Pin input is low. /
<>	144:ef7eb2e8f9f7	1922	#define GPIO_IN_PIN15_High (1UL) /!< Pin input is high. /
<>	144:ef7eb2e8f9f7	1923
<>	144:ef7eb2e8f9f7	1924	/* Bit 14 : Pin 14. */
<>	144:ef7eb2e8f9f7	1925	#define GPIO_IN_PIN14_Pos (14UL) /!< Position of PIN14 field. /
<>	144:ef7eb2e8f9f7	1926	#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /!< Bit mask of PIN14 field. /
<>	144:ef7eb2e8f9f7	1927	#define GPIO_IN_PIN14_Low (0UL) /!< Pin input is low. /
<>	144:ef7eb2e8f9f7	1928	#define GPIO_IN_PIN14_High (1UL) /!< Pin input is high. /
<>	144:ef7eb2e8f9f7	1929
<>	144:ef7eb2e8f9f7	1930	/* Bit 13 : Pin 13. */
<>	144:ef7eb2e8f9f7	1931	#define GPIO_IN_PIN13_Pos (13UL) /!< Position of PIN13 field. /
<>	144:ef7eb2e8f9f7	1932	#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /!< Bit mask of PIN13 field. /
<>	144:ef7eb2e8f9f7	1933	#define GPIO_IN_PIN13_Low (0UL) /!< Pin input is low. /
<>	144:ef7eb2e8f9f7	1934	#define GPIO_IN_PIN13_High (1UL) /!< Pin input is high. /
<>	144:ef7eb2e8f9f7	1935
<>	144:ef7eb2e8f9f7	1936	/* Bit 12 : Pin 12. */
<>	144:ef7eb2e8f9f7	1937	#define GPIO_IN_PIN12_Pos (12UL) /!< Position of PIN12 field. /
<>	144:ef7eb2e8f9f7	1938	#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /!< Bit mask of PIN12 field. /
<>	144:ef7eb2e8f9f7	1939	#define GPIO_IN_PIN12_Low (0UL) /!< Pin input is low. /
<>	144:ef7eb2e8f9f7	1940	#define GPIO_IN_PIN12_High (1UL) /!< Pin input is high. /
<>	144:ef7eb2e8f9f7	1941
<>	144:ef7eb2e8f9f7	1942	/* Bit 11 : Pin 11. */
<>	144:ef7eb2e8f9f7	1943	#define GPIO_IN_PIN11_Pos (11UL) /!< Position of PIN11 field. /
<>	144:ef7eb2e8f9f7	1944	#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /!< Bit mask of PIN11 field. /
<>	144:ef7eb2e8f9f7	1945	#define GPIO_IN_PIN11_Low (0UL) /!< Pin input is low. /
<>	144:ef7eb2e8f9f7	1946	#define GPIO_IN_PIN11_High (1UL) /!< Pin input is high. /
<>	144:ef7eb2e8f9f7	1947
<>	144:ef7eb2e8f9f7	1948	/* Bit 10 : Pin 10. */
<>	144:ef7eb2e8f9f7	1949	#define GPIO_IN_PIN10_Pos (10UL) /!< Position of PIN10 field. /
<>	144:ef7eb2e8f9f7	1950	#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /!< Bit mask of PIN10 field. /
<>	144:ef7eb2e8f9f7	1951	#define GPIO_IN_PIN10_Low (0UL) /!< Pin input is low. /
<>	144:ef7eb2e8f9f7	1952	#define GPIO_IN_PIN10_High (1UL) /!< Pin input is high. /
<>	144:ef7eb2e8f9f7	1953
<>	144:ef7eb2e8f9f7	1954	/* Bit 9 : Pin 9. */
<>	144:ef7eb2e8f9f7	1955	#define GPIO_IN_PIN9_Pos (9UL) /!< Position of PIN9 field. /
<>	144:ef7eb2e8f9f7	1956	#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /!< Bit mask of PIN9 field. /
<>	144:ef7eb2e8f9f7	1957	#define GPIO_IN_PIN9_Low (0UL) /!< Pin input is low. /
<>	144:ef7eb2e8f9f7	1958	#define GPIO_IN_PIN9_High (1UL) /!< Pin input is high. /
<>	144:ef7eb2e8f9f7	1959
<>	144:ef7eb2e8f9f7	1960	/* Bit 8 : Pin 8. */
<>	144:ef7eb2e8f9f7	1961	#define GPIO_IN_PIN8_Pos (8UL) /!< Position of PIN8 field. /
<>	144:ef7eb2e8f9f7	1962	#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /!< Bit mask of PIN8 field. /
<>	144:ef7eb2e8f9f7	1963	#define GPIO_IN_PIN8_Low (0UL) /!< Pin input is low. /
<>	144:ef7eb2e8f9f7	1964	#define GPIO_IN_PIN8_High (1UL) /!< Pin input is high. /
<>	144:ef7eb2e8f9f7	1965
<>	144:ef7eb2e8f9f7	1966	/* Bit 7 : Pin 7. */
<>	144:ef7eb2e8f9f7	1967	#define GPIO_IN_PIN7_Pos (7UL) /!< Position of PIN7 field. /
<>	144:ef7eb2e8f9f7	1968	#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /!< Bit mask of PIN7 field. /
<>	144:ef7eb2e8f9f7	1969	#define GPIO_IN_PIN7_Low (0UL) /!< Pin input is low. /
<>	144:ef7eb2e8f9f7	1970	#define GPIO_IN_PIN7_High (1UL) /!< Pin input is high. /
<>	144:ef7eb2e8f9f7	1971
<>	144:ef7eb2e8f9f7	1972	/* Bit 6 : Pin 6. */
<>	144:ef7eb2e8f9f7	1973	#define GPIO_IN_PIN6_Pos (6UL) /!< Position of PIN6 field. /
<>	144:ef7eb2e8f9f7	1974	#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /!< Bit mask of PIN6 field. /
<>	144:ef7eb2e8f9f7	1975	#define GPIO_IN_PIN6_Low (0UL) /!< Pin input is low. /
<>	144:ef7eb2e8f9f7	1976	#define GPIO_IN_PIN6_High (1UL) /!< Pin input is high. /
<>	144:ef7eb2e8f9f7	1977
<>	144:ef7eb2e8f9f7	1978	/* Bit 5 : Pin 5. */
<>	144:ef7eb2e8f9f7	1979	#define GPIO_IN_PIN5_Pos (5UL) /!< Position of PIN5 field. /
<>	144:ef7eb2e8f9f7	1980	#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /!< Bit mask of PIN5 field. /
<>	144:ef7eb2e8f9f7	1981	#define GPIO_IN_PIN5_Low (0UL) /!< Pin input is low. /
<>	144:ef7eb2e8f9f7	1982	#define GPIO_IN_PIN5_High (1UL) /!< Pin input is high. /
<>	144:ef7eb2e8f9f7	1983
<>	144:ef7eb2e8f9f7	1984	/* Bit 4 : Pin 4. */
<>	144:ef7eb2e8f9f7	1985	#define GPIO_IN_PIN4_Pos (4UL) /!< Position of PIN4 field. /
<>	144:ef7eb2e8f9f7	1986	#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /!< Bit mask of PIN4 field. /
<>	144:ef7eb2e8f9f7	1987	#define GPIO_IN_PIN4_Low (0UL) /!< Pin input is low. /
<>	144:ef7eb2e8f9f7	1988	#define GPIO_IN_PIN4_High (1UL) /!< Pin input is high. /
<>	144:ef7eb2e8f9f7	1989
<>	144:ef7eb2e8f9f7	1990	/* Bit 3 : Pin 3. */
<>	144:ef7eb2e8f9f7	1991	#define GPIO_IN_PIN3_Pos (3UL) /!< Position of PIN3 field. /
<>	144:ef7eb2e8f9f7	1992	#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /!< Bit mask of PIN3 field. /
<>	144:ef7eb2e8f9f7	1993	#define GPIO_IN_PIN3_Low (0UL) /!< Pin input is low. /
<>	144:ef7eb2e8f9f7	1994	#define GPIO_IN_PIN3_High (1UL) /!< Pin input is high. /
<>	144:ef7eb2e8f9f7	1995
<>	144:ef7eb2e8f9f7	1996	/* Bit 2 : Pin 2. */
<>	144:ef7eb2e8f9f7	1997	#define GPIO_IN_PIN2_Pos (2UL) /!< Position of PIN2 field. /
<>	144:ef7eb2e8f9f7	1998	#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /!< Bit mask of PIN2 field. /
<>	144:ef7eb2e8f9f7	1999	#define GPIO_IN_PIN2_Low (0UL) /!< Pin input is low. /
<>	144:ef7eb2e8f9f7	2000	#define GPIO_IN_PIN2_High (1UL) /!< Pin input is high. /
<>	144:ef7eb2e8f9f7	2001
<>	144:ef7eb2e8f9f7	2002	/* Bit 1 : Pin 1. */
<>	144:ef7eb2e8f9f7	2003	#define GPIO_IN_PIN1_Pos (1UL) /!< Position of PIN1 field. /
<>	144:ef7eb2e8f9f7	2004	#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /!< Bit mask of PIN1 field. /
<>	144:ef7eb2e8f9f7	2005	#define GPIO_IN_PIN1_Low (0UL) /!< Pin input is low. /
<>	144:ef7eb2e8f9f7	2006	#define GPIO_IN_PIN1_High (1UL) /!< Pin input is high. /
<>	144:ef7eb2e8f9f7	2007
<>	144:ef7eb2e8f9f7	2008	/* Bit 0 : Pin 0. */
<>	144:ef7eb2e8f9f7	2009	#define GPIO_IN_PIN0_Pos (0UL) /!< Position of PIN0 field. /
<>	144:ef7eb2e8f9f7	2010	#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /!< Bit mask of PIN0 field. /
<>	144:ef7eb2e8f9f7	2011	#define GPIO_IN_PIN0_Low (0UL) /!< Pin input is low. /
<>	144:ef7eb2e8f9f7	2012	#define GPIO_IN_PIN0_High (1UL) /!< Pin input is high. /
<>	144:ef7eb2e8f9f7	2013
<>	144:ef7eb2e8f9f7	2014	/* Register: GPIO_DIR */
<>	144:ef7eb2e8f9f7	2015	/* Description: Direction of GPIO pins. */
<>	144:ef7eb2e8f9f7	2016
<>	144:ef7eb2e8f9f7	2017	/* Bit 31 : Pin 31. */
<>	144:ef7eb2e8f9f7	2018	#define GPIO_DIR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
<>	144:ef7eb2e8f9f7	2019	#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /!< Bit mask of PIN31 field. /
<>	144:ef7eb2e8f9f7	2020	#define GPIO_DIR_PIN31_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2021	#define GPIO_DIR_PIN31_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2022
<>	144:ef7eb2e8f9f7	2023	/* Bit 30 : Pin 30. */
<>	144:ef7eb2e8f9f7	2024	#define GPIO_DIR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
<>	144:ef7eb2e8f9f7	2025	#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /!< Bit mask of PIN30 field. /
<>	144:ef7eb2e8f9f7	2026	#define GPIO_DIR_PIN30_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2027	#define GPIO_DIR_PIN30_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2028
<>	144:ef7eb2e8f9f7	2029	/* Bit 29 : Pin 29. */
<>	144:ef7eb2e8f9f7	2030	#define GPIO_DIR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
<>	144:ef7eb2e8f9f7	2031	#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /!< Bit mask of PIN29 field. /
<>	144:ef7eb2e8f9f7	2032	#define GPIO_DIR_PIN29_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2033	#define GPIO_DIR_PIN29_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2034
<>	144:ef7eb2e8f9f7	2035	/* Bit 28 : Pin 28. */
<>	144:ef7eb2e8f9f7	2036	#define GPIO_DIR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
<>	144:ef7eb2e8f9f7	2037	#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /!< Bit mask of PIN28 field. /
<>	144:ef7eb2e8f9f7	2038	#define GPIO_DIR_PIN28_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2039	#define GPIO_DIR_PIN28_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2040
<>	144:ef7eb2e8f9f7	2041	/* Bit 27 : Pin 27. */
<>	144:ef7eb2e8f9f7	2042	#define GPIO_DIR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
<>	144:ef7eb2e8f9f7	2043	#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /!< Bit mask of PIN27 field. /
<>	144:ef7eb2e8f9f7	2044	#define GPIO_DIR_PIN27_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2045	#define GPIO_DIR_PIN27_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2046
<>	144:ef7eb2e8f9f7	2047	/* Bit 26 : Pin 26. */
<>	144:ef7eb2e8f9f7	2048	#define GPIO_DIR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
<>	144:ef7eb2e8f9f7	2049	#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /!< Bit mask of PIN26 field. /
<>	144:ef7eb2e8f9f7	2050	#define GPIO_DIR_PIN26_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2051	#define GPIO_DIR_PIN26_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2052
<>	144:ef7eb2e8f9f7	2053	/* Bit 25 : Pin 25. */
<>	144:ef7eb2e8f9f7	2054	#define GPIO_DIR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
<>	144:ef7eb2e8f9f7	2055	#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /!< Bit mask of PIN25 field. /
<>	144:ef7eb2e8f9f7	2056	#define GPIO_DIR_PIN25_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2057	#define GPIO_DIR_PIN25_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2058
<>	144:ef7eb2e8f9f7	2059	/* Bit 24 : Pin 24. */
<>	144:ef7eb2e8f9f7	2060	#define GPIO_DIR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
<>	144:ef7eb2e8f9f7	2061	#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /!< Bit mask of PIN24 field. /
<>	144:ef7eb2e8f9f7	2062	#define GPIO_DIR_PIN24_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2063	#define GPIO_DIR_PIN24_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2064
<>	144:ef7eb2e8f9f7	2065	/* Bit 23 : Pin 23. */
<>	144:ef7eb2e8f9f7	2066	#define GPIO_DIR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
<>	144:ef7eb2e8f9f7	2067	#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /!< Bit mask of PIN23 field. /
<>	144:ef7eb2e8f9f7	2068	#define GPIO_DIR_PIN23_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2069	#define GPIO_DIR_PIN23_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2070
<>	144:ef7eb2e8f9f7	2071	/* Bit 22 : Pin 22. */
<>	144:ef7eb2e8f9f7	2072	#define GPIO_DIR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
<>	144:ef7eb2e8f9f7	2073	#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /!< Bit mask of PIN22 field. /
<>	144:ef7eb2e8f9f7	2074	#define GPIO_DIR_PIN22_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2075	#define GPIO_DIR_PIN22_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2076
<>	144:ef7eb2e8f9f7	2077	/* Bit 21 : Pin 21. */
<>	144:ef7eb2e8f9f7	2078	#define GPIO_DIR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
<>	144:ef7eb2e8f9f7	2079	#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /!< Bit mask of PIN21 field. /
<>	144:ef7eb2e8f9f7	2080	#define GPIO_DIR_PIN21_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2081	#define GPIO_DIR_PIN21_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2082
<>	144:ef7eb2e8f9f7	2083	/* Bit 20 : Pin 20. */
<>	144:ef7eb2e8f9f7	2084	#define GPIO_DIR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
<>	144:ef7eb2e8f9f7	2085	#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /!< Bit mask of PIN20 field. /
<>	144:ef7eb2e8f9f7	2086	#define GPIO_DIR_PIN20_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2087	#define GPIO_DIR_PIN20_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2088
<>	144:ef7eb2e8f9f7	2089	/* Bit 19 : Pin 19. */
<>	144:ef7eb2e8f9f7	2090	#define GPIO_DIR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
<>	144:ef7eb2e8f9f7	2091	#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /!< Bit mask of PIN19 field. /
<>	144:ef7eb2e8f9f7	2092	#define GPIO_DIR_PIN19_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2093	#define GPIO_DIR_PIN19_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2094
<>	144:ef7eb2e8f9f7	2095	/* Bit 18 : Pin 18. */
<>	144:ef7eb2e8f9f7	2096	#define GPIO_DIR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
<>	144:ef7eb2e8f9f7	2097	#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /!< Bit mask of PIN18 field. /
<>	144:ef7eb2e8f9f7	2098	#define GPIO_DIR_PIN18_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2099	#define GPIO_DIR_PIN18_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2100
<>	144:ef7eb2e8f9f7	2101	/* Bit 17 : Pin 17. */
<>	144:ef7eb2e8f9f7	2102	#define GPIO_DIR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
<>	144:ef7eb2e8f9f7	2103	#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /!< Bit mask of PIN17 field. /
<>	144:ef7eb2e8f9f7	2104	#define GPIO_DIR_PIN17_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2105	#define GPIO_DIR_PIN17_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2106
<>	144:ef7eb2e8f9f7	2107	/* Bit 16 : Pin 16. */
<>	144:ef7eb2e8f9f7	2108	#define GPIO_DIR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
<>	144:ef7eb2e8f9f7	2109	#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /!< Bit mask of PIN16 field. /
<>	144:ef7eb2e8f9f7	2110	#define GPIO_DIR_PIN16_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2111	#define GPIO_DIR_PIN16_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2112
<>	144:ef7eb2e8f9f7	2113	/* Bit 15 : Pin 15. */
<>	144:ef7eb2e8f9f7	2114	#define GPIO_DIR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
<>	144:ef7eb2e8f9f7	2115	#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /!< Bit mask of PIN15 field. /
<>	144:ef7eb2e8f9f7	2116	#define GPIO_DIR_PIN15_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2117	#define GPIO_DIR_PIN15_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2118
<>	144:ef7eb2e8f9f7	2119	/* Bit 14 : Pin 14. */
<>	144:ef7eb2e8f9f7	2120	#define GPIO_DIR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
<>	144:ef7eb2e8f9f7	2121	#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /!< Bit mask of PIN14 field. /
<>	144:ef7eb2e8f9f7	2122	#define GPIO_DIR_PIN14_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2123	#define GPIO_DIR_PIN14_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2124
<>	144:ef7eb2e8f9f7	2125	/* Bit 13 : Pin 13. */
<>	144:ef7eb2e8f9f7	2126	#define GPIO_DIR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
<>	144:ef7eb2e8f9f7	2127	#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /!< Bit mask of PIN13 field. /
<>	144:ef7eb2e8f9f7	2128	#define GPIO_DIR_PIN13_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2129	#define GPIO_DIR_PIN13_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2130
<>	144:ef7eb2e8f9f7	2131	/* Bit 12 : Pin 12. */
<>	144:ef7eb2e8f9f7	2132	#define GPIO_DIR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
<>	144:ef7eb2e8f9f7	2133	#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /!< Bit mask of PIN12 field. /
<>	144:ef7eb2e8f9f7	2134	#define GPIO_DIR_PIN12_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2135	#define GPIO_DIR_PIN12_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2136
<>	144:ef7eb2e8f9f7	2137	/* Bit 11 : Pin 11. */
<>	144:ef7eb2e8f9f7	2138	#define GPIO_DIR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
<>	144:ef7eb2e8f9f7	2139	#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /!< Bit mask of PIN11 field. /
<>	144:ef7eb2e8f9f7	2140	#define GPIO_DIR_PIN11_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2141	#define GPIO_DIR_PIN11_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2142
<>	144:ef7eb2e8f9f7	2143	/* Bit 10 : Pin 10. */
<>	144:ef7eb2e8f9f7	2144	#define GPIO_DIR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
<>	144:ef7eb2e8f9f7	2145	#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /!< Bit mask of PIN10 field. /
<>	144:ef7eb2e8f9f7	2146	#define GPIO_DIR_PIN10_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2147	#define GPIO_DIR_PIN10_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2148
<>	144:ef7eb2e8f9f7	2149	/* Bit 9 : Pin 9. */
<>	144:ef7eb2e8f9f7	2150	#define GPIO_DIR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
<>	144:ef7eb2e8f9f7	2151	#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /!< Bit mask of PIN9 field. /
<>	144:ef7eb2e8f9f7	2152	#define GPIO_DIR_PIN9_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2153	#define GPIO_DIR_PIN9_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2154
<>	144:ef7eb2e8f9f7	2155	/* Bit 8 : Pin 8. */
<>	144:ef7eb2e8f9f7	2156	#define GPIO_DIR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
<>	144:ef7eb2e8f9f7	2157	#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /!< Bit mask of PIN8 field. /
<>	144:ef7eb2e8f9f7	2158	#define GPIO_DIR_PIN8_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2159	#define GPIO_DIR_PIN8_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2160
<>	144:ef7eb2e8f9f7	2161	/* Bit 7 : Pin 7. */
<>	144:ef7eb2e8f9f7	2162	#define GPIO_DIR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
<>	144:ef7eb2e8f9f7	2163	#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /!< Bit mask of PIN7 field. /
<>	144:ef7eb2e8f9f7	2164	#define GPIO_DIR_PIN7_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2165	#define GPIO_DIR_PIN7_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2166
<>	144:ef7eb2e8f9f7	2167	/* Bit 6 : Pin 6. */
<>	144:ef7eb2e8f9f7	2168	#define GPIO_DIR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
<>	144:ef7eb2e8f9f7	2169	#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /!< Bit mask of PIN6 field. /
<>	144:ef7eb2e8f9f7	2170	#define GPIO_DIR_PIN6_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2171	#define GPIO_DIR_PIN6_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2172
<>	144:ef7eb2e8f9f7	2173	/* Bit 5 : Pin 5. */
<>	144:ef7eb2e8f9f7	2174	#define GPIO_DIR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
<>	144:ef7eb2e8f9f7	2175	#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /!< Bit mask of PIN5 field. /
<>	144:ef7eb2e8f9f7	2176	#define GPIO_DIR_PIN5_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2177	#define GPIO_DIR_PIN5_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2178
<>	144:ef7eb2e8f9f7	2179	/* Bit 4 : Pin 4. */
<>	144:ef7eb2e8f9f7	2180	#define GPIO_DIR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
<>	144:ef7eb2e8f9f7	2181	#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /!< Bit mask of PIN4 field. /
<>	144:ef7eb2e8f9f7	2182	#define GPIO_DIR_PIN4_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2183	#define GPIO_DIR_PIN4_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2184
<>	144:ef7eb2e8f9f7	2185	/* Bit 3 : Pin 3. */
<>	144:ef7eb2e8f9f7	2186	#define GPIO_DIR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
<>	144:ef7eb2e8f9f7	2187	#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /!< Bit mask of PIN3 field. /
<>	144:ef7eb2e8f9f7	2188	#define GPIO_DIR_PIN3_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2189	#define GPIO_DIR_PIN3_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2190
<>	144:ef7eb2e8f9f7	2191	/* Bit 2 : Pin 2. */
<>	144:ef7eb2e8f9f7	2192	#define GPIO_DIR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
<>	144:ef7eb2e8f9f7	2193	#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /!< Bit mask of PIN2 field. /
<>	144:ef7eb2e8f9f7	2194	#define GPIO_DIR_PIN2_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2195	#define GPIO_DIR_PIN2_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2196
<>	144:ef7eb2e8f9f7	2197	/* Bit 1 : Pin 1. */
<>	144:ef7eb2e8f9f7	2198	#define GPIO_DIR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
<>	144:ef7eb2e8f9f7	2199	#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /!< Bit mask of PIN1 field. /
<>	144:ef7eb2e8f9f7	2200	#define GPIO_DIR_PIN1_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2201	#define GPIO_DIR_PIN1_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2202
<>	144:ef7eb2e8f9f7	2203	/* Bit 0 : Pin 0. */
<>	144:ef7eb2e8f9f7	2204	#define GPIO_DIR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
<>	144:ef7eb2e8f9f7	2205	#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /!< Bit mask of PIN0 field. /
<>	144:ef7eb2e8f9f7	2206	#define GPIO_DIR_PIN0_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2207	#define GPIO_DIR_PIN0_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2208
<>	144:ef7eb2e8f9f7	2209	/* Register: GPIO_DIRSET */
<>	144:ef7eb2e8f9f7	2210	/* Description: DIR set register. */
<>	144:ef7eb2e8f9f7	2211
<>	144:ef7eb2e8f9f7	2212	/* Bit 31 : Set as output pin 31. */
<>	144:ef7eb2e8f9f7	2213	#define GPIO_DIRSET_PIN31_Pos (31UL) /!< Position of PIN31 field. /
<>	144:ef7eb2e8f9f7	2214	#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /!< Bit mask of PIN31 field. /
<>	144:ef7eb2e8f9f7	2215	#define GPIO_DIRSET_PIN31_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2216	#define GPIO_DIRSET_PIN31_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2217	#define GPIO_DIRSET_PIN31_Set (1UL) /!< Set pin as output. /
<>	144:ef7eb2e8f9f7	2218
<>	144:ef7eb2e8f9f7	2219	/* Bit 30 : Set as output pin 30. */
<>	144:ef7eb2e8f9f7	2220	#define GPIO_DIRSET_PIN30_Pos (30UL) /!< Position of PIN30 field. /
<>	144:ef7eb2e8f9f7	2221	#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /!< Bit mask of PIN30 field. /
<>	144:ef7eb2e8f9f7	2222	#define GPIO_DIRSET_PIN30_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2223	#define GPIO_DIRSET_PIN30_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2224	#define GPIO_DIRSET_PIN30_Set (1UL) /!< Set pin as output. /
<>	144:ef7eb2e8f9f7	2225
<>	144:ef7eb2e8f9f7	2226	/* Bit 29 : Set as output pin 29. */
<>	144:ef7eb2e8f9f7	2227	#define GPIO_DIRSET_PIN29_Pos (29UL) /!< Position of PIN29 field. /
<>	144:ef7eb2e8f9f7	2228	#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /!< Bit mask of PIN29 field. /
<>	144:ef7eb2e8f9f7	2229	#define GPIO_DIRSET_PIN29_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2230	#define GPIO_DIRSET_PIN29_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2231	#define GPIO_DIRSET_PIN29_Set (1UL) /!< Set pin as output. /
<>	144:ef7eb2e8f9f7	2232
<>	144:ef7eb2e8f9f7	2233	/* Bit 28 : Set as output pin 28. */
<>	144:ef7eb2e8f9f7	2234	#define GPIO_DIRSET_PIN28_Pos (28UL) /!< Position of PIN28 field. /
<>	144:ef7eb2e8f9f7	2235	#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /!< Bit mask of PIN28 field. /
<>	144:ef7eb2e8f9f7	2236	#define GPIO_DIRSET_PIN28_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2237	#define GPIO_DIRSET_PIN28_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2238	#define GPIO_DIRSET_PIN28_Set (1UL) /!< Set pin as output. /
<>	144:ef7eb2e8f9f7	2239
<>	144:ef7eb2e8f9f7	2240	/* Bit 27 : Set as output pin 27. */
<>	144:ef7eb2e8f9f7	2241	#define GPIO_DIRSET_PIN27_Pos (27UL) /!< Position of PIN27 field. /
<>	144:ef7eb2e8f9f7	2242	#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /!< Bit mask of PIN27 field. /
<>	144:ef7eb2e8f9f7	2243	#define GPIO_DIRSET_PIN27_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2244	#define GPIO_DIRSET_PIN27_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2245	#define GPIO_DIRSET_PIN27_Set (1UL) /!< Set pin as output. /
<>	144:ef7eb2e8f9f7	2246
<>	144:ef7eb2e8f9f7	2247	/* Bit 26 : Set as output pin 26. */
<>	144:ef7eb2e8f9f7	2248	#define GPIO_DIRSET_PIN26_Pos (26UL) /!< Position of PIN26 field. /
<>	144:ef7eb2e8f9f7	2249	#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /!< Bit mask of PIN26 field. /
<>	144:ef7eb2e8f9f7	2250	#define GPIO_DIRSET_PIN26_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2251	#define GPIO_DIRSET_PIN26_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2252	#define GPIO_DIRSET_PIN26_Set (1UL) /!< Set pin as output. /
<>	144:ef7eb2e8f9f7	2253
<>	144:ef7eb2e8f9f7	2254	/* Bit 25 : Set as output pin 25. */
<>	144:ef7eb2e8f9f7	2255	#define GPIO_DIRSET_PIN25_Pos (25UL) /!< Position of PIN25 field. /
<>	144:ef7eb2e8f9f7	2256	#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /!< Bit mask of PIN25 field. /
<>	144:ef7eb2e8f9f7	2257	#define GPIO_DIRSET_PIN25_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2258	#define GPIO_DIRSET_PIN25_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2259	#define GPIO_DIRSET_PIN25_Set (1UL) /!< Set pin as output. /
<>	144:ef7eb2e8f9f7	2260
<>	144:ef7eb2e8f9f7	2261	/* Bit 24 : Set as output pin 24. */
<>	144:ef7eb2e8f9f7	2262	#define GPIO_DIRSET_PIN24_Pos (24UL) /!< Position of PIN24 field. /
<>	144:ef7eb2e8f9f7	2263	#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /!< Bit mask of PIN24 field. /
<>	144:ef7eb2e8f9f7	2264	#define GPIO_DIRSET_PIN24_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2265	#define GPIO_DIRSET_PIN24_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2266	#define GPIO_DIRSET_PIN24_Set (1UL) /!< Set pin as output. /
<>	144:ef7eb2e8f9f7	2267
<>	144:ef7eb2e8f9f7	2268	/* Bit 23 : Set as output pin 23. */
<>	144:ef7eb2e8f9f7	2269	#define GPIO_DIRSET_PIN23_Pos (23UL) /!< Position of PIN23 field. /
<>	144:ef7eb2e8f9f7	2270	#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /!< Bit mask of PIN23 field. /
<>	144:ef7eb2e8f9f7	2271	#define GPIO_DIRSET_PIN23_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2272	#define GPIO_DIRSET_PIN23_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2273	#define GPIO_DIRSET_PIN23_Set (1UL) /!< Set pin as output. /
<>	144:ef7eb2e8f9f7	2274
<>	144:ef7eb2e8f9f7	2275	/* Bit 22 : Set as output pin 22. */
<>	144:ef7eb2e8f9f7	2276	#define GPIO_DIRSET_PIN22_Pos (22UL) /!< Position of PIN22 field. /
<>	144:ef7eb2e8f9f7	2277	#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /!< Bit mask of PIN22 field. /
<>	144:ef7eb2e8f9f7	2278	#define GPIO_DIRSET_PIN22_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2279	#define GPIO_DIRSET_PIN22_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2280	#define GPIO_DIRSET_PIN22_Set (1UL) /!< Set pin as output. /
<>	144:ef7eb2e8f9f7	2281
<>	144:ef7eb2e8f9f7	2282	/* Bit 21 : Set as output pin 21. */
<>	144:ef7eb2e8f9f7	2283	#define GPIO_DIRSET_PIN21_Pos (21UL) /!< Position of PIN21 field. /
<>	144:ef7eb2e8f9f7	2284	#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /!< Bit mask of PIN21 field. /
<>	144:ef7eb2e8f9f7	2285	#define GPIO_DIRSET_PIN21_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2286	#define GPIO_DIRSET_PIN21_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2287	#define GPIO_DIRSET_PIN21_Set (1UL) /!< Set pin as output. /
<>	144:ef7eb2e8f9f7	2288
<>	144:ef7eb2e8f9f7	2289	/* Bit 20 : Set as output pin 20. */
<>	144:ef7eb2e8f9f7	2290	#define GPIO_DIRSET_PIN20_Pos (20UL) /!< Position of PIN20 field. /
<>	144:ef7eb2e8f9f7	2291	#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /!< Bit mask of PIN20 field. /
<>	144:ef7eb2e8f9f7	2292	#define GPIO_DIRSET_PIN20_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2293	#define GPIO_DIRSET_PIN20_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2294	#define GPIO_DIRSET_PIN20_Set (1UL) /!< Set pin as output. /
<>	144:ef7eb2e8f9f7	2295
<>	144:ef7eb2e8f9f7	2296	/* Bit 19 : Set as output pin 19. */
<>	144:ef7eb2e8f9f7	2297	#define GPIO_DIRSET_PIN19_Pos (19UL) /!< Position of PIN19 field. /
<>	144:ef7eb2e8f9f7	2298	#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /!< Bit mask of PIN19 field. /
<>	144:ef7eb2e8f9f7	2299	#define GPIO_DIRSET_PIN19_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2300	#define GPIO_DIRSET_PIN19_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2301	#define GPIO_DIRSET_PIN19_Set (1UL) /!< Set pin as output. /
<>	144:ef7eb2e8f9f7	2302
<>	144:ef7eb2e8f9f7	2303	/* Bit 18 : Set as output pin 18. */
<>	144:ef7eb2e8f9f7	2304	#define GPIO_DIRSET_PIN18_Pos (18UL) /!< Position of PIN18 field. /
<>	144:ef7eb2e8f9f7	2305	#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /!< Bit mask of PIN18 field. /
<>	144:ef7eb2e8f9f7	2306	#define GPIO_DIRSET_PIN18_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2307	#define GPIO_DIRSET_PIN18_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2308	#define GPIO_DIRSET_PIN18_Set (1UL) /!< Set pin as output. /
<>	144:ef7eb2e8f9f7	2309
<>	144:ef7eb2e8f9f7	2310	/* Bit 17 : Set as output pin 17. */
<>	144:ef7eb2e8f9f7	2311	#define GPIO_DIRSET_PIN17_Pos (17UL) /!< Position of PIN17 field. /
<>	144:ef7eb2e8f9f7	2312	#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /!< Bit mask of PIN17 field. /
<>	144:ef7eb2e8f9f7	2313	#define GPIO_DIRSET_PIN17_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2314	#define GPIO_DIRSET_PIN17_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2315	#define GPIO_DIRSET_PIN17_Set (1UL) /!< Set pin as output. /
<>	144:ef7eb2e8f9f7	2316
<>	144:ef7eb2e8f9f7	2317	/* Bit 16 : Set as output pin 16. */
<>	144:ef7eb2e8f9f7	2318	#define GPIO_DIRSET_PIN16_Pos (16UL) /!< Position of PIN16 field. /
<>	144:ef7eb2e8f9f7	2319	#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /!< Bit mask of PIN16 field. /
<>	144:ef7eb2e8f9f7	2320	#define GPIO_DIRSET_PIN16_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2321	#define GPIO_DIRSET_PIN16_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2322	#define GPIO_DIRSET_PIN16_Set (1UL) /!< Set pin as output. /
<>	144:ef7eb2e8f9f7	2323
<>	144:ef7eb2e8f9f7	2324	/* Bit 15 : Set as output pin 15. */
<>	144:ef7eb2e8f9f7	2325	#define GPIO_DIRSET_PIN15_Pos (15UL) /!< Position of PIN15 field. /
<>	144:ef7eb2e8f9f7	2326	#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /!< Bit mask of PIN15 field. /
<>	144:ef7eb2e8f9f7	2327	#define GPIO_DIRSET_PIN15_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2328	#define GPIO_DIRSET_PIN15_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2329	#define GPIO_DIRSET_PIN15_Set (1UL) /!< Set pin as output. /
<>	144:ef7eb2e8f9f7	2330
<>	144:ef7eb2e8f9f7	2331	/* Bit 14 : Set as output pin 14. */
<>	144:ef7eb2e8f9f7	2332	#define GPIO_DIRSET_PIN14_Pos (14UL) /!< Position of PIN14 field. /
<>	144:ef7eb2e8f9f7	2333	#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /!< Bit mask of PIN14 field. /
<>	144:ef7eb2e8f9f7	2334	#define GPIO_DIRSET_PIN14_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2335	#define GPIO_DIRSET_PIN14_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2336	#define GPIO_DIRSET_PIN14_Set (1UL) /!< Set pin as output. /
<>	144:ef7eb2e8f9f7	2337
<>	144:ef7eb2e8f9f7	2338	/* Bit 13 : Set as output pin 13. */
<>	144:ef7eb2e8f9f7	2339	#define GPIO_DIRSET_PIN13_Pos (13UL) /!< Position of PIN13 field. /
<>	144:ef7eb2e8f9f7	2340	#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /!< Bit mask of PIN13 field. /
<>	144:ef7eb2e8f9f7	2341	#define GPIO_DIRSET_PIN13_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2342	#define GPIO_DIRSET_PIN13_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2343	#define GPIO_DIRSET_PIN13_Set (1UL) /!< Set pin as output. /
<>	144:ef7eb2e8f9f7	2344
<>	144:ef7eb2e8f9f7	2345	/* Bit 12 : Set as output pin 12. */
<>	144:ef7eb2e8f9f7	2346	#define GPIO_DIRSET_PIN12_Pos (12UL) /!< Position of PIN12 field. /
<>	144:ef7eb2e8f9f7	2347	#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /!< Bit mask of PIN12 field. /
<>	144:ef7eb2e8f9f7	2348	#define GPIO_DIRSET_PIN12_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2349	#define GPIO_DIRSET_PIN12_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2350	#define GPIO_DIRSET_PIN12_Set (1UL) /!< Set pin as output. /
<>	144:ef7eb2e8f9f7	2351
<>	144:ef7eb2e8f9f7	2352	/* Bit 11 : Set as output pin 11. */
<>	144:ef7eb2e8f9f7	2353	#define GPIO_DIRSET_PIN11_Pos (11UL) /!< Position of PIN11 field. /
<>	144:ef7eb2e8f9f7	2354	#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /!< Bit mask of PIN11 field. /
<>	144:ef7eb2e8f9f7	2355	#define GPIO_DIRSET_PIN11_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2356	#define GPIO_DIRSET_PIN11_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2357	#define GPIO_DIRSET_PIN11_Set (1UL) /!< Set pin as output. /
<>	144:ef7eb2e8f9f7	2358
<>	144:ef7eb2e8f9f7	2359	/* Bit 10 : Set as output pin 10. */
<>	144:ef7eb2e8f9f7	2360	#define GPIO_DIRSET_PIN10_Pos (10UL) /!< Position of PIN10 field. /
<>	144:ef7eb2e8f9f7	2361	#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /!< Bit mask of PIN10 field. /
<>	144:ef7eb2e8f9f7	2362	#define GPIO_DIRSET_PIN10_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2363	#define GPIO_DIRSET_PIN10_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2364	#define GPIO_DIRSET_PIN10_Set (1UL) /!< Set pin as output. /
<>	144:ef7eb2e8f9f7	2365
<>	144:ef7eb2e8f9f7	2366	/* Bit 9 : Set as output pin 9. */
<>	144:ef7eb2e8f9f7	2367	#define GPIO_DIRSET_PIN9_Pos (9UL) /!< Position of PIN9 field. /
<>	144:ef7eb2e8f9f7	2368	#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /!< Bit mask of PIN9 field. /
<>	144:ef7eb2e8f9f7	2369	#define GPIO_DIRSET_PIN9_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2370	#define GPIO_DIRSET_PIN9_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2371	#define GPIO_DIRSET_PIN9_Set (1UL) /!< Set pin as output. /
<>	144:ef7eb2e8f9f7	2372
<>	144:ef7eb2e8f9f7	2373	/* Bit 8 : Set as output pin 8. */
<>	144:ef7eb2e8f9f7	2374	#define GPIO_DIRSET_PIN8_Pos (8UL) /!< Position of PIN8 field. /
<>	144:ef7eb2e8f9f7	2375	#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /!< Bit mask of PIN8 field. /
<>	144:ef7eb2e8f9f7	2376	#define GPIO_DIRSET_PIN8_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2377	#define GPIO_DIRSET_PIN8_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2378	#define GPIO_DIRSET_PIN8_Set (1UL) /!< Set pin as output. /
<>	144:ef7eb2e8f9f7	2379
<>	144:ef7eb2e8f9f7	2380	/* Bit 7 : Set as output pin 7. */
<>	144:ef7eb2e8f9f7	2381	#define GPIO_DIRSET_PIN7_Pos (7UL) /!< Position of PIN7 field. /
<>	144:ef7eb2e8f9f7	2382	#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /!< Bit mask of PIN7 field. /
<>	144:ef7eb2e8f9f7	2383	#define GPIO_DIRSET_PIN7_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2384	#define GPIO_DIRSET_PIN7_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2385	#define GPIO_DIRSET_PIN7_Set (1UL) /!< Set pin as output. /
<>	144:ef7eb2e8f9f7	2386
<>	144:ef7eb2e8f9f7	2387	/* Bit 6 : Set as output pin 6. */
<>	144:ef7eb2e8f9f7	2388	#define GPIO_DIRSET_PIN6_Pos (6UL) /!< Position of PIN6 field. /
<>	144:ef7eb2e8f9f7	2389	#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /!< Bit mask of PIN6 field. /
<>	144:ef7eb2e8f9f7	2390	#define GPIO_DIRSET_PIN6_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2391	#define GPIO_DIRSET_PIN6_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2392	#define GPIO_DIRSET_PIN6_Set (1UL) /!< Set pin as output. /
<>	144:ef7eb2e8f9f7	2393
<>	144:ef7eb2e8f9f7	2394	/* Bit 5 : Set as output pin 5. */
<>	144:ef7eb2e8f9f7	2395	#define GPIO_DIRSET_PIN5_Pos (5UL) /!< Position of PIN5 field. /
<>	144:ef7eb2e8f9f7	2396	#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /!< Bit mask of PIN5 field. /
<>	144:ef7eb2e8f9f7	2397	#define GPIO_DIRSET_PIN5_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2398	#define GPIO_DIRSET_PIN5_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2399	#define GPIO_DIRSET_PIN5_Set (1UL) /!< Set pin as output. /
<>	144:ef7eb2e8f9f7	2400
<>	144:ef7eb2e8f9f7	2401	/* Bit 4 : Set as output pin 4. */
<>	144:ef7eb2e8f9f7	2402	#define GPIO_DIRSET_PIN4_Pos (4UL) /!< Position of PIN4 field. /
<>	144:ef7eb2e8f9f7	2403	#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /!< Bit mask of PIN4 field. /
<>	144:ef7eb2e8f9f7	2404	#define GPIO_DIRSET_PIN4_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2405	#define GPIO_DIRSET_PIN4_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2406	#define GPIO_DIRSET_PIN4_Set (1UL) /!< Set pin as output. /
<>	144:ef7eb2e8f9f7	2407
<>	144:ef7eb2e8f9f7	2408	/* Bit 3 : Set as output pin 3. */
<>	144:ef7eb2e8f9f7	2409	#define GPIO_DIRSET_PIN3_Pos (3UL) /!< Position of PIN3 field. /
<>	144:ef7eb2e8f9f7	2410	#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /!< Bit mask of PIN3 field. /
<>	144:ef7eb2e8f9f7	2411	#define GPIO_DIRSET_PIN3_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2412	#define GPIO_DIRSET_PIN3_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2413	#define GPIO_DIRSET_PIN3_Set (1UL) /!< Set pin as output. /
<>	144:ef7eb2e8f9f7	2414
<>	144:ef7eb2e8f9f7	2415	/* Bit 2 : Set as output pin 2. */
<>	144:ef7eb2e8f9f7	2416	#define GPIO_DIRSET_PIN2_Pos (2UL) /!< Position of PIN2 field. /
<>	144:ef7eb2e8f9f7	2417	#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /!< Bit mask of PIN2 field. /
<>	144:ef7eb2e8f9f7	2418	#define GPIO_DIRSET_PIN2_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2419	#define GPIO_DIRSET_PIN2_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2420	#define GPIO_DIRSET_PIN2_Set (1UL) /!< Set pin as output. /
<>	144:ef7eb2e8f9f7	2421
<>	144:ef7eb2e8f9f7	2422	/* Bit 1 : Set as output pin 1. */
<>	144:ef7eb2e8f9f7	2423	#define GPIO_DIRSET_PIN1_Pos (1UL) /!< Position of PIN1 field. /
<>	144:ef7eb2e8f9f7	2424	#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /!< Bit mask of PIN1 field. /
<>	144:ef7eb2e8f9f7	2425	#define GPIO_DIRSET_PIN1_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2426	#define GPIO_DIRSET_PIN1_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2427	#define GPIO_DIRSET_PIN1_Set (1UL) /!< Set pin as output. /
<>	144:ef7eb2e8f9f7	2428
<>	144:ef7eb2e8f9f7	2429	/* Bit 0 : Set as output pin 0. */
<>	144:ef7eb2e8f9f7	2430	#define GPIO_DIRSET_PIN0_Pos (0UL) /!< Position of PIN0 field. /
<>	144:ef7eb2e8f9f7	2431	#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /!< Bit mask of PIN0 field. /
<>	144:ef7eb2e8f9f7	2432	#define GPIO_DIRSET_PIN0_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2433	#define GPIO_DIRSET_PIN0_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2434	#define GPIO_DIRSET_PIN0_Set (1UL) /!< Set pin as output. /
<>	144:ef7eb2e8f9f7	2435
<>	144:ef7eb2e8f9f7	2436	/* Register: GPIO_DIRCLR */
<>	144:ef7eb2e8f9f7	2437	/* Description: DIR clear register. */
<>	144:ef7eb2e8f9f7	2438
<>	144:ef7eb2e8f9f7	2439	/* Bit 31 : Set as input pin 31. */
<>	144:ef7eb2e8f9f7	2440	#define GPIO_DIRCLR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
<>	144:ef7eb2e8f9f7	2441	#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /!< Bit mask of PIN31 field. /
<>	144:ef7eb2e8f9f7	2442	#define GPIO_DIRCLR_PIN31_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2443	#define GPIO_DIRCLR_PIN31_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2444	#define GPIO_DIRCLR_PIN31_Clear (1UL) /!< Set pin as input. /
<>	144:ef7eb2e8f9f7	2445
<>	144:ef7eb2e8f9f7	2446	/* Bit 30 : Set as input pin 30. */
<>	144:ef7eb2e8f9f7	2447	#define GPIO_DIRCLR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
<>	144:ef7eb2e8f9f7	2448	#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /!< Bit mask of PIN30 field. /
<>	144:ef7eb2e8f9f7	2449	#define GPIO_DIRCLR_PIN30_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2450	#define GPIO_DIRCLR_PIN30_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2451	#define GPIO_DIRCLR_PIN30_Clear (1UL) /!< Set pin as input. /
<>	144:ef7eb2e8f9f7	2452
<>	144:ef7eb2e8f9f7	2453	/* Bit 29 : Set as input pin 29. */
<>	144:ef7eb2e8f9f7	2454	#define GPIO_DIRCLR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
<>	144:ef7eb2e8f9f7	2455	#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /!< Bit mask of PIN29 field. /
<>	144:ef7eb2e8f9f7	2456	#define GPIO_DIRCLR_PIN29_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2457	#define GPIO_DIRCLR_PIN29_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2458	#define GPIO_DIRCLR_PIN29_Clear (1UL) /!< Set pin as input. /
<>	144:ef7eb2e8f9f7	2459
<>	144:ef7eb2e8f9f7	2460	/* Bit 28 : Set as input pin 28. */
<>	144:ef7eb2e8f9f7	2461	#define GPIO_DIRCLR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
<>	144:ef7eb2e8f9f7	2462	#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /!< Bit mask of PIN28 field. /
<>	144:ef7eb2e8f9f7	2463	#define GPIO_DIRCLR_PIN28_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2464	#define GPIO_DIRCLR_PIN28_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2465	#define GPIO_DIRCLR_PIN28_Clear (1UL) /!< Set pin as input. /
<>	144:ef7eb2e8f9f7	2466
<>	144:ef7eb2e8f9f7	2467	/* Bit 27 : Set as input pin 27. */
<>	144:ef7eb2e8f9f7	2468	#define GPIO_DIRCLR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
<>	144:ef7eb2e8f9f7	2469	#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /!< Bit mask of PIN27 field. /
<>	144:ef7eb2e8f9f7	2470	#define GPIO_DIRCLR_PIN27_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2471	#define GPIO_DIRCLR_PIN27_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2472	#define GPIO_DIRCLR_PIN27_Clear (1UL) /!< Set pin as input. /
<>	144:ef7eb2e8f9f7	2473
<>	144:ef7eb2e8f9f7	2474	/* Bit 26 : Set as input pin 26. */
<>	144:ef7eb2e8f9f7	2475	#define GPIO_DIRCLR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
<>	144:ef7eb2e8f9f7	2476	#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /!< Bit mask of PIN26 field. /
<>	144:ef7eb2e8f9f7	2477	#define GPIO_DIRCLR_PIN26_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2478	#define GPIO_DIRCLR_PIN26_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2479	#define GPIO_DIRCLR_PIN26_Clear (1UL) /!< Set pin as input. /
<>	144:ef7eb2e8f9f7	2480
<>	144:ef7eb2e8f9f7	2481	/* Bit 25 : Set as input pin 25. */
<>	144:ef7eb2e8f9f7	2482	#define GPIO_DIRCLR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
<>	144:ef7eb2e8f9f7	2483	#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /!< Bit mask of PIN25 field. /
<>	144:ef7eb2e8f9f7	2484	#define GPIO_DIRCLR_PIN25_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2485	#define GPIO_DIRCLR_PIN25_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2486	#define GPIO_DIRCLR_PIN25_Clear (1UL) /!< Set pin as input. /
<>	144:ef7eb2e8f9f7	2487
<>	144:ef7eb2e8f9f7	2488	/* Bit 24 : Set as input pin 24. */
<>	144:ef7eb2e8f9f7	2489	#define GPIO_DIRCLR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
<>	144:ef7eb2e8f9f7	2490	#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /!< Bit mask of PIN24 field. /
<>	144:ef7eb2e8f9f7	2491	#define GPIO_DIRCLR_PIN24_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2492	#define GPIO_DIRCLR_PIN24_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2493	#define GPIO_DIRCLR_PIN24_Clear (1UL) /!< Set pin as input. /
<>	144:ef7eb2e8f9f7	2494
<>	144:ef7eb2e8f9f7	2495	/* Bit 23 : Set as input pin 23. */
<>	144:ef7eb2e8f9f7	2496	#define GPIO_DIRCLR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
<>	144:ef7eb2e8f9f7	2497	#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /!< Bit mask of PIN23 field. /
<>	144:ef7eb2e8f9f7	2498	#define GPIO_DIRCLR_PIN23_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2499	#define GPIO_DIRCLR_PIN23_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2500	#define GPIO_DIRCLR_PIN23_Clear (1UL) /!< Set pin as input. /
<>	144:ef7eb2e8f9f7	2501
<>	144:ef7eb2e8f9f7	2502	/* Bit 22 : Set as input pin 22. */
<>	144:ef7eb2e8f9f7	2503	#define GPIO_DIRCLR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
<>	144:ef7eb2e8f9f7	2504	#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /!< Bit mask of PIN22 field. /
<>	144:ef7eb2e8f9f7	2505	#define GPIO_DIRCLR_PIN22_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2506	#define GPIO_DIRCLR_PIN22_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2507	#define GPIO_DIRCLR_PIN22_Clear (1UL) /!< Set pin as input. /
<>	144:ef7eb2e8f9f7	2508
<>	144:ef7eb2e8f9f7	2509	/* Bit 21 : Set as input pin 21. */
<>	144:ef7eb2e8f9f7	2510	#define GPIO_DIRCLR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
<>	144:ef7eb2e8f9f7	2511	#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /!< Bit mask of PIN21 field. /
<>	144:ef7eb2e8f9f7	2512	#define GPIO_DIRCLR_PIN21_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2513	#define GPIO_DIRCLR_PIN21_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2514	#define GPIO_DIRCLR_PIN21_Clear (1UL) /!< Set pin as input. /
<>	144:ef7eb2e8f9f7	2515
<>	144:ef7eb2e8f9f7	2516	/* Bit 20 : Set as input pin 20. */
<>	144:ef7eb2e8f9f7	2517	#define GPIO_DIRCLR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
<>	144:ef7eb2e8f9f7	2518	#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /!< Bit mask of PIN20 field. /
<>	144:ef7eb2e8f9f7	2519	#define GPIO_DIRCLR_PIN20_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2520	#define GPIO_DIRCLR_PIN20_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2521	#define GPIO_DIRCLR_PIN20_Clear (1UL) /!< Set pin as input. /
<>	144:ef7eb2e8f9f7	2522
<>	144:ef7eb2e8f9f7	2523	/* Bit 19 : Set as input pin 19. */
<>	144:ef7eb2e8f9f7	2524	#define GPIO_DIRCLR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
<>	144:ef7eb2e8f9f7	2525	#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /!< Bit mask of PIN19 field. /
<>	144:ef7eb2e8f9f7	2526	#define GPIO_DIRCLR_PIN19_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2527	#define GPIO_DIRCLR_PIN19_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2528	#define GPIO_DIRCLR_PIN19_Clear (1UL) /!< Set pin as input. /
<>	144:ef7eb2e8f9f7	2529
<>	144:ef7eb2e8f9f7	2530	/* Bit 18 : Set as input pin 18. */
<>	144:ef7eb2e8f9f7	2531	#define GPIO_DIRCLR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
<>	144:ef7eb2e8f9f7	2532	#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /!< Bit mask of PIN18 field. /
<>	144:ef7eb2e8f9f7	2533	#define GPIO_DIRCLR_PIN18_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2534	#define GPIO_DIRCLR_PIN18_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2535	#define GPIO_DIRCLR_PIN18_Clear (1UL) /!< Set pin as input. /
<>	144:ef7eb2e8f9f7	2536
<>	144:ef7eb2e8f9f7	2537	/* Bit 17 : Set as input pin 17. */
<>	144:ef7eb2e8f9f7	2538	#define GPIO_DIRCLR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
<>	144:ef7eb2e8f9f7	2539	#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /!< Bit mask of PIN17 field. /
<>	144:ef7eb2e8f9f7	2540	#define GPIO_DIRCLR_PIN17_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2541	#define GPIO_DIRCLR_PIN17_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2542	#define GPIO_DIRCLR_PIN17_Clear (1UL) /!< Set pin as input. /
<>	144:ef7eb2e8f9f7	2543
<>	144:ef7eb2e8f9f7	2544	/* Bit 16 : Set as input pin 16. */
<>	144:ef7eb2e8f9f7	2545	#define GPIO_DIRCLR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
<>	144:ef7eb2e8f9f7	2546	#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /!< Bit mask of PIN16 field. /
<>	144:ef7eb2e8f9f7	2547	#define GPIO_DIRCLR_PIN16_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2548	#define GPIO_DIRCLR_PIN16_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2549	#define GPIO_DIRCLR_PIN16_Clear (1UL) /!< Set pin as input. /
<>	144:ef7eb2e8f9f7	2550
<>	144:ef7eb2e8f9f7	2551	/* Bit 15 : Set as input pin 15. */
<>	144:ef7eb2e8f9f7	2552	#define GPIO_DIRCLR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
<>	144:ef7eb2e8f9f7	2553	#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /!< Bit mask of PIN15 field. /
<>	144:ef7eb2e8f9f7	2554	#define GPIO_DIRCLR_PIN15_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2555	#define GPIO_DIRCLR_PIN15_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2556	#define GPIO_DIRCLR_PIN15_Clear (1UL) /!< Set pin as input. /
<>	144:ef7eb2e8f9f7	2557
<>	144:ef7eb2e8f9f7	2558	/* Bit 14 : Set as input pin 14. */
<>	144:ef7eb2e8f9f7	2559	#define GPIO_DIRCLR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
<>	144:ef7eb2e8f9f7	2560	#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /!< Bit mask of PIN14 field. /
<>	144:ef7eb2e8f9f7	2561	#define GPIO_DIRCLR_PIN14_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2562	#define GPIO_DIRCLR_PIN14_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2563	#define GPIO_DIRCLR_PIN14_Clear (1UL) /!< Set pin as input. /
<>	144:ef7eb2e8f9f7	2564
<>	144:ef7eb2e8f9f7	2565	/* Bit 13 : Set as input pin 13. */
<>	144:ef7eb2e8f9f7	2566	#define GPIO_DIRCLR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
<>	144:ef7eb2e8f9f7	2567	#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /!< Bit mask of PIN13 field. /
<>	144:ef7eb2e8f9f7	2568	#define GPIO_DIRCLR_PIN13_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2569	#define GPIO_DIRCLR_PIN13_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2570	#define GPIO_DIRCLR_PIN13_Clear (1UL) /!< Set pin as input. /
<>	144:ef7eb2e8f9f7	2571
<>	144:ef7eb2e8f9f7	2572	/* Bit 12 : Set as input pin 12. */
<>	144:ef7eb2e8f9f7	2573	#define GPIO_DIRCLR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
<>	144:ef7eb2e8f9f7	2574	#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /!< Bit mask of PIN12 field. /
<>	144:ef7eb2e8f9f7	2575	#define GPIO_DIRCLR_PIN12_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2576	#define GPIO_DIRCLR_PIN12_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2577	#define GPIO_DIRCLR_PIN12_Clear (1UL) /!< Set pin as input. /
<>	144:ef7eb2e8f9f7	2578
<>	144:ef7eb2e8f9f7	2579	/* Bit 11 : Set as input pin 11. */
<>	144:ef7eb2e8f9f7	2580	#define GPIO_DIRCLR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
<>	144:ef7eb2e8f9f7	2581	#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /!< Bit mask of PIN11 field. /
<>	144:ef7eb2e8f9f7	2582	#define GPIO_DIRCLR_PIN11_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2583	#define GPIO_DIRCLR_PIN11_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2584	#define GPIO_DIRCLR_PIN11_Clear (1UL) /!< Set pin as input. /
<>	144:ef7eb2e8f9f7	2585
<>	144:ef7eb2e8f9f7	2586	/* Bit 10 : Set as input pin 10. */
<>	144:ef7eb2e8f9f7	2587	#define GPIO_DIRCLR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
<>	144:ef7eb2e8f9f7	2588	#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /!< Bit mask of PIN10 field. /
<>	144:ef7eb2e8f9f7	2589	#define GPIO_DIRCLR_PIN10_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2590	#define GPIO_DIRCLR_PIN10_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2591	#define GPIO_DIRCLR_PIN10_Clear (1UL) /!< Set pin as input. /
<>	144:ef7eb2e8f9f7	2592
<>	144:ef7eb2e8f9f7	2593	/* Bit 9 : Set as input pin 9. */
<>	144:ef7eb2e8f9f7	2594	#define GPIO_DIRCLR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
<>	144:ef7eb2e8f9f7	2595	#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /!< Bit mask of PIN9 field. /
<>	144:ef7eb2e8f9f7	2596	#define GPIO_DIRCLR_PIN9_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2597	#define GPIO_DIRCLR_PIN9_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2598	#define GPIO_DIRCLR_PIN9_Clear (1UL) /!< Set pin as input. /
<>	144:ef7eb2e8f9f7	2599
<>	144:ef7eb2e8f9f7	2600	/* Bit 8 : Set as input pin 8. */
<>	144:ef7eb2e8f9f7	2601	#define GPIO_DIRCLR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
<>	144:ef7eb2e8f9f7	2602	#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /!< Bit mask of PIN8 field. /
<>	144:ef7eb2e8f9f7	2603	#define GPIO_DIRCLR_PIN8_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2604	#define GPIO_DIRCLR_PIN8_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2605	#define GPIO_DIRCLR_PIN8_Clear (1UL) /!< Set pin as input. /
<>	144:ef7eb2e8f9f7	2606
<>	144:ef7eb2e8f9f7	2607	/* Bit 7 : Set as input pin 7. */
<>	144:ef7eb2e8f9f7	2608	#define GPIO_DIRCLR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
<>	144:ef7eb2e8f9f7	2609	#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /!< Bit mask of PIN7 field. /
<>	144:ef7eb2e8f9f7	2610	#define GPIO_DIRCLR_PIN7_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2611	#define GPIO_DIRCLR_PIN7_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2612	#define GPIO_DIRCLR_PIN7_Clear (1UL) /!< Set pin as input. /
<>	144:ef7eb2e8f9f7	2613
<>	144:ef7eb2e8f9f7	2614	/* Bit 6 : Set as input pin 6. */
<>	144:ef7eb2e8f9f7	2615	#define GPIO_DIRCLR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
<>	144:ef7eb2e8f9f7	2616	#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /!< Bit mask of PIN6 field. /
<>	144:ef7eb2e8f9f7	2617	#define GPIO_DIRCLR_PIN6_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2618	#define GPIO_DIRCLR_PIN6_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2619	#define GPIO_DIRCLR_PIN6_Clear (1UL) /!< Set pin as input. /
<>	144:ef7eb2e8f9f7	2620
<>	144:ef7eb2e8f9f7	2621	/* Bit 5 : Set as input pin 5. */
<>	144:ef7eb2e8f9f7	2622	#define GPIO_DIRCLR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
<>	144:ef7eb2e8f9f7	2623	#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /!< Bit mask of PIN5 field. /
<>	144:ef7eb2e8f9f7	2624	#define GPIO_DIRCLR_PIN5_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2625	#define GPIO_DIRCLR_PIN5_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2626	#define GPIO_DIRCLR_PIN5_Clear (1UL) /!< Set pin as input. /
<>	144:ef7eb2e8f9f7	2627
<>	144:ef7eb2e8f9f7	2628	/* Bit 4 : Set as input pin 4. */
<>	144:ef7eb2e8f9f7	2629	#define GPIO_DIRCLR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
<>	144:ef7eb2e8f9f7	2630	#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /!< Bit mask of PIN4 field. /
<>	144:ef7eb2e8f9f7	2631	#define GPIO_DIRCLR_PIN4_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2632	#define GPIO_DIRCLR_PIN4_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2633	#define GPIO_DIRCLR_PIN4_Clear (1UL) /!< Set pin as input. /
<>	144:ef7eb2e8f9f7	2634
<>	144:ef7eb2e8f9f7	2635	/* Bit 3 : Set as input pin 3. */
<>	144:ef7eb2e8f9f7	2636	#define GPIO_DIRCLR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
<>	144:ef7eb2e8f9f7	2637	#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /!< Bit mask of PIN3 field. /
<>	144:ef7eb2e8f9f7	2638	#define GPIO_DIRCLR_PIN3_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2639	#define GPIO_DIRCLR_PIN3_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2640	#define GPIO_DIRCLR_PIN3_Clear (1UL) /!< Set pin as input. /
<>	144:ef7eb2e8f9f7	2641
<>	144:ef7eb2e8f9f7	2642	/* Bit 2 : Set as input pin 2. */
<>	144:ef7eb2e8f9f7	2643	#define GPIO_DIRCLR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
<>	144:ef7eb2e8f9f7	2644	#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /!< Bit mask of PIN2 field. /
<>	144:ef7eb2e8f9f7	2645	#define GPIO_DIRCLR_PIN2_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2646	#define GPIO_DIRCLR_PIN2_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2647	#define GPIO_DIRCLR_PIN2_Clear (1UL) /!< Set pin as input. /
<>	144:ef7eb2e8f9f7	2648
<>	144:ef7eb2e8f9f7	2649	/* Bit 1 : Set as input pin 1. */
<>	144:ef7eb2e8f9f7	2650	#define GPIO_DIRCLR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
<>	144:ef7eb2e8f9f7	2651	#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /!< Bit mask of PIN1 field. /
<>	144:ef7eb2e8f9f7	2652	#define GPIO_DIRCLR_PIN1_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2653	#define GPIO_DIRCLR_PIN1_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2654	#define GPIO_DIRCLR_PIN1_Clear (1UL) /!< Set pin as input. /
<>	144:ef7eb2e8f9f7	2655
<>	144:ef7eb2e8f9f7	2656	/* Bit 0 : Set as input pin 0. */
<>	144:ef7eb2e8f9f7	2657	#define GPIO_DIRCLR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
<>	144:ef7eb2e8f9f7	2658	#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /!< Bit mask of PIN0 field. /
<>	144:ef7eb2e8f9f7	2659	#define GPIO_DIRCLR_PIN0_Input (0UL) /!< Pin set as input. /
<>	144:ef7eb2e8f9f7	2660	#define GPIO_DIRCLR_PIN0_Output (1UL) /!< Pin set as output. /
<>	144:ef7eb2e8f9f7	2661	#define GPIO_DIRCLR_PIN0_Clear (1UL) /!< Set pin as input. /
<>	144:ef7eb2e8f9f7	2662
<>	144:ef7eb2e8f9f7	2663	/* Register: GPIO_PIN_CNF */
<>	144:ef7eb2e8f9f7	2664	/* Description: Configuration of GPIO pins. */
<>	144:ef7eb2e8f9f7	2665
<>	144:ef7eb2e8f9f7	2666	/* Bits 17..16 : Pin sensing mechanism. */
<>	144:ef7eb2e8f9f7	2667	#define GPIO_PIN_CNF_SENSE_Pos (16UL) /!< Position of SENSE field. /
<>	144:ef7eb2e8f9f7	2668	#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /!< Bit mask of SENSE field. /
<>	144:ef7eb2e8f9f7	2669	#define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /!< Disabled. /
<>	144:ef7eb2e8f9f7	2670	#define GPIO_PIN_CNF_SENSE_High (0x02UL) /!< Wakeup on high level. /
<>	144:ef7eb2e8f9f7	2671	#define GPIO_PIN_CNF_SENSE_Low (0x03UL) /!< Wakeup on low level. /
<>	144:ef7eb2e8f9f7	2672
<>	144:ef7eb2e8f9f7	2673	/* Bits 10..8 : Drive configuration. */
<>	144:ef7eb2e8f9f7	2674	#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /!< Position of DRIVE field. /
<>	144:ef7eb2e8f9f7	2675	#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /!< Bit mask of DRIVE field. /
<>	144:ef7eb2e8f9f7	2676	#define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /!< Standard '0', Standard '1'. /
<>	144:ef7eb2e8f9f7	2677	#define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /!< High '0', Standard '1'. /
<>	144:ef7eb2e8f9f7	2678	#define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /!< Standard '0', High '1'. /
<>	144:ef7eb2e8f9f7	2679	#define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /!< High '0', High '1'. /
<>	144:ef7eb2e8f9f7	2680	#define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /!< Disconnected '0', Standard '1'. /
<>	144:ef7eb2e8f9f7	2681	#define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /!< Disconnected '0', High '1'. /
<>	144:ef7eb2e8f9f7	2682	#define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /!< Standard '0', Disconnected '1'. /
<>	144:ef7eb2e8f9f7	2683	#define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /!< High '0', Disconnected '1'. /
<>	144:ef7eb2e8f9f7	2684
<>	144:ef7eb2e8f9f7	2685	/* Bits 3..2 : Pull-up or -down configuration. */
<>	144:ef7eb2e8f9f7	2686	#define GPIO_PIN_CNF_PULL_Pos (2UL) /!< Position of PULL field. /
<>	144:ef7eb2e8f9f7	2687	#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /!< Bit mask of PULL field. /
<>	144:ef7eb2e8f9f7	2688	#define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /!< No pull. /
<>	144:ef7eb2e8f9f7	2689	#define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /!< Pulldown on pin. /
<>	144:ef7eb2e8f9f7	2690	#define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /!< Pullup on pin. /
<>	144:ef7eb2e8f9f7	2691
<>	144:ef7eb2e8f9f7	2692	/* Bit 1 : Connect or disconnect input path. */
<>	144:ef7eb2e8f9f7	2693	#define GPIO_PIN_CNF_INPUT_Pos (1UL) /!< Position of INPUT field. /
<>	144:ef7eb2e8f9f7	2694	#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /!< Bit mask of INPUT field. /
<>	144:ef7eb2e8f9f7	2695	#define GPIO_PIN_CNF_INPUT_Connect (0UL) /!< Connect input pin. /
<>	144:ef7eb2e8f9f7	2696	#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /!< Disconnect input pin. /
<>	144:ef7eb2e8f9f7	2697
<>	144:ef7eb2e8f9f7	2698	/* Bit 0 : Pin direction. */
<>	144:ef7eb2e8f9f7	2699	#define GPIO_PIN_CNF_DIR_Pos (0UL) /!< Position of DIR field. /
<>	144:ef7eb2e8f9f7	2700	#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /!< Bit mask of DIR field. /
<>	144:ef7eb2e8f9f7	2701	#define GPIO_PIN_CNF_DIR_Input (0UL) /!< Configure pin as an input pin. /
<>	144:ef7eb2e8f9f7	2702	#define GPIO_PIN_CNF_DIR_Output (1UL) /!< Configure pin as an output pin. /
<>	144:ef7eb2e8f9f7	2703
<>	144:ef7eb2e8f9f7	2704
<>	144:ef7eb2e8f9f7	2705	/* Peripheral: GPIOTE */
<>	144:ef7eb2e8f9f7	2706	/* Description: GPIO tasks and events. */
<>	144:ef7eb2e8f9f7	2707
<>	144:ef7eb2e8f9f7	2708	/* Register: GPIOTE_INTENSET */
<>	144:ef7eb2e8f9f7	2709	/* Description: Interrupt enable set register. */
<>	144:ef7eb2e8f9f7	2710
<>	144:ef7eb2e8f9f7	2711	/* Bit 31 : Enable interrupt on PORT event. */
<>	144:ef7eb2e8f9f7	2712	#define GPIOTE_INTENSET_PORT_Pos (31UL) /!< Position of PORT field. /
<>	144:ef7eb2e8f9f7	2713	#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /!< Bit mask of PORT field. /
<>	144:ef7eb2e8f9f7	2714	#define GPIOTE_INTENSET_PORT_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	2715	#define GPIOTE_INTENSET_PORT_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	2716	#define GPIOTE_INTENSET_PORT_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	2717
<>	144:ef7eb2e8f9f7	2718	/* Bit 3 : Enable interrupt on IN[3] event. */
<>	144:ef7eb2e8f9f7	2719	#define GPIOTE_INTENSET_IN3_Pos (3UL) /!< Position of IN3 field. /
<>	144:ef7eb2e8f9f7	2720	#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /!< Bit mask of IN3 field. /
<>	144:ef7eb2e8f9f7	2721	#define GPIOTE_INTENSET_IN3_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	2722	#define GPIOTE_INTENSET_IN3_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	2723	#define GPIOTE_INTENSET_IN3_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	2724
<>	144:ef7eb2e8f9f7	2725	/* Bit 2 : Enable interrupt on IN[2] event. */
<>	144:ef7eb2e8f9f7	2726	#define GPIOTE_INTENSET_IN2_Pos (2UL) /!< Position of IN2 field. /
<>	144:ef7eb2e8f9f7	2727	#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /!< Bit mask of IN2 field. /
<>	144:ef7eb2e8f9f7	2728	#define GPIOTE_INTENSET_IN2_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	2729	#define GPIOTE_INTENSET_IN2_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	2730	#define GPIOTE_INTENSET_IN2_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	2731
<>	144:ef7eb2e8f9f7	2732	/* Bit 1 : Enable interrupt on IN[1] event. */
<>	144:ef7eb2e8f9f7	2733	#define GPIOTE_INTENSET_IN1_Pos (1UL) /!< Position of IN1 field. /
<>	144:ef7eb2e8f9f7	2734	#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /!< Bit mask of IN1 field. /
<>	144:ef7eb2e8f9f7	2735	#define GPIOTE_INTENSET_IN1_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	2736	#define GPIOTE_INTENSET_IN1_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	2737	#define GPIOTE_INTENSET_IN1_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	2738
<>	144:ef7eb2e8f9f7	2739	/* Bit 0 : Enable interrupt on IN[0] event. */
<>	144:ef7eb2e8f9f7	2740	#define GPIOTE_INTENSET_IN0_Pos (0UL) /!< Position of IN0 field. /
<>	144:ef7eb2e8f9f7	2741	#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /!< Bit mask of IN0 field. /
<>	144:ef7eb2e8f9f7	2742	#define GPIOTE_INTENSET_IN0_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	2743	#define GPIOTE_INTENSET_IN0_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	2744	#define GPIOTE_INTENSET_IN0_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	2745
<>	144:ef7eb2e8f9f7	2746	/* Register: GPIOTE_INTENCLR */
<>	144:ef7eb2e8f9f7	2747	/* Description: Interrupt enable clear register. */
<>	144:ef7eb2e8f9f7	2748
<>	144:ef7eb2e8f9f7	2749	/* Bit 31 : Disable interrupt on PORT event. */
<>	144:ef7eb2e8f9f7	2750	#define GPIOTE_INTENCLR_PORT_Pos (31UL) /!< Position of PORT field. /
<>	144:ef7eb2e8f9f7	2751	#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /!< Bit mask of PORT field. /
<>	144:ef7eb2e8f9f7	2752	#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	2753	#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	2754	#define GPIOTE_INTENCLR_PORT_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	2755
<>	144:ef7eb2e8f9f7	2756	/* Bit 3 : Disable interrupt on IN[3] event. */
<>	144:ef7eb2e8f9f7	2757	#define GPIOTE_INTENCLR_IN3_Pos (3UL) /!< Position of IN3 field. /
<>	144:ef7eb2e8f9f7	2758	#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /!< Bit mask of IN3 field. /
<>	144:ef7eb2e8f9f7	2759	#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	2760	#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	2761	#define GPIOTE_INTENCLR_IN3_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	2762
<>	144:ef7eb2e8f9f7	2763	/* Bit 2 : Disable interrupt on IN[2] event. */
<>	144:ef7eb2e8f9f7	2764	#define GPIOTE_INTENCLR_IN2_Pos (2UL) /!< Position of IN2 field. /
<>	144:ef7eb2e8f9f7	2765	#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /!< Bit mask of IN2 field. /
<>	144:ef7eb2e8f9f7	2766	#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	2767	#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	2768	#define GPIOTE_INTENCLR_IN2_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	2769
<>	144:ef7eb2e8f9f7	2770	/* Bit 1 : Disable interrupt on IN[1] event. */
<>	144:ef7eb2e8f9f7	2771	#define GPIOTE_INTENCLR_IN1_Pos (1UL) /!< Position of IN1 field. /
<>	144:ef7eb2e8f9f7	2772	#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /!< Bit mask of IN1 field. /
<>	144:ef7eb2e8f9f7	2773	#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	2774	#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	2775	#define GPIOTE_INTENCLR_IN1_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	2776
<>	144:ef7eb2e8f9f7	2777	/* Bit 0 : Disable interrupt on IN[0] event. */
<>	144:ef7eb2e8f9f7	2778	#define GPIOTE_INTENCLR_IN0_Pos (0UL) /!< Position of IN0 field. /
<>	144:ef7eb2e8f9f7	2779	#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /!< Bit mask of IN0 field. /
<>	144:ef7eb2e8f9f7	2780	#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	2781	#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	2782	#define GPIOTE_INTENCLR_IN0_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	2783
<>	144:ef7eb2e8f9f7	2784	/* Register: GPIOTE_CONFIG */
<>	144:ef7eb2e8f9f7	2785	/* Description: Channel configuration registers. */
<>	144:ef7eb2e8f9f7	2786
<>	144:ef7eb2e8f9f7	2787	/* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */
<>	144:ef7eb2e8f9f7	2788	#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /!< Position of OUTINIT field. /
<>	144:ef7eb2e8f9f7	2789	#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /!< Bit mask of OUTINIT field. /
<>	144:ef7eb2e8f9f7	2790	#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /!< Initial low output when in task mode. /
<>	144:ef7eb2e8f9f7	2791	#define GPIOTE_CONFIG_OUTINIT_High (1UL) /!< Initial high output when in task mode. /
<>	144:ef7eb2e8f9f7	2792
<>	144:ef7eb2e8f9f7	2793	/* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */
<>	144:ef7eb2e8f9f7	2794	#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /!< Position of POLARITY field. /
<>	144:ef7eb2e8f9f7	2795	#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /!< Bit mask of POLARITY field. /
<>	144:ef7eb2e8f9f7	2796	#define GPIOTE_CONFIG_POLARITY_None (0x00UL) /!< No task or event. /
<>	144:ef7eb2e8f9f7	2797	#define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /!< Low to high. /
<>	144:ef7eb2e8f9f7	2798	#define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /!< High to low. /
<>	144:ef7eb2e8f9f7	2799	#define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /!< Toggle. /
<>	144:ef7eb2e8f9f7	2800
<>	144:ef7eb2e8f9f7	2801	/* Bits 12..8 : Pin select. */
<>	144:ef7eb2e8f9f7	2802	#define GPIOTE_CONFIG_PSEL_Pos (8UL) /!< Position of PSEL field. /
<>	144:ef7eb2e8f9f7	2803	#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /!< Bit mask of PSEL field. /
<>	144:ef7eb2e8f9f7	2804
<>	144:ef7eb2e8f9f7	2805	/* Bits 1..0 : Mode */
<>	144:ef7eb2e8f9f7	2806	#define GPIOTE_CONFIG_MODE_Pos (0UL) /!< Position of MODE field. /
<>	144:ef7eb2e8f9f7	2807	#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /!< Bit mask of MODE field. /
<>	144:ef7eb2e8f9f7	2808	#define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /!< Disabled. /
<>	144:ef7eb2e8f9f7	2809	#define GPIOTE_CONFIG_MODE_Event (0x01UL) /!< Channel configure in event mode. /
<>	144:ef7eb2e8f9f7	2810	#define GPIOTE_CONFIG_MODE_Task (0x03UL) /!< Channel configure in task mode. /
<>	144:ef7eb2e8f9f7	2811
<>	144:ef7eb2e8f9f7	2812	/* Register: GPIOTE_POWER */
<>	144:ef7eb2e8f9f7	2813	/* Description: Peripheral power control. */
<>	144:ef7eb2e8f9f7	2814
<>	144:ef7eb2e8f9f7	2815	/* Bit 0 : Peripheral power control. */
<>	144:ef7eb2e8f9f7	2816	#define GPIOTE_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
<>	144:ef7eb2e8f9f7	2817	#define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /!< Bit mask of POWER field. /
<>	144:ef7eb2e8f9f7	2818	#define GPIOTE_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
<>	144:ef7eb2e8f9f7	2819	#define GPIOTE_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
<>	144:ef7eb2e8f9f7	2820
<>	144:ef7eb2e8f9f7	2821
<>	144:ef7eb2e8f9f7	2822	/* Peripheral: LPCOMP */
<>	144:ef7eb2e8f9f7	2823	/* Description: Low power comparator. */
<>	144:ef7eb2e8f9f7	2824
<>	144:ef7eb2e8f9f7	2825	/* Register: LPCOMP_SHORTS */
<>	144:ef7eb2e8f9f7	2826	/* Description: Shortcuts for the LPCOMP. */
<>	144:ef7eb2e8f9f7	2827
<>	144:ef7eb2e8f9f7	2828	/* Bit 4 : Shortcut between CROSS event and STOP task. */
<>	144:ef7eb2e8f9f7	2829	#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /!< Position of CROSS_STOP field. /
<>	144:ef7eb2e8f9f7	2830	#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /!< Bit mask of CROSS_STOP field. /
<>	144:ef7eb2e8f9f7	2831	#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /!< Shortcut disabled. /
<>	144:ef7eb2e8f9f7	2832	#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /!< Shortcut enabled. /
<>	144:ef7eb2e8f9f7	2833
<>	144:ef7eb2e8f9f7	2834	/* Bit 3 : Shortcut between UP event and STOP task. */
<>	144:ef7eb2e8f9f7	2835	#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /!< Position of UP_STOP field. /
<>	144:ef7eb2e8f9f7	2836	#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /!< Bit mask of UP_STOP field. /
<>	144:ef7eb2e8f9f7	2837	#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /!< Shortcut disabled. /
<>	144:ef7eb2e8f9f7	2838	#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /!< Shortcut enabled. /
<>	144:ef7eb2e8f9f7	2839
<>	144:ef7eb2e8f9f7	2840	/* Bit 2 : Shortcut between DOWN event and STOP task. */
<>	144:ef7eb2e8f9f7	2841	#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /!< Position of DOWN_STOP field. /
<>	144:ef7eb2e8f9f7	2842	#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /!< Bit mask of DOWN_STOP field. /
<>	144:ef7eb2e8f9f7	2843	#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /!< Shortcut disabled. /
<>	144:ef7eb2e8f9f7	2844	#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /!< Shortcut enabled. /
<>	144:ef7eb2e8f9f7	2845
<>	144:ef7eb2e8f9f7	2846	/* Bit 1 : Shortcut between RADY event and STOP task. */
<>	144:ef7eb2e8f9f7	2847	#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /!< Position of READY_STOP field. /
<>	144:ef7eb2e8f9f7	2848	#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /!< Bit mask of READY_STOP field. /
<>	144:ef7eb2e8f9f7	2849	#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /!< Shortcut disabled. /
<>	144:ef7eb2e8f9f7	2850	#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /!< Shortcut enabled. /
<>	144:ef7eb2e8f9f7	2851
<>	144:ef7eb2e8f9f7	2852	/* Bit 0 : Shortcut between READY event and SAMPLE task. */
<>	144:ef7eb2e8f9f7	2853	#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /!< Position of READY_SAMPLE field. /
<>	144:ef7eb2e8f9f7	2854	#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /!< Bit mask of READY_SAMPLE field. /
<>	144:ef7eb2e8f9f7	2855	#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /!< Shortcut disabled. /
<>	144:ef7eb2e8f9f7	2856	#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /!< Shortcut enabled. /
<>	144:ef7eb2e8f9f7	2857
<>	144:ef7eb2e8f9f7	2858	/* Register: LPCOMP_INTENSET */
<>	144:ef7eb2e8f9f7	2859	/* Description: Interrupt enable set register. */
<>	144:ef7eb2e8f9f7	2860
<>	144:ef7eb2e8f9f7	2861	/* Bit 3 : Enable interrupt on CROSS event. */
<>	144:ef7eb2e8f9f7	2862	#define LPCOMP_INTENSET_CROSS_Pos (3UL) /!< Position of CROSS field. /
<>	144:ef7eb2e8f9f7	2863	#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /!< Bit mask of CROSS field. /
<>	144:ef7eb2e8f9f7	2864	#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	2865	#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	2866	#define LPCOMP_INTENSET_CROSS_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	2867
<>	144:ef7eb2e8f9f7	2868	/* Bit 2 : Enable interrupt on UP event. */
<>	144:ef7eb2e8f9f7	2869	#define LPCOMP_INTENSET_UP_Pos (2UL) /!< Position of UP field. /
<>	144:ef7eb2e8f9f7	2870	#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /!< Bit mask of UP field. /
<>	144:ef7eb2e8f9f7	2871	#define LPCOMP_INTENSET_UP_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	2872	#define LPCOMP_INTENSET_UP_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	2873	#define LPCOMP_INTENSET_UP_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	2874
<>	144:ef7eb2e8f9f7	2875	/* Bit 1 : Enable interrupt on DOWN event. */
<>	144:ef7eb2e8f9f7	2876	#define LPCOMP_INTENSET_DOWN_Pos (1UL) /!< Position of DOWN field. /
<>	144:ef7eb2e8f9f7	2877	#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /!< Bit mask of DOWN field. /
<>	144:ef7eb2e8f9f7	2878	#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	2879	#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	2880	#define LPCOMP_INTENSET_DOWN_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	2881
<>	144:ef7eb2e8f9f7	2882	/* Bit 0 : Enable interrupt on READY event. */
<>	144:ef7eb2e8f9f7	2883	#define LPCOMP_INTENSET_READY_Pos (0UL) /!< Position of READY field. /
<>	144:ef7eb2e8f9f7	2884	#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /!< Bit mask of READY field. /
<>	144:ef7eb2e8f9f7	2885	#define LPCOMP_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	2886	#define LPCOMP_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	2887	#define LPCOMP_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	2888
<>	144:ef7eb2e8f9f7	2889	/* Register: LPCOMP_INTENCLR */
<>	144:ef7eb2e8f9f7	2890	/* Description: Interrupt enable clear register. */
<>	144:ef7eb2e8f9f7	2891
<>	144:ef7eb2e8f9f7	2892	/* Bit 3 : Disable interrupt on CROSS event. */
<>	144:ef7eb2e8f9f7	2893	#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /!< Position of CROSS field. /
<>	144:ef7eb2e8f9f7	2894	#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /!< Bit mask of CROSS field. /
<>	144:ef7eb2e8f9f7	2895	#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	2896	#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	2897	#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	2898
<>	144:ef7eb2e8f9f7	2899	/* Bit 2 : Disable interrupt on UP event. */
<>	144:ef7eb2e8f9f7	2900	#define LPCOMP_INTENCLR_UP_Pos (2UL) /!< Position of UP field. /
<>	144:ef7eb2e8f9f7	2901	#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /!< Bit mask of UP field. /
<>	144:ef7eb2e8f9f7	2902	#define LPCOMP_INTENCLR_UP_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	2903	#define LPCOMP_INTENCLR_UP_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	2904	#define LPCOMP_INTENCLR_UP_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	2905
<>	144:ef7eb2e8f9f7	2906	/* Bit 1 : Disable interrupt on DOWN event. */
<>	144:ef7eb2e8f9f7	2907	#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /!< Position of DOWN field. /
<>	144:ef7eb2e8f9f7	2908	#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /!< Bit mask of DOWN field. /
<>	144:ef7eb2e8f9f7	2909	#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	2910	#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	2911	#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	2912
<>	144:ef7eb2e8f9f7	2913	/* Bit 0 : Disable interrupt on READY event. */
<>	144:ef7eb2e8f9f7	2914	#define LPCOMP_INTENCLR_READY_Pos (0UL) /!< Position of READY field. /
<>	144:ef7eb2e8f9f7	2915	#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
<>	144:ef7eb2e8f9f7	2916	#define LPCOMP_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	2917	#define LPCOMP_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	2918	#define LPCOMP_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	2919
<>	144:ef7eb2e8f9f7	2920	/* Register: LPCOMP_RESULT */
<>	144:ef7eb2e8f9f7	2921	/* Description: Result of last compare. */
<>	144:ef7eb2e8f9f7	2922
<>	144:ef7eb2e8f9f7	2923	/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
<>	144:ef7eb2e8f9f7	2924	#define LPCOMP_RESULT_RESULT_Pos (0UL) /!< Position of RESULT field. /
<>	144:ef7eb2e8f9f7	2925	#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /!< Bit mask of RESULT field. /
<>	144:ef7eb2e8f9f7	2926	#define LPCOMP_RESULT_RESULT_Bellow (0UL) /!< Input voltage is bellow the reference threshold. /
<>	144:ef7eb2e8f9f7	2927	#define LPCOMP_RESULT_RESULT_Above (1UL) /!< Input voltage is above the reference threshold. /
<>	144:ef7eb2e8f9f7	2928
<>	144:ef7eb2e8f9f7	2929	/* Register: LPCOMP_ENABLE */
<>	144:ef7eb2e8f9f7	2930	/* Description: Enable the LPCOMP. */
<>	144:ef7eb2e8f9f7	2931
<>	144:ef7eb2e8f9f7	2932	/* Bits 1..0 : Enable or disable LPCOMP. */
<>	144:ef7eb2e8f9f7	2933	#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
<>	144:ef7eb2e8f9f7	2934	#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
<>	144:ef7eb2e8f9f7	2935	#define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled LPCOMP. /
<>	144:ef7eb2e8f9f7	2936	#define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /!< Enable LPCOMP. /
<>	144:ef7eb2e8f9f7	2937
<>	144:ef7eb2e8f9f7	2938	/* Register: LPCOMP_PSEL */
<>	144:ef7eb2e8f9f7	2939	/* Description: Input pin select. */
<>	144:ef7eb2e8f9f7	2940
<>	144:ef7eb2e8f9f7	2941	/* Bits 2..0 : Analog input pin select. */
<>	144:ef7eb2e8f9f7	2942	#define LPCOMP_PSEL_PSEL_Pos (0UL) /!< Position of PSEL field. /
<>	144:ef7eb2e8f9f7	2943	#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /!< Bit mask of PSEL field. /
<>	144:ef7eb2e8f9f7	2944	#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /!< Use analog input 0 as analog input. /
<>	144:ef7eb2e8f9f7	2945	#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /!< Use analog input 1 as analog input. /
<>	144:ef7eb2e8f9f7	2946	#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /!< Use analog input 2 as analog input. /
<>	144:ef7eb2e8f9f7	2947	#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /!< Use analog input 3 as analog input. /
<>	144:ef7eb2e8f9f7	2948	#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /!< Use analog input 4 as analog input. /
<>	144:ef7eb2e8f9f7	2949	#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /!< Use analog input 5 as analog input. /
<>	144:ef7eb2e8f9f7	2950	#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /!< Use analog input 6 as analog input. /
<>	144:ef7eb2e8f9f7	2951	#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /!< Use analog input 7 as analog input. /
<>	144:ef7eb2e8f9f7	2952
<>	144:ef7eb2e8f9f7	2953	/* Register: LPCOMP_REFSEL */
<>	144:ef7eb2e8f9f7	2954	/* Description: Reference select. */
<>	144:ef7eb2e8f9f7	2955
<>	144:ef7eb2e8f9f7	2956	/* Bits 2..0 : Reference select. */
<>	144:ef7eb2e8f9f7	2957	#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /!< Position of REFSEL field. /
<>	144:ef7eb2e8f9f7	2958	#define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /!< Bit mask of REFSEL field. /
<>	144:ef7eb2e8f9f7	2959	#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /!< Use supply with a 1/8 prescaler as reference. /
<>	144:ef7eb2e8f9f7	2960	#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /!< Use supply with a 2/8 prescaler as reference. /
<>	144:ef7eb2e8f9f7	2961	#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /!< Use supply with a 3/8 prescaler as reference. /
<>	144:ef7eb2e8f9f7	2962	#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /!< Use supply with a 4/8 prescaler as reference. /
<>	144:ef7eb2e8f9f7	2963	#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /!< Use supply with a 5/8 prescaler as reference. /
<>	144:ef7eb2e8f9f7	2964	#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /!< Use supply with a 6/8 prescaler as reference. /
<>	144:ef7eb2e8f9f7	2965	#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /!< Use supply with a 7/8 prescaler as reference. /
<>	144:ef7eb2e8f9f7	2966	#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /!< Use external analog reference as reference. /
<>	144:ef7eb2e8f9f7	2967
<>	144:ef7eb2e8f9f7	2968	/* Register: LPCOMP_EXTREFSEL */
<>	144:ef7eb2e8f9f7	2969	/* Description: External reference select. */
<>	144:ef7eb2e8f9f7	2970
<>	144:ef7eb2e8f9f7	2971	/* Bit 0 : External analog reference pin selection. */
<>	144:ef7eb2e8f9f7	2972	#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /!< Position of EXTREFSEL field. /
<>	144:ef7eb2e8f9f7	2973	#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /!< Bit mask of EXTREFSEL field. /
<>	144:ef7eb2e8f9f7	2974	#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /!< Use analog reference 0 as reference. /
<>	144:ef7eb2e8f9f7	2975	#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /!< Use analog reference 1 as reference. /
<>	144:ef7eb2e8f9f7	2976
<>	144:ef7eb2e8f9f7	2977	/* Register: LPCOMP_ANADETECT */
<>	144:ef7eb2e8f9f7	2978	/* Description: Analog detect configuration. */
<>	144:ef7eb2e8f9f7	2979
<>	144:ef7eb2e8f9f7	2980	/* Bits 1..0 : Analog detect configuration. */
<>	144:ef7eb2e8f9f7	2981	#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /!< Position of ANADETECT field. /
<>	144:ef7eb2e8f9f7	2982	#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /!< Bit mask of ANADETECT field. /
<>	144:ef7eb2e8f9f7	2983	#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /!< Generate ANADETEC on crossing, both upwards and downwards crossing. /
<>	144:ef7eb2e8f9f7	2984	#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /!< Generate ANADETEC on upwards crossing only. /
<>	144:ef7eb2e8f9f7	2985	#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /!< Generate ANADETEC on downwards crossing only. /
<>	144:ef7eb2e8f9f7	2986
<>	144:ef7eb2e8f9f7	2987	/* Register: LPCOMP_POWER */
<>	144:ef7eb2e8f9f7	2988	/* Description: Peripheral power control. */
<>	144:ef7eb2e8f9f7	2989
<>	144:ef7eb2e8f9f7	2990	/* Bit 0 : Peripheral power control. */
<>	144:ef7eb2e8f9f7	2991	#define LPCOMP_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
<>	144:ef7eb2e8f9f7	2992	#define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /!< Bit mask of POWER field. /
<>	144:ef7eb2e8f9f7	2993	#define LPCOMP_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
<>	144:ef7eb2e8f9f7	2994	#define LPCOMP_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
<>	144:ef7eb2e8f9f7	2995
<>	144:ef7eb2e8f9f7	2996
<>	144:ef7eb2e8f9f7	2997	/* Peripheral: MPU */
<>	144:ef7eb2e8f9f7	2998	/* Description: Memory Protection Unit. */
<>	144:ef7eb2e8f9f7	2999
<>	144:ef7eb2e8f9f7	3000	/* Register: MPU_PERR0 */
<>	144:ef7eb2e8f9f7	3001	/* Description: Configuration of peripherals in mpu regions. */
<>	144:ef7eb2e8f9f7	3002
<>	144:ef7eb2e8f9f7	3003	/* Bit 31 : PPI region configuration. */
<>	144:ef7eb2e8f9f7	3004	#define MPU_PERR0_PPI_Pos (31UL) /!< Position of PPI field. /
<>	144:ef7eb2e8f9f7	3005	#define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /!< Bit mask of PPI field. /
<>	144:ef7eb2e8f9f7	3006	#define MPU_PERR0_PPI_InRegion1 (0UL) /!< Peripheral configured in region 1. /
<>	144:ef7eb2e8f9f7	3007	#define MPU_PERR0_PPI_InRegion0 (1UL) /!< Peripheral configured in region 0. /
<>	144:ef7eb2e8f9f7	3008
<>	144:ef7eb2e8f9f7	3009	/* Bit 30 : NVMC region configuration. */
<>	144:ef7eb2e8f9f7	3010	#define MPU_PERR0_NVMC_Pos (30UL) /!< Position of NVMC field. /
<>	144:ef7eb2e8f9f7	3011	#define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /!< Bit mask of NVMC field. /
<>	144:ef7eb2e8f9f7	3012	#define MPU_PERR0_NVMC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
<>	144:ef7eb2e8f9f7	3013	#define MPU_PERR0_NVMC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
<>	144:ef7eb2e8f9f7	3014
<>	144:ef7eb2e8f9f7	3015	/* Bit 19 : LPCOMP region configuration. */
<>	144:ef7eb2e8f9f7	3016	#define MPU_PERR0_LPCOMP_Pos (19UL) /!< Position of LPCOMP field. /
<>	144:ef7eb2e8f9f7	3017	#define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /!< Bit mask of LPCOMP field. /
<>	144:ef7eb2e8f9f7	3018	#define MPU_PERR0_LPCOMP_InRegion1 (0UL) /!< Peripheral configured in region 1. /
<>	144:ef7eb2e8f9f7	3019	#define MPU_PERR0_LPCOMP_InRegion0 (1UL) /!< Peripheral configured in region 0. /
<>	144:ef7eb2e8f9f7	3020
<>	144:ef7eb2e8f9f7	3021	/* Bit 18 : QDEC region configuration. */
<>	144:ef7eb2e8f9f7	3022	#define MPU_PERR0_QDEC_Pos (18UL) /!< Position of QDEC field. /
<>	144:ef7eb2e8f9f7	3023	#define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /!< Bit mask of QDEC field. /
<>	144:ef7eb2e8f9f7	3024	#define MPU_PERR0_QDEC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
<>	144:ef7eb2e8f9f7	3025	#define MPU_PERR0_QDEC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
<>	144:ef7eb2e8f9f7	3026
<>	144:ef7eb2e8f9f7	3027	/* Bit 17 : RTC1 region configuration. */
<>	144:ef7eb2e8f9f7	3028	#define MPU_PERR0_RTC1_Pos (17UL) /!< Position of RTC1 field. /
<>	144:ef7eb2e8f9f7	3029	#define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /!< Bit mask of RTC1 field. /
<>	144:ef7eb2e8f9f7	3030	#define MPU_PERR0_RTC1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
<>	144:ef7eb2e8f9f7	3031	#define MPU_PERR0_RTC1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
<>	144:ef7eb2e8f9f7	3032
<>	144:ef7eb2e8f9f7	3033	/* Bit 16 : WDT region configuration. */
<>	144:ef7eb2e8f9f7	3034	#define MPU_PERR0_WDT_Pos (16UL) /!< Position of WDT field. /
<>	144:ef7eb2e8f9f7	3035	#define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /!< Bit mask of WDT field. /
<>	144:ef7eb2e8f9f7	3036	#define MPU_PERR0_WDT_InRegion1 (0UL) /!< Peripheral configured in region 1. /
<>	144:ef7eb2e8f9f7	3037	#define MPU_PERR0_WDT_InRegion0 (1UL) /!< Peripheral configured in region 0. /
<>	144:ef7eb2e8f9f7	3038
<>	144:ef7eb2e8f9f7	3039	/* Bit 15 : CCM and AAR region configuration. */
<>	144:ef7eb2e8f9f7	3040	#define MPU_PERR0_CCM_AAR_Pos (15UL) /!< Position of CCM_AAR field. /
<>	144:ef7eb2e8f9f7	3041	#define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /!< Bit mask of CCM_AAR field. /
<>	144:ef7eb2e8f9f7	3042	#define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /!< Peripheral configured in region 1. /
<>	144:ef7eb2e8f9f7	3043	#define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /!< Peripheral configured in region 0. /
<>	144:ef7eb2e8f9f7	3044
<>	144:ef7eb2e8f9f7	3045	/* Bit 14 : ECB region configuration. */
<>	144:ef7eb2e8f9f7	3046	#define MPU_PERR0_ECB_Pos (14UL) /!< Position of ECB field. /
<>	144:ef7eb2e8f9f7	3047	#define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /!< Bit mask of ECB field. /
<>	144:ef7eb2e8f9f7	3048	#define MPU_PERR0_ECB_InRegion1 (0UL) /!< Peripheral configured in region 1. /
<>	144:ef7eb2e8f9f7	3049	#define MPU_PERR0_ECB_InRegion0 (1UL) /!< Peripheral configured in region 0. /
<>	144:ef7eb2e8f9f7	3050
<>	144:ef7eb2e8f9f7	3051	/* Bit 13 : RNG region configuration. */
<>	144:ef7eb2e8f9f7	3052	#define MPU_PERR0_RNG_Pos (13UL) /!< Position of RNG field. /
<>	144:ef7eb2e8f9f7	3053	#define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /!< Bit mask of RNG field. /
<>	144:ef7eb2e8f9f7	3054	#define MPU_PERR0_RNG_InRegion1 (0UL) /!< Peripheral configured in region 1. /
<>	144:ef7eb2e8f9f7	3055	#define MPU_PERR0_RNG_InRegion0 (1UL) /!< Peripheral configured in region 0. /
<>	144:ef7eb2e8f9f7	3056
<>	144:ef7eb2e8f9f7	3057	/* Bit 12 : TEMP region configuration. */
<>	144:ef7eb2e8f9f7	3058	#define MPU_PERR0_TEMP_Pos (12UL) /!< Position of TEMP field. /
<>	144:ef7eb2e8f9f7	3059	#define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /!< Bit mask of TEMP field. /
<>	144:ef7eb2e8f9f7	3060	#define MPU_PERR0_TEMP_InRegion1 (0UL) /!< Peripheral configured in region 1. /
<>	144:ef7eb2e8f9f7	3061	#define MPU_PERR0_TEMP_InRegion0 (1UL) /!< Peripheral configured in region 0. /
<>	144:ef7eb2e8f9f7	3062
<>	144:ef7eb2e8f9f7	3063	/* Bit 11 : RTC0 region configuration. */
<>	144:ef7eb2e8f9f7	3064	#define MPU_PERR0_RTC0_Pos (11UL) /!< Position of RTC0 field. /
<>	144:ef7eb2e8f9f7	3065	#define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /!< Bit mask of RTC0 field. /
<>	144:ef7eb2e8f9f7	3066	#define MPU_PERR0_RTC0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
<>	144:ef7eb2e8f9f7	3067	#define MPU_PERR0_RTC0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
<>	144:ef7eb2e8f9f7	3068
<>	144:ef7eb2e8f9f7	3069	/* Bit 10 : TIMER2 region configuration. */
<>	144:ef7eb2e8f9f7	3070	#define MPU_PERR0_TIMER2_Pos (10UL) /!< Position of TIMER2 field. /
<>	144:ef7eb2e8f9f7	3071	#define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /!< Bit mask of TIMER2 field. /
<>	144:ef7eb2e8f9f7	3072	#define MPU_PERR0_TIMER2_InRegion1 (0UL) /!< Peripheral configured in region 1. /
<>	144:ef7eb2e8f9f7	3073	#define MPU_PERR0_TIMER2_InRegion0 (1UL) /!< Peripheral configured in region 0. /
<>	144:ef7eb2e8f9f7	3074
<>	144:ef7eb2e8f9f7	3075	/* Bit 9 : TIMER1 region configuration. */
<>	144:ef7eb2e8f9f7	3076	#define MPU_PERR0_TIMER1_Pos (9UL) /!< Position of TIMER1 field. /
<>	144:ef7eb2e8f9f7	3077	#define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /!< Bit mask of TIMER1 field. /
<>	144:ef7eb2e8f9f7	3078	#define MPU_PERR0_TIMER1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
<>	144:ef7eb2e8f9f7	3079	#define MPU_PERR0_TIMER1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
<>	144:ef7eb2e8f9f7	3080
<>	144:ef7eb2e8f9f7	3081	/* Bit 8 : TIMER0 region configuration. */
<>	144:ef7eb2e8f9f7	3082	#define MPU_PERR0_TIMER0_Pos (8UL) /!< Position of TIMER0 field. /
<>	144:ef7eb2e8f9f7	3083	#define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /!< Bit mask of TIMER0 field. /
<>	144:ef7eb2e8f9f7	3084	#define MPU_PERR0_TIMER0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
<>	144:ef7eb2e8f9f7	3085	#define MPU_PERR0_TIMER0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
<>	144:ef7eb2e8f9f7	3086
<>	144:ef7eb2e8f9f7	3087	/* Bit 7 : ADC region configuration. */
<>	144:ef7eb2e8f9f7	3088	#define MPU_PERR0_ADC_Pos (7UL) /!< Position of ADC field. /
<>	144:ef7eb2e8f9f7	3089	#define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /!< Bit mask of ADC field. /
<>	144:ef7eb2e8f9f7	3090	#define MPU_PERR0_ADC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
<>	144:ef7eb2e8f9f7	3091	#define MPU_PERR0_ADC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
<>	144:ef7eb2e8f9f7	3092
<>	144:ef7eb2e8f9f7	3093	/* Bit 6 : GPIOTE region configuration. */
<>	144:ef7eb2e8f9f7	3094	#define MPU_PERR0_GPIOTE_Pos (6UL) /!< Position of GPIOTE field. /
<>	144:ef7eb2e8f9f7	3095	#define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /!< Bit mask of GPIOTE field. /
<>	144:ef7eb2e8f9f7	3096	#define MPU_PERR0_GPIOTE_InRegion1 (0UL) /!< Peripheral configured in region 1. /
<>	144:ef7eb2e8f9f7	3097	#define MPU_PERR0_GPIOTE_InRegion0 (1UL) /!< Peripheral configured in region 0. /
<>	144:ef7eb2e8f9f7	3098
<>	144:ef7eb2e8f9f7	3099	/* Bit 4 : SPI1 and TWI1 region configuration. */
<>	144:ef7eb2e8f9f7	3100	#define MPU_PERR0_SPI1_TWI1_Pos (4UL) /!< Position of SPI1_TWI1 field. /
<>	144:ef7eb2e8f9f7	3101	#define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /!< Bit mask of SPI1_TWI1 field. /
<>	144:ef7eb2e8f9f7	3102	#define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
<>	144:ef7eb2e8f9f7	3103	#define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
<>	144:ef7eb2e8f9f7	3104
<>	144:ef7eb2e8f9f7	3105	/* Bit 3 : SPI0 and TWI0 region configuration. */
<>	144:ef7eb2e8f9f7	3106	#define MPU_PERR0_SPI0_TWI0_Pos (3UL) /!< Position of SPI0_TWI0 field. /
<>	144:ef7eb2e8f9f7	3107	#define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /!< Bit mask of SPI0_TWI0 field. /
<>	144:ef7eb2e8f9f7	3108	#define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
<>	144:ef7eb2e8f9f7	3109	#define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
<>	144:ef7eb2e8f9f7	3110
<>	144:ef7eb2e8f9f7	3111	/* Bit 2 : UART0 region configuration. */
<>	144:ef7eb2e8f9f7	3112	#define MPU_PERR0_UART0_Pos (2UL) /!< Position of UART0 field. /
<>	144:ef7eb2e8f9f7	3113	#define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /!< Bit mask of UART0 field. /
<>	144:ef7eb2e8f9f7	3114	#define MPU_PERR0_UART0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
<>	144:ef7eb2e8f9f7	3115	#define MPU_PERR0_UART0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
<>	144:ef7eb2e8f9f7	3116
<>	144:ef7eb2e8f9f7	3117	/* Bit 1 : RADIO region configuration. */
<>	144:ef7eb2e8f9f7	3118	#define MPU_PERR0_RADIO_Pos (1UL) /!< Position of RADIO field. /
<>	144:ef7eb2e8f9f7	3119	#define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /!< Bit mask of RADIO field. /
<>	144:ef7eb2e8f9f7	3120	#define MPU_PERR0_RADIO_InRegion1 (0UL) /!< Peripheral configured in region 1. /
<>	144:ef7eb2e8f9f7	3121	#define MPU_PERR0_RADIO_InRegion0 (1UL) /!< Peripheral configured in region 0. /
<>	144:ef7eb2e8f9f7	3122
<>	144:ef7eb2e8f9f7	3123	/* Bit 0 : POWER_CLOCK region configuration. */
<>	144:ef7eb2e8f9f7	3124	#define MPU_PERR0_POWER_CLOCK_Pos (0UL) /!< Position of POWER_CLOCK field. /
<>	144:ef7eb2e8f9f7	3125	#define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /!< Bit mask of POWER_CLOCK field. /
<>	144:ef7eb2e8f9f7	3126	#define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /!< Peripheral configured in region 1. /
<>	144:ef7eb2e8f9f7	3127	#define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /!< Peripheral configured in region 0. /
<>	144:ef7eb2e8f9f7	3128
<>	144:ef7eb2e8f9f7	3129	/* Register: MPU_PROTENSET0 */
<>	144:ef7eb2e8f9f7	3130	/* Description: Erase and write protection bit enable set register. */
<>	144:ef7eb2e8f9f7	3131
<>	144:ef7eb2e8f9f7	3132	/* Bit 31 : Protection enable for region 31. */
<>	144:ef7eb2e8f9f7	3133	#define MPU_PROTENSET0_PROTREG31_Pos (31UL) /!< Position of PROTREG31 field. /
<>	144:ef7eb2e8f9f7	3134	#define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /!< Bit mask of PROTREG31 field. /
<>	144:ef7eb2e8f9f7	3135	#define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3136	#define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3137	#define MPU_PROTENSET0_PROTREG31_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3138
<>	144:ef7eb2e8f9f7	3139	/* Bit 30 : Protection enable for region 30. */
<>	144:ef7eb2e8f9f7	3140	#define MPU_PROTENSET0_PROTREG30_Pos (30UL) /!< Position of PROTREG30 field. /
<>	144:ef7eb2e8f9f7	3141	#define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /!< Bit mask of PROTREG30 field. /
<>	144:ef7eb2e8f9f7	3142	#define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3143	#define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3144	#define MPU_PROTENSET0_PROTREG30_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3145
<>	144:ef7eb2e8f9f7	3146	/* Bit 29 : Protection enable for region 29. */
<>	144:ef7eb2e8f9f7	3147	#define MPU_PROTENSET0_PROTREG29_Pos (29UL) /!< Position of PROTREG29 field. /
<>	144:ef7eb2e8f9f7	3148	#define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /!< Bit mask of PROTREG29 field. /
<>	144:ef7eb2e8f9f7	3149	#define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3150	#define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3151	#define MPU_PROTENSET0_PROTREG29_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3152
<>	144:ef7eb2e8f9f7	3153	/* Bit 28 : Protection enable for region 28. */
<>	144:ef7eb2e8f9f7	3154	#define MPU_PROTENSET0_PROTREG28_Pos (28UL) /!< Position of PROTREG28 field. /
<>	144:ef7eb2e8f9f7	3155	#define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /!< Bit mask of PROTREG28 field. /
<>	144:ef7eb2e8f9f7	3156	#define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3157	#define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3158	#define MPU_PROTENSET0_PROTREG28_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3159
<>	144:ef7eb2e8f9f7	3160	/* Bit 27 : Protection enable for region 27. */
<>	144:ef7eb2e8f9f7	3161	#define MPU_PROTENSET0_PROTREG27_Pos (27UL) /!< Position of PROTREG27 field. /
<>	144:ef7eb2e8f9f7	3162	#define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /!< Bit mask of PROTREG27 field. /
<>	144:ef7eb2e8f9f7	3163	#define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3164	#define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3165	#define MPU_PROTENSET0_PROTREG27_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3166
<>	144:ef7eb2e8f9f7	3167	/* Bit 26 : Protection enable for region 26. */
<>	144:ef7eb2e8f9f7	3168	#define MPU_PROTENSET0_PROTREG26_Pos (26UL) /!< Position of PROTREG26 field. /
<>	144:ef7eb2e8f9f7	3169	#define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /!< Bit mask of PROTREG26 field. /
<>	144:ef7eb2e8f9f7	3170	#define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3171	#define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3172	#define MPU_PROTENSET0_PROTREG26_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3173
<>	144:ef7eb2e8f9f7	3174	/* Bit 25 : Protection enable for region 25. */
<>	144:ef7eb2e8f9f7	3175	#define MPU_PROTENSET0_PROTREG25_Pos (25UL) /!< Position of PROTREG25 field. /
<>	144:ef7eb2e8f9f7	3176	#define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /!< Bit mask of PROTREG25 field. /
<>	144:ef7eb2e8f9f7	3177	#define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3178	#define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3179	#define MPU_PROTENSET0_PROTREG25_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3180
<>	144:ef7eb2e8f9f7	3181	/* Bit 24 : Protection enable for region 24. */
<>	144:ef7eb2e8f9f7	3182	#define MPU_PROTENSET0_PROTREG24_Pos (24UL) /!< Position of PROTREG24 field. /
<>	144:ef7eb2e8f9f7	3183	#define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /!< Bit mask of PROTREG24 field. /
<>	144:ef7eb2e8f9f7	3184	#define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3185	#define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3186	#define MPU_PROTENSET0_PROTREG24_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3187
<>	144:ef7eb2e8f9f7	3188	/* Bit 23 : Protection enable for region 23. */
<>	144:ef7eb2e8f9f7	3189	#define MPU_PROTENSET0_PROTREG23_Pos (23UL) /!< Position of PROTREG23 field. /
<>	144:ef7eb2e8f9f7	3190	#define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /!< Bit mask of PROTREG23 field. /
<>	144:ef7eb2e8f9f7	3191	#define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3192	#define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3193	#define MPU_PROTENSET0_PROTREG23_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3194
<>	144:ef7eb2e8f9f7	3195	/* Bit 22 : Protection enable for region 22. */
<>	144:ef7eb2e8f9f7	3196	#define MPU_PROTENSET0_PROTREG22_Pos (22UL) /!< Position of PROTREG22 field. /
<>	144:ef7eb2e8f9f7	3197	#define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /!< Bit mask of PROTREG22 field. /
<>	144:ef7eb2e8f9f7	3198	#define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3199	#define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3200	#define MPU_PROTENSET0_PROTREG22_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3201
<>	144:ef7eb2e8f9f7	3202	/* Bit 21 : Protection enable for region 21. */
<>	144:ef7eb2e8f9f7	3203	#define MPU_PROTENSET0_PROTREG21_Pos (21UL) /!< Position of PROTREG21 field. /
<>	144:ef7eb2e8f9f7	3204	#define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /!< Bit mask of PROTREG21 field. /
<>	144:ef7eb2e8f9f7	3205	#define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3206	#define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3207	#define MPU_PROTENSET0_PROTREG21_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3208
<>	144:ef7eb2e8f9f7	3209	/* Bit 20 : Protection enable for region 20. */
<>	144:ef7eb2e8f9f7	3210	#define MPU_PROTENSET0_PROTREG20_Pos (20UL) /!< Position of PROTREG20 field. /
<>	144:ef7eb2e8f9f7	3211	#define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /!< Bit mask of PROTREG20 field. /
<>	144:ef7eb2e8f9f7	3212	#define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3213	#define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3214	#define MPU_PROTENSET0_PROTREG20_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3215
<>	144:ef7eb2e8f9f7	3216	/* Bit 19 : Protection enable for region 19. */
<>	144:ef7eb2e8f9f7	3217	#define MPU_PROTENSET0_PROTREG19_Pos (19UL) /!< Position of PROTREG19 field. /
<>	144:ef7eb2e8f9f7	3218	#define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /!< Bit mask of PROTREG19 field. /
<>	144:ef7eb2e8f9f7	3219	#define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3220	#define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3221	#define MPU_PROTENSET0_PROTREG19_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3222
<>	144:ef7eb2e8f9f7	3223	/* Bit 18 : Protection enable for region 18. */
<>	144:ef7eb2e8f9f7	3224	#define MPU_PROTENSET0_PROTREG18_Pos (18UL) /!< Position of PROTREG18 field. /
<>	144:ef7eb2e8f9f7	3225	#define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /!< Bit mask of PROTREG18 field. /
<>	144:ef7eb2e8f9f7	3226	#define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3227	#define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3228	#define MPU_PROTENSET0_PROTREG18_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3229
<>	144:ef7eb2e8f9f7	3230	/* Bit 17 : Protection enable for region 17. */
<>	144:ef7eb2e8f9f7	3231	#define MPU_PROTENSET0_PROTREG17_Pos (17UL) /!< Position of PROTREG17 field. /
<>	144:ef7eb2e8f9f7	3232	#define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /!< Bit mask of PROTREG17 field. /
<>	144:ef7eb2e8f9f7	3233	#define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3234	#define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3235	#define MPU_PROTENSET0_PROTREG17_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3236
<>	144:ef7eb2e8f9f7	3237	/* Bit 16 : Protection enable for region 16. */
<>	144:ef7eb2e8f9f7	3238	#define MPU_PROTENSET0_PROTREG16_Pos (16UL) /!< Position of PROTREG16 field. /
<>	144:ef7eb2e8f9f7	3239	#define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /!< Bit mask of PROTREG16 field. /
<>	144:ef7eb2e8f9f7	3240	#define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3241	#define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3242	#define MPU_PROTENSET0_PROTREG16_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3243
<>	144:ef7eb2e8f9f7	3244	/* Bit 15 : Protection enable for region 15. */
<>	144:ef7eb2e8f9f7	3245	#define MPU_PROTENSET0_PROTREG15_Pos (15UL) /!< Position of PROTREG15 field. /
<>	144:ef7eb2e8f9f7	3246	#define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /!< Bit mask of PROTREG15 field. /
<>	144:ef7eb2e8f9f7	3247	#define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3248	#define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3249	#define MPU_PROTENSET0_PROTREG15_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3250
<>	144:ef7eb2e8f9f7	3251	/* Bit 14 : Protection enable for region 14. */
<>	144:ef7eb2e8f9f7	3252	#define MPU_PROTENSET0_PROTREG14_Pos (14UL) /!< Position of PROTREG14 field. /
<>	144:ef7eb2e8f9f7	3253	#define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /!< Bit mask of PROTREG14 field. /
<>	144:ef7eb2e8f9f7	3254	#define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3255	#define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3256	#define MPU_PROTENSET0_PROTREG14_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3257
<>	144:ef7eb2e8f9f7	3258	/* Bit 13 : Protection enable for region 13. */
<>	144:ef7eb2e8f9f7	3259	#define MPU_PROTENSET0_PROTREG13_Pos (13UL) /!< Position of PROTREG13 field. /
<>	144:ef7eb2e8f9f7	3260	#define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /!< Bit mask of PROTREG13 field. /
<>	144:ef7eb2e8f9f7	3261	#define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3262	#define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3263	#define MPU_PROTENSET0_PROTREG13_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3264
<>	144:ef7eb2e8f9f7	3265	/* Bit 12 : Protection enable for region 12. */
<>	144:ef7eb2e8f9f7	3266	#define MPU_PROTENSET0_PROTREG12_Pos (12UL) /!< Position of PROTREG12 field. /
<>	144:ef7eb2e8f9f7	3267	#define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /!< Bit mask of PROTREG12 field. /
<>	144:ef7eb2e8f9f7	3268	#define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3269	#define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3270	#define MPU_PROTENSET0_PROTREG12_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3271
<>	144:ef7eb2e8f9f7	3272	/* Bit 11 : Protection enable for region 11. */
<>	144:ef7eb2e8f9f7	3273	#define MPU_PROTENSET0_PROTREG11_Pos (11UL) /!< Position of PROTREG11 field. /
<>	144:ef7eb2e8f9f7	3274	#define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /!< Bit mask of PROTREG11 field. /
<>	144:ef7eb2e8f9f7	3275	#define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3276	#define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3277	#define MPU_PROTENSET0_PROTREG11_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3278
<>	144:ef7eb2e8f9f7	3279	/* Bit 10 : Protection enable for region 10. */
<>	144:ef7eb2e8f9f7	3280	#define MPU_PROTENSET0_PROTREG10_Pos (10UL) /!< Position of PROTREG10 field. /
<>	144:ef7eb2e8f9f7	3281	#define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /!< Bit mask of PROTREG10 field. /
<>	144:ef7eb2e8f9f7	3282	#define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3283	#define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3284	#define MPU_PROTENSET0_PROTREG10_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3285
<>	144:ef7eb2e8f9f7	3286	/* Bit 9 : Protection enable for region 9. */
<>	144:ef7eb2e8f9f7	3287	#define MPU_PROTENSET0_PROTREG9_Pos (9UL) /!< Position of PROTREG9 field. /
<>	144:ef7eb2e8f9f7	3288	#define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /!< Bit mask of PROTREG9 field. /
<>	144:ef7eb2e8f9f7	3289	#define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3290	#define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3291	#define MPU_PROTENSET0_PROTREG9_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3292
<>	144:ef7eb2e8f9f7	3293	/* Bit 8 : Protection enable for region 8. */
<>	144:ef7eb2e8f9f7	3294	#define MPU_PROTENSET0_PROTREG8_Pos (8UL) /!< Position of PROTREG8 field. /
<>	144:ef7eb2e8f9f7	3295	#define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /!< Bit mask of PROTREG8 field. /
<>	144:ef7eb2e8f9f7	3296	#define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3297	#define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3298	#define MPU_PROTENSET0_PROTREG8_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3299
<>	144:ef7eb2e8f9f7	3300	/* Bit 7 : Protection enable for region 7. */
<>	144:ef7eb2e8f9f7	3301	#define MPU_PROTENSET0_PROTREG7_Pos (7UL) /!< Position of PROTREG7 field. /
<>	144:ef7eb2e8f9f7	3302	#define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /!< Bit mask of PROTREG7 field. /
<>	144:ef7eb2e8f9f7	3303	#define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3304	#define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3305	#define MPU_PROTENSET0_PROTREG7_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3306
<>	144:ef7eb2e8f9f7	3307	/* Bit 6 : Protection enable for region 6. */
<>	144:ef7eb2e8f9f7	3308	#define MPU_PROTENSET0_PROTREG6_Pos (6UL) /!< Position of PROTREG6 field. /
<>	144:ef7eb2e8f9f7	3309	#define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /!< Bit mask of PROTREG6 field. /
<>	144:ef7eb2e8f9f7	3310	#define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3311	#define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3312	#define MPU_PROTENSET0_PROTREG6_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3313
<>	144:ef7eb2e8f9f7	3314	/* Bit 5 : Protection enable for region 5. */
<>	144:ef7eb2e8f9f7	3315	#define MPU_PROTENSET0_PROTREG5_Pos (5UL) /!< Position of PROTREG5 field. /
<>	144:ef7eb2e8f9f7	3316	#define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /!< Bit mask of PROTREG5 field. /
<>	144:ef7eb2e8f9f7	3317	#define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3318	#define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3319	#define MPU_PROTENSET0_PROTREG5_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3320
<>	144:ef7eb2e8f9f7	3321	/* Bit 4 : Protection enable for region 4. */
<>	144:ef7eb2e8f9f7	3322	#define MPU_PROTENSET0_PROTREG4_Pos (4UL) /!< Position of PROTREG4 field. /
<>	144:ef7eb2e8f9f7	3323	#define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /!< Bit mask of PROTREG4 field. /
<>	144:ef7eb2e8f9f7	3324	#define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3325	#define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3326	#define MPU_PROTENSET0_PROTREG4_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3327
<>	144:ef7eb2e8f9f7	3328	/* Bit 3 : Protection enable for region 3. */
<>	144:ef7eb2e8f9f7	3329	#define MPU_PROTENSET0_PROTREG3_Pos (3UL) /!< Position of PROTREG3 field. /
<>	144:ef7eb2e8f9f7	3330	#define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /!< Bit mask of PROTREG3 field. /
<>	144:ef7eb2e8f9f7	3331	#define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3332	#define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3333	#define MPU_PROTENSET0_PROTREG3_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3334
<>	144:ef7eb2e8f9f7	3335	/* Bit 2 : Protection enable for region 2. */
<>	144:ef7eb2e8f9f7	3336	#define MPU_PROTENSET0_PROTREG2_Pos (2UL) /!< Position of PROTREG2 field. /
<>	144:ef7eb2e8f9f7	3337	#define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /!< Bit mask of PROTREG2 field. /
<>	144:ef7eb2e8f9f7	3338	#define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3339	#define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3340	#define MPU_PROTENSET0_PROTREG2_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3341
<>	144:ef7eb2e8f9f7	3342	/* Bit 1 : Protection enable for region 1. */
<>	144:ef7eb2e8f9f7	3343	#define MPU_PROTENSET0_PROTREG1_Pos (1UL) /!< Position of PROTREG1 field. /
<>	144:ef7eb2e8f9f7	3344	#define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /!< Bit mask of PROTREG1 field. /
<>	144:ef7eb2e8f9f7	3345	#define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3346	#define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3347	#define MPU_PROTENSET0_PROTREG1_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3348
<>	144:ef7eb2e8f9f7	3349	/* Bit 0 : Protection enable for region 0. */
<>	144:ef7eb2e8f9f7	3350	#define MPU_PROTENSET0_PROTREG0_Pos (0UL) /!< Position of PROTREG0 field. /
<>	144:ef7eb2e8f9f7	3351	#define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /!< Bit mask of PROTREG0 field. /
<>	144:ef7eb2e8f9f7	3352	#define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3353	#define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3354	#define MPU_PROTENSET0_PROTREG0_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3355
<>	144:ef7eb2e8f9f7	3356	/* Register: MPU_PROTENSET1 */
<>	144:ef7eb2e8f9f7	3357	/* Description: Erase and write protection bit enable set register. */
<>	144:ef7eb2e8f9f7	3358
<>	144:ef7eb2e8f9f7	3359	/* Bit 31 : Protection enable for region 63. */
<>	144:ef7eb2e8f9f7	3360	#define MPU_PROTENSET1_PROTREG63_Pos (31UL) /!< Position of PROTREG63 field. /
<>	144:ef7eb2e8f9f7	3361	#define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /!< Bit mask of PROTREG63 field. /
<>	144:ef7eb2e8f9f7	3362	#define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3363	#define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3364	#define MPU_PROTENSET1_PROTREG63_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3365
<>	144:ef7eb2e8f9f7	3366	/* Bit 30 : Protection enable for region 62. */
<>	144:ef7eb2e8f9f7	3367	#define MPU_PROTENSET1_PROTREG62_Pos (30UL) /!< Position of PROTREG62 field. /
<>	144:ef7eb2e8f9f7	3368	#define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /!< Bit mask of PROTREG62 field. /
<>	144:ef7eb2e8f9f7	3369	#define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3370	#define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3371	#define MPU_PROTENSET1_PROTREG62_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3372
<>	144:ef7eb2e8f9f7	3373	/* Bit 29 : Protection enable for region 61. */
<>	144:ef7eb2e8f9f7	3374	#define MPU_PROTENSET1_PROTREG61_Pos (29UL) /!< Position of PROTREG61 field. /
<>	144:ef7eb2e8f9f7	3375	#define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /!< Bit mask of PROTREG61 field. /
<>	144:ef7eb2e8f9f7	3376	#define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3377	#define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3378	#define MPU_PROTENSET1_PROTREG61_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3379
<>	144:ef7eb2e8f9f7	3380	/* Bit 28 : Protection enable for region 60. */
<>	144:ef7eb2e8f9f7	3381	#define MPU_PROTENSET1_PROTREG60_Pos (28UL) /!< Position of PROTREG60 field. /
<>	144:ef7eb2e8f9f7	3382	#define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /!< Bit mask of PROTREG60 field. /
<>	144:ef7eb2e8f9f7	3383	#define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3384	#define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3385	#define MPU_PROTENSET1_PROTREG60_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3386
<>	144:ef7eb2e8f9f7	3387	/* Bit 27 : Protection enable for region 59. */
<>	144:ef7eb2e8f9f7	3388	#define MPU_PROTENSET1_PROTREG59_Pos (27UL) /!< Position of PROTREG59 field. /
<>	144:ef7eb2e8f9f7	3389	#define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /!< Bit mask of PROTREG59 field. /
<>	144:ef7eb2e8f9f7	3390	#define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3391	#define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3392	#define MPU_PROTENSET1_PROTREG59_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3393
<>	144:ef7eb2e8f9f7	3394	/* Bit 26 : Protection enable for region 58. */
<>	144:ef7eb2e8f9f7	3395	#define MPU_PROTENSET1_PROTREG58_Pos (26UL) /!< Position of PROTREG58 field. /
<>	144:ef7eb2e8f9f7	3396	#define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /!< Bit mask of PROTREG58 field. /
<>	144:ef7eb2e8f9f7	3397	#define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3398	#define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3399	#define MPU_PROTENSET1_PROTREG58_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3400
<>	144:ef7eb2e8f9f7	3401	/* Bit 25 : Protection enable for region 57. */
<>	144:ef7eb2e8f9f7	3402	#define MPU_PROTENSET1_PROTREG57_Pos (25UL) /!< Position of PROTREG57 field. /
<>	144:ef7eb2e8f9f7	3403	#define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /!< Bit mask of PROTREG57 field. /
<>	144:ef7eb2e8f9f7	3404	#define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3405	#define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3406	#define MPU_PROTENSET1_PROTREG57_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3407
<>	144:ef7eb2e8f9f7	3408	/* Bit 24 : Protection enable for region 56. */
<>	144:ef7eb2e8f9f7	3409	#define MPU_PROTENSET1_PROTREG56_Pos (24UL) /!< Position of PROTREG56 field. /
<>	144:ef7eb2e8f9f7	3410	#define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /!< Bit mask of PROTREG56 field. /
<>	144:ef7eb2e8f9f7	3411	#define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3412	#define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3413	#define MPU_PROTENSET1_PROTREG56_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3414
<>	144:ef7eb2e8f9f7	3415	/* Bit 23 : Protection enable for region 55. */
<>	144:ef7eb2e8f9f7	3416	#define MPU_PROTENSET1_PROTREG55_Pos (23UL) /!< Position of PROTREG55 field. /
<>	144:ef7eb2e8f9f7	3417	#define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /!< Bit mask of PROTREG55 field. /
<>	144:ef7eb2e8f9f7	3418	#define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3419	#define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3420	#define MPU_PROTENSET1_PROTREG55_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3421
<>	144:ef7eb2e8f9f7	3422	/* Bit 22 : Protection enable for region 54. */
<>	144:ef7eb2e8f9f7	3423	#define MPU_PROTENSET1_PROTREG54_Pos (22UL) /!< Position of PROTREG54 field. /
<>	144:ef7eb2e8f9f7	3424	#define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /!< Bit mask of PROTREG54 field. /
<>	144:ef7eb2e8f9f7	3425	#define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3426	#define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3427	#define MPU_PROTENSET1_PROTREG54_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3428
<>	144:ef7eb2e8f9f7	3429	/* Bit 21 : Protection enable for region 53. */
<>	144:ef7eb2e8f9f7	3430	#define MPU_PROTENSET1_PROTREG53_Pos (21UL) /!< Position of PROTREG53 field. /
<>	144:ef7eb2e8f9f7	3431	#define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /!< Bit mask of PROTREG53 field. /
<>	144:ef7eb2e8f9f7	3432	#define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3433	#define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3434	#define MPU_PROTENSET1_PROTREG53_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3435
<>	144:ef7eb2e8f9f7	3436	/* Bit 20 : Protection enable for region 52. */
<>	144:ef7eb2e8f9f7	3437	#define MPU_PROTENSET1_PROTREG52_Pos (20UL) /!< Position of PROTREG52 field. /
<>	144:ef7eb2e8f9f7	3438	#define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /!< Bit mask of PROTREG52 field. /
<>	144:ef7eb2e8f9f7	3439	#define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3440	#define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3441	#define MPU_PROTENSET1_PROTREG52_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3442
<>	144:ef7eb2e8f9f7	3443	/* Bit 19 : Protection enable for region 51. */
<>	144:ef7eb2e8f9f7	3444	#define MPU_PROTENSET1_PROTREG51_Pos (19UL) /!< Position of PROTREG51 field. /
<>	144:ef7eb2e8f9f7	3445	#define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /!< Bit mask of PROTREG51 field. /
<>	144:ef7eb2e8f9f7	3446	#define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3447	#define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3448	#define MPU_PROTENSET1_PROTREG51_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3449
<>	144:ef7eb2e8f9f7	3450	/* Bit 18 : Protection enable for region 50. */
<>	144:ef7eb2e8f9f7	3451	#define MPU_PROTENSET1_PROTREG50_Pos (18UL) /!< Position of PROTREG50 field. /
<>	144:ef7eb2e8f9f7	3452	#define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /!< Bit mask of PROTREG50 field. /
<>	144:ef7eb2e8f9f7	3453	#define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3454	#define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3455	#define MPU_PROTENSET1_PROTREG50_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3456
<>	144:ef7eb2e8f9f7	3457	/* Bit 17 : Protection enable for region 49. */
<>	144:ef7eb2e8f9f7	3458	#define MPU_PROTENSET1_PROTREG49_Pos (17UL) /!< Position of PROTREG49 field. /
<>	144:ef7eb2e8f9f7	3459	#define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /!< Bit mask of PROTREG49 field. /
<>	144:ef7eb2e8f9f7	3460	#define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3461	#define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3462	#define MPU_PROTENSET1_PROTREG49_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3463
<>	144:ef7eb2e8f9f7	3464	/* Bit 16 : Protection enable for region 48. */
<>	144:ef7eb2e8f9f7	3465	#define MPU_PROTENSET1_PROTREG48_Pos (16UL) /!< Position of PROTREG48 field. /
<>	144:ef7eb2e8f9f7	3466	#define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /!< Bit mask of PROTREG48 field. /
<>	144:ef7eb2e8f9f7	3467	#define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3468	#define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3469	#define MPU_PROTENSET1_PROTREG48_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3470
<>	144:ef7eb2e8f9f7	3471	/* Bit 15 : Protection enable for region 47. */
<>	144:ef7eb2e8f9f7	3472	#define MPU_PROTENSET1_PROTREG47_Pos (15UL) /!< Position of PROTREG47 field. /
<>	144:ef7eb2e8f9f7	3473	#define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /!< Bit mask of PROTREG47 field. /
<>	144:ef7eb2e8f9f7	3474	#define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3475	#define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3476	#define MPU_PROTENSET1_PROTREG47_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3477
<>	144:ef7eb2e8f9f7	3478	/* Bit 14 : Protection enable for region 46. */
<>	144:ef7eb2e8f9f7	3479	#define MPU_PROTENSET1_PROTREG46_Pos (14UL) /!< Position of PROTREG46 field. /
<>	144:ef7eb2e8f9f7	3480	#define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /!< Bit mask of PROTREG46 field. /
<>	144:ef7eb2e8f9f7	3481	#define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3482	#define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3483	#define MPU_PROTENSET1_PROTREG46_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3484
<>	144:ef7eb2e8f9f7	3485	/* Bit 13 : Protection enable for region 45. */
<>	144:ef7eb2e8f9f7	3486	#define MPU_PROTENSET1_PROTREG45_Pos (13UL) /!< Position of PROTREG45 field. /
<>	144:ef7eb2e8f9f7	3487	#define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /!< Bit mask of PROTREG45 field. /
<>	144:ef7eb2e8f9f7	3488	#define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3489	#define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3490	#define MPU_PROTENSET1_PROTREG45_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3491
<>	144:ef7eb2e8f9f7	3492	/* Bit 12 : Protection enable for region 44. */
<>	144:ef7eb2e8f9f7	3493	#define MPU_PROTENSET1_PROTREG44_Pos (12UL) /!< Position of PROTREG44 field. /
<>	144:ef7eb2e8f9f7	3494	#define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /!< Bit mask of PROTREG44 field. /
<>	144:ef7eb2e8f9f7	3495	#define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3496	#define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3497	#define MPU_PROTENSET1_PROTREG44_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3498
<>	144:ef7eb2e8f9f7	3499	/* Bit 11 : Protection enable for region 43. */
<>	144:ef7eb2e8f9f7	3500	#define MPU_PROTENSET1_PROTREG43_Pos (11UL) /!< Position of PROTREG43 field. /
<>	144:ef7eb2e8f9f7	3501	#define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /!< Bit mask of PROTREG43 field. /
<>	144:ef7eb2e8f9f7	3502	#define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3503	#define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3504	#define MPU_PROTENSET1_PROTREG43_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3505
<>	144:ef7eb2e8f9f7	3506	/* Bit 10 : Protection enable for region 42. */
<>	144:ef7eb2e8f9f7	3507	#define MPU_PROTENSET1_PROTREG42_Pos (10UL) /!< Position of PROTREG42 field. /
<>	144:ef7eb2e8f9f7	3508	#define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /!< Bit mask of PROTREG42 field. /
<>	144:ef7eb2e8f9f7	3509	#define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3510	#define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3511	#define MPU_PROTENSET1_PROTREG42_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3512
<>	144:ef7eb2e8f9f7	3513	/* Bit 9 : Protection enable for region 41. */
<>	144:ef7eb2e8f9f7	3514	#define MPU_PROTENSET1_PROTREG41_Pos (9UL) /!< Position of PROTREG41 field. /
<>	144:ef7eb2e8f9f7	3515	#define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /!< Bit mask of PROTREG41 field. /
<>	144:ef7eb2e8f9f7	3516	#define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3517	#define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3518	#define MPU_PROTENSET1_PROTREG41_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3519
<>	144:ef7eb2e8f9f7	3520	/* Bit 8 : Protection enable for region 40. */
<>	144:ef7eb2e8f9f7	3521	#define MPU_PROTENSET1_PROTREG40_Pos (8UL) /!< Position of PROTREG40 field. /
<>	144:ef7eb2e8f9f7	3522	#define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /!< Bit mask of PROTREG40 field. /
<>	144:ef7eb2e8f9f7	3523	#define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3524	#define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3525	#define MPU_PROTENSET1_PROTREG40_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3526
<>	144:ef7eb2e8f9f7	3527	/* Bit 7 : Protection enable for region 39. */
<>	144:ef7eb2e8f9f7	3528	#define MPU_PROTENSET1_PROTREG39_Pos (7UL) /!< Position of PROTREG39 field. /
<>	144:ef7eb2e8f9f7	3529	#define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /!< Bit mask of PROTREG39 field. /
<>	144:ef7eb2e8f9f7	3530	#define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3531	#define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3532	#define MPU_PROTENSET1_PROTREG39_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3533
<>	144:ef7eb2e8f9f7	3534	/* Bit 6 : Protection enable for region 38. */
<>	144:ef7eb2e8f9f7	3535	#define MPU_PROTENSET1_PROTREG38_Pos (6UL) /!< Position of PROTREG38 field. /
<>	144:ef7eb2e8f9f7	3536	#define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /!< Bit mask of PROTREG38 field. /
<>	144:ef7eb2e8f9f7	3537	#define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3538	#define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3539	#define MPU_PROTENSET1_PROTREG38_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3540
<>	144:ef7eb2e8f9f7	3541	/* Bit 5 : Protection enable for region 37. */
<>	144:ef7eb2e8f9f7	3542	#define MPU_PROTENSET1_PROTREG37_Pos (5UL) /!< Position of PROTREG37 field. /
<>	144:ef7eb2e8f9f7	3543	#define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /!< Bit mask of PROTREG37 field. /
<>	144:ef7eb2e8f9f7	3544	#define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3545	#define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3546	#define MPU_PROTENSET1_PROTREG37_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3547
<>	144:ef7eb2e8f9f7	3548	/* Bit 4 : Protection enable for region 36. */
<>	144:ef7eb2e8f9f7	3549	#define MPU_PROTENSET1_PROTREG36_Pos (4UL) /!< Position of PROTREG36 field. /
<>	144:ef7eb2e8f9f7	3550	#define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /!< Bit mask of PROTREG36 field. /
<>	144:ef7eb2e8f9f7	3551	#define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3552	#define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3553	#define MPU_PROTENSET1_PROTREG36_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3554
<>	144:ef7eb2e8f9f7	3555	/* Bit 3 : Protection enable for region 35. */
<>	144:ef7eb2e8f9f7	3556	#define MPU_PROTENSET1_PROTREG35_Pos (3UL) /!< Position of PROTREG35 field. /
<>	144:ef7eb2e8f9f7	3557	#define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /!< Bit mask of PROTREG35 field. /
<>	144:ef7eb2e8f9f7	3558	#define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3559	#define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3560	#define MPU_PROTENSET1_PROTREG35_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3561
<>	144:ef7eb2e8f9f7	3562	/* Bit 2 : Protection enable for region 34. */
<>	144:ef7eb2e8f9f7	3563	#define MPU_PROTENSET1_PROTREG34_Pos (2UL) /!< Position of PROTREG34 field. /
<>	144:ef7eb2e8f9f7	3564	#define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /!< Bit mask of PROTREG34 field. /
<>	144:ef7eb2e8f9f7	3565	#define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3566	#define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3567	#define MPU_PROTENSET1_PROTREG34_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3568
<>	144:ef7eb2e8f9f7	3569	/* Bit 1 : Protection enable for region 33. */
<>	144:ef7eb2e8f9f7	3570	#define MPU_PROTENSET1_PROTREG33_Pos (1UL) /!< Position of PROTREG33 field. /
<>	144:ef7eb2e8f9f7	3571	#define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /!< Bit mask of PROTREG33 field. /
<>	144:ef7eb2e8f9f7	3572	#define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3573	#define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3574	#define MPU_PROTENSET1_PROTREG33_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3575
<>	144:ef7eb2e8f9f7	3576	/* Bit 0 : Protection enable for region 32. */
<>	144:ef7eb2e8f9f7	3577	#define MPU_PROTENSET1_PROTREG32_Pos (0UL) /!< Position of PROTREG32 field. /
<>	144:ef7eb2e8f9f7	3578	#define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /!< Bit mask of PROTREG32 field. /
<>	144:ef7eb2e8f9f7	3579	#define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3580	#define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3581	#define MPU_PROTENSET1_PROTREG32_Set (1UL) /!< Enable protection on write. /
<>	144:ef7eb2e8f9f7	3582
<>	144:ef7eb2e8f9f7	3583	/* Register: MPU_DISABLEINDEBUG */
<>	144:ef7eb2e8f9f7	3584	/* Description: Disable erase and write protection mechanism in debug mode. */
<>	144:ef7eb2e8f9f7	3585
<>	144:ef7eb2e8f9f7	3586	/* Bit 0 : Disable protection mechanism in debug mode. */
<>	144:ef7eb2e8f9f7	3587	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /!< Position of DISABLEINDEBUG field. /
<>	144:ef7eb2e8f9f7	3588	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /!< Bit mask of DISABLEINDEBUG field. /
<>	144:ef7eb2e8f9f7	3589	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /!< Protection enabled. /
<>	144:ef7eb2e8f9f7	3590	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /!< Protection disabled. /
<>	144:ef7eb2e8f9f7	3591
<>	144:ef7eb2e8f9f7	3592	/* Register: MPU_PROTBLOCKSIZE */
<>	144:ef7eb2e8f9f7	3593	/* Description: Erase and write protection block size. */
<>	144:ef7eb2e8f9f7	3594
<>	144:ef7eb2e8f9f7	3595	/* Bits 1..0 : Erase and write protection block size. */
<>	144:ef7eb2e8f9f7	3596	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /!< Position of PROTBLOCKSIZE field. /
<>	144:ef7eb2e8f9f7	3597	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /!< Bit mask of PROTBLOCKSIZE field. /
<>	144:ef7eb2e8f9f7	3598	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /!< Erase and write protection block size is 4k. /
<>	144:ef7eb2e8f9f7	3599
<>	144:ef7eb2e8f9f7	3600
<>	144:ef7eb2e8f9f7	3601	/* Peripheral: NVMC */
<>	144:ef7eb2e8f9f7	3602	/* Description: Non Volatile Memory Controller. */
<>	144:ef7eb2e8f9f7	3603
<>	144:ef7eb2e8f9f7	3604	/* Register: NVMC_READY */
<>	144:ef7eb2e8f9f7	3605	/* Description: Ready flag. */
<>	144:ef7eb2e8f9f7	3606
<>	144:ef7eb2e8f9f7	3607	/* Bit 0 : NVMC ready. */
<>	144:ef7eb2e8f9f7	3608	#define NVMC_READY_READY_Pos (0UL) /!< Position of READY field. /
<>	144:ef7eb2e8f9f7	3609	#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /!< Bit mask of READY field. /
<>	144:ef7eb2e8f9f7	3610	#define NVMC_READY_READY_Busy (0UL) /!< NVMC is busy (on-going write or erase operation). /
<>	144:ef7eb2e8f9f7	3611	#define NVMC_READY_READY_Ready (1UL) /!< NVMC is ready. /
<>	144:ef7eb2e8f9f7	3612
<>	144:ef7eb2e8f9f7	3613	/* Register: NVMC_CONFIG */
<>	144:ef7eb2e8f9f7	3614	/* Description: Configuration register. */
<>	144:ef7eb2e8f9f7	3615
<>	144:ef7eb2e8f9f7	3616	/* Bits 1..0 : Program write enable. */
<>	144:ef7eb2e8f9f7	3617	#define NVMC_CONFIG_WEN_Pos (0UL) /!< Position of WEN field. /
<>	144:ef7eb2e8f9f7	3618	#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /!< Bit mask of WEN field. /
<>	144:ef7eb2e8f9f7	3619	#define NVMC_CONFIG_WEN_Ren (0x00UL) /!< Read only access. /
<>	144:ef7eb2e8f9f7	3620	#define NVMC_CONFIG_WEN_Wen (0x01UL) /!< Write enabled. /
<>	144:ef7eb2e8f9f7	3621	#define NVMC_CONFIG_WEN_Een (0x02UL) /!< Erase enabled. /
<>	144:ef7eb2e8f9f7	3622
<>	144:ef7eb2e8f9f7	3623	/* Register: NVMC_ERASEALL */
<>	144:ef7eb2e8f9f7	3624	/* Description: Register for erasing all non-volatile user memory. */
<>	144:ef7eb2e8f9f7	3625
<>	144:ef7eb2e8f9f7	3626	/* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */
<>	144:ef7eb2e8f9f7	3627	#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /!< Position of ERASEALL field. /
<>	144:ef7eb2e8f9f7	3628	#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /!< Bit mask of ERASEALL field. /
<>	144:ef7eb2e8f9f7	3629	#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /!< No operation. /
<>	144:ef7eb2e8f9f7	3630	#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /!< Start chip erase. /
<>	144:ef7eb2e8f9f7	3631
<>	144:ef7eb2e8f9f7	3632	/* Register: NVMC_ERASEUICR */
<>	144:ef7eb2e8f9f7	3633	/* Description: Register for start erasing User Information Congfiguration Registers. */
<>	144:ef7eb2e8f9f7	3634
<>	144:ef7eb2e8f9f7	3635	/* Bit 0 : It can only be used when all contents of code region 1 are erased. */
<>	144:ef7eb2e8f9f7	3636	#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /!< Position of ERASEUICR field. /
<>	144:ef7eb2e8f9f7	3637	#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /!< Bit mask of ERASEUICR field. /
<>	144:ef7eb2e8f9f7	3638	#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /!< No operation. /
<>	144:ef7eb2e8f9f7	3639	#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /!< Start UICR erase. /
<>	144:ef7eb2e8f9f7	3640
<>	144:ef7eb2e8f9f7	3641
<>	144:ef7eb2e8f9f7	3642	/* Peripheral: POWER */
<>	144:ef7eb2e8f9f7	3643	/* Description: Power Control. */
<>	144:ef7eb2e8f9f7	3644
<>	144:ef7eb2e8f9f7	3645	/* Register: POWER_INTENSET */
<>	144:ef7eb2e8f9f7	3646	/* Description: Interrupt enable set register. */
<>	144:ef7eb2e8f9f7	3647
<>	144:ef7eb2e8f9f7	3648	/* Bit 2 : Enable interrupt on POFWARN event. */
<>	144:ef7eb2e8f9f7	3649	#define POWER_INTENSET_POFWARN_Pos (2UL) /!< Position of POFWARN field. /
<>	144:ef7eb2e8f9f7	3650	#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /!< Bit mask of POFWARN field. /
<>	144:ef7eb2e8f9f7	3651	#define POWER_INTENSET_POFWARN_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	3652	#define POWER_INTENSET_POFWARN_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	3653	#define POWER_INTENSET_POFWARN_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	3654
<>	144:ef7eb2e8f9f7	3655	/* Register: POWER_INTENCLR */
<>	144:ef7eb2e8f9f7	3656	/* Description: Interrupt enable clear register. */
<>	144:ef7eb2e8f9f7	3657
<>	144:ef7eb2e8f9f7	3658	/* Bit 2 : Disable interrupt on POFWARN event. */
<>	144:ef7eb2e8f9f7	3659	#define POWER_INTENCLR_POFWARN_Pos (2UL) /!< Position of POFWARN field. /
<>	144:ef7eb2e8f9f7	3660	#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /!< Bit mask of POFWARN field. /
<>	144:ef7eb2e8f9f7	3661	#define POWER_INTENCLR_POFWARN_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	3662	#define POWER_INTENCLR_POFWARN_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	3663	#define POWER_INTENCLR_POFWARN_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	3664
<>	144:ef7eb2e8f9f7	3665	/* Register: POWER_RESETREAS */
<>	144:ef7eb2e8f9f7	3666	/* Description: Reset reason. */
<>	144:ef7eb2e8f9f7	3667
<>	144:ef7eb2e8f9f7	3668	/* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */
<>	144:ef7eb2e8f9f7	3669	#define POWER_RESETREAS_DIF_Pos (18UL) /!< Position of DIF field. /
<>	144:ef7eb2e8f9f7	3670	#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /!< Bit mask of DIF field. /
<>	144:ef7eb2e8f9f7	3671	#define POWER_RESETREAS_DIF_NotDetected (0UL) /!< Reset not detected. /
<>	144:ef7eb2e8f9f7	3672	#define POWER_RESETREAS_DIF_Detected (1UL) /!< Reset detected. /
<>	144:ef7eb2e8f9f7	3673
<>	144:ef7eb2e8f9f7	3674	/* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */
<>	144:ef7eb2e8f9f7	3675	#define POWER_RESETREAS_LPCOMP_Pos (17UL) /!< Position of LPCOMP field. /
<>	144:ef7eb2e8f9f7	3676	#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /!< Bit mask of LPCOMP field. /
<>	144:ef7eb2e8f9f7	3677	#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /!< Reset not detected. /
<>	144:ef7eb2e8f9f7	3678	#define POWER_RESETREAS_LPCOMP_Detected (1UL) /!< Reset detected. /
<>	144:ef7eb2e8f9f7	3679
<>	144:ef7eb2e8f9f7	3680	/* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */
<>	144:ef7eb2e8f9f7	3681	#define POWER_RESETREAS_OFF_Pos (16UL) /!< Position of OFF field. /
<>	144:ef7eb2e8f9f7	3682	#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /!< Bit mask of OFF field. /
<>	144:ef7eb2e8f9f7	3683	#define POWER_RESETREAS_OFF_NotDetected (0UL) /!< Reset not detected. /
<>	144:ef7eb2e8f9f7	3684	#define POWER_RESETREAS_OFF_Detected (1UL) /!< Reset detected. /
<>	144:ef7eb2e8f9f7	3685
<>	144:ef7eb2e8f9f7	3686	/* Bit 3 : Reset from CPU lock-up detected. */
<>	144:ef7eb2e8f9f7	3687	#define POWER_RESETREAS_LOCKUP_Pos (3UL) /!< Position of LOCKUP field. /
<>	144:ef7eb2e8f9f7	3688	#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /!< Bit mask of LOCKUP field. /
<>	144:ef7eb2e8f9f7	3689	#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /!< Reset not detected. /
<>	144:ef7eb2e8f9f7	3690	#define POWER_RESETREAS_LOCKUP_Detected (1UL) /!< Reset detected. /
<>	144:ef7eb2e8f9f7	3691
<>	144:ef7eb2e8f9f7	3692	/* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */
<>	144:ef7eb2e8f9f7	3693	#define POWER_RESETREAS_SREQ_Pos (2UL) /!< Position of SREQ field. /
<>	144:ef7eb2e8f9f7	3694	#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /!< Bit mask of SREQ field. /
<>	144:ef7eb2e8f9f7	3695	#define POWER_RESETREAS_SREQ_NotDetected (0UL) /!< Reset not detected. /
<>	144:ef7eb2e8f9f7	3696	#define POWER_RESETREAS_SREQ_Detected (1UL) /!< Reset detected. /
<>	144:ef7eb2e8f9f7	3697
<>	144:ef7eb2e8f9f7	3698	/* Bit 1 : Reset from watchdog detected. */
<>	144:ef7eb2e8f9f7	3699	#define POWER_RESETREAS_DOG_Pos (1UL) /!< Position of DOG field. /
<>	144:ef7eb2e8f9f7	3700	#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /!< Bit mask of DOG field. /
<>	144:ef7eb2e8f9f7	3701	#define POWER_RESETREAS_DOG_NotDetected (0UL) /!< Reset not detected. /
<>	144:ef7eb2e8f9f7	3702	#define POWER_RESETREAS_DOG_Detected (1UL) /!< Reset detected. /
<>	144:ef7eb2e8f9f7	3703
<>	144:ef7eb2e8f9f7	3704	/* Bit 0 : Reset from pin-reset detected. */
<>	144:ef7eb2e8f9f7	3705	#define POWER_RESETREAS_RESETPIN_Pos (0UL) /!< Position of RESETPIN field. /
<>	144:ef7eb2e8f9f7	3706	#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /!< Bit mask of RESETPIN field. /
<>	144:ef7eb2e8f9f7	3707	#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /!< Reset not detected. /
<>	144:ef7eb2e8f9f7	3708	#define POWER_RESETREAS_RESETPIN_Detected (1UL) /!< Reset detected. /
<>	144:ef7eb2e8f9f7	3709
<>	144:ef7eb2e8f9f7	3710	/* Register: POWER_RAMSTATUS */
<>	144:ef7eb2e8f9f7	3711	/* Description: Ram status register. */
<>	144:ef7eb2e8f9f7	3712
<>	144:ef7eb2e8f9f7	3713	/* Bit 3 : RAM block 3 status. */
<>	144:ef7eb2e8f9f7	3714	#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /!< Position of RAMBLOCK3 field. /
<>	144:ef7eb2e8f9f7	3715	#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /!< Bit mask of RAMBLOCK3 field. /
<>	144:ef7eb2e8f9f7	3716	#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /!< RAM block 3 is off or powering up. /
<>	144:ef7eb2e8f9f7	3717	#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /!< RAM block 3 is on. /
<>	144:ef7eb2e8f9f7	3718
<>	144:ef7eb2e8f9f7	3719	/* Bit 2 : RAM block 2 status. */
<>	144:ef7eb2e8f9f7	3720	#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /!< Position of RAMBLOCK2 field. /
<>	144:ef7eb2e8f9f7	3721	#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /!< Bit mask of RAMBLOCK2 field. /
<>	144:ef7eb2e8f9f7	3722	#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /!< RAM block 2 is off or powering up. /
<>	144:ef7eb2e8f9f7	3723	#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /!< RAM block 2 is on. /
<>	144:ef7eb2e8f9f7	3724
<>	144:ef7eb2e8f9f7	3725	/* Bit 1 : RAM block 1 status. */
<>	144:ef7eb2e8f9f7	3726	#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /!< Position of RAMBLOCK1 field. /
<>	144:ef7eb2e8f9f7	3727	#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /!< Bit mask of RAMBLOCK1 field. /
<>	144:ef7eb2e8f9f7	3728	#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /!< RAM block 1 is off or powering up. /
<>	144:ef7eb2e8f9f7	3729	#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /!< RAM block 1 is on. /
<>	144:ef7eb2e8f9f7	3730
<>	144:ef7eb2e8f9f7	3731	/* Bit 0 : RAM block 0 status. */
<>	144:ef7eb2e8f9f7	3732	#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /!< Position of RAMBLOCK0 field. /
<>	144:ef7eb2e8f9f7	3733	#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /!< Bit mask of RAMBLOCK0 field. /
<>	144:ef7eb2e8f9f7	3734	#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /!< RAM block 0 is off or powering up. /
<>	144:ef7eb2e8f9f7	3735	#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /!< RAM block 0 is on. /
<>	144:ef7eb2e8f9f7	3736
<>	144:ef7eb2e8f9f7	3737	/* Register: POWER_SYSTEMOFF */
<>	144:ef7eb2e8f9f7	3738	/* Description: System off register. */
<>	144:ef7eb2e8f9f7	3739
<>	144:ef7eb2e8f9f7	3740	/* Bit 0 : Enter system off mode. */
<>	144:ef7eb2e8f9f7	3741	#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /!< Position of SYSTEMOFF field. /
<>	144:ef7eb2e8f9f7	3742	#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /!< Bit mask of SYSTEMOFF field. /
<>	144:ef7eb2e8f9f7	3743	#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /!< Enter system off mode. /
<>	144:ef7eb2e8f9f7	3744
<>	144:ef7eb2e8f9f7	3745	/* Register: POWER_POFCON */
<>	144:ef7eb2e8f9f7	3746	/* Description: Power failure configuration. */
<>	144:ef7eb2e8f9f7	3747
<>	144:ef7eb2e8f9f7	3748	/* Bits 2..1 : Set threshold level. */
<>	144:ef7eb2e8f9f7	3749	#define POWER_POFCON_THRESHOLD_Pos (1UL) /!< Position of THRESHOLD field. /
<>	144:ef7eb2e8f9f7	3750	#define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /!< Bit mask of THRESHOLD field. /
<>	144:ef7eb2e8f9f7	3751	#define POWER_POFCON_THRESHOLD_V21 (0x00UL) /!< Set threshold to 2.1Volts. /
<>	144:ef7eb2e8f9f7	3752	#define POWER_POFCON_THRESHOLD_V23 (0x01UL) /!< Set threshold to 2.3Volts. /
<>	144:ef7eb2e8f9f7	3753	#define POWER_POFCON_THRESHOLD_V25 (0x02UL) /!< Set threshold to 2.5Volts. /
<>	144:ef7eb2e8f9f7	3754	#define POWER_POFCON_THRESHOLD_V27 (0x03UL) /!< Set threshold to 2.7Volts. /
<>	144:ef7eb2e8f9f7	3755
<>	144:ef7eb2e8f9f7	3756	/* Bit 0 : Power failure comparator enable. */
<>	144:ef7eb2e8f9f7	3757	#define POWER_POFCON_POF_Pos (0UL) /!< Position of POF field. /
<>	144:ef7eb2e8f9f7	3758	#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /!< Bit mask of POF field. /
<>	144:ef7eb2e8f9f7	3759	#define POWER_POFCON_POF_Disabled (0UL) /!< Disabled. /
<>	144:ef7eb2e8f9f7	3760	#define POWER_POFCON_POF_Enabled (1UL) /!< Enabled. /
<>	144:ef7eb2e8f9f7	3761
<>	144:ef7eb2e8f9f7	3762	/* Register: POWER_GPREGRET */
<>	144:ef7eb2e8f9f7	3763	/* Description: General purpose retention register. This register is a retained register. */
<>	144:ef7eb2e8f9f7	3764
<>	144:ef7eb2e8f9f7	3765	/* Bits 7..0 : General purpose retention register. */
<>	144:ef7eb2e8f9f7	3766	#define POWER_GPREGRET_GPREGRET_Pos (0UL) /!< Position of GPREGRET field. /
<>	144:ef7eb2e8f9f7	3767	#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /!< Bit mask of GPREGRET field. /
<>	144:ef7eb2e8f9f7	3768
<>	144:ef7eb2e8f9f7	3769	/* Register: POWER_RAMON */
<>	144:ef7eb2e8f9f7	3770	/* Description: Ram on/off. */
<>	144:ef7eb2e8f9f7	3771
<>	144:ef7eb2e8f9f7	3772	/* Bit 17 : RAM block 1 behaviour in OFF mode. */
<>	144:ef7eb2e8f9f7	3773	#define POWER_RAMON_OFFRAM1_Pos (17UL) /!< Position of OFFRAM1 field. /
<>	144:ef7eb2e8f9f7	3774	#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /!< Bit mask of OFFRAM1 field. /
<>	144:ef7eb2e8f9f7	3775	#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /!< RAM block 1 OFF in OFF mode. /
<>	144:ef7eb2e8f9f7	3776	#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /!< RAM block 1 ON in OFF mode. /
<>	144:ef7eb2e8f9f7	3777
<>	144:ef7eb2e8f9f7	3778	/* Bit 16 : RAM block 0 behaviour in OFF mode. */
<>	144:ef7eb2e8f9f7	3779	#define POWER_RAMON_OFFRAM0_Pos (16UL) /!< Position of OFFRAM0 field. /
<>	144:ef7eb2e8f9f7	3780	#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /!< Bit mask of OFFRAM0 field. /
<>	144:ef7eb2e8f9f7	3781	#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /!< RAM block 0 OFF in OFF mode. /
<>	144:ef7eb2e8f9f7	3782	#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /!< RAM block 0 ON in OFF mode. /
<>	144:ef7eb2e8f9f7	3783
<>	144:ef7eb2e8f9f7	3784	/* Bit 1 : RAM block 1 behaviour in ON mode. */
<>	144:ef7eb2e8f9f7	3785	#define POWER_RAMON_ONRAM1_Pos (1UL) /!< Position of ONRAM1 field. /
<>	144:ef7eb2e8f9f7	3786	#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /!< Bit mask of ONRAM1 field. /
<>	144:ef7eb2e8f9f7	3787	#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /!< RAM block 1 OFF in ON mode. /
<>	144:ef7eb2e8f9f7	3788	#define POWER_RAMON_ONRAM1_RAM1On (1UL) /!< RAM block 1 ON in ON mode. /
<>	144:ef7eb2e8f9f7	3789
<>	144:ef7eb2e8f9f7	3790	/* Bit 0 : RAM block 0 behaviour in ON mode. */
<>	144:ef7eb2e8f9f7	3791	#define POWER_RAMON_ONRAM0_Pos (0UL) /!< Position of ONRAM0 field. /
<>	144:ef7eb2e8f9f7	3792	#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /!< Bit mask of ONRAM0 field. /
<>	144:ef7eb2e8f9f7	3793	#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /!< RAM block 0 OFF in ON mode. /
<>	144:ef7eb2e8f9f7	3794	#define POWER_RAMON_ONRAM0_RAM0On (1UL) /!< RAM block 0 ON in ON mode. /
<>	144:ef7eb2e8f9f7	3795
<>	144:ef7eb2e8f9f7	3796	/* Register: POWER_RESET */
<>	144:ef7eb2e8f9f7	3797	/* Description: Pin reset functionality configuration register. This register is a retained register. */
<>	144:ef7eb2e8f9f7	3798
<>	144:ef7eb2e8f9f7	3799	/* Bit 0 : Enable or disable pin reset in debug interface mode. */
<>	144:ef7eb2e8f9f7	3800	#define POWER_RESET_RESET_Pos (0UL) /!< Position of RESET field. /
<>	144:ef7eb2e8f9f7	3801	#define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /!< Bit mask of RESET field. /
<>	144:ef7eb2e8f9f7	3802	#define POWER_RESET_RESET_Disabled (0UL) /!< Pin reset in debug interface mode disabled. /
<>	144:ef7eb2e8f9f7	3803	#define POWER_RESET_RESET_Enabled (1UL) /!< Pin reset in debug interface mode enabled. /
<>	144:ef7eb2e8f9f7	3804
<>	144:ef7eb2e8f9f7	3805	/* Register: POWER_RAMONB */
<>	144:ef7eb2e8f9f7	3806	/* Description: Ram on/off. */
<>	144:ef7eb2e8f9f7	3807
<>	144:ef7eb2e8f9f7	3808	/* Bit 17 : RAM block 3 behaviour in OFF mode. */
<>	144:ef7eb2e8f9f7	3809	#define POWER_RAMONB_OFFRAM3_Pos (17UL) /!< Position of OFFRAM3 field. /
<>	144:ef7eb2e8f9f7	3810	#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /!< Bit mask of OFFRAM3 field. /
<>	144:ef7eb2e8f9f7	3811	#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /!< RAM block 3 OFF in OFF mode. /
<>	144:ef7eb2e8f9f7	3812	#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /!< RAM block 3 ON in OFF mode. /
<>	144:ef7eb2e8f9f7	3813
<>	144:ef7eb2e8f9f7	3814	/* Bit 16 : RAM block 2 behaviour in OFF mode. */
<>	144:ef7eb2e8f9f7	3815	#define POWER_RAMONB_OFFRAM2_Pos (16UL) /!< Position of OFFRAM2 field. /
<>	144:ef7eb2e8f9f7	3816	#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /!< Bit mask of OFFRAM2 field. /
<>	144:ef7eb2e8f9f7	3817	#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /!< RAM block 2 OFF in OFF mode. /
<>	144:ef7eb2e8f9f7	3818	#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /!< RAM block 2 ON in OFF mode. /
<>	144:ef7eb2e8f9f7	3819
<>	144:ef7eb2e8f9f7	3820	/* Bit 1 : RAM block 3 behaviour in ON mode. */
<>	144:ef7eb2e8f9f7	3821	#define POWER_RAMONB_ONRAM3_Pos (1UL) /!< Position of ONRAM3 field. /
<>	144:ef7eb2e8f9f7	3822	#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /!< Bit mask of ONRAM3 field. /
<>	144:ef7eb2e8f9f7	3823	#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /!< RAM block 33 OFF in ON mode. /
<>	144:ef7eb2e8f9f7	3824	#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /!< RAM block 3 ON in ON mode. /
<>	144:ef7eb2e8f9f7	3825
<>	144:ef7eb2e8f9f7	3826	/* Bit 0 : RAM block 2 behaviour in ON mode. */
<>	144:ef7eb2e8f9f7	3827	#define POWER_RAMONB_ONRAM2_Pos (0UL) /!< Position of ONRAM2 field. /
<>	144:ef7eb2e8f9f7	3828	#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /!< Bit mask of ONRAM2 field. /
<>	144:ef7eb2e8f9f7	3829	#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /!< RAM block 2 OFF in ON mode. /
<>	144:ef7eb2e8f9f7	3830	#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /!< RAM block 2 ON in ON mode. /
<>	144:ef7eb2e8f9f7	3831
<>	144:ef7eb2e8f9f7	3832	/* Register: POWER_DCDCEN */
<>	144:ef7eb2e8f9f7	3833	/* Description: DCDC converter enable configuration register. */
<>	144:ef7eb2e8f9f7	3834
<>	144:ef7eb2e8f9f7	3835	/* Bit 0 : Enable DCDC converter. */
<>	144:ef7eb2e8f9f7	3836	#define POWER_DCDCEN_DCDCEN_Pos (0UL) /!< Position of DCDCEN field. /
<>	144:ef7eb2e8f9f7	3837	#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /!< Bit mask of DCDCEN field. /
<>	144:ef7eb2e8f9f7	3838	#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /!< DCDC converter disabled. /
<>	144:ef7eb2e8f9f7	3839	#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /!< DCDC converter enabled. /
<>	144:ef7eb2e8f9f7	3840
<>	144:ef7eb2e8f9f7	3841	/* Register: POWER_DCDCFORCE */
<>	144:ef7eb2e8f9f7	3842	/* Description: DCDC power-up force register. */
<>	144:ef7eb2e8f9f7	3843
<>	144:ef7eb2e8f9f7	3844	/* Bit 1 : DCDC power-up force on. */
<>	144:ef7eb2e8f9f7	3845	#define POWER_DCDCFORCE_FORCEON_Pos (1UL) /!< Position of FORCEON field. /
<>	144:ef7eb2e8f9f7	3846	#define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /!< Bit mask of FORCEON field. /
<>	144:ef7eb2e8f9f7	3847	#define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /!< No force. /
<>	144:ef7eb2e8f9f7	3848	#define POWER_DCDCFORCE_FORCEON_Force (1UL) /!< Force. /
<>	144:ef7eb2e8f9f7	3849
<>	144:ef7eb2e8f9f7	3850	/* Bit 0 : DCDC power-up force off. */
<>	144:ef7eb2e8f9f7	3851	#define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /!< Position of FORCEOFF field. /
<>	144:ef7eb2e8f9f7	3852	#define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /!< Bit mask of FORCEOFF field. /
<>	144:ef7eb2e8f9f7	3853	#define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /!< No force. /
<>	144:ef7eb2e8f9f7	3854	#define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /!< Force. /
<>	144:ef7eb2e8f9f7	3855
<>	144:ef7eb2e8f9f7	3856
<>	144:ef7eb2e8f9f7	3857	/* Peripheral: PPI */
<>	144:ef7eb2e8f9f7	3858	/* Description: PPI controller. */
<>	144:ef7eb2e8f9f7	3859
<>	144:ef7eb2e8f9f7	3860	/* Register: PPI_CHEN */
<>	144:ef7eb2e8f9f7	3861	/* Description: Channel enable. */
<>	144:ef7eb2e8f9f7	3862
<>	144:ef7eb2e8f9f7	3863	/* Bit 31 : Enable PPI channel 31. */
<>	144:ef7eb2e8f9f7	3864	#define PPI_CHEN_CH31_Pos (31UL) /!< Position of CH31 field. /
<>	144:ef7eb2e8f9f7	3865	#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /!< Bit mask of CH31 field. /
<>	144:ef7eb2e8f9f7	3866	#define PPI_CHEN_CH31_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	3867	#define PPI_CHEN_CH31_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	3868
<>	144:ef7eb2e8f9f7	3869	/* Bit 30 : Enable PPI channel 30. */
<>	144:ef7eb2e8f9f7	3870	#define PPI_CHEN_CH30_Pos (30UL) /!< Position of CH30 field. /
<>	144:ef7eb2e8f9f7	3871	#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /!< Bit mask of CH30 field. /
<>	144:ef7eb2e8f9f7	3872	#define PPI_CHEN_CH30_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	3873	#define PPI_CHEN_CH30_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	3874
<>	144:ef7eb2e8f9f7	3875	/* Bit 29 : Enable PPI channel 29. */
<>	144:ef7eb2e8f9f7	3876	#define PPI_CHEN_CH29_Pos (29UL) /!< Position of CH29 field. /
<>	144:ef7eb2e8f9f7	3877	#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /!< Bit mask of CH29 field. /
<>	144:ef7eb2e8f9f7	3878	#define PPI_CHEN_CH29_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	3879	#define PPI_CHEN_CH29_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	3880
<>	144:ef7eb2e8f9f7	3881	/* Bit 28 : Enable PPI channel 28. */
<>	144:ef7eb2e8f9f7	3882	#define PPI_CHEN_CH28_Pos (28UL) /!< Position of CH28 field. /
<>	144:ef7eb2e8f9f7	3883	#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /!< Bit mask of CH28 field. /
<>	144:ef7eb2e8f9f7	3884	#define PPI_CHEN_CH28_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	3885	#define PPI_CHEN_CH28_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	3886
<>	144:ef7eb2e8f9f7	3887	/* Bit 27 : Enable PPI channel 27. */
<>	144:ef7eb2e8f9f7	3888	#define PPI_CHEN_CH27_Pos (27UL) /!< Position of CH27 field. /
<>	144:ef7eb2e8f9f7	3889	#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /!< Bit mask of CH27 field. /
<>	144:ef7eb2e8f9f7	3890	#define PPI_CHEN_CH27_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	3891	#define PPI_CHEN_CH27_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	3892
<>	144:ef7eb2e8f9f7	3893	/* Bit 26 : Enable PPI channel 26. */
<>	144:ef7eb2e8f9f7	3894	#define PPI_CHEN_CH26_Pos (26UL) /!< Position of CH26 field. /
<>	144:ef7eb2e8f9f7	3895	#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /!< Bit mask of CH26 field. /
<>	144:ef7eb2e8f9f7	3896	#define PPI_CHEN_CH26_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	3897	#define PPI_CHEN_CH26_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	3898
<>	144:ef7eb2e8f9f7	3899	/* Bit 25 : Enable PPI channel 25. */
<>	144:ef7eb2e8f9f7	3900	#define PPI_CHEN_CH25_Pos (25UL) /!< Position of CH25 field. /
<>	144:ef7eb2e8f9f7	3901	#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /!< Bit mask of CH25 field. /
<>	144:ef7eb2e8f9f7	3902	#define PPI_CHEN_CH25_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	3903	#define PPI_CHEN_CH25_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	3904
<>	144:ef7eb2e8f9f7	3905	/* Bit 24 : Enable PPI channel 24. */
<>	144:ef7eb2e8f9f7	3906	#define PPI_CHEN_CH24_Pos (24UL) /!< Position of CH24 field. /
<>	144:ef7eb2e8f9f7	3907	#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /!< Bit mask of CH24 field. /
<>	144:ef7eb2e8f9f7	3908	#define PPI_CHEN_CH24_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	3909	#define PPI_CHEN_CH24_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	3910
<>	144:ef7eb2e8f9f7	3911	/* Bit 23 : Enable PPI channel 23. */
<>	144:ef7eb2e8f9f7	3912	#define PPI_CHEN_CH23_Pos (23UL) /!< Position of CH23 field. /
<>	144:ef7eb2e8f9f7	3913	#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /!< Bit mask of CH23 field. /
<>	144:ef7eb2e8f9f7	3914	#define PPI_CHEN_CH23_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	3915	#define PPI_CHEN_CH23_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	3916
<>	144:ef7eb2e8f9f7	3917	/* Bit 22 : Enable PPI channel 22. */
<>	144:ef7eb2e8f9f7	3918	#define PPI_CHEN_CH22_Pos (22UL) /!< Position of CH22 field. /
<>	144:ef7eb2e8f9f7	3919	#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /!< Bit mask of CH22 field. /
<>	144:ef7eb2e8f9f7	3920	#define PPI_CHEN_CH22_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	3921	#define PPI_CHEN_CH22_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	3922
<>	144:ef7eb2e8f9f7	3923	/* Bit 21 : Enable PPI channel 21. */
<>	144:ef7eb2e8f9f7	3924	#define PPI_CHEN_CH21_Pos (21UL) /!< Position of CH21 field. /
<>	144:ef7eb2e8f9f7	3925	#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /!< Bit mask of CH21 field. /
<>	144:ef7eb2e8f9f7	3926	#define PPI_CHEN_CH21_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	3927	#define PPI_CHEN_CH21_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	3928
<>	144:ef7eb2e8f9f7	3929	/* Bit 20 : Enable PPI channel 20. */
<>	144:ef7eb2e8f9f7	3930	#define PPI_CHEN_CH20_Pos (20UL) /!< Position of CH20 field. /
<>	144:ef7eb2e8f9f7	3931	#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /!< Bit mask of CH20 field. /
<>	144:ef7eb2e8f9f7	3932	#define PPI_CHEN_CH20_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	3933	#define PPI_CHEN_CH20_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	3934
<>	144:ef7eb2e8f9f7	3935	/* Bit 15 : Enable PPI channel 15. */
<>	144:ef7eb2e8f9f7	3936	#define PPI_CHEN_CH15_Pos (15UL) /!< Position of CH15 field. /
<>	144:ef7eb2e8f9f7	3937	#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /!< Bit mask of CH15 field. /
<>	144:ef7eb2e8f9f7	3938	#define PPI_CHEN_CH15_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	3939	#define PPI_CHEN_CH15_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	3940
<>	144:ef7eb2e8f9f7	3941	/* Bit 14 : Enable PPI channel 14. */
<>	144:ef7eb2e8f9f7	3942	#define PPI_CHEN_CH14_Pos (14UL) /!< Position of CH14 field. /
<>	144:ef7eb2e8f9f7	3943	#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /!< Bit mask of CH14 field. /
<>	144:ef7eb2e8f9f7	3944	#define PPI_CHEN_CH14_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	3945	#define PPI_CHEN_CH14_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	3946
<>	144:ef7eb2e8f9f7	3947	/* Bit 13 : Enable PPI channel 13. */
<>	144:ef7eb2e8f9f7	3948	#define PPI_CHEN_CH13_Pos (13UL) /!< Position of CH13 field. /
<>	144:ef7eb2e8f9f7	3949	#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /!< Bit mask of CH13 field. /
<>	144:ef7eb2e8f9f7	3950	#define PPI_CHEN_CH13_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	3951	#define PPI_CHEN_CH13_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	3952
<>	144:ef7eb2e8f9f7	3953	/* Bit 12 : Enable PPI channel 12. */
<>	144:ef7eb2e8f9f7	3954	#define PPI_CHEN_CH12_Pos (12UL) /!< Position of CH12 field. /
<>	144:ef7eb2e8f9f7	3955	#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /!< Bit mask of CH12 field. /
<>	144:ef7eb2e8f9f7	3956	#define PPI_CHEN_CH12_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	3957	#define PPI_CHEN_CH12_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	3958
<>	144:ef7eb2e8f9f7	3959	/* Bit 11 : Enable PPI channel 11. */
<>	144:ef7eb2e8f9f7	3960	#define PPI_CHEN_CH11_Pos (11UL) /!< Position of CH11 field. /
<>	144:ef7eb2e8f9f7	3961	#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /!< Bit mask of CH11 field. /
<>	144:ef7eb2e8f9f7	3962	#define PPI_CHEN_CH11_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	3963	#define PPI_CHEN_CH11_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	3964
<>	144:ef7eb2e8f9f7	3965	/* Bit 10 : Enable PPI channel 10. */
<>	144:ef7eb2e8f9f7	3966	#define PPI_CHEN_CH10_Pos (10UL) /!< Position of CH10 field. /
<>	144:ef7eb2e8f9f7	3967	#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /!< Bit mask of CH10 field. /
<>	144:ef7eb2e8f9f7	3968	#define PPI_CHEN_CH10_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	3969	#define PPI_CHEN_CH10_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	3970
<>	144:ef7eb2e8f9f7	3971	/* Bit 9 : Enable PPI channel 9. */
<>	144:ef7eb2e8f9f7	3972	#define PPI_CHEN_CH9_Pos (9UL) /!< Position of CH9 field. /
<>	144:ef7eb2e8f9f7	3973	#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /!< Bit mask of CH9 field. /
<>	144:ef7eb2e8f9f7	3974	#define PPI_CHEN_CH9_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	3975	#define PPI_CHEN_CH9_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	3976
<>	144:ef7eb2e8f9f7	3977	/* Bit 8 : Enable PPI channel 8. */
<>	144:ef7eb2e8f9f7	3978	#define PPI_CHEN_CH8_Pos (8UL) /!< Position of CH8 field. /
<>	144:ef7eb2e8f9f7	3979	#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /!< Bit mask of CH8 field. /
<>	144:ef7eb2e8f9f7	3980	#define PPI_CHEN_CH8_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	3981	#define PPI_CHEN_CH8_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	3982
<>	144:ef7eb2e8f9f7	3983	/* Bit 7 : Enable PPI channel 7. */
<>	144:ef7eb2e8f9f7	3984	#define PPI_CHEN_CH7_Pos (7UL) /!< Position of CH7 field. /
<>	144:ef7eb2e8f9f7	3985	#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /!< Bit mask of CH7 field. /
<>	144:ef7eb2e8f9f7	3986	#define PPI_CHEN_CH7_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	3987	#define PPI_CHEN_CH7_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	3988
<>	144:ef7eb2e8f9f7	3989	/* Bit 6 : Enable PPI channel 6. */
<>	144:ef7eb2e8f9f7	3990	#define PPI_CHEN_CH6_Pos (6UL) /!< Position of CH6 field. /
<>	144:ef7eb2e8f9f7	3991	#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /!< Bit mask of CH6 field. /
<>	144:ef7eb2e8f9f7	3992	#define PPI_CHEN_CH6_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	3993	#define PPI_CHEN_CH6_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	3994
<>	144:ef7eb2e8f9f7	3995	/* Bit 5 : Enable PPI channel 5. */
<>	144:ef7eb2e8f9f7	3996	#define PPI_CHEN_CH5_Pos (5UL) /!< Position of CH5 field. /
<>	144:ef7eb2e8f9f7	3997	#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /!< Bit mask of CH5 field. /
<>	144:ef7eb2e8f9f7	3998	#define PPI_CHEN_CH5_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	3999	#define PPI_CHEN_CH5_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4000
<>	144:ef7eb2e8f9f7	4001	/* Bit 4 : Enable PPI channel 4. */
<>	144:ef7eb2e8f9f7	4002	#define PPI_CHEN_CH4_Pos (4UL) /!< Position of CH4 field. /
<>	144:ef7eb2e8f9f7	4003	#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /!< Bit mask of CH4 field. /
<>	144:ef7eb2e8f9f7	4004	#define PPI_CHEN_CH4_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4005	#define PPI_CHEN_CH4_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4006
<>	144:ef7eb2e8f9f7	4007	/* Bit 3 : Enable PPI channel 3. */
<>	144:ef7eb2e8f9f7	4008	#define PPI_CHEN_CH3_Pos (3UL) /!< Position of CH3 field. /
<>	144:ef7eb2e8f9f7	4009	#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /!< Bit mask of CH3 field. /
<>	144:ef7eb2e8f9f7	4010	#define PPI_CHEN_CH3_Disabled (0UL) /!< Channel disabled /
<>	144:ef7eb2e8f9f7	4011	#define PPI_CHEN_CH3_Enabled (1UL) /!< Channel enabled /
<>	144:ef7eb2e8f9f7	4012
<>	144:ef7eb2e8f9f7	4013	/* Bit 2 : Enable PPI channel 2. */
<>	144:ef7eb2e8f9f7	4014	#define PPI_CHEN_CH2_Pos (2UL) /!< Position of CH2 field. /
<>	144:ef7eb2e8f9f7	4015	#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /!< Bit mask of CH2 field. /
<>	144:ef7eb2e8f9f7	4016	#define PPI_CHEN_CH2_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4017	#define PPI_CHEN_CH2_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4018
<>	144:ef7eb2e8f9f7	4019	/* Bit 1 : Enable PPI channel 1. */
<>	144:ef7eb2e8f9f7	4020	#define PPI_CHEN_CH1_Pos (1UL) /!< Position of CH1 field. /
<>	144:ef7eb2e8f9f7	4021	#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /!< Bit mask of CH1 field. /
<>	144:ef7eb2e8f9f7	4022	#define PPI_CHEN_CH1_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4023	#define PPI_CHEN_CH1_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4024
<>	144:ef7eb2e8f9f7	4025	/* Bit 0 : Enable PPI channel 0. */
<>	144:ef7eb2e8f9f7	4026	#define PPI_CHEN_CH0_Pos (0UL) /!< Position of CH0 field. /
<>	144:ef7eb2e8f9f7	4027	#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /!< Bit mask of CH0 field. /
<>	144:ef7eb2e8f9f7	4028	#define PPI_CHEN_CH0_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4029	#define PPI_CHEN_CH0_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4030
<>	144:ef7eb2e8f9f7	4031	/* Register: PPI_CHENSET */
<>	144:ef7eb2e8f9f7	4032	/* Description: Channel enable set. */
<>	144:ef7eb2e8f9f7	4033
<>	144:ef7eb2e8f9f7	4034	/* Bit 31 : Enable PPI channel 31. */
<>	144:ef7eb2e8f9f7	4035	#define PPI_CHENSET_CH31_Pos (31UL) /!< Position of CH31 field. /
<>	144:ef7eb2e8f9f7	4036	#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /!< Bit mask of CH31 field. /
<>	144:ef7eb2e8f9f7	4037	#define PPI_CHENSET_CH31_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4038	#define PPI_CHENSET_CH31_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4039	#define PPI_CHENSET_CH31_Set (1UL) /!< Enable channel on write. /
<>	144:ef7eb2e8f9f7	4040
<>	144:ef7eb2e8f9f7	4041	/* Bit 30 : Enable PPI channel 30. */
<>	144:ef7eb2e8f9f7	4042	#define PPI_CHENSET_CH30_Pos (30UL) /!< Position of CH30 field. /
<>	144:ef7eb2e8f9f7	4043	#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /!< Bit mask of CH30 field. /
<>	144:ef7eb2e8f9f7	4044	#define PPI_CHENSET_CH30_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4045	#define PPI_CHENSET_CH30_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4046	#define PPI_CHENSET_CH30_Set (1UL) /!< Enable channel on write. /
<>	144:ef7eb2e8f9f7	4047
<>	144:ef7eb2e8f9f7	4048	/* Bit 29 : Enable PPI channel 29. */
<>	144:ef7eb2e8f9f7	4049	#define PPI_CHENSET_CH29_Pos (29UL) /!< Position of CH29 field. /
<>	144:ef7eb2e8f9f7	4050	#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /!< Bit mask of CH29 field. /
<>	144:ef7eb2e8f9f7	4051	#define PPI_CHENSET_CH29_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4052	#define PPI_CHENSET_CH29_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4053	#define PPI_CHENSET_CH29_Set (1UL) /!< Enable channel on write. /
<>	144:ef7eb2e8f9f7	4054
<>	144:ef7eb2e8f9f7	4055	/* Bit 28 : Enable PPI channel 28. */
<>	144:ef7eb2e8f9f7	4056	#define PPI_CHENSET_CH28_Pos (28UL) /!< Position of CH28 field. /
<>	144:ef7eb2e8f9f7	4057	#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /!< Bit mask of CH28 field. /
<>	144:ef7eb2e8f9f7	4058	#define PPI_CHENSET_CH28_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4059	#define PPI_CHENSET_CH28_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4060	#define PPI_CHENSET_CH28_Set (1UL) /!< Enable channel on write. /
<>	144:ef7eb2e8f9f7	4061
<>	144:ef7eb2e8f9f7	4062	/* Bit 27 : Enable PPI channel 27. */
<>	144:ef7eb2e8f9f7	4063	#define PPI_CHENSET_CH27_Pos (27UL) /!< Position of CH27 field. /
<>	144:ef7eb2e8f9f7	4064	#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /!< Bit mask of CH27 field. /
<>	144:ef7eb2e8f9f7	4065	#define PPI_CHENSET_CH27_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4066	#define PPI_CHENSET_CH27_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4067	#define PPI_CHENSET_CH27_Set (1UL) /!< Enable channel on write. /
<>	144:ef7eb2e8f9f7	4068
<>	144:ef7eb2e8f9f7	4069	/* Bit 26 : Enable PPI channel 26. */
<>	144:ef7eb2e8f9f7	4070	#define PPI_CHENSET_CH26_Pos (26UL) /!< Position of CH26 field. /
<>	144:ef7eb2e8f9f7	4071	#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /!< Bit mask of CH26 field. /
<>	144:ef7eb2e8f9f7	4072	#define PPI_CHENSET_CH26_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4073	#define PPI_CHENSET_CH26_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4074	#define PPI_CHENSET_CH26_Set (1UL) /!< Enable channel on write. /
<>	144:ef7eb2e8f9f7	4075
<>	144:ef7eb2e8f9f7	4076	/* Bit 25 : Enable PPI channel 25. */
<>	144:ef7eb2e8f9f7	4077	#define PPI_CHENSET_CH25_Pos (25UL) /!< Position of CH25 field. /
<>	144:ef7eb2e8f9f7	4078	#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /!< Bit mask of CH25 field. /
<>	144:ef7eb2e8f9f7	4079	#define PPI_CHENSET_CH25_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4080	#define PPI_CHENSET_CH25_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4081	#define PPI_CHENSET_CH25_Set (1UL) /!< Enable channel on write. /
<>	144:ef7eb2e8f9f7	4082
<>	144:ef7eb2e8f9f7	4083	/* Bit 24 : Enable PPI channel 24. */
<>	144:ef7eb2e8f9f7	4084	#define PPI_CHENSET_CH24_Pos (24UL) /!< Position of CH24 field. /
<>	144:ef7eb2e8f9f7	4085	#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /!< Bit mask of CH24 field. /
<>	144:ef7eb2e8f9f7	4086	#define PPI_CHENSET_CH24_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4087	#define PPI_CHENSET_CH24_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4088	#define PPI_CHENSET_CH24_Set (1UL) /!< Enable channel on write. /
<>	144:ef7eb2e8f9f7	4089
<>	144:ef7eb2e8f9f7	4090	/* Bit 23 : Enable PPI channel 23. */
<>	144:ef7eb2e8f9f7	4091	#define PPI_CHENSET_CH23_Pos (23UL) /!< Position of CH23 field. /
<>	144:ef7eb2e8f9f7	4092	#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /!< Bit mask of CH23 field. /
<>	144:ef7eb2e8f9f7	4093	#define PPI_CHENSET_CH23_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4094	#define PPI_CHENSET_CH23_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4095	#define PPI_CHENSET_CH23_Set (1UL) /!< Enable channel on write. /
<>	144:ef7eb2e8f9f7	4096
<>	144:ef7eb2e8f9f7	4097	/* Bit 22 : Enable PPI channel 22. */
<>	144:ef7eb2e8f9f7	4098	#define PPI_CHENSET_CH22_Pos (22UL) /!< Position of CH22 field. /
<>	144:ef7eb2e8f9f7	4099	#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /!< Bit mask of CH22 field. /
<>	144:ef7eb2e8f9f7	4100	#define PPI_CHENSET_CH22_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4101	#define PPI_CHENSET_CH22_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4102	#define PPI_CHENSET_CH22_Set (1UL) /!< Enable channel on write. /
<>	144:ef7eb2e8f9f7	4103
<>	144:ef7eb2e8f9f7	4104	/* Bit 21 : Enable PPI channel 21. */
<>	144:ef7eb2e8f9f7	4105	#define PPI_CHENSET_CH21_Pos (21UL) /!< Position of CH21 field. /
<>	144:ef7eb2e8f9f7	4106	#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /!< Bit mask of CH21 field. /
<>	144:ef7eb2e8f9f7	4107	#define PPI_CHENSET_CH21_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4108	#define PPI_CHENSET_CH21_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4109	#define PPI_CHENSET_CH21_Set (1UL) /!< Enable channel on write. /
<>	144:ef7eb2e8f9f7	4110
<>	144:ef7eb2e8f9f7	4111	/* Bit 20 : Enable PPI channel 20. */
<>	144:ef7eb2e8f9f7	4112	#define PPI_CHENSET_CH20_Pos (20UL) /!< Position of CH20 field. /
<>	144:ef7eb2e8f9f7	4113	#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /!< Bit mask of CH20 field. /
<>	144:ef7eb2e8f9f7	4114	#define PPI_CHENSET_CH20_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4115	#define PPI_CHENSET_CH20_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4116	#define PPI_CHENSET_CH20_Set (1UL) /!< Enable channel on write. /
<>	144:ef7eb2e8f9f7	4117
<>	144:ef7eb2e8f9f7	4118	/* Bit 15 : Enable PPI channel 15. */
<>	144:ef7eb2e8f9f7	4119	#define PPI_CHENSET_CH15_Pos (15UL) /!< Position of CH15 field. /
<>	144:ef7eb2e8f9f7	4120	#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /!< Bit mask of CH15 field. /
<>	144:ef7eb2e8f9f7	4121	#define PPI_CHENSET_CH15_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4122	#define PPI_CHENSET_CH15_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4123	#define PPI_CHENSET_CH15_Set (1UL) /!< Enable channel on write. /
<>	144:ef7eb2e8f9f7	4124
<>	144:ef7eb2e8f9f7	4125	/* Bit 14 : Enable PPI channel 14. */
<>	144:ef7eb2e8f9f7	4126	#define PPI_CHENSET_CH14_Pos (14UL) /!< Position of CH14 field. /
<>	144:ef7eb2e8f9f7	4127	#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /!< Bit mask of CH14 field. /
<>	144:ef7eb2e8f9f7	4128	#define PPI_CHENSET_CH14_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4129	#define PPI_CHENSET_CH14_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4130	#define PPI_CHENSET_CH14_Set (1UL) /!< Enable channel on write. /
<>	144:ef7eb2e8f9f7	4131
<>	144:ef7eb2e8f9f7	4132	/* Bit 13 : Enable PPI channel 13. */
<>	144:ef7eb2e8f9f7	4133	#define PPI_CHENSET_CH13_Pos (13UL) /!< Position of CH13 field. /
<>	144:ef7eb2e8f9f7	4134	#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /!< Bit mask of CH13 field. /
<>	144:ef7eb2e8f9f7	4135	#define PPI_CHENSET_CH13_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4136	#define PPI_CHENSET_CH13_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4137	#define PPI_CHENSET_CH13_Set (1UL) /!< Enable channel on write. /
<>	144:ef7eb2e8f9f7	4138
<>	144:ef7eb2e8f9f7	4139	/* Bit 12 : Enable PPI channel 12. */
<>	144:ef7eb2e8f9f7	4140	#define PPI_CHENSET_CH12_Pos (12UL) /!< Position of CH12 field. /
<>	144:ef7eb2e8f9f7	4141	#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /!< Bit mask of CH12 field. /
<>	144:ef7eb2e8f9f7	4142	#define PPI_CHENSET_CH12_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4143	#define PPI_CHENSET_CH12_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4144	#define PPI_CHENSET_CH12_Set (1UL) /!< Enable channel on write. /
<>	144:ef7eb2e8f9f7	4145
<>	144:ef7eb2e8f9f7	4146	/* Bit 11 : Enable PPI channel 11. */
<>	144:ef7eb2e8f9f7	4147	#define PPI_CHENSET_CH11_Pos (11UL) /!< Position of CH11 field. /
<>	144:ef7eb2e8f9f7	4148	#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /!< Bit mask of CH11 field. /
<>	144:ef7eb2e8f9f7	4149	#define PPI_CHENSET_CH11_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4150	#define PPI_CHENSET_CH11_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4151	#define PPI_CHENSET_CH11_Set (1UL) /!< Enable channel on write. /
<>	144:ef7eb2e8f9f7	4152
<>	144:ef7eb2e8f9f7	4153	/* Bit 10 : Enable PPI channel 10. */
<>	144:ef7eb2e8f9f7	4154	#define PPI_CHENSET_CH10_Pos (10UL) /!< Position of CH10 field. /
<>	144:ef7eb2e8f9f7	4155	#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /!< Bit mask of CH10 field. /
<>	144:ef7eb2e8f9f7	4156	#define PPI_CHENSET_CH10_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4157	#define PPI_CHENSET_CH10_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4158	#define PPI_CHENSET_CH10_Set (1UL) /!< Enable channel on write. /
<>	144:ef7eb2e8f9f7	4159
<>	144:ef7eb2e8f9f7	4160	/* Bit 9 : Enable PPI channel 9. */
<>	144:ef7eb2e8f9f7	4161	#define PPI_CHENSET_CH9_Pos (9UL) /!< Position of CH9 field. /
<>	144:ef7eb2e8f9f7	4162	#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /!< Bit mask of CH9 field. /
<>	144:ef7eb2e8f9f7	4163	#define PPI_CHENSET_CH9_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4164	#define PPI_CHENSET_CH9_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4165	#define PPI_CHENSET_CH9_Set (1UL) /!< Enable channel on write. /
<>	144:ef7eb2e8f9f7	4166
<>	144:ef7eb2e8f9f7	4167	/* Bit 8 : Enable PPI channel 8. */
<>	144:ef7eb2e8f9f7	4168	#define PPI_CHENSET_CH8_Pos (8UL) /!< Position of CH8 field. /
<>	144:ef7eb2e8f9f7	4169	#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /!< Bit mask of CH8 field. /
<>	144:ef7eb2e8f9f7	4170	#define PPI_CHENSET_CH8_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4171	#define PPI_CHENSET_CH8_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4172	#define PPI_CHENSET_CH8_Set (1UL) /!< Enable channel on write. /
<>	144:ef7eb2e8f9f7	4173
<>	144:ef7eb2e8f9f7	4174	/* Bit 7 : Enable PPI channel 7. */
<>	144:ef7eb2e8f9f7	4175	#define PPI_CHENSET_CH7_Pos (7UL) /!< Position of CH7 field. /
<>	144:ef7eb2e8f9f7	4176	#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /!< Bit mask of CH7 field. /
<>	144:ef7eb2e8f9f7	4177	#define PPI_CHENSET_CH7_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4178	#define PPI_CHENSET_CH7_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4179	#define PPI_CHENSET_CH7_Set (1UL) /!< Enable channel on write. /
<>	144:ef7eb2e8f9f7	4180
<>	144:ef7eb2e8f9f7	4181	/* Bit 6 : Enable PPI channel 6. */
<>	144:ef7eb2e8f9f7	4182	#define PPI_CHENSET_CH6_Pos (6UL) /!< Position of CH6 field. /
<>	144:ef7eb2e8f9f7	4183	#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /!< Bit mask of CH6 field. /
<>	144:ef7eb2e8f9f7	4184	#define PPI_CHENSET_CH6_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4185	#define PPI_CHENSET_CH6_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4186	#define PPI_CHENSET_CH6_Set (1UL) /!< Enable channel on write. /
<>	144:ef7eb2e8f9f7	4187
<>	144:ef7eb2e8f9f7	4188	/* Bit 5 : Enable PPI channel 5. */
<>	144:ef7eb2e8f9f7	4189	#define PPI_CHENSET_CH5_Pos (5UL) /!< Position of CH5 field. /
<>	144:ef7eb2e8f9f7	4190	#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /!< Bit mask of CH5 field. /
<>	144:ef7eb2e8f9f7	4191	#define PPI_CHENSET_CH5_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4192	#define PPI_CHENSET_CH5_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4193	#define PPI_CHENSET_CH5_Set (1UL) /!< Enable channel on write. /
<>	144:ef7eb2e8f9f7	4194
<>	144:ef7eb2e8f9f7	4195	/* Bit 4 : Enable PPI channel 4. */
<>	144:ef7eb2e8f9f7	4196	#define PPI_CHENSET_CH4_Pos (4UL) /!< Position of CH4 field. /
<>	144:ef7eb2e8f9f7	4197	#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /!< Bit mask of CH4 field. /
<>	144:ef7eb2e8f9f7	4198	#define PPI_CHENSET_CH4_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4199	#define PPI_CHENSET_CH4_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4200	#define PPI_CHENSET_CH4_Set (1UL) /!< Enable channel on write. /
<>	144:ef7eb2e8f9f7	4201
<>	144:ef7eb2e8f9f7	4202	/* Bit 3 : Enable PPI channel 3. */
<>	144:ef7eb2e8f9f7	4203	#define PPI_CHENSET_CH3_Pos (3UL) /!< Position of CH3 field. /
<>	144:ef7eb2e8f9f7	4204	#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /!< Bit mask of CH3 field. /
<>	144:ef7eb2e8f9f7	4205	#define PPI_CHENSET_CH3_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4206	#define PPI_CHENSET_CH3_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4207	#define PPI_CHENSET_CH3_Set (1UL) /!< Enable channel on write. /
<>	144:ef7eb2e8f9f7	4208
<>	144:ef7eb2e8f9f7	4209	/* Bit 2 : Enable PPI channel 2. */
<>	144:ef7eb2e8f9f7	4210	#define PPI_CHENSET_CH2_Pos (2UL) /!< Position of CH2 field. /
<>	144:ef7eb2e8f9f7	4211	#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /!< Bit mask of CH2 field. /
<>	144:ef7eb2e8f9f7	4212	#define PPI_CHENSET_CH2_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4213	#define PPI_CHENSET_CH2_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4214	#define PPI_CHENSET_CH2_Set (1UL) /!< Enable channel on write. /
<>	144:ef7eb2e8f9f7	4215
<>	144:ef7eb2e8f9f7	4216	/* Bit 1 : Enable PPI channel 1. */
<>	144:ef7eb2e8f9f7	4217	#define PPI_CHENSET_CH1_Pos (1UL) /!< Position of CH1 field. /
<>	144:ef7eb2e8f9f7	4218	#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /!< Bit mask of CH1 field. /
<>	144:ef7eb2e8f9f7	4219	#define PPI_CHENSET_CH1_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4220	#define PPI_CHENSET_CH1_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4221	#define PPI_CHENSET_CH1_Set (1UL) /!< Enable channel on write. /
<>	144:ef7eb2e8f9f7	4222
<>	144:ef7eb2e8f9f7	4223	/* Bit 0 : Enable PPI channel 0. */
<>	144:ef7eb2e8f9f7	4224	#define PPI_CHENSET_CH0_Pos (0UL) /!< Position of CH0 field. /
<>	144:ef7eb2e8f9f7	4225	#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /!< Bit mask of CH0 field. /
<>	144:ef7eb2e8f9f7	4226	#define PPI_CHENSET_CH0_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4227	#define PPI_CHENSET_CH0_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4228	#define PPI_CHENSET_CH0_Set (1UL) /!< Enable channel on write. /
<>	144:ef7eb2e8f9f7	4229
<>	144:ef7eb2e8f9f7	4230	/* Register: PPI_CHENCLR */
<>	144:ef7eb2e8f9f7	4231	/* Description: Channel enable clear. */
<>	144:ef7eb2e8f9f7	4232
<>	144:ef7eb2e8f9f7	4233	/* Bit 31 : Disable PPI channel 31. */
<>	144:ef7eb2e8f9f7	4234	#define PPI_CHENCLR_CH31_Pos (31UL) /!< Position of CH31 field. /
<>	144:ef7eb2e8f9f7	4235	#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /!< Bit mask of CH31 field. /
<>	144:ef7eb2e8f9f7	4236	#define PPI_CHENCLR_CH31_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4237	#define PPI_CHENCLR_CH31_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4238	#define PPI_CHENCLR_CH31_Clear (1UL) /!< Disable channel on write. /
<>	144:ef7eb2e8f9f7	4239
<>	144:ef7eb2e8f9f7	4240	/* Bit 30 : Disable PPI channel 30. */
<>	144:ef7eb2e8f9f7	4241	#define PPI_CHENCLR_CH30_Pos (30UL) /!< Position of CH30 field. /
<>	144:ef7eb2e8f9f7	4242	#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /!< Bit mask of CH30 field. /
<>	144:ef7eb2e8f9f7	4243	#define PPI_CHENCLR_CH30_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4244	#define PPI_CHENCLR_CH30_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4245	#define PPI_CHENCLR_CH30_Clear (1UL) /!< Disable channel on write. /
<>	144:ef7eb2e8f9f7	4246
<>	144:ef7eb2e8f9f7	4247	/* Bit 29 : Disable PPI channel 29. */
<>	144:ef7eb2e8f9f7	4248	#define PPI_CHENCLR_CH29_Pos (29UL) /!< Position of CH29 field. /
<>	144:ef7eb2e8f9f7	4249	#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /!< Bit mask of CH29 field. /
<>	144:ef7eb2e8f9f7	4250	#define PPI_CHENCLR_CH29_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4251	#define PPI_CHENCLR_CH29_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4252	#define PPI_CHENCLR_CH29_Clear (1UL) /!< Disable channel on write. /
<>	144:ef7eb2e8f9f7	4253
<>	144:ef7eb2e8f9f7	4254	/* Bit 28 : Disable PPI channel 28. */
<>	144:ef7eb2e8f9f7	4255	#define PPI_CHENCLR_CH28_Pos (28UL) /!< Position of CH28 field. /
<>	144:ef7eb2e8f9f7	4256	#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /!< Bit mask of CH28 field. /
<>	144:ef7eb2e8f9f7	4257	#define PPI_CHENCLR_CH28_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4258	#define PPI_CHENCLR_CH28_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4259	#define PPI_CHENCLR_CH28_Clear (1UL) /!< Disable channel on write. /
<>	144:ef7eb2e8f9f7	4260
<>	144:ef7eb2e8f9f7	4261	/* Bit 27 : Disable PPI channel 27. */
<>	144:ef7eb2e8f9f7	4262	#define PPI_CHENCLR_CH27_Pos (27UL) /!< Position of CH27 field. /
<>	144:ef7eb2e8f9f7	4263	#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /!< Bit mask of CH27 field. /
<>	144:ef7eb2e8f9f7	4264	#define PPI_CHENCLR_CH27_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4265	#define PPI_CHENCLR_CH27_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4266	#define PPI_CHENCLR_CH27_Clear (1UL) /!< Disable channel on write. /
<>	144:ef7eb2e8f9f7	4267
<>	144:ef7eb2e8f9f7	4268	/* Bit 26 : Disable PPI channel 26. */
<>	144:ef7eb2e8f9f7	4269	#define PPI_CHENCLR_CH26_Pos (26UL) /!< Position of CH26 field. /
<>	144:ef7eb2e8f9f7	4270	#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /!< Bit mask of CH26 field. /
<>	144:ef7eb2e8f9f7	4271	#define PPI_CHENCLR_CH26_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4272	#define PPI_CHENCLR_CH26_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4273	#define PPI_CHENCLR_CH26_Clear (1UL) /!< Disable channel on write. /
<>	144:ef7eb2e8f9f7	4274
<>	144:ef7eb2e8f9f7	4275	/* Bit 25 : Disable PPI channel 25. */
<>	144:ef7eb2e8f9f7	4276	#define PPI_CHENCLR_CH25_Pos (25UL) /!< Position of CH25 field. /
<>	144:ef7eb2e8f9f7	4277	#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /!< Bit mask of CH25 field. /
<>	144:ef7eb2e8f9f7	4278	#define PPI_CHENCLR_CH25_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4279	#define PPI_CHENCLR_CH25_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4280	#define PPI_CHENCLR_CH25_Clear (1UL) /!< Disable channel on write. /
<>	144:ef7eb2e8f9f7	4281
<>	144:ef7eb2e8f9f7	4282	/* Bit 24 : Disable PPI channel 24. */
<>	144:ef7eb2e8f9f7	4283	#define PPI_CHENCLR_CH24_Pos (24UL) /!< Position of CH24 field. /
<>	144:ef7eb2e8f9f7	4284	#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /!< Bit mask of CH24 field. /
<>	144:ef7eb2e8f9f7	4285	#define PPI_CHENCLR_CH24_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4286	#define PPI_CHENCLR_CH24_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4287	#define PPI_CHENCLR_CH24_Clear (1UL) /!< Disable channel on write. /
<>	144:ef7eb2e8f9f7	4288
<>	144:ef7eb2e8f9f7	4289	/* Bit 23 : Disable PPI channel 23. */
<>	144:ef7eb2e8f9f7	4290	#define PPI_CHENCLR_CH23_Pos (23UL) /!< Position of CH23 field. /
<>	144:ef7eb2e8f9f7	4291	#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /!< Bit mask of CH23 field. /
<>	144:ef7eb2e8f9f7	4292	#define PPI_CHENCLR_CH23_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4293	#define PPI_CHENCLR_CH23_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4294	#define PPI_CHENCLR_CH23_Clear (1UL) /!< Disable channel on write. /
<>	144:ef7eb2e8f9f7	4295
<>	144:ef7eb2e8f9f7	4296	/* Bit 22 : Disable PPI channel 22. */
<>	144:ef7eb2e8f9f7	4297	#define PPI_CHENCLR_CH22_Pos (22UL) /!< Position of CH22 field. /
<>	144:ef7eb2e8f9f7	4298	#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /!< Bit mask of CH22 field. /
<>	144:ef7eb2e8f9f7	4299	#define PPI_CHENCLR_CH22_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4300	#define PPI_CHENCLR_CH22_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4301	#define PPI_CHENCLR_CH22_Clear (1UL) /!< Disable channel on write. /
<>	144:ef7eb2e8f9f7	4302
<>	144:ef7eb2e8f9f7	4303	/* Bit 21 : Disable PPI channel 21. */
<>	144:ef7eb2e8f9f7	4304	#define PPI_CHENCLR_CH21_Pos (21UL) /!< Position of CH21 field. /
<>	144:ef7eb2e8f9f7	4305	#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /!< Bit mask of CH21 field. /
<>	144:ef7eb2e8f9f7	4306	#define PPI_CHENCLR_CH21_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4307	#define PPI_CHENCLR_CH21_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4308	#define PPI_CHENCLR_CH21_Clear (1UL) /!< Disable channel on write. /
<>	144:ef7eb2e8f9f7	4309
<>	144:ef7eb2e8f9f7	4310	/* Bit 20 : Disable PPI channel 20. */
<>	144:ef7eb2e8f9f7	4311	#define PPI_CHENCLR_CH20_Pos (20UL) /!< Position of CH20 field. /
<>	144:ef7eb2e8f9f7	4312	#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /!< Bit mask of CH20 field. /
<>	144:ef7eb2e8f9f7	4313	#define PPI_CHENCLR_CH20_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4314	#define PPI_CHENCLR_CH20_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4315	#define PPI_CHENCLR_CH20_Clear (1UL) /!< Disable channel on write. /
<>	144:ef7eb2e8f9f7	4316
<>	144:ef7eb2e8f9f7	4317	/* Bit 15 : Disable PPI channel 15. */
<>	144:ef7eb2e8f9f7	4318	#define PPI_CHENCLR_CH15_Pos (15UL) /!< Position of CH15 field. /
<>	144:ef7eb2e8f9f7	4319	#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /!< Bit mask of CH15 field. /
<>	144:ef7eb2e8f9f7	4320	#define PPI_CHENCLR_CH15_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4321	#define PPI_CHENCLR_CH15_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4322	#define PPI_CHENCLR_CH15_Clear (1UL) /!< Disable channel on write. /
<>	144:ef7eb2e8f9f7	4323
<>	144:ef7eb2e8f9f7	4324	/* Bit 14 : Disable PPI channel 14. */
<>	144:ef7eb2e8f9f7	4325	#define PPI_CHENCLR_CH14_Pos (14UL) /!< Position of CH14 field. /
<>	144:ef7eb2e8f9f7	4326	#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /!< Bit mask of CH14 field. /
<>	144:ef7eb2e8f9f7	4327	#define PPI_CHENCLR_CH14_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4328	#define PPI_CHENCLR_CH14_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4329	#define PPI_CHENCLR_CH14_Clear (1UL) /!< Disable channel on write. /
<>	144:ef7eb2e8f9f7	4330
<>	144:ef7eb2e8f9f7	4331	/* Bit 13 : Disable PPI channel 13. */
<>	144:ef7eb2e8f9f7	4332	#define PPI_CHENCLR_CH13_Pos (13UL) /!< Position of CH13 field. /
<>	144:ef7eb2e8f9f7	4333	#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /!< Bit mask of CH13 field. /
<>	144:ef7eb2e8f9f7	4334	#define PPI_CHENCLR_CH13_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4335	#define PPI_CHENCLR_CH13_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4336	#define PPI_CHENCLR_CH13_Clear (1UL) /!< Disable channel on write. /
<>	144:ef7eb2e8f9f7	4337
<>	144:ef7eb2e8f9f7	4338	/* Bit 12 : Disable PPI channel 12. */
<>	144:ef7eb2e8f9f7	4339	#define PPI_CHENCLR_CH12_Pos (12UL) /!< Position of CH12 field. /
<>	144:ef7eb2e8f9f7	4340	#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /!< Bit mask of CH12 field. /
<>	144:ef7eb2e8f9f7	4341	#define PPI_CHENCLR_CH12_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4342	#define PPI_CHENCLR_CH12_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4343	#define PPI_CHENCLR_CH12_Clear (1UL) /!< Disable channel on write. /
<>	144:ef7eb2e8f9f7	4344
<>	144:ef7eb2e8f9f7	4345	/* Bit 11 : Disable PPI channel 11. */
<>	144:ef7eb2e8f9f7	4346	#define PPI_CHENCLR_CH11_Pos (11UL) /!< Position of CH11 field. /
<>	144:ef7eb2e8f9f7	4347	#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /!< Bit mask of CH11 field. /
<>	144:ef7eb2e8f9f7	4348	#define PPI_CHENCLR_CH11_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4349	#define PPI_CHENCLR_CH11_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4350	#define PPI_CHENCLR_CH11_Clear (1UL) /!< Disable channel on write. /
<>	144:ef7eb2e8f9f7	4351
<>	144:ef7eb2e8f9f7	4352	/* Bit 10 : Disable PPI channel 10. */
<>	144:ef7eb2e8f9f7	4353	#define PPI_CHENCLR_CH10_Pos (10UL) /!< Position of CH10 field. /
<>	144:ef7eb2e8f9f7	4354	#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /!< Bit mask of CH10 field. /
<>	144:ef7eb2e8f9f7	4355	#define PPI_CHENCLR_CH10_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4356	#define PPI_CHENCLR_CH10_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4357	#define PPI_CHENCLR_CH10_Clear (1UL) /!< Disable channel on write. /
<>	144:ef7eb2e8f9f7	4358
<>	144:ef7eb2e8f9f7	4359	/* Bit 9 : Disable PPI channel 9. */
<>	144:ef7eb2e8f9f7	4360	#define PPI_CHENCLR_CH9_Pos (9UL) /!< Position of CH9 field. /
<>	144:ef7eb2e8f9f7	4361	#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /!< Bit mask of CH9 field. /
<>	144:ef7eb2e8f9f7	4362	#define PPI_CHENCLR_CH9_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4363	#define PPI_CHENCLR_CH9_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4364	#define PPI_CHENCLR_CH9_Clear (1UL) /!< Disable channel on write. /
<>	144:ef7eb2e8f9f7	4365
<>	144:ef7eb2e8f9f7	4366	/* Bit 8 : Disable PPI channel 8. */
<>	144:ef7eb2e8f9f7	4367	#define PPI_CHENCLR_CH8_Pos (8UL) /!< Position of CH8 field. /
<>	144:ef7eb2e8f9f7	4368	#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /!< Bit mask of CH8 field. /
<>	144:ef7eb2e8f9f7	4369	#define PPI_CHENCLR_CH8_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4370	#define PPI_CHENCLR_CH8_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4371	#define PPI_CHENCLR_CH8_Clear (1UL) /!< Disable channel on write. /
<>	144:ef7eb2e8f9f7	4372
<>	144:ef7eb2e8f9f7	4373	/* Bit 7 : Disable PPI channel 7. */
<>	144:ef7eb2e8f9f7	4374	#define PPI_CHENCLR_CH7_Pos (7UL) /!< Position of CH7 field. /
<>	144:ef7eb2e8f9f7	4375	#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /!< Bit mask of CH7 field. /
<>	144:ef7eb2e8f9f7	4376	#define PPI_CHENCLR_CH7_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4377	#define PPI_CHENCLR_CH7_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4378	#define PPI_CHENCLR_CH7_Clear (1UL) /!< Disable channel on write. /
<>	144:ef7eb2e8f9f7	4379
<>	144:ef7eb2e8f9f7	4380	/* Bit 6 : Disable PPI channel 6. */
<>	144:ef7eb2e8f9f7	4381	#define PPI_CHENCLR_CH6_Pos (6UL) /!< Position of CH6 field. /
<>	144:ef7eb2e8f9f7	4382	#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /!< Bit mask of CH6 field. /
<>	144:ef7eb2e8f9f7	4383	#define PPI_CHENCLR_CH6_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4384	#define PPI_CHENCLR_CH6_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4385	#define PPI_CHENCLR_CH6_Clear (1UL) /!< Disable channel on write. /
<>	144:ef7eb2e8f9f7	4386
<>	144:ef7eb2e8f9f7	4387	/* Bit 5 : Disable PPI channel 5. */
<>	144:ef7eb2e8f9f7	4388	#define PPI_CHENCLR_CH5_Pos (5UL) /!< Position of CH5 field. /
<>	144:ef7eb2e8f9f7	4389	#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /!< Bit mask of CH5 field. /
<>	144:ef7eb2e8f9f7	4390	#define PPI_CHENCLR_CH5_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4391	#define PPI_CHENCLR_CH5_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4392	#define PPI_CHENCLR_CH5_Clear (1UL) /!< Disable channel on write. /
<>	144:ef7eb2e8f9f7	4393
<>	144:ef7eb2e8f9f7	4394	/* Bit 4 : Disable PPI channel 4. */
<>	144:ef7eb2e8f9f7	4395	#define PPI_CHENCLR_CH4_Pos (4UL) /!< Position of CH4 field. /
<>	144:ef7eb2e8f9f7	4396	#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /!< Bit mask of CH4 field. /
<>	144:ef7eb2e8f9f7	4397	#define PPI_CHENCLR_CH4_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4398	#define PPI_CHENCLR_CH4_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4399	#define PPI_CHENCLR_CH4_Clear (1UL) /!< Disable channel on write. /
<>	144:ef7eb2e8f9f7	4400
<>	144:ef7eb2e8f9f7	4401	/* Bit 3 : Disable PPI channel 3. */
<>	144:ef7eb2e8f9f7	4402	#define PPI_CHENCLR_CH3_Pos (3UL) /!< Position of CH3 field. /
<>	144:ef7eb2e8f9f7	4403	#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /!< Bit mask of CH3 field. /
<>	144:ef7eb2e8f9f7	4404	#define PPI_CHENCLR_CH3_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4405	#define PPI_CHENCLR_CH3_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4406	#define PPI_CHENCLR_CH3_Clear (1UL) /!< Disable channel on write. /
<>	144:ef7eb2e8f9f7	4407
<>	144:ef7eb2e8f9f7	4408	/* Bit 2 : Disable PPI channel 2. */
<>	144:ef7eb2e8f9f7	4409	#define PPI_CHENCLR_CH2_Pos (2UL) /!< Position of CH2 field. /
<>	144:ef7eb2e8f9f7	4410	#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /!< Bit mask of CH2 field. /
<>	144:ef7eb2e8f9f7	4411	#define PPI_CHENCLR_CH2_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4412	#define PPI_CHENCLR_CH2_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4413	#define PPI_CHENCLR_CH2_Clear (1UL) /!< Disable channel on write. /
<>	144:ef7eb2e8f9f7	4414
<>	144:ef7eb2e8f9f7	4415	/* Bit 1 : Disable PPI channel 1. */
<>	144:ef7eb2e8f9f7	4416	#define PPI_CHENCLR_CH1_Pos (1UL) /!< Position of CH1 field. /
<>	144:ef7eb2e8f9f7	4417	#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /!< Bit mask of CH1 field. /
<>	144:ef7eb2e8f9f7	4418	#define PPI_CHENCLR_CH1_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4419	#define PPI_CHENCLR_CH1_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4420	#define PPI_CHENCLR_CH1_Clear (1UL) /!< Disable channel on write. /
<>	144:ef7eb2e8f9f7	4421
<>	144:ef7eb2e8f9f7	4422	/* Bit 0 : Disable PPI channel 0. */
<>	144:ef7eb2e8f9f7	4423	#define PPI_CHENCLR_CH0_Pos (0UL) /!< Position of CH0 field. /
<>	144:ef7eb2e8f9f7	4424	#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /!< Bit mask of CH0 field. /
<>	144:ef7eb2e8f9f7	4425	#define PPI_CHENCLR_CH0_Disabled (0UL) /!< Channel disabled. /
<>	144:ef7eb2e8f9f7	4426	#define PPI_CHENCLR_CH0_Enabled (1UL) /!< Channel enabled. /
<>	144:ef7eb2e8f9f7	4427	#define PPI_CHENCLR_CH0_Clear (1UL) /!< Disable channel on write. /
<>	144:ef7eb2e8f9f7	4428
<>	144:ef7eb2e8f9f7	4429	/* Register: PPI_CHG */
<>	144:ef7eb2e8f9f7	4430	/* Description: Channel group configuration. */
<>	144:ef7eb2e8f9f7	4431
<>	144:ef7eb2e8f9f7	4432	/* Bit 31 : Include CH31 in channel group. */
<>	144:ef7eb2e8f9f7	4433	#define PPI_CHG_CH31_Pos (31UL) /!< Position of CH31 field. /
<>	144:ef7eb2e8f9f7	4434	#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /!< Bit mask of CH31 field. /
<>	144:ef7eb2e8f9f7	4435	#define PPI_CHG_CH31_Excluded (0UL) /!< Channel excluded. /
<>	144:ef7eb2e8f9f7	4436	#define PPI_CHG_CH31_Included (1UL) /!< Channel included. /
<>	144:ef7eb2e8f9f7	4437
<>	144:ef7eb2e8f9f7	4438	/* Bit 30 : Include CH30 in channel group. */
<>	144:ef7eb2e8f9f7	4439	#define PPI_CHG_CH30_Pos (30UL) /!< Position of CH30 field. /
<>	144:ef7eb2e8f9f7	4440	#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /!< Bit mask of CH30 field. /
<>	144:ef7eb2e8f9f7	4441	#define PPI_CHG_CH30_Excluded (0UL) /!< Channel excluded. /
<>	144:ef7eb2e8f9f7	4442	#define PPI_CHG_CH30_Included (1UL) /!< Channel included. /
<>	144:ef7eb2e8f9f7	4443
<>	144:ef7eb2e8f9f7	4444	/* Bit 29 : Include CH29 in channel group. */
<>	144:ef7eb2e8f9f7	4445	#define PPI_CHG_CH29_Pos (29UL) /!< Position of CH29 field. /
<>	144:ef7eb2e8f9f7	4446	#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /!< Bit mask of CH29 field. /
<>	144:ef7eb2e8f9f7	4447	#define PPI_CHG_CH29_Excluded (0UL) /!< Channel excluded. /
<>	144:ef7eb2e8f9f7	4448	#define PPI_CHG_CH29_Included (1UL) /!< Channel included. /
<>	144:ef7eb2e8f9f7	4449
<>	144:ef7eb2e8f9f7	4450	/* Bit 28 : Include CH28 in channel group. */
<>	144:ef7eb2e8f9f7	4451	#define PPI_CHG_CH28_Pos (28UL) /!< Position of CH28 field. /
<>	144:ef7eb2e8f9f7	4452	#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /!< Bit mask of CH28 field. /
<>	144:ef7eb2e8f9f7	4453	#define PPI_CHG_CH28_Excluded (0UL) /!< Channel excluded. /
<>	144:ef7eb2e8f9f7	4454	#define PPI_CHG_CH28_Included (1UL) /!< Channel included. /
<>	144:ef7eb2e8f9f7	4455
<>	144:ef7eb2e8f9f7	4456	/* Bit 27 : Include CH27 in channel group. */
<>	144:ef7eb2e8f9f7	4457	#define PPI_CHG_CH27_Pos (27UL) /!< Position of CH27 field. /
<>	144:ef7eb2e8f9f7	4458	#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /!< Bit mask of CH27 field. /
<>	144:ef7eb2e8f9f7	4459	#define PPI_CHG_CH27_Excluded (0UL) /!< Channel excluded. /
<>	144:ef7eb2e8f9f7	4460	#define PPI_CHG_CH27_Included (1UL) /!< Channel included. /
<>	144:ef7eb2e8f9f7	4461
<>	144:ef7eb2e8f9f7	4462	/* Bit 26 : Include CH26 in channel group. */
<>	144:ef7eb2e8f9f7	4463	#define PPI_CHG_CH26_Pos (26UL) /!< Position of CH26 field. /
<>	144:ef7eb2e8f9f7	4464	#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /!< Bit mask of CH26 field. /
<>	144:ef7eb2e8f9f7	4465	#define PPI_CHG_CH26_Excluded (0UL) /!< Channel excluded. /
<>	144:ef7eb2e8f9f7	4466	#define PPI_CHG_CH26_Included (1UL) /!< Channel included. /
<>	144:ef7eb2e8f9f7	4467
<>	144:ef7eb2e8f9f7	4468	/* Bit 25 : Include CH25 in channel group. */
<>	144:ef7eb2e8f9f7	4469	#define PPI_CHG_CH25_Pos (25UL) /!< Position of CH25 field. /
<>	144:ef7eb2e8f9f7	4470	#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /!< Bit mask of CH25 field. /
<>	144:ef7eb2e8f9f7	4471	#define PPI_CHG_CH25_Excluded (0UL) /!< Channel excluded. /
<>	144:ef7eb2e8f9f7	4472	#define PPI_CHG_CH25_Included (1UL) /!< Channel included. /
<>	144:ef7eb2e8f9f7	4473
<>	144:ef7eb2e8f9f7	4474	/* Bit 24 : Include CH24 in channel group. */
<>	144:ef7eb2e8f9f7	4475	#define PPI_CHG_CH24_Pos (24UL) /!< Position of CH24 field. /
<>	144:ef7eb2e8f9f7	4476	#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /!< Bit mask of CH24 field. /
<>	144:ef7eb2e8f9f7	4477	#define PPI_CHG_CH24_Excluded (0UL) /!< Channel excluded. /
<>	144:ef7eb2e8f9f7	4478	#define PPI_CHG_CH24_Included (1UL) /!< Channel included. /
<>	144:ef7eb2e8f9f7	4479
<>	144:ef7eb2e8f9f7	4480	/* Bit 23 : Include CH23 in channel group. */
<>	144:ef7eb2e8f9f7	4481	#define PPI_CHG_CH23_Pos (23UL) /!< Position of CH23 field. /
<>	144:ef7eb2e8f9f7	4482	#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /!< Bit mask of CH23 field. /
<>	144:ef7eb2e8f9f7	4483	#define PPI_CHG_CH23_Excluded (0UL) /!< Channel excluded. /
<>	144:ef7eb2e8f9f7	4484	#define PPI_CHG_CH23_Included (1UL) /!< Channel included. /
<>	144:ef7eb2e8f9f7	4485
<>	144:ef7eb2e8f9f7	4486	/* Bit 22 : Include CH22 in channel group. */
<>	144:ef7eb2e8f9f7	4487	#define PPI_CHG_CH22_Pos (22UL) /!< Position of CH22 field. /
<>	144:ef7eb2e8f9f7	4488	#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /!< Bit mask of CH22 field. /
<>	144:ef7eb2e8f9f7	4489	#define PPI_CHG_CH22_Excluded (0UL) /!< Channel excluded. /
<>	144:ef7eb2e8f9f7	4490	#define PPI_CHG_CH22_Included (1UL) /!< Channel included. /
<>	144:ef7eb2e8f9f7	4491
<>	144:ef7eb2e8f9f7	4492	/* Bit 21 : Include CH21 in channel group. */
<>	144:ef7eb2e8f9f7	4493	#define PPI_CHG_CH21_Pos (21UL) /!< Position of CH21 field. /
<>	144:ef7eb2e8f9f7	4494	#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /!< Bit mask of CH21 field. /
<>	144:ef7eb2e8f9f7	4495	#define PPI_CHG_CH21_Excluded (0UL) /!< Channel excluded. /
<>	144:ef7eb2e8f9f7	4496	#define PPI_CHG_CH21_Included (1UL) /!< Channel included. /
<>	144:ef7eb2e8f9f7	4497
<>	144:ef7eb2e8f9f7	4498	/* Bit 20 : Include CH20 in channel group. */
<>	144:ef7eb2e8f9f7	4499	#define PPI_CHG_CH20_Pos (20UL) /!< Position of CH20 field. /
<>	144:ef7eb2e8f9f7	4500	#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /!< Bit mask of CH20 field. /
<>	144:ef7eb2e8f9f7	4501	#define PPI_CHG_CH20_Excluded (0UL) /!< Channel excluded. /
<>	144:ef7eb2e8f9f7	4502	#define PPI_CHG_CH20_Included (1UL) /!< Channel included. /
<>	144:ef7eb2e8f9f7	4503
<>	144:ef7eb2e8f9f7	4504	/* Bit 15 : Include CH15 in channel group. */
<>	144:ef7eb2e8f9f7	4505	#define PPI_CHG_CH15_Pos (15UL) /!< Position of CH15 field. /
<>	144:ef7eb2e8f9f7	4506	#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /!< Bit mask of CH15 field. /
<>	144:ef7eb2e8f9f7	4507	#define PPI_CHG_CH15_Excluded (0UL) /!< Channel excluded. /
<>	144:ef7eb2e8f9f7	4508	#define PPI_CHG_CH15_Included (1UL) /!< Channel included. /
<>	144:ef7eb2e8f9f7	4509
<>	144:ef7eb2e8f9f7	4510	/* Bit 14 : Include CH14 in channel group. */
<>	144:ef7eb2e8f9f7	4511	#define PPI_CHG_CH14_Pos (14UL) /!< Position of CH14 field. /
<>	144:ef7eb2e8f9f7	4512	#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /!< Bit mask of CH14 field. /
<>	144:ef7eb2e8f9f7	4513	#define PPI_CHG_CH14_Excluded (0UL) /!< Channel excluded. /
<>	144:ef7eb2e8f9f7	4514	#define PPI_CHG_CH14_Included (1UL) /!< Channel included. /
<>	144:ef7eb2e8f9f7	4515
<>	144:ef7eb2e8f9f7	4516	/* Bit 13 : Include CH13 in channel group. */
<>	144:ef7eb2e8f9f7	4517	#define PPI_CHG_CH13_Pos (13UL) /!< Position of CH13 field. /
<>	144:ef7eb2e8f9f7	4518	#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /!< Bit mask of CH13 field. /
<>	144:ef7eb2e8f9f7	4519	#define PPI_CHG_CH13_Excluded (0UL) /!< Channel excluded. /
<>	144:ef7eb2e8f9f7	4520	#define PPI_CHG_CH13_Included (1UL) /!< Channel included. /
<>	144:ef7eb2e8f9f7	4521
<>	144:ef7eb2e8f9f7	4522	/* Bit 12 : Include CH12 in channel group. */
<>	144:ef7eb2e8f9f7	4523	#define PPI_CHG_CH12_Pos (12UL) /!< Position of CH12 field. /
<>	144:ef7eb2e8f9f7	4524	#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /!< Bit mask of CH12 field. /
<>	144:ef7eb2e8f9f7	4525	#define PPI_CHG_CH12_Excluded (0UL) /!< Channel excluded. /
<>	144:ef7eb2e8f9f7	4526	#define PPI_CHG_CH12_Included (1UL) /!< Channel included. /
<>	144:ef7eb2e8f9f7	4527
<>	144:ef7eb2e8f9f7	4528	/* Bit 11 : Include CH11 in channel group. */
<>	144:ef7eb2e8f9f7	4529	#define PPI_CHG_CH11_Pos (11UL) /!< Position of CH11 field. /
<>	144:ef7eb2e8f9f7	4530	#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /!< Bit mask of CH11 field. /
<>	144:ef7eb2e8f9f7	4531	#define PPI_CHG_CH11_Excluded (0UL) /!< Channel excluded. /
<>	144:ef7eb2e8f9f7	4532	#define PPI_CHG_CH11_Included (1UL) /!< Channel included. /
<>	144:ef7eb2e8f9f7	4533
<>	144:ef7eb2e8f9f7	4534	/* Bit 10 : Include CH10 in channel group. */
<>	144:ef7eb2e8f9f7	4535	#define PPI_CHG_CH10_Pos (10UL) /!< Position of CH10 field. /
<>	144:ef7eb2e8f9f7	4536	#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /!< Bit mask of CH10 field. /
<>	144:ef7eb2e8f9f7	4537	#define PPI_CHG_CH10_Excluded (0UL) /!< Channel excluded. /
<>	144:ef7eb2e8f9f7	4538	#define PPI_CHG_CH10_Included (1UL) /!< Channel included. /
<>	144:ef7eb2e8f9f7	4539
<>	144:ef7eb2e8f9f7	4540	/* Bit 9 : Include CH9 in channel group. */
<>	144:ef7eb2e8f9f7	4541	#define PPI_CHG_CH9_Pos (9UL) /!< Position of CH9 field. /
<>	144:ef7eb2e8f9f7	4542	#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /!< Bit mask of CH9 field. /
<>	144:ef7eb2e8f9f7	4543	#define PPI_CHG_CH9_Excluded (0UL) /!< Channel excluded. /
<>	144:ef7eb2e8f9f7	4544	#define PPI_CHG_CH9_Included (1UL) /!< Channel included. /
<>	144:ef7eb2e8f9f7	4545
<>	144:ef7eb2e8f9f7	4546	/* Bit 8 : Include CH8 in channel group. */
<>	144:ef7eb2e8f9f7	4547	#define PPI_CHG_CH8_Pos (8UL) /!< Position of CH8 field. /
<>	144:ef7eb2e8f9f7	4548	#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /!< Bit mask of CH8 field. /
<>	144:ef7eb2e8f9f7	4549	#define PPI_CHG_CH8_Excluded (0UL) /!< Channel excluded. /
<>	144:ef7eb2e8f9f7	4550	#define PPI_CHG_CH8_Included (1UL) /!< Channel included. /
<>	144:ef7eb2e8f9f7	4551
<>	144:ef7eb2e8f9f7	4552	/* Bit 7 : Include CH7 in channel group. */
<>	144:ef7eb2e8f9f7	4553	#define PPI_CHG_CH7_Pos (7UL) /!< Position of CH7 field. /
<>	144:ef7eb2e8f9f7	4554	#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /!< Bit mask of CH7 field. /
<>	144:ef7eb2e8f9f7	4555	#define PPI_CHG_CH7_Excluded (0UL) /!< Channel excluded. /
<>	144:ef7eb2e8f9f7	4556	#define PPI_CHG_CH7_Included (1UL) /!< Channel included. /
<>	144:ef7eb2e8f9f7	4557
<>	144:ef7eb2e8f9f7	4558	/* Bit 6 : Include CH6 in channel group. */
<>	144:ef7eb2e8f9f7	4559	#define PPI_CHG_CH6_Pos (6UL) /!< Position of CH6 field. /
<>	144:ef7eb2e8f9f7	4560	#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /!< Bit mask of CH6 field. /
<>	144:ef7eb2e8f9f7	4561	#define PPI_CHG_CH6_Excluded (0UL) /!< Channel excluded. /
<>	144:ef7eb2e8f9f7	4562	#define PPI_CHG_CH6_Included (1UL) /!< Channel included. /
<>	144:ef7eb2e8f9f7	4563
<>	144:ef7eb2e8f9f7	4564	/* Bit 5 : Include CH5 in channel group. */
<>	144:ef7eb2e8f9f7	4565	#define PPI_CHG_CH5_Pos (5UL) /!< Position of CH5 field. /
<>	144:ef7eb2e8f9f7	4566	#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /!< Bit mask of CH5 field. /
<>	144:ef7eb2e8f9f7	4567	#define PPI_CHG_CH5_Excluded (0UL) /!< Channel excluded. /
<>	144:ef7eb2e8f9f7	4568	#define PPI_CHG_CH5_Included (1UL) /!< Channel included. /
<>	144:ef7eb2e8f9f7	4569
<>	144:ef7eb2e8f9f7	4570	/* Bit 4 : Include CH4 in channel group. */
<>	144:ef7eb2e8f9f7	4571	#define PPI_CHG_CH4_Pos (4UL) /!< Position of CH4 field. /
<>	144:ef7eb2e8f9f7	4572	#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /!< Bit mask of CH4 field. /
<>	144:ef7eb2e8f9f7	4573	#define PPI_CHG_CH4_Excluded (0UL) /!< Channel excluded. /
<>	144:ef7eb2e8f9f7	4574	#define PPI_CHG_CH4_Included (1UL) /!< Channel included. /
<>	144:ef7eb2e8f9f7	4575
<>	144:ef7eb2e8f9f7	4576	/* Bit 3 : Include CH3 in channel group. */
<>	144:ef7eb2e8f9f7	4577	#define PPI_CHG_CH3_Pos (3UL) /!< Position of CH3 field. /
<>	144:ef7eb2e8f9f7	4578	#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /!< Bit mask of CH3 field. /
<>	144:ef7eb2e8f9f7	4579	#define PPI_CHG_CH3_Excluded (0UL) /!< Channel excluded. /
<>	144:ef7eb2e8f9f7	4580	#define PPI_CHG_CH3_Included (1UL) /!< Channel included. /
<>	144:ef7eb2e8f9f7	4581
<>	144:ef7eb2e8f9f7	4582	/* Bit 2 : Include CH2 in channel group. */
<>	144:ef7eb2e8f9f7	4583	#define PPI_CHG_CH2_Pos (2UL) /!< Position of CH2 field. /
<>	144:ef7eb2e8f9f7	4584	#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /!< Bit mask of CH2 field. /
<>	144:ef7eb2e8f9f7	4585	#define PPI_CHG_CH2_Excluded (0UL) /!< Channel excluded. /
<>	144:ef7eb2e8f9f7	4586	#define PPI_CHG_CH2_Included (1UL) /!< Channel included. /
<>	144:ef7eb2e8f9f7	4587
<>	144:ef7eb2e8f9f7	4588	/* Bit 1 : Include CH1 in channel group. */
<>	144:ef7eb2e8f9f7	4589	#define PPI_CHG_CH1_Pos (1UL) /!< Position of CH1 field. /
<>	144:ef7eb2e8f9f7	4590	#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /!< Bit mask of CH1 field. /
<>	144:ef7eb2e8f9f7	4591	#define PPI_CHG_CH1_Excluded (0UL) /!< Channel excluded. /
<>	144:ef7eb2e8f9f7	4592	#define PPI_CHG_CH1_Included (1UL) /!< Channel included. /
<>	144:ef7eb2e8f9f7	4593
<>	144:ef7eb2e8f9f7	4594	/* Bit 0 : Include CH0 in channel group. */
<>	144:ef7eb2e8f9f7	4595	#define PPI_CHG_CH0_Pos (0UL) /!< Position of CH0 field. /
<>	144:ef7eb2e8f9f7	4596	#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /!< Bit mask of CH0 field. /
<>	144:ef7eb2e8f9f7	4597	#define PPI_CHG_CH0_Excluded (0UL) /!< Channel excluded. /
<>	144:ef7eb2e8f9f7	4598	#define PPI_CHG_CH0_Included (1UL) /!< Channel included. /
<>	144:ef7eb2e8f9f7	4599
<>	144:ef7eb2e8f9f7	4600
<>	144:ef7eb2e8f9f7	4601	/* Peripheral: QDEC */
<>	144:ef7eb2e8f9f7	4602	/* Description: Rotary decoder. */
<>	144:ef7eb2e8f9f7	4603
<>	144:ef7eb2e8f9f7	4604	/* Register: QDEC_SHORTS */
<>	144:ef7eb2e8f9f7	4605	/* Description: Shortcuts for the QDEC. */
<>	144:ef7eb2e8f9f7	4606
<>	144:ef7eb2e8f9f7	4607	/* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */
<>	144:ef7eb2e8f9f7	4608	#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /!< Position of SAMPLERDY_STOP field. /
<>	144:ef7eb2e8f9f7	4609	#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /!< Bit mask of SAMPLERDY_STOP field. /
<>	144:ef7eb2e8f9f7	4610	#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /!< Shortcut disabled. /
<>	144:ef7eb2e8f9f7	4611	#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /!< Shortcut enabled. /
<>	144:ef7eb2e8f9f7	4612
<>	144:ef7eb2e8f9f7	4613	/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */
<>	144:ef7eb2e8f9f7	4614	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /!< Position of REPORTRDY_READCLRACC field. /
<>	144:ef7eb2e8f9f7	4615	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /!< Bit mask of REPORTRDY_READCLRACC field. /
<>	144:ef7eb2e8f9f7	4616	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /!< Shortcut disabled. /
<>	144:ef7eb2e8f9f7	4617	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /!< Shortcut enabled. /
<>	144:ef7eb2e8f9f7	4618
<>	144:ef7eb2e8f9f7	4619	/* Register: QDEC_INTENSET */
<>	144:ef7eb2e8f9f7	4620	/* Description: Interrupt enable set register. */
<>	144:ef7eb2e8f9f7	4621
<>	144:ef7eb2e8f9f7	4622	/* Bit 2 : Enable interrupt on ACCOF event. */
<>	144:ef7eb2e8f9f7	4623	#define QDEC_INTENSET_ACCOF_Pos (2UL) /!< Position of ACCOF field. /
<>	144:ef7eb2e8f9f7	4624	#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /!< Bit mask of ACCOF field. /
<>	144:ef7eb2e8f9f7	4625	#define QDEC_INTENSET_ACCOF_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	4626	#define QDEC_INTENSET_ACCOF_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	4627	#define QDEC_INTENSET_ACCOF_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	4628
<>	144:ef7eb2e8f9f7	4629	/* Bit 1 : Enable interrupt on REPORTRDY event. */
<>	144:ef7eb2e8f9f7	4630	#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /!< Position of REPORTRDY field. /
<>	144:ef7eb2e8f9f7	4631	#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /!< Bit mask of REPORTRDY field. /
<>	144:ef7eb2e8f9f7	4632	#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	4633	#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	4634	#define QDEC_INTENSET_REPORTRDY_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	4635
<>	144:ef7eb2e8f9f7	4636	/* Bit 0 : Enable interrupt on SAMPLERDY event. */
<>	144:ef7eb2e8f9f7	4637	#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /!< Position of SAMPLERDY field. /
<>	144:ef7eb2e8f9f7	4638	#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /!< Bit mask of SAMPLERDY field. /
<>	144:ef7eb2e8f9f7	4639	#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	4640	#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	4641	#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	4642
<>	144:ef7eb2e8f9f7	4643	/* Register: QDEC_INTENCLR */
<>	144:ef7eb2e8f9f7	4644	/* Description: Interrupt enable clear register. */
<>	144:ef7eb2e8f9f7	4645
<>	144:ef7eb2e8f9f7	4646	/* Bit 2 : Disable interrupt on ACCOF event. */
<>	144:ef7eb2e8f9f7	4647	#define QDEC_INTENCLR_ACCOF_Pos (2UL) /!< Position of ACCOF field. /
<>	144:ef7eb2e8f9f7	4648	#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /!< Bit mask of ACCOF field. /
<>	144:ef7eb2e8f9f7	4649	#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	4650	#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	4651	#define QDEC_INTENCLR_ACCOF_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	4652
<>	144:ef7eb2e8f9f7	4653	/* Bit 1 : Disable interrupt on REPORTRDY event. */
<>	144:ef7eb2e8f9f7	4654	#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /!< Position of REPORTRDY field. /
<>	144:ef7eb2e8f9f7	4655	#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /!< Bit mask of REPORTRDY field. /
<>	144:ef7eb2e8f9f7	4656	#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	4657	#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	4658	#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	4659
<>	144:ef7eb2e8f9f7	4660	/* Bit 0 : Disable interrupt on SAMPLERDY event. */
<>	144:ef7eb2e8f9f7	4661	#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /!< Position of SAMPLERDY field. /
<>	144:ef7eb2e8f9f7	4662	#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /!< Bit mask of SAMPLERDY field. /
<>	144:ef7eb2e8f9f7	4663	#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	4664	#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	4665	#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	4666
<>	144:ef7eb2e8f9f7	4667	/* Register: QDEC_ENABLE */
<>	144:ef7eb2e8f9f7	4668	/* Description: Enable the QDEC. */
<>	144:ef7eb2e8f9f7	4669
<>	144:ef7eb2e8f9f7	4670	/* Bit 0 : Enable or disable QDEC. */
<>	144:ef7eb2e8f9f7	4671	#define QDEC_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
<>	144:ef7eb2e8f9f7	4672	#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
<>	144:ef7eb2e8f9f7	4673	#define QDEC_ENABLE_ENABLE_Disabled (0UL) /!< Disabled QDEC. /
<>	144:ef7eb2e8f9f7	4674	#define QDEC_ENABLE_ENABLE_Enabled (1UL) /!< Enable QDEC. /
<>	144:ef7eb2e8f9f7	4675
<>	144:ef7eb2e8f9f7	4676	/* Register: QDEC_LEDPOL */
<>	144:ef7eb2e8f9f7	4677	/* Description: LED output pin polarity. */
<>	144:ef7eb2e8f9f7	4678
<>	144:ef7eb2e8f9f7	4679	/* Bit 0 : LED output pin polarity. */
<>	144:ef7eb2e8f9f7	4680	#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /!< Position of LEDPOL field. /
<>	144:ef7eb2e8f9f7	4681	#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /!< Bit mask of LEDPOL field. /
<>	144:ef7eb2e8f9f7	4682	#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /!< LED output is active low. /
<>	144:ef7eb2e8f9f7	4683	#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /!< LED output is active high. /
<>	144:ef7eb2e8f9f7	4684
<>	144:ef7eb2e8f9f7	4685	/* Register: QDEC_SAMPLEPER */
<>	144:ef7eb2e8f9f7	4686	/* Description: Sample period. */
<>	144:ef7eb2e8f9f7	4687
<>	144:ef7eb2e8f9f7	4688	/* Bits 2..0 : Sample period. */
<>	144:ef7eb2e8f9f7	4689	#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /!< Position of SAMPLEPER field. /
<>	144:ef7eb2e8f9f7	4690	#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /!< Bit mask of SAMPLEPER field. /
<>	144:ef7eb2e8f9f7	4691	#define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /!< 128us sample period. /
<>	144:ef7eb2e8f9f7	4692	#define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /!< 256us sample period. /
<>	144:ef7eb2e8f9f7	4693	#define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /!< 512us sample period. /
<>	144:ef7eb2e8f9f7	4694	#define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /!< 1024us sample period. /
<>	144:ef7eb2e8f9f7	4695	#define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /!< 2048us sample period. /
<>	144:ef7eb2e8f9f7	4696	#define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /!< 4096us sample period. /
<>	144:ef7eb2e8f9f7	4697	#define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /!< 8192us sample period. /
<>	144:ef7eb2e8f9f7	4698	#define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /!< 16384us sample period. /
<>	144:ef7eb2e8f9f7	4699
<>	144:ef7eb2e8f9f7	4700	/* Register: QDEC_SAMPLE */
<>	144:ef7eb2e8f9f7	4701	/* Description: Motion sample value. */
<>	144:ef7eb2e8f9f7	4702
<>	144:ef7eb2e8f9f7	4703	/* Bits 31..0 : Last sample taken in compliment to 2. */
<>	144:ef7eb2e8f9f7	4704	#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /!< Position of SAMPLE field. /
<>	144:ef7eb2e8f9f7	4705	#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /!< Bit mask of SAMPLE field. /
<>	144:ef7eb2e8f9f7	4706
<>	144:ef7eb2e8f9f7	4707	/* Register: QDEC_REPORTPER */
<>	144:ef7eb2e8f9f7	4708	/* Description: Number of samples to generate an EVENT_REPORTRDY. */
<>	144:ef7eb2e8f9f7	4709
<>	144:ef7eb2e8f9f7	4710	/* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */
<>	144:ef7eb2e8f9f7	4711	#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /!< Position of REPORTPER field. /
<>	144:ef7eb2e8f9f7	4712	#define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /!< Bit mask of REPORTPER field. /
<>	144:ef7eb2e8f9f7	4713	#define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /!< 10 samples per report. /
<>	144:ef7eb2e8f9f7	4714	#define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /!< 40 samples per report. /
<>	144:ef7eb2e8f9f7	4715	#define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /!< 80 samples per report. /
<>	144:ef7eb2e8f9f7	4716	#define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /!< 120 samples per report. /
<>	144:ef7eb2e8f9f7	4717	#define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /!< 160 samples per report. /
<>	144:ef7eb2e8f9f7	4718	#define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /!< 200 samples per report. /
<>	144:ef7eb2e8f9f7	4719	#define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /!< 240 samples per report. /
<>	144:ef7eb2e8f9f7	4720	#define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /!< 280 samples per report. /
<>	144:ef7eb2e8f9f7	4721
<>	144:ef7eb2e8f9f7	4722	/* Register: QDEC_DBFEN */
<>	144:ef7eb2e8f9f7	4723	/* Description: Enable debouncer input filters. */
<>	144:ef7eb2e8f9f7	4724
<>	144:ef7eb2e8f9f7	4725	/* Bit 0 : Enable debounce input filters. */
<>	144:ef7eb2e8f9f7	4726	#define QDEC_DBFEN_DBFEN_Pos (0UL) /!< Position of DBFEN field. /
<>	144:ef7eb2e8f9f7	4727	#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /!< Bit mask of DBFEN field. /
<>	144:ef7eb2e8f9f7	4728	#define QDEC_DBFEN_DBFEN_Disabled (0UL) /!< Debounce input filters disabled. /
<>	144:ef7eb2e8f9f7	4729	#define QDEC_DBFEN_DBFEN_Enabled (1UL) /!< Debounce input filters enabled. /
<>	144:ef7eb2e8f9f7	4730
<>	144:ef7eb2e8f9f7	4731	/* Register: QDEC_LEDPRE */
<>	144:ef7eb2e8f9f7	4732	/* Description: Time LED is switched ON before the sample. */
<>	144:ef7eb2e8f9f7	4733
<>	144:ef7eb2e8f9f7	4734	/* Bits 8..0 : Period in us the LED in switched on prior to sampling. */
<>	144:ef7eb2e8f9f7	4735	#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /!< Position of LEDPRE field. /
<>	144:ef7eb2e8f9f7	4736	#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /!< Bit mask of LEDPRE field. /
<>	144:ef7eb2e8f9f7	4737
<>	144:ef7eb2e8f9f7	4738	/* Register: QDEC_ACCDBL */
<>	144:ef7eb2e8f9f7	4739	/* Description: Accumulated double (error) transitions register. */
<>	144:ef7eb2e8f9f7	4740
<>	144:ef7eb2e8f9f7	4741	/* Bits 3..0 : Accumulated double (error) transitions. */
<>	144:ef7eb2e8f9f7	4742	#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /!< Position of ACCDBL field. /
<>	144:ef7eb2e8f9f7	4743	#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /!< Bit mask of ACCDBL field. /
<>	144:ef7eb2e8f9f7	4744
<>	144:ef7eb2e8f9f7	4745	/* Register: QDEC_ACCDBLREAD */
<>	144:ef7eb2e8f9f7	4746	/* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */
<>	144:ef7eb2e8f9f7	4747
<>	144:ef7eb2e8f9f7	4748	/* Bits 3..0 : Snapshot of accumulated double (error) transitions. */
<>	144:ef7eb2e8f9f7	4749	#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /!< Position of ACCDBLREAD field. /
<>	144:ef7eb2e8f9f7	4750	#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /!< Bit mask of ACCDBLREAD field. /
<>	144:ef7eb2e8f9f7	4751
<>	144:ef7eb2e8f9f7	4752	/* Register: QDEC_POWER */
<>	144:ef7eb2e8f9f7	4753	/* Description: Peripheral power control. */
<>	144:ef7eb2e8f9f7	4754
<>	144:ef7eb2e8f9f7	4755	/* Bit 0 : Peripheral power control. */
<>	144:ef7eb2e8f9f7	4756	#define QDEC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
<>	144:ef7eb2e8f9f7	4757	#define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
<>	144:ef7eb2e8f9f7	4758	#define QDEC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
<>	144:ef7eb2e8f9f7	4759	#define QDEC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
<>	144:ef7eb2e8f9f7	4760
<>	144:ef7eb2e8f9f7	4761
<>	144:ef7eb2e8f9f7	4762	/* Peripheral: RADIO */
<>	144:ef7eb2e8f9f7	4763	/* Description: The radio. */
<>	144:ef7eb2e8f9f7	4764
<>	144:ef7eb2e8f9f7	4765	/* Register: RADIO_SHORTS */
<>	144:ef7eb2e8f9f7	4766	/* Description: Shortcuts for the radio. */
<>	144:ef7eb2e8f9f7	4767
<>	144:ef7eb2e8f9f7	4768	/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */
<>	144:ef7eb2e8f9f7	4769	#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /!< Position of DISABLED_RSSISTOP field. /
<>	144:ef7eb2e8f9f7	4770	#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /!< Bit mask of DISABLED_RSSISTOP field. /
<>	144:ef7eb2e8f9f7	4771	#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /!< Shortcut disabled. /
<>	144:ef7eb2e8f9f7	4772	#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /!< Shortcut enabled. /
<>	144:ef7eb2e8f9f7	4773
<>	144:ef7eb2e8f9f7	4774	/* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */
<>	144:ef7eb2e8f9f7	4775	#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /!< Position of ADDRESS_BCSTART field. /
<>	144:ef7eb2e8f9f7	4776	#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /!< Bit mask of ADDRESS_BCSTART field. /
<>	144:ef7eb2e8f9f7	4777	#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /!< Shortcut disabled. /
<>	144:ef7eb2e8f9f7	4778	#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /!< Shortcut enabled. /
<>	144:ef7eb2e8f9f7	4779
<>	144:ef7eb2e8f9f7	4780	/* Bit 5 : Shortcut between END event and START task. */
<>	144:ef7eb2e8f9f7	4781	#define RADIO_SHORTS_END_START_Pos (5UL) /!< Position of END_START field. /
<>	144:ef7eb2e8f9f7	4782	#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /!< Bit mask of END_START field. /
<>	144:ef7eb2e8f9f7	4783	#define RADIO_SHORTS_END_START_Disabled (0UL) /!< Shortcut disabled. /
<>	144:ef7eb2e8f9f7	4784	#define RADIO_SHORTS_END_START_Enabled (1UL) /!< Shortcut enabled. /
<>	144:ef7eb2e8f9f7	4785
<>	144:ef7eb2e8f9f7	4786	/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */
<>	144:ef7eb2e8f9f7	4787	#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /!< Position of ADDRESS_RSSISTART field. /
<>	144:ef7eb2e8f9f7	4788	#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /!< Bit mask of ADDRESS_RSSISTART field. /
<>	144:ef7eb2e8f9f7	4789	#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /!< Shortcut disabled. /
<>	144:ef7eb2e8f9f7	4790	#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /!< Shortcut enabled. /
<>	144:ef7eb2e8f9f7	4791
<>	144:ef7eb2e8f9f7	4792	/* Bit 3 : Shortcut between DISABLED event and RXEN task. */
<>	144:ef7eb2e8f9f7	4793	#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /!< Position of DISABLED_RXEN field. /
<>	144:ef7eb2e8f9f7	4794	#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /!< Bit mask of DISABLED_RXEN field. /
<>	144:ef7eb2e8f9f7	4795	#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /!< Shortcut disabled. /
<>	144:ef7eb2e8f9f7	4796	#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /!< Shortcut enabled. /
<>	144:ef7eb2e8f9f7	4797
<>	144:ef7eb2e8f9f7	4798	/* Bit 2 : Shortcut between DISABLED event and TXEN task. */
<>	144:ef7eb2e8f9f7	4799	#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /!< Position of DISABLED_TXEN field. /
<>	144:ef7eb2e8f9f7	4800	#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /!< Bit mask of DISABLED_TXEN field. /
<>	144:ef7eb2e8f9f7	4801	#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /!< Shortcut disabled. /
<>	144:ef7eb2e8f9f7	4802	#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /!< Shortcut enabled. /
<>	144:ef7eb2e8f9f7	4803
<>	144:ef7eb2e8f9f7	4804	/* Bit 1 : Shortcut between END event and DISABLE task. */
<>	144:ef7eb2e8f9f7	4805	#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /!< Position of END_DISABLE field. /
<>	144:ef7eb2e8f9f7	4806	#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /!< Bit mask of END_DISABLE field. /
<>	144:ef7eb2e8f9f7	4807	#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /!< Shortcut disabled. /
<>	144:ef7eb2e8f9f7	4808	#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /!< Shortcut enabled. /
<>	144:ef7eb2e8f9f7	4809
<>	144:ef7eb2e8f9f7	4810	/* Bit 0 : Shortcut between READY event and START task. */
<>	144:ef7eb2e8f9f7	4811	#define RADIO_SHORTS_READY_START_Pos (0UL) /!< Position of READY_START field. /
<>	144:ef7eb2e8f9f7	4812	#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /!< Bit mask of READY_START field. /
<>	144:ef7eb2e8f9f7	4813	#define RADIO_SHORTS_READY_START_Disabled (0UL) /!< Shortcut disabled. /
<>	144:ef7eb2e8f9f7	4814	#define RADIO_SHORTS_READY_START_Enabled (1UL) /!< Shortcut enabled. /
<>	144:ef7eb2e8f9f7	4815
<>	144:ef7eb2e8f9f7	4816	/* Register: RADIO_INTENSET */
<>	144:ef7eb2e8f9f7	4817	/* Description: Interrupt enable set register. */
<>	144:ef7eb2e8f9f7	4818
<>	144:ef7eb2e8f9f7	4819	/* Bit 10 : Enable interrupt on BCMATCH event. */
<>	144:ef7eb2e8f9f7	4820	#define RADIO_INTENSET_BCMATCH_Pos (10UL) /!< Position of BCMATCH field. /
<>	144:ef7eb2e8f9f7	4821	#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /!< Bit mask of BCMATCH field. /
<>	144:ef7eb2e8f9f7	4822	#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	4823	#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	4824	#define RADIO_INTENSET_BCMATCH_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	4825
<>	144:ef7eb2e8f9f7	4826	/* Bit 7 : Enable interrupt on RSSIEND event. */
<>	144:ef7eb2e8f9f7	4827	#define RADIO_INTENSET_RSSIEND_Pos (7UL) /!< Position of RSSIEND field. /
<>	144:ef7eb2e8f9f7	4828	#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /!< Bit mask of RSSIEND field. /
<>	144:ef7eb2e8f9f7	4829	#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	4830	#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	4831	#define RADIO_INTENSET_RSSIEND_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	4832
<>	144:ef7eb2e8f9f7	4833	/* Bit 6 : Enable interrupt on DEVMISS event. */
<>	144:ef7eb2e8f9f7	4834	#define RADIO_INTENSET_DEVMISS_Pos (6UL) /!< Position of DEVMISS field. /
<>	144:ef7eb2e8f9f7	4835	#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /!< Bit mask of DEVMISS field. /
<>	144:ef7eb2e8f9f7	4836	#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	4837	#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	4838	#define RADIO_INTENSET_DEVMISS_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	4839
<>	144:ef7eb2e8f9f7	4840	/* Bit 5 : Enable interrupt on DEVMATCH event. */
<>	144:ef7eb2e8f9f7	4841	#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /!< Position of DEVMATCH field. /
<>	144:ef7eb2e8f9f7	4842	#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /!< Bit mask of DEVMATCH field. /
<>	144:ef7eb2e8f9f7	4843	#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	4844	#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	4845	#define RADIO_INTENSET_DEVMATCH_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	4846
<>	144:ef7eb2e8f9f7	4847	/* Bit 4 : Enable interrupt on DISABLED event. */
<>	144:ef7eb2e8f9f7	4848	#define RADIO_INTENSET_DISABLED_Pos (4UL) /!< Position of DISABLED field. /
<>	144:ef7eb2e8f9f7	4849	#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /!< Bit mask of DISABLED field. /
<>	144:ef7eb2e8f9f7	4850	#define RADIO_INTENSET_DISABLED_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	4851	#define RADIO_INTENSET_DISABLED_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	4852	#define RADIO_INTENSET_DISABLED_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	4853
<>	144:ef7eb2e8f9f7	4854	/* Bit 3 : Enable interrupt on END event. */
<>	144:ef7eb2e8f9f7	4855	#define RADIO_INTENSET_END_Pos (3UL) /!< Position of END field. /
<>	144:ef7eb2e8f9f7	4856	#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /!< Bit mask of END field. /
<>	144:ef7eb2e8f9f7	4857	#define RADIO_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	4858	#define RADIO_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	4859	#define RADIO_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	4860
<>	144:ef7eb2e8f9f7	4861	/* Bit 2 : Enable interrupt on PAYLOAD event. */
<>	144:ef7eb2e8f9f7	4862	#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /!< Position of PAYLOAD field. /
<>	144:ef7eb2e8f9f7	4863	#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /!< Bit mask of PAYLOAD field. /
<>	144:ef7eb2e8f9f7	4864	#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	4865	#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	4866	#define RADIO_INTENSET_PAYLOAD_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	4867
<>	144:ef7eb2e8f9f7	4868	/* Bit 1 : Enable interrupt on ADDRESS event. */
<>	144:ef7eb2e8f9f7	4869	#define RADIO_INTENSET_ADDRESS_Pos (1UL) /!< Position of ADDRESS field. /
<>	144:ef7eb2e8f9f7	4870	#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
<>	144:ef7eb2e8f9f7	4871	#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	4872	#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	4873	#define RADIO_INTENSET_ADDRESS_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	4874
<>	144:ef7eb2e8f9f7	4875	/* Bit 0 : Enable interrupt on READY event. */
<>	144:ef7eb2e8f9f7	4876	#define RADIO_INTENSET_READY_Pos (0UL) /!< Position of READY field. /
<>	144:ef7eb2e8f9f7	4877	#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /!< Bit mask of READY field. /
<>	144:ef7eb2e8f9f7	4878	#define RADIO_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	4879	#define RADIO_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	4880	#define RADIO_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	4881
<>	144:ef7eb2e8f9f7	4882	/* Register: RADIO_INTENCLR */
<>	144:ef7eb2e8f9f7	4883	/* Description: Interrupt enable clear register. */
<>	144:ef7eb2e8f9f7	4884
<>	144:ef7eb2e8f9f7	4885	/* Bit 10 : Disable interrupt on BCMATCH event. */
<>	144:ef7eb2e8f9f7	4886	#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /!< Position of BCMATCH field. /
<>	144:ef7eb2e8f9f7	4887	#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /!< Bit mask of BCMATCH field. /
<>	144:ef7eb2e8f9f7	4888	#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	4889	#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	4890	#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	4891
<>	144:ef7eb2e8f9f7	4892	/* Bit 7 : Disable interrupt on RSSIEND event. */
<>	144:ef7eb2e8f9f7	4893	#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /!< Position of RSSIEND field. /
<>	144:ef7eb2e8f9f7	4894	#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /!< Bit mask of RSSIEND field. /
<>	144:ef7eb2e8f9f7	4895	#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	4896	#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	4897	#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	4898
<>	144:ef7eb2e8f9f7	4899	/* Bit 6 : Disable interrupt on DEVMISS event. */
<>	144:ef7eb2e8f9f7	4900	#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /!< Position of DEVMISS field. /
<>	144:ef7eb2e8f9f7	4901	#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /!< Bit mask of DEVMISS field. /
<>	144:ef7eb2e8f9f7	4902	#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	4903	#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	4904	#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	4905
<>	144:ef7eb2e8f9f7	4906	/* Bit 5 : Disable interrupt on DEVMATCH event. */
<>	144:ef7eb2e8f9f7	4907	#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /!< Position of DEVMATCH field. /
<>	144:ef7eb2e8f9f7	4908	#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /!< Bit mask of DEVMATCH field. /
<>	144:ef7eb2e8f9f7	4909	#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	4910	#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	4911	#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	4912
<>	144:ef7eb2e8f9f7	4913	/* Bit 4 : Disable interrupt on DISABLED event. */
<>	144:ef7eb2e8f9f7	4914	#define RADIO_INTENCLR_DISABLED_Pos (4UL) /!< Position of DISABLED field. /
<>	144:ef7eb2e8f9f7	4915	#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /!< Bit mask of DISABLED field. /
<>	144:ef7eb2e8f9f7	4916	#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	4917	#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	4918	#define RADIO_INTENCLR_DISABLED_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	4919
<>	144:ef7eb2e8f9f7	4920	/* Bit 3 : Disable interrupt on END event. */
<>	144:ef7eb2e8f9f7	4921	#define RADIO_INTENCLR_END_Pos (3UL) /!< Position of END field. /
<>	144:ef7eb2e8f9f7	4922	#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /!< Bit mask of END field. /
<>	144:ef7eb2e8f9f7	4923	#define RADIO_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	4924	#define RADIO_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	4925	#define RADIO_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	4926
<>	144:ef7eb2e8f9f7	4927	/* Bit 2 : Disable interrupt on PAYLOAD event. */
<>	144:ef7eb2e8f9f7	4928	#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /!< Position of PAYLOAD field. /
<>	144:ef7eb2e8f9f7	4929	#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /!< Bit mask of PAYLOAD field. /
<>	144:ef7eb2e8f9f7	4930	#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	4931	#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	4932	#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	4933
<>	144:ef7eb2e8f9f7	4934	/* Bit 1 : Disable interrupt on ADDRESS event. */
<>	144:ef7eb2e8f9f7	4935	#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /!< Position of ADDRESS field. /
<>	144:ef7eb2e8f9f7	4936	#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
<>	144:ef7eb2e8f9f7	4937	#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	4938	#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	4939	#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	4940
<>	144:ef7eb2e8f9f7	4941	/* Bit 0 : Disable interrupt on READY event. */
<>	144:ef7eb2e8f9f7	4942	#define RADIO_INTENCLR_READY_Pos (0UL) /!< Position of READY field. /
<>	144:ef7eb2e8f9f7	4943	#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
<>	144:ef7eb2e8f9f7	4944	#define RADIO_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	4945	#define RADIO_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	4946	#define RADIO_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	4947
<>	144:ef7eb2e8f9f7	4948	/* Register: RADIO_CRCSTATUS */
<>	144:ef7eb2e8f9f7	4949	/* Description: CRC status of received packet. */
<>	144:ef7eb2e8f9f7	4950
<>	144:ef7eb2e8f9f7	4951	/* Bit 0 : CRC status of received packet. */
<>	144:ef7eb2e8f9f7	4952	#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /!< Position of CRCSTATUS field. /
<>	144:ef7eb2e8f9f7	4953	#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /!< Bit mask of CRCSTATUS field. /
<>	144:ef7eb2e8f9f7	4954	#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /!< Packet received with CRC error. /
<>	144:ef7eb2e8f9f7	4955	#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /!< Packet received with CRC ok. /
<>	144:ef7eb2e8f9f7	4956
<>	144:ef7eb2e8f9f7	4957	/* Register: RADIO_RXMATCH */
<>	144:ef7eb2e8f9f7	4958	/* Description: Received address. */
<>	144:ef7eb2e8f9f7	4959
<>	144:ef7eb2e8f9f7	4960	/* Bits 2..0 : Logical address in which previous packet was received. */
<>	144:ef7eb2e8f9f7	4961	#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /!< Position of RXMATCH field. /
<>	144:ef7eb2e8f9f7	4962	#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /!< Bit mask of RXMATCH field. /
<>	144:ef7eb2e8f9f7	4963
<>	144:ef7eb2e8f9f7	4964	/* Register: RADIO_RXCRC */
<>	144:ef7eb2e8f9f7	4965	/* Description: Received CRC. */
<>	144:ef7eb2e8f9f7	4966
<>	144:ef7eb2e8f9f7	4967	/* Bits 23..0 : CRC field of previously received packet. */
<>	144:ef7eb2e8f9f7	4968	#define RADIO_RXCRC_RXCRC_Pos (0UL) /!< Position of RXCRC field. /
<>	144:ef7eb2e8f9f7	4969	#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /!< Bit mask of RXCRC field. /
<>	144:ef7eb2e8f9f7	4970
<>	144:ef7eb2e8f9f7	4971	/* Register: RADIO_DAI */
<>	144:ef7eb2e8f9f7	4972	/* Description: Device address match index. */
<>	144:ef7eb2e8f9f7	4973
<>	144:ef7eb2e8f9f7	4974	/* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */
<>	144:ef7eb2e8f9f7	4975	#define RADIO_DAI_DAI_Pos (0UL) /!< Position of DAI field. /
<>	144:ef7eb2e8f9f7	4976	#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /!< Bit mask of DAI field. /
<>	144:ef7eb2e8f9f7	4977
<>	144:ef7eb2e8f9f7	4978	/* Register: RADIO_FREQUENCY */
<>	144:ef7eb2e8f9f7	4979	/* Description: Frequency. */
<>	144:ef7eb2e8f9f7	4980
<>	144:ef7eb2e8f9f7	4981	/* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task. */
<>	144:ef7eb2e8f9f7	4982	#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
<>	144:ef7eb2e8f9f7	4983	#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
<>	144:ef7eb2e8f9f7	4984
<>	144:ef7eb2e8f9f7	4985	/* Register: RADIO_TXPOWER */
<>	144:ef7eb2e8f9f7	4986	/* Description: Output power. */
<>	144:ef7eb2e8f9f7	4987
<>	144:ef7eb2e8f9f7	4988	/* Bits 7..0 : Radio output power. Decision point: TXEN task. */
<>	144:ef7eb2e8f9f7	4989	#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /!< Position of TXPOWER field. /
<>	144:ef7eb2e8f9f7	4990	#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /!< Bit mask of TXPOWER field. /
<>	144:ef7eb2e8f9f7	4991	#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /!< 0dBm. /
<>	144:ef7eb2e8f9f7	4992	#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /!< +4dBm. /
<>	144:ef7eb2e8f9f7	4993	#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /!< -30dBm. /
<>	144:ef7eb2e8f9f7	4994	#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /!< -20dBm. /
<>	144:ef7eb2e8f9f7	4995	#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /!< -16dBm. /
<>	144:ef7eb2e8f9f7	4996	#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /!< -12dBm. /
<>	144:ef7eb2e8f9f7	4997	#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /!< -8dBm. /
<>	144:ef7eb2e8f9f7	4998	#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /!< -4dBm. /
<>	144:ef7eb2e8f9f7	4999
<>	144:ef7eb2e8f9f7	5000	/* Register: RADIO_MODE */
<>	144:ef7eb2e8f9f7	5001	/* Description: Data rate and modulation. */
<>	144:ef7eb2e8f9f7	5002
<>	144:ef7eb2e8f9f7	5003	/* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */
<>	144:ef7eb2e8f9f7	5004	#define RADIO_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
<>	144:ef7eb2e8f9f7	5005	#define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /!< Bit mask of MODE field. /
<>	144:ef7eb2e8f9f7	5006	#define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /!< 1Mbit/s Nordic propietary radio mode. /
<>	144:ef7eb2e8f9f7	5007	#define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /!< 2Mbit/s Nordic propietary radio mode. /
<>	144:ef7eb2e8f9f7	5008	#define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /!< 250kbit/s Nordic propietary radio mode. /
<>	144:ef7eb2e8f9f7	5009	#define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /!< 1Mbit/s Bluetooth Low Energy /
<>	144:ef7eb2e8f9f7	5010
<>	144:ef7eb2e8f9f7	5011	/* Register: RADIO_PCNF0 */
<>	144:ef7eb2e8f9f7	5012	/* Description: Packet configuration 0. */
<>	144:ef7eb2e8f9f7	5013
<>	144:ef7eb2e8f9f7	5014	/* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */
<>	144:ef7eb2e8f9f7	5015	#define RADIO_PCNF0_S1LEN_Pos (16UL) /!< Position of S1LEN field. /
<>	144:ef7eb2e8f9f7	5016	#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /!< Bit mask of S1LEN field. /
<>	144:ef7eb2e8f9f7	5017
<>	144:ef7eb2e8f9f7	5018	/* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */
<>	144:ef7eb2e8f9f7	5019	#define RADIO_PCNF0_S0LEN_Pos (8UL) /!< Position of S0LEN field. /
<>	144:ef7eb2e8f9f7	5020	#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /!< Bit mask of S0LEN field. /
<>	144:ef7eb2e8f9f7	5021
<>	144:ef7eb2e8f9f7	5022	/* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */
<>	144:ef7eb2e8f9f7	5023	#define RADIO_PCNF0_LFLEN_Pos (0UL) /!< Position of LFLEN field. /
<>	144:ef7eb2e8f9f7	5024	#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /!< Bit mask of LFLEN field. /
<>	144:ef7eb2e8f9f7	5025
<>	144:ef7eb2e8f9f7	5026	/* Register: RADIO_PCNF1 */
<>	144:ef7eb2e8f9f7	5027	/* Description: Packet configuration 1. */
<>	144:ef7eb2e8f9f7	5028
<>	144:ef7eb2e8f9f7	5029	/* Bit 25 : Packet whitening enable. */
<>	144:ef7eb2e8f9f7	5030	#define RADIO_PCNF1_WHITEEN_Pos (25UL) /!< Position of WHITEEN field. /
<>	144:ef7eb2e8f9f7	5031	#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /!< Bit mask of WHITEEN field. /
<>	144:ef7eb2e8f9f7	5032	#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /!< Whitening disabled. /
<>	144:ef7eb2e8f9f7	5033	#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /!< Whitening enabled. /
<>	144:ef7eb2e8f9f7	5034
<>	144:ef7eb2e8f9f7	5035	/* Bit 24 : On air endianness of packet length field. Decision point: START task. */
<>	144:ef7eb2e8f9f7	5036	#define RADIO_PCNF1_ENDIAN_Pos (24UL) /!< Position of ENDIAN field. /
<>	144:ef7eb2e8f9f7	5037	#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /!< Bit mask of ENDIAN field. /
<>	144:ef7eb2e8f9f7	5038	#define RADIO_PCNF1_ENDIAN_Little (0UL) /!< Least significant bit on air first /
<>	144:ef7eb2e8f9f7	5039	#define RADIO_PCNF1_ENDIAN_Big (1UL) /!< Most significant bit on air first /
<>	144:ef7eb2e8f9f7	5040
<>	144:ef7eb2e8f9f7	5041	/* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */
<>	144:ef7eb2e8f9f7	5042	#define RADIO_PCNF1_BALEN_Pos (16UL) /!< Position of BALEN field. /
<>	144:ef7eb2e8f9f7	5043	#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /!< Bit mask of BALEN field. /
<>	144:ef7eb2e8f9f7	5044
<>	144:ef7eb2e8f9f7	5045	/* Bits 15..8 : Static length in number of bytes. Decision point: START task. */
<>	144:ef7eb2e8f9f7	5046	#define RADIO_PCNF1_STATLEN_Pos (8UL) /!< Position of STATLEN field. /
<>	144:ef7eb2e8f9f7	5047	#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /!< Bit mask of STATLEN field. /
<>	144:ef7eb2e8f9f7	5048
<>	144:ef7eb2e8f9f7	5049	/* Bits 7..0 : Maximum length of packet payload in number of bytes. */
<>	144:ef7eb2e8f9f7	5050	#define RADIO_PCNF1_MAXLEN_Pos (0UL) /!< Position of MAXLEN field. /
<>	144:ef7eb2e8f9f7	5051	#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /!< Bit mask of MAXLEN field. /
<>	144:ef7eb2e8f9f7	5052
<>	144:ef7eb2e8f9f7	5053	/* Register: RADIO_PREFIX0 */
<>	144:ef7eb2e8f9f7	5054	/* Description: Prefixes bytes for logical addresses 0 to 3. */
<>	144:ef7eb2e8f9f7	5055
<>	144:ef7eb2e8f9f7	5056	/* Bits 31..24 : Address prefix 3. Decision point: START task. */
<>	144:ef7eb2e8f9f7	5057	#define RADIO_PREFIX0_AP3_Pos (24UL) /!< Position of AP3 field. /
<>	144:ef7eb2e8f9f7	5058	#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /!< Bit mask of AP3 field. /
<>	144:ef7eb2e8f9f7	5059
<>	144:ef7eb2e8f9f7	5060	/* Bits 23..16 : Address prefix 2. Decision point: START task. */
<>	144:ef7eb2e8f9f7	5061	#define RADIO_PREFIX0_AP2_Pos (16UL) /!< Position of AP2 field. /
<>	144:ef7eb2e8f9f7	5062	#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /!< Bit mask of AP2 field. /
<>	144:ef7eb2e8f9f7	5063
<>	144:ef7eb2e8f9f7	5064	/* Bits 15..8 : Address prefix 1. Decision point: START task. */
<>	144:ef7eb2e8f9f7	5065	#define RADIO_PREFIX0_AP1_Pos (8UL) /!< Position of AP1 field. /
<>	144:ef7eb2e8f9f7	5066	#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /!< Bit mask of AP1 field. /
<>	144:ef7eb2e8f9f7	5067
<>	144:ef7eb2e8f9f7	5068	/* Bits 7..0 : Address prefix 0. Decision point: START task. */
<>	144:ef7eb2e8f9f7	5069	#define RADIO_PREFIX0_AP0_Pos (0UL) /!< Position of AP0 field. /
<>	144:ef7eb2e8f9f7	5070	#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /!< Bit mask of AP0 field. /
<>	144:ef7eb2e8f9f7	5071
<>	144:ef7eb2e8f9f7	5072	/* Register: RADIO_PREFIX1 */
<>	144:ef7eb2e8f9f7	5073	/* Description: Prefixes bytes for logical addresses 4 to 7. */
<>	144:ef7eb2e8f9f7	5074
<>	144:ef7eb2e8f9f7	5075	/* Bits 31..24 : Address prefix 7. Decision point: START task. */
<>	144:ef7eb2e8f9f7	5076	#define RADIO_PREFIX1_AP7_Pos (24UL) /!< Position of AP7 field. /
<>	144:ef7eb2e8f9f7	5077	#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /!< Bit mask of AP7 field. /
<>	144:ef7eb2e8f9f7	5078
<>	144:ef7eb2e8f9f7	5079	/* Bits 23..16 : Address prefix 6. Decision point: START task. */
<>	144:ef7eb2e8f9f7	5080	#define RADIO_PREFIX1_AP6_Pos (16UL) /!< Position of AP6 field. /
<>	144:ef7eb2e8f9f7	5081	#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /!< Bit mask of AP6 field. /
<>	144:ef7eb2e8f9f7	5082
<>	144:ef7eb2e8f9f7	5083	/* Bits 15..8 : Address prefix 5. Decision point: START task. */
<>	144:ef7eb2e8f9f7	5084	#define RADIO_PREFIX1_AP5_Pos (8UL) /!< Position of AP5 field. /
<>	144:ef7eb2e8f9f7	5085	#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /!< Bit mask of AP5 field. /
<>	144:ef7eb2e8f9f7	5086
<>	144:ef7eb2e8f9f7	5087	/* Bits 7..0 : Address prefix 4. Decision point: START task. */
<>	144:ef7eb2e8f9f7	5088	#define RADIO_PREFIX1_AP4_Pos (0UL) /!< Position of AP4 field. /
<>	144:ef7eb2e8f9f7	5089	#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /!< Bit mask of AP4 field. /
<>	144:ef7eb2e8f9f7	5090
<>	144:ef7eb2e8f9f7	5091	/* Register: RADIO_TXADDRESS */
<>	144:ef7eb2e8f9f7	5092	/* Description: Transmit address select. */
<>	144:ef7eb2e8f9f7	5093
<>	144:ef7eb2e8f9f7	5094	/* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */
<>	144:ef7eb2e8f9f7	5095	#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /!< Position of TXADDRESS field. /
<>	144:ef7eb2e8f9f7	5096	#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /!< Bit mask of TXADDRESS field. /
<>	144:ef7eb2e8f9f7	5097
<>	144:ef7eb2e8f9f7	5098	/* Register: RADIO_RXADDRESSES */
<>	144:ef7eb2e8f9f7	5099	/* Description: Receive address select. */
<>	144:ef7eb2e8f9f7	5100
<>	144:ef7eb2e8f9f7	5101	/* Bit 7 : Enable reception on logical address 7. Decision point: START task. */
<>	144:ef7eb2e8f9f7	5102	#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /!< Position of ADDR7 field. /
<>	144:ef7eb2e8f9f7	5103	#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /!< Bit mask of ADDR7 field. /
<>	144:ef7eb2e8f9f7	5104	#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /!< Reception disabled. /
<>	144:ef7eb2e8f9f7	5105	#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /!< Reception enabled. /
<>	144:ef7eb2e8f9f7	5106
<>	144:ef7eb2e8f9f7	5107	/* Bit 6 : Enable reception on logical address 6. Decision point: START task. */
<>	144:ef7eb2e8f9f7	5108	#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /!< Position of ADDR6 field. /
<>	144:ef7eb2e8f9f7	5109	#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /!< Bit mask of ADDR6 field. /
<>	144:ef7eb2e8f9f7	5110	#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /!< Reception disabled. /
<>	144:ef7eb2e8f9f7	5111	#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /!< Reception enabled. /
<>	144:ef7eb2e8f9f7	5112
<>	144:ef7eb2e8f9f7	5113	/* Bit 5 : Enable reception on logical address 5. Decision point: START task. */
<>	144:ef7eb2e8f9f7	5114	#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /!< Position of ADDR5 field. /
<>	144:ef7eb2e8f9f7	5115	#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /!< Bit mask of ADDR5 field. /
<>	144:ef7eb2e8f9f7	5116	#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /!< Reception disabled. /
<>	144:ef7eb2e8f9f7	5117	#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /!< Reception enabled. /
<>	144:ef7eb2e8f9f7	5118
<>	144:ef7eb2e8f9f7	5119	/* Bit 4 : Enable reception on logical address 4. Decision point: START task. */
<>	144:ef7eb2e8f9f7	5120	#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /!< Position of ADDR4 field. /
<>	144:ef7eb2e8f9f7	5121	#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /!< Bit mask of ADDR4 field. /
<>	144:ef7eb2e8f9f7	5122	#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /!< Reception disabled. /
<>	144:ef7eb2e8f9f7	5123	#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /!< Reception enabled. /
<>	144:ef7eb2e8f9f7	5124
<>	144:ef7eb2e8f9f7	5125	/* Bit 3 : Enable reception on logical address 3. Decision point: START task. */
<>	144:ef7eb2e8f9f7	5126	#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /!< Position of ADDR3 field. /
<>	144:ef7eb2e8f9f7	5127	#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /!< Bit mask of ADDR3 field. /
<>	144:ef7eb2e8f9f7	5128	#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /!< Reception disabled. /
<>	144:ef7eb2e8f9f7	5129	#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /!< Reception enabled. /
<>	144:ef7eb2e8f9f7	5130
<>	144:ef7eb2e8f9f7	5131	/* Bit 2 : Enable reception on logical address 2. Decision point: START task. */
<>	144:ef7eb2e8f9f7	5132	#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /!< Position of ADDR2 field. /
<>	144:ef7eb2e8f9f7	5133	#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /!< Bit mask of ADDR2 field. /
<>	144:ef7eb2e8f9f7	5134	#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /!< Reception disabled. /
<>	144:ef7eb2e8f9f7	5135	#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /!< Reception enabled. /
<>	144:ef7eb2e8f9f7	5136
<>	144:ef7eb2e8f9f7	5137	/* Bit 1 : Enable reception on logical address 1. Decision point: START task. */
<>	144:ef7eb2e8f9f7	5138	#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /!< Position of ADDR1 field. /
<>	144:ef7eb2e8f9f7	5139	#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /!< Bit mask of ADDR1 field. /
<>	144:ef7eb2e8f9f7	5140	#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /!< Reception disabled. /
<>	144:ef7eb2e8f9f7	5141	#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /!< Reception enabled. /
<>	144:ef7eb2e8f9f7	5142
<>	144:ef7eb2e8f9f7	5143	/* Bit 0 : Enable reception on logical address 0. Decision point: START task. */
<>	144:ef7eb2e8f9f7	5144	#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /!< Position of ADDR0 field. /
<>	144:ef7eb2e8f9f7	5145	#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /!< Bit mask of ADDR0 field. /
<>	144:ef7eb2e8f9f7	5146	#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /!< Reception disabled. /
<>	144:ef7eb2e8f9f7	5147	#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /!< Reception enabled. /
<>	144:ef7eb2e8f9f7	5148
<>	144:ef7eb2e8f9f7	5149	/* Register: RADIO_CRCCNF */
<>	144:ef7eb2e8f9f7	5150	/* Description: CRC configuration. */
<>	144:ef7eb2e8f9f7	5151
<>	144:ef7eb2e8f9f7	5152	/* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */
<>	144:ef7eb2e8f9f7	5153	#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /!< Position of SKIPADDR field. /
<>	144:ef7eb2e8f9f7	5154	#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /!< Bit mask of SKIPADDR field. /
<>	144:ef7eb2e8f9f7	5155	#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /!< Include packet address in CRC calculation. /
<>	144:ef7eb2e8f9f7	5156	#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. /
<>	144:ef7eb2e8f9f7	5157
<>	144:ef7eb2e8f9f7	5158	/* Bits 1..0 : CRC length. Decision point: START task. */
<>	144:ef7eb2e8f9f7	5159	#define RADIO_CRCCNF_LEN_Pos (0UL) /!< Position of LEN field. /
<>	144:ef7eb2e8f9f7	5160	#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /!< Bit mask of LEN field. /
<>	144:ef7eb2e8f9f7	5161	#define RADIO_CRCCNF_LEN_Disabled (0UL) /!< CRC calculation disabled. /
<>	144:ef7eb2e8f9f7	5162	#define RADIO_CRCCNF_LEN_One (1UL) /!< One byte long CRC. /
<>	144:ef7eb2e8f9f7	5163	#define RADIO_CRCCNF_LEN_Two (2UL) /!< Two bytes long CRC. /
<>	144:ef7eb2e8f9f7	5164	#define RADIO_CRCCNF_LEN_Three (3UL) /!< Three bytes long CRC. /
<>	144:ef7eb2e8f9f7	5165
<>	144:ef7eb2e8f9f7	5166	/* Register: RADIO_CRCPOLY */
<>	144:ef7eb2e8f9f7	5167	/* Description: CRC polynomial. */
<>	144:ef7eb2e8f9f7	5168
<>	144:ef7eb2e8f9f7	5169	/* Bits 23..0 : CRC polynomial. Decision point: START task. */
<>	144:ef7eb2e8f9f7	5170	#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /!< Position of CRCPOLY field. /
<>	144:ef7eb2e8f9f7	5171	#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /!< Bit mask of CRCPOLY field. /
<>	144:ef7eb2e8f9f7	5172
<>	144:ef7eb2e8f9f7	5173	/* Register: RADIO_CRCINIT */
<>	144:ef7eb2e8f9f7	5174	/* Description: CRC initial value. */
<>	144:ef7eb2e8f9f7	5175
<>	144:ef7eb2e8f9f7	5176	/* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */
<>	144:ef7eb2e8f9f7	5177	#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /!< Position of CRCINIT field. /
<>	144:ef7eb2e8f9f7	5178	#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /!< Bit mask of CRCINIT field. /
<>	144:ef7eb2e8f9f7	5179
<>	144:ef7eb2e8f9f7	5180	/* Register: RADIO_TEST */
<>	144:ef7eb2e8f9f7	5181	/* Description: Test features enable register. */
<>	144:ef7eb2e8f9f7	5182
<>	144:ef7eb2e8f9f7	5183	/* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */
<>	144:ef7eb2e8f9f7	5184	#define RADIO_TEST_PLLLOCK_Pos (1UL) /!< Position of PLLLOCK field. /
<>	144:ef7eb2e8f9f7	5185	#define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /!< Bit mask of PLLLOCK field. /
<>	144:ef7eb2e8f9f7	5186	#define RADIO_TEST_PLLLOCK_Disabled (0UL) /!< PLL lock disabled. /
<>	144:ef7eb2e8f9f7	5187	#define RADIO_TEST_PLLLOCK_Enabled (1UL) /!< PLL lock enabled. /
<>	144:ef7eb2e8f9f7	5188
<>	144:ef7eb2e8f9f7	5189	/* Bit 0 : Constant carrier. Decision point: TXEN task. */
<>	144:ef7eb2e8f9f7	5190	#define RADIO_TEST_CONSTCARRIER_Pos (0UL) /!< Position of CONSTCARRIER field. /
<>	144:ef7eb2e8f9f7	5191	#define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /!< Bit mask of CONSTCARRIER field. /
<>	144:ef7eb2e8f9f7	5192	#define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /!< Constant carrier disabled. /
<>	144:ef7eb2e8f9f7	5193	#define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /!< Constant carrier enabled. /
<>	144:ef7eb2e8f9f7	5194
<>	144:ef7eb2e8f9f7	5195	/* Register: RADIO_TIFS */
<>	144:ef7eb2e8f9f7	5196	/* Description: Inter Frame Spacing in microseconds. */
<>	144:ef7eb2e8f9f7	5197
<>	144:ef7eb2e8f9f7	5198	/* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */
<>	144:ef7eb2e8f9f7	5199	#define RADIO_TIFS_TIFS_Pos (0UL) /!< Position of TIFS field. /
<>	144:ef7eb2e8f9f7	5200	#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /!< Bit mask of TIFS field. /
<>	144:ef7eb2e8f9f7	5201
<>	144:ef7eb2e8f9f7	5202	/* Register: RADIO_RSSISAMPLE */
<>	144:ef7eb2e8f9f7	5203	/* Description: RSSI sample. */
<>	144:ef7eb2e8f9f7	5204
<>	144:ef7eb2e8f9f7	5205	/* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */
<>	144:ef7eb2e8f9f7	5206	#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /!< Position of RSSISAMPLE field. /
<>	144:ef7eb2e8f9f7	5207	#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /!< Bit mask of RSSISAMPLE field. /
<>	144:ef7eb2e8f9f7	5208
<>	144:ef7eb2e8f9f7	5209	/* Register: RADIO_STATE */
<>	144:ef7eb2e8f9f7	5210	/* Description: Current radio state. */
<>	144:ef7eb2e8f9f7	5211
<>	144:ef7eb2e8f9f7	5212	/* Bits 3..0 : Current radio state. */
<>	144:ef7eb2e8f9f7	5213	#define RADIO_STATE_STATE_Pos (0UL) /!< Position of STATE field. /
<>	144:ef7eb2e8f9f7	5214	#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /!< Bit mask of STATE field. /
<>	144:ef7eb2e8f9f7	5215	#define RADIO_STATE_STATE_Disabled (0x00UL) /!< Radio is in the Disabled state. /
<>	144:ef7eb2e8f9f7	5216	#define RADIO_STATE_STATE_RxRu (0x01UL) /!< Radio is in the Rx Ramp Up state. /
<>	144:ef7eb2e8f9f7	5217	#define RADIO_STATE_STATE_RxIdle (0x02UL) /!< Radio is in the Rx Idle state. /
<>	144:ef7eb2e8f9f7	5218	#define RADIO_STATE_STATE_Rx (0x03UL) /!< Radio is in the Rx state. /
<>	144:ef7eb2e8f9f7	5219	#define RADIO_STATE_STATE_RxDisable (0x04UL) /!< Radio is in the Rx Disable state. /
<>	144:ef7eb2e8f9f7	5220	#define RADIO_STATE_STATE_TxRu (0x09UL) /!< Radio is in the Tx Ramp Up state. /
<>	144:ef7eb2e8f9f7	5221	#define RADIO_STATE_STATE_TxIdle (0x0AUL) /!< Radio is in the Tx Idle state. /
<>	144:ef7eb2e8f9f7	5222	#define RADIO_STATE_STATE_Tx (0x0BUL) /!< Radio is in the Tx state. /
<>	144:ef7eb2e8f9f7	5223	#define RADIO_STATE_STATE_TxDisable (0x0CUL) /!< Radio is in the Tx Disable state. /
<>	144:ef7eb2e8f9f7	5224
<>	144:ef7eb2e8f9f7	5225	/* Register: RADIO_DATAWHITEIV */
<>	144:ef7eb2e8f9f7	5226	/* Description: Data whitening initial value. */
<>	144:ef7eb2e8f9f7	5227
<>	144:ef7eb2e8f9f7	5228	/* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */
<>	144:ef7eb2e8f9f7	5229	#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /!< Position of DATAWHITEIV field. /
<>	144:ef7eb2e8f9f7	5230	#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /!< Bit mask of DATAWHITEIV field. /
<>	144:ef7eb2e8f9f7	5231
<>	144:ef7eb2e8f9f7	5232	/* Register: RADIO_DAP */
<>	144:ef7eb2e8f9f7	5233	/* Description: Device address prefix. */
<>	144:ef7eb2e8f9f7	5234
<>	144:ef7eb2e8f9f7	5235	/* Bits 15..0 : Device address prefix. */
<>	144:ef7eb2e8f9f7	5236	#define RADIO_DAP_DAP_Pos (0UL) /!< Position of DAP field. /
<>	144:ef7eb2e8f9f7	5237	#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /!< Bit mask of DAP field. /
<>	144:ef7eb2e8f9f7	5238
<>	144:ef7eb2e8f9f7	5239	/* Register: RADIO_DACNF */
<>	144:ef7eb2e8f9f7	5240	/* Description: Device address match configuration. */
<>	144:ef7eb2e8f9f7	5241
<>	144:ef7eb2e8f9f7	5242	/* Bit 15 : TxAdd for device address 7. */
<>	144:ef7eb2e8f9f7	5243	#define RADIO_DACNF_TXADD7_Pos (15UL) /!< Position of TXADD7 field. /
<>	144:ef7eb2e8f9f7	5244	#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /!< Bit mask of TXADD7 field. /
<>	144:ef7eb2e8f9f7	5245
<>	144:ef7eb2e8f9f7	5246	/* Bit 14 : TxAdd for device address 6. */
<>	144:ef7eb2e8f9f7	5247	#define RADIO_DACNF_TXADD6_Pos (14UL) /!< Position of TXADD6 field. /
<>	144:ef7eb2e8f9f7	5248	#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /!< Bit mask of TXADD6 field. /
<>	144:ef7eb2e8f9f7	5249
<>	144:ef7eb2e8f9f7	5250	/* Bit 13 : TxAdd for device address 5. */
<>	144:ef7eb2e8f9f7	5251	#define RADIO_DACNF_TXADD5_Pos (13UL) /!< Position of TXADD5 field. /
<>	144:ef7eb2e8f9f7	5252	#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /!< Bit mask of TXADD5 field. /
<>	144:ef7eb2e8f9f7	5253
<>	144:ef7eb2e8f9f7	5254	/* Bit 12 : TxAdd for device address 4. */
<>	144:ef7eb2e8f9f7	5255	#define RADIO_DACNF_TXADD4_Pos (12UL) /!< Position of TXADD4 field. /
<>	144:ef7eb2e8f9f7	5256	#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /!< Bit mask of TXADD4 field. /
<>	144:ef7eb2e8f9f7	5257
<>	144:ef7eb2e8f9f7	5258	/* Bit 11 : TxAdd for device address 3. */
<>	144:ef7eb2e8f9f7	5259	#define RADIO_DACNF_TXADD3_Pos (11UL) /!< Position of TXADD3 field. /
<>	144:ef7eb2e8f9f7	5260	#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /!< Bit mask of TXADD3 field. /
<>	144:ef7eb2e8f9f7	5261
<>	144:ef7eb2e8f9f7	5262	/* Bit 10 : TxAdd for device address 2. */
<>	144:ef7eb2e8f9f7	5263	#define RADIO_DACNF_TXADD2_Pos (10UL) /!< Position of TXADD2 field. /
<>	144:ef7eb2e8f9f7	5264	#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /!< Bit mask of TXADD2 field. /
<>	144:ef7eb2e8f9f7	5265
<>	144:ef7eb2e8f9f7	5266	/* Bit 9 : TxAdd for device address 1. */
<>	144:ef7eb2e8f9f7	5267	#define RADIO_DACNF_TXADD1_Pos (9UL) /!< Position of TXADD1 field. /
<>	144:ef7eb2e8f9f7	5268	#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /!< Bit mask of TXADD1 field. /
<>	144:ef7eb2e8f9f7	5269
<>	144:ef7eb2e8f9f7	5270	/* Bit 8 : TxAdd for device address 0. */
<>	144:ef7eb2e8f9f7	5271	#define RADIO_DACNF_TXADD0_Pos (8UL) /!< Position of TXADD0 field. /
<>	144:ef7eb2e8f9f7	5272	#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /!< Bit mask of TXADD0 field. /
<>	144:ef7eb2e8f9f7	5273
<>	144:ef7eb2e8f9f7	5274	/* Bit 7 : Enable or disable device address matching using device address 7. */
<>	144:ef7eb2e8f9f7	5275	#define RADIO_DACNF_ENA7_Pos (7UL) /!< Position of ENA7 field. /
<>	144:ef7eb2e8f9f7	5276	#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /!< Bit mask of ENA7 field. /
<>	144:ef7eb2e8f9f7	5277	#define RADIO_DACNF_ENA7_Disabled (0UL) /!< Disabled. /
<>	144:ef7eb2e8f9f7	5278	#define RADIO_DACNF_ENA7_Enabled (1UL) /!< Enabled. /
<>	144:ef7eb2e8f9f7	5279
<>	144:ef7eb2e8f9f7	5280	/* Bit 6 : Enable or disable device address matching using device address 6. */
<>	144:ef7eb2e8f9f7	5281	#define RADIO_DACNF_ENA6_Pos (6UL) /!< Position of ENA6 field. /
<>	144:ef7eb2e8f9f7	5282	#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /!< Bit mask of ENA6 field. /
<>	144:ef7eb2e8f9f7	5283	#define RADIO_DACNF_ENA6_Disabled (0UL) /!< Disabled. /
<>	144:ef7eb2e8f9f7	5284	#define RADIO_DACNF_ENA6_Enabled (1UL) /!< Enabled. /
<>	144:ef7eb2e8f9f7	5285
<>	144:ef7eb2e8f9f7	5286	/* Bit 5 : Enable or disable device address matching using device address 5. */
<>	144:ef7eb2e8f9f7	5287	#define RADIO_DACNF_ENA5_Pos (5UL) /!< Position of ENA5 field. /
<>	144:ef7eb2e8f9f7	5288	#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /!< Bit mask of ENA5 field. /
<>	144:ef7eb2e8f9f7	5289	#define RADIO_DACNF_ENA5_Disabled (0UL) /!< Disabled. /
<>	144:ef7eb2e8f9f7	5290	#define RADIO_DACNF_ENA5_Enabled (1UL) /!< Enabled. /
<>	144:ef7eb2e8f9f7	5291
<>	144:ef7eb2e8f9f7	5292	/* Bit 4 : Enable or disable device address matching using device address 4. */
<>	144:ef7eb2e8f9f7	5293	#define RADIO_DACNF_ENA4_Pos (4UL) /!< Position of ENA4 field. /
<>	144:ef7eb2e8f9f7	5294	#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /!< Bit mask of ENA4 field. /
<>	144:ef7eb2e8f9f7	5295	#define RADIO_DACNF_ENA4_Disabled (0UL) /!< Disabled. /
<>	144:ef7eb2e8f9f7	5296	#define RADIO_DACNF_ENA4_Enabled (1UL) /!< Enabled. /
<>	144:ef7eb2e8f9f7	5297
<>	144:ef7eb2e8f9f7	5298	/* Bit 3 : Enable or disable device address matching using device address 3. */
<>	144:ef7eb2e8f9f7	5299	#define RADIO_DACNF_ENA3_Pos (3UL) /!< Position of ENA3 field. /
<>	144:ef7eb2e8f9f7	5300	#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /!< Bit mask of ENA3 field. /
<>	144:ef7eb2e8f9f7	5301	#define RADIO_DACNF_ENA3_Disabled (0UL) /!< Disabled. /
<>	144:ef7eb2e8f9f7	5302	#define RADIO_DACNF_ENA3_Enabled (1UL) /!< Enabled. /
<>	144:ef7eb2e8f9f7	5303
<>	144:ef7eb2e8f9f7	5304	/* Bit 2 : Enable or disable device address matching using device address 2. */
<>	144:ef7eb2e8f9f7	5305	#define RADIO_DACNF_ENA2_Pos (2UL) /!< Position of ENA2 field. /
<>	144:ef7eb2e8f9f7	5306	#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /!< Bit mask of ENA2 field. /
<>	144:ef7eb2e8f9f7	5307	#define RADIO_DACNF_ENA2_Disabled (0UL) /!< Disabled. /
<>	144:ef7eb2e8f9f7	5308	#define RADIO_DACNF_ENA2_Enabled (1UL) /!< Enabled. /
<>	144:ef7eb2e8f9f7	5309
<>	144:ef7eb2e8f9f7	5310	/* Bit 1 : Enable or disable device address matching using device address 1. */
<>	144:ef7eb2e8f9f7	5311	#define RADIO_DACNF_ENA1_Pos (1UL) /!< Position of ENA1 field. /
<>	144:ef7eb2e8f9f7	5312	#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /!< Bit mask of ENA1 field. /
<>	144:ef7eb2e8f9f7	5313	#define RADIO_DACNF_ENA1_Disabled (0UL) /!< Disabled. /
<>	144:ef7eb2e8f9f7	5314	#define RADIO_DACNF_ENA1_Enabled (1UL) /!< Enabled. /
<>	144:ef7eb2e8f9f7	5315
<>	144:ef7eb2e8f9f7	5316	/* Bit 0 : Enable or disable device address matching using device address 0. */
<>	144:ef7eb2e8f9f7	5317	#define RADIO_DACNF_ENA0_Pos (0UL) /!< Position of ENA0 field. /
<>	144:ef7eb2e8f9f7	5318	#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /!< Bit mask of ENA0 field. /
<>	144:ef7eb2e8f9f7	5319	#define RADIO_DACNF_ENA0_Disabled (0UL) /!< Disabled. /
<>	144:ef7eb2e8f9f7	5320	#define RADIO_DACNF_ENA0_Enabled (1UL) /!< Enabled. /
<>	144:ef7eb2e8f9f7	5321
<>	144:ef7eb2e8f9f7	5322	/* Register: RADIO_OVERRIDE0 */
<>	144:ef7eb2e8f9f7	5323	/* Description: Trim value override register 0. */
<>	144:ef7eb2e8f9f7	5324
<>	144:ef7eb2e8f9f7	5325	/* Bits 31..0 : Trim value override 0. */
<>	144:ef7eb2e8f9f7	5326	#define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /!< Position of OVERRIDE0 field. /
<>	144:ef7eb2e8f9f7	5327	#define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /!< Bit mask of OVERRIDE0 field. /
<>	144:ef7eb2e8f9f7	5328
<>	144:ef7eb2e8f9f7	5329	/* Register: RADIO_OVERRIDE1 */
<>	144:ef7eb2e8f9f7	5330	/* Description: Trim value override register 1. */
<>	144:ef7eb2e8f9f7	5331
<>	144:ef7eb2e8f9f7	5332	/* Bits 31..0 : Trim value override 1. */
<>	144:ef7eb2e8f9f7	5333	#define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /!< Position of OVERRIDE1 field. /
<>	144:ef7eb2e8f9f7	5334	#define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /!< Bit mask of OVERRIDE1 field. /
<>	144:ef7eb2e8f9f7	5335
<>	144:ef7eb2e8f9f7	5336	/* Register: RADIO_OVERRIDE2 */
<>	144:ef7eb2e8f9f7	5337	/* Description: Trim value override register 2. */
<>	144:ef7eb2e8f9f7	5338
<>	144:ef7eb2e8f9f7	5339	/* Bits 31..0 : Trim value override 2. */
<>	144:ef7eb2e8f9f7	5340	#define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /!< Position of OVERRIDE2 field. /
<>	144:ef7eb2e8f9f7	5341	#define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /!< Bit mask of OVERRIDE2 field. /
<>	144:ef7eb2e8f9f7	5342
<>	144:ef7eb2e8f9f7	5343	/* Register: RADIO_OVERRIDE3 */
<>	144:ef7eb2e8f9f7	5344	/* Description: Trim value override register 3. */
<>	144:ef7eb2e8f9f7	5345
<>	144:ef7eb2e8f9f7	5346	/* Bits 31..0 : Trim value override 3. */
<>	144:ef7eb2e8f9f7	5347	#define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /!< Position of OVERRIDE3 field. /
<>	144:ef7eb2e8f9f7	5348	#define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /!< Bit mask of OVERRIDE3 field. /
<>	144:ef7eb2e8f9f7	5349
<>	144:ef7eb2e8f9f7	5350	/* Register: RADIO_OVERRIDE4 */
<>	144:ef7eb2e8f9f7	5351	/* Description: Trim value override register 4. */
<>	144:ef7eb2e8f9f7	5352
<>	144:ef7eb2e8f9f7	5353	/* Bit 31 : Enable or disable override of default trim values. */
<>	144:ef7eb2e8f9f7	5354	#define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /!< Position of ENABLE field. /
<>	144:ef7eb2e8f9f7	5355	#define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /!< Bit mask of ENABLE field. /
<>	144:ef7eb2e8f9f7	5356	#define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /!< Override trim values disabled. /
<>	144:ef7eb2e8f9f7	5357	#define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /!< Override trim values enabled. /
<>	144:ef7eb2e8f9f7	5358
<>	144:ef7eb2e8f9f7	5359	/* Bits 27..0 : Trim value override 4. */
<>	144:ef7eb2e8f9f7	5360	#define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /!< Position of OVERRIDE4 field. /
<>	144:ef7eb2e8f9f7	5361	#define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /!< Bit mask of OVERRIDE4 field. /
<>	144:ef7eb2e8f9f7	5362
<>	144:ef7eb2e8f9f7	5363	/* Register: RADIO_POWER */
<>	144:ef7eb2e8f9f7	5364	/* Description: Peripheral power control. */
<>	144:ef7eb2e8f9f7	5365
<>	144:ef7eb2e8f9f7	5366	/* Bit 0 : Peripheral power control. */
<>	144:ef7eb2e8f9f7	5367	#define RADIO_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
<>	144:ef7eb2e8f9f7	5368	#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /!< Bit mask of POWER field. /
<>	144:ef7eb2e8f9f7	5369	#define RADIO_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
<>	144:ef7eb2e8f9f7	5370	#define RADIO_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
<>	144:ef7eb2e8f9f7	5371
<>	144:ef7eb2e8f9f7	5372
<>	144:ef7eb2e8f9f7	5373	/* Peripheral: RNG */
<>	144:ef7eb2e8f9f7	5374	/* Description: Random Number Generator. */
<>	144:ef7eb2e8f9f7	5375
<>	144:ef7eb2e8f9f7	5376	/* Register: RNG_SHORTS */
<>	144:ef7eb2e8f9f7	5377	/* Description: Shortcuts for the RNG. */
<>	144:ef7eb2e8f9f7	5378
<>	144:ef7eb2e8f9f7	5379	/* Bit 0 : Shortcut between VALRDY event and STOP task. */
<>	144:ef7eb2e8f9f7	5380	#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /!< Position of VALRDY_STOP field. /
<>	144:ef7eb2e8f9f7	5381	#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /!< Bit mask of VALRDY_STOP field. /
<>	144:ef7eb2e8f9f7	5382	#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /!< Shortcut disabled. /
<>	144:ef7eb2e8f9f7	5383	#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /!< Shortcut enabled. /
<>	144:ef7eb2e8f9f7	5384
<>	144:ef7eb2e8f9f7	5385	/* Register: RNG_INTENSET */
<>	144:ef7eb2e8f9f7	5386	/* Description: Interrupt enable set register */
<>	144:ef7eb2e8f9f7	5387
<>	144:ef7eb2e8f9f7	5388	/* Bit 0 : Enable interrupt on VALRDY event. */
<>	144:ef7eb2e8f9f7	5389	#define RNG_INTENSET_VALRDY_Pos (0UL) /!< Position of VALRDY field. /
<>	144:ef7eb2e8f9f7	5390	#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /!< Bit mask of VALRDY field. /
<>	144:ef7eb2e8f9f7	5391	#define RNG_INTENSET_VALRDY_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	5392	#define RNG_INTENSET_VALRDY_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	5393	#define RNG_INTENSET_VALRDY_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	5394
<>	144:ef7eb2e8f9f7	5395	/* Register: RNG_INTENCLR */
<>	144:ef7eb2e8f9f7	5396	/* Description: Interrupt enable clear register */
<>	144:ef7eb2e8f9f7	5397
<>	144:ef7eb2e8f9f7	5398	/* Bit 0 : Disable interrupt on VALRDY event. */
<>	144:ef7eb2e8f9f7	5399	#define RNG_INTENCLR_VALRDY_Pos (0UL) /!< Position of VALRDY field. /
<>	144:ef7eb2e8f9f7	5400	#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /!< Bit mask of VALRDY field. /
<>	144:ef7eb2e8f9f7	5401	#define RNG_INTENCLR_VALRDY_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	5402	#define RNG_INTENCLR_VALRDY_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	5403	#define RNG_INTENCLR_VALRDY_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	5404
<>	144:ef7eb2e8f9f7	5405	/* Register: RNG_CONFIG */
<>	144:ef7eb2e8f9f7	5406	/* Description: Configuration register. */
<>	144:ef7eb2e8f9f7	5407
<>	144:ef7eb2e8f9f7	5408	/* Bit 0 : Digital error correction enable. */
<>	144:ef7eb2e8f9f7	5409	#define RNG_CONFIG_DERCEN_Pos (0UL) /!< Position of DERCEN field. /
<>	144:ef7eb2e8f9f7	5410	#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /!< Bit mask of DERCEN field. /
<>	144:ef7eb2e8f9f7	5411	#define RNG_CONFIG_DERCEN_Disabled (0UL) /!< Digital error correction disabled. /
<>	144:ef7eb2e8f9f7	5412	#define RNG_CONFIG_DERCEN_Enabled (1UL) /!< Digital error correction enabled. /
<>	144:ef7eb2e8f9f7	5413
<>	144:ef7eb2e8f9f7	5414	/* Register: RNG_VALUE */
<>	144:ef7eb2e8f9f7	5415	/* Description: RNG random number. */
<>	144:ef7eb2e8f9f7	5416
<>	144:ef7eb2e8f9f7	5417	/* Bits 7..0 : Generated random number. */
<>	144:ef7eb2e8f9f7	5418	#define RNG_VALUE_VALUE_Pos (0UL) /!< Position of VALUE field. /
<>	144:ef7eb2e8f9f7	5419	#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /!< Bit mask of VALUE field. /
<>	144:ef7eb2e8f9f7	5420
<>	144:ef7eb2e8f9f7	5421	/* Register: RNG_POWER */
<>	144:ef7eb2e8f9f7	5422	/* Description: Peripheral power control. */
<>	144:ef7eb2e8f9f7	5423
<>	144:ef7eb2e8f9f7	5424	/* Bit 0 : Peripheral power control. */
<>	144:ef7eb2e8f9f7	5425	#define RNG_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
<>	144:ef7eb2e8f9f7	5426	#define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /!< Bit mask of POWER field. /
<>	144:ef7eb2e8f9f7	5427	#define RNG_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
<>	144:ef7eb2e8f9f7	5428	#define RNG_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
<>	144:ef7eb2e8f9f7	5429
<>	144:ef7eb2e8f9f7	5430
<>	144:ef7eb2e8f9f7	5431	/* Peripheral: RTC */
<>	144:ef7eb2e8f9f7	5432	/* Description: Real time counter 0. */
<>	144:ef7eb2e8f9f7	5433
<>	144:ef7eb2e8f9f7	5434	/* Register: RTC_INTENSET */
<>	144:ef7eb2e8f9f7	5435	/* Description: Interrupt enable set register. */
<>	144:ef7eb2e8f9f7	5436
<>	144:ef7eb2e8f9f7	5437	/* Bit 19 : Enable interrupt on COMPARE[3] event. */
<>	144:ef7eb2e8f9f7	5438	#define RTC_INTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
<>	144:ef7eb2e8f9f7	5439	#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
<>	144:ef7eb2e8f9f7	5440	#define RTC_INTENSET_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	5441	#define RTC_INTENSET_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	5442	#define RTC_INTENSET_COMPARE3_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	5443
<>	144:ef7eb2e8f9f7	5444	/* Bit 18 : Enable interrupt on COMPARE[2] event. */
<>	144:ef7eb2e8f9f7	5445	#define RTC_INTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
<>	144:ef7eb2e8f9f7	5446	#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
<>	144:ef7eb2e8f9f7	5447	#define RTC_INTENSET_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	5448	#define RTC_INTENSET_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	5449	#define RTC_INTENSET_COMPARE2_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	5450
<>	144:ef7eb2e8f9f7	5451	/* Bit 17 : Enable interrupt on COMPARE[1] event. */
<>	144:ef7eb2e8f9f7	5452	#define RTC_INTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
<>	144:ef7eb2e8f9f7	5453	#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
<>	144:ef7eb2e8f9f7	5454	#define RTC_INTENSET_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	5455	#define RTC_INTENSET_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	5456	#define RTC_INTENSET_COMPARE1_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	5457
<>	144:ef7eb2e8f9f7	5458	/* Bit 16 : Enable interrupt on COMPARE[0] event. */
<>	144:ef7eb2e8f9f7	5459	#define RTC_INTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
<>	144:ef7eb2e8f9f7	5460	#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
<>	144:ef7eb2e8f9f7	5461	#define RTC_INTENSET_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	5462	#define RTC_INTENSET_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	5463	#define RTC_INTENSET_COMPARE0_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	5464
<>	144:ef7eb2e8f9f7	5465	/* Bit 1 : Enable interrupt on OVRFLW event. */
<>	144:ef7eb2e8f9f7	5466	#define RTC_INTENSET_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
<>	144:ef7eb2e8f9f7	5467	#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
<>	144:ef7eb2e8f9f7	5468	#define RTC_INTENSET_OVRFLW_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	5469	#define RTC_INTENSET_OVRFLW_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	5470	#define RTC_INTENSET_OVRFLW_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	5471
<>	144:ef7eb2e8f9f7	5472	/* Bit 0 : Enable interrupt on TICK event. */
<>	144:ef7eb2e8f9f7	5473	#define RTC_INTENSET_TICK_Pos (0UL) /!< Position of TICK field. /
<>	144:ef7eb2e8f9f7	5474	#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /!< Bit mask of TICK field. /
<>	144:ef7eb2e8f9f7	5475	#define RTC_INTENSET_TICK_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	5476	#define RTC_INTENSET_TICK_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	5477	#define RTC_INTENSET_TICK_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	5478
<>	144:ef7eb2e8f9f7	5479	/* Register: RTC_INTENCLR */
<>	144:ef7eb2e8f9f7	5480	/* Description: Interrupt enable clear register. */
<>	144:ef7eb2e8f9f7	5481
<>	144:ef7eb2e8f9f7	5482	/* Bit 19 : Disable interrupt on COMPARE[3] event. */
<>	144:ef7eb2e8f9f7	5483	#define RTC_INTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
<>	144:ef7eb2e8f9f7	5484	#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
<>	144:ef7eb2e8f9f7	5485	#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	5486	#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	5487	#define RTC_INTENCLR_COMPARE3_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	5488
<>	144:ef7eb2e8f9f7	5489	/* Bit 18 : Disable interrupt on COMPARE[2] event. */
<>	144:ef7eb2e8f9f7	5490	#define RTC_INTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
<>	144:ef7eb2e8f9f7	5491	#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
<>	144:ef7eb2e8f9f7	5492	#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	5493	#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	5494	#define RTC_INTENCLR_COMPARE2_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	5495
<>	144:ef7eb2e8f9f7	5496	/* Bit 17 : Disable interrupt on COMPARE[1] event. */
<>	144:ef7eb2e8f9f7	5497	#define RTC_INTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
<>	144:ef7eb2e8f9f7	5498	#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
<>	144:ef7eb2e8f9f7	5499	#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	5500	#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	5501	#define RTC_INTENCLR_COMPARE1_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	5502
<>	144:ef7eb2e8f9f7	5503	/* Bit 16 : Disable interrupt on COMPARE[0] event. */
<>	144:ef7eb2e8f9f7	5504	#define RTC_INTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
<>	144:ef7eb2e8f9f7	5505	#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
<>	144:ef7eb2e8f9f7	5506	#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	5507	#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	5508	#define RTC_INTENCLR_COMPARE0_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	5509
<>	144:ef7eb2e8f9f7	5510	/* Bit 1 : Disable interrupt on OVRFLW event. */
<>	144:ef7eb2e8f9f7	5511	#define RTC_INTENCLR_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
<>	144:ef7eb2e8f9f7	5512	#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
<>	144:ef7eb2e8f9f7	5513	#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	5514	#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	5515	#define RTC_INTENCLR_OVRFLW_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	5516
<>	144:ef7eb2e8f9f7	5517	/* Bit 0 : Disable interrupt on TICK event. */
<>	144:ef7eb2e8f9f7	5518	#define RTC_INTENCLR_TICK_Pos (0UL) /!< Position of TICK field. /
<>	144:ef7eb2e8f9f7	5519	#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /!< Bit mask of TICK field. /
<>	144:ef7eb2e8f9f7	5520	#define RTC_INTENCLR_TICK_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	5521	#define RTC_INTENCLR_TICK_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	5522	#define RTC_INTENCLR_TICK_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	5523
<>	144:ef7eb2e8f9f7	5524	/* Register: RTC_EVTEN */
<>	144:ef7eb2e8f9f7	5525	/* Description: Configures event enable routing to PPI for each RTC event. */
<>	144:ef7eb2e8f9f7	5526
<>	144:ef7eb2e8f9f7	5527	/* Bit 19 : COMPARE[3] event enable. */
<>	144:ef7eb2e8f9f7	5528	#define RTC_EVTEN_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
<>	144:ef7eb2e8f9f7	5529	#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
<>	144:ef7eb2e8f9f7	5530	#define RTC_EVTEN_COMPARE3_Disabled (0UL) /!< Event disabled. /
<>	144:ef7eb2e8f9f7	5531	#define RTC_EVTEN_COMPARE3_Enabled (1UL) /!< Event enabled. /
<>	144:ef7eb2e8f9f7	5532
<>	144:ef7eb2e8f9f7	5533	/* Bit 18 : COMPARE[2] event enable. */
<>	144:ef7eb2e8f9f7	5534	#define RTC_EVTEN_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
<>	144:ef7eb2e8f9f7	5535	#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
<>	144:ef7eb2e8f9f7	5536	#define RTC_EVTEN_COMPARE2_Disabled (0UL) /!< Event disabled. /
<>	144:ef7eb2e8f9f7	5537	#define RTC_EVTEN_COMPARE2_Enabled (1UL) /!< Event enabled. /
<>	144:ef7eb2e8f9f7	5538
<>	144:ef7eb2e8f9f7	5539	/* Bit 17 : COMPARE[1] event enable. */
<>	144:ef7eb2e8f9f7	5540	#define RTC_EVTEN_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
<>	144:ef7eb2e8f9f7	5541	#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
<>	144:ef7eb2e8f9f7	5542	#define RTC_EVTEN_COMPARE1_Disabled (0UL) /!< Event disabled. /
<>	144:ef7eb2e8f9f7	5543	#define RTC_EVTEN_COMPARE1_Enabled (1UL) /!< Event enabled. /
<>	144:ef7eb2e8f9f7	5544
<>	144:ef7eb2e8f9f7	5545	/* Bit 16 : COMPARE[0] event enable. */
<>	144:ef7eb2e8f9f7	5546	#define RTC_EVTEN_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
<>	144:ef7eb2e8f9f7	5547	#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
<>	144:ef7eb2e8f9f7	5548	#define RTC_EVTEN_COMPARE0_Disabled (0UL) /!< Event disabled. /
<>	144:ef7eb2e8f9f7	5549	#define RTC_EVTEN_COMPARE0_Enabled (1UL) /!< Event enabled. /
<>	144:ef7eb2e8f9f7	5550
<>	144:ef7eb2e8f9f7	5551	/* Bit 1 : OVRFLW event enable. */
<>	144:ef7eb2e8f9f7	5552	#define RTC_EVTEN_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
<>	144:ef7eb2e8f9f7	5553	#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
<>	144:ef7eb2e8f9f7	5554	#define RTC_EVTEN_OVRFLW_Disabled (0UL) /!< Event disabled. /
<>	144:ef7eb2e8f9f7	5555	#define RTC_EVTEN_OVRFLW_Enabled (1UL) /!< Event enabled. /
<>	144:ef7eb2e8f9f7	5556
<>	144:ef7eb2e8f9f7	5557	/* Bit 0 : TICK event enable. */
<>	144:ef7eb2e8f9f7	5558	#define RTC_EVTEN_TICK_Pos (0UL) /!< Position of TICK field. /
<>	144:ef7eb2e8f9f7	5559	#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /!< Bit mask of TICK field. /
<>	144:ef7eb2e8f9f7	5560	#define RTC_EVTEN_TICK_Disabled (0UL) /!< Event disabled. /
<>	144:ef7eb2e8f9f7	5561	#define RTC_EVTEN_TICK_Enabled (1UL) /!< Event enabled. /
<>	144:ef7eb2e8f9f7	5562
<>	144:ef7eb2e8f9f7	5563	/* Register: RTC_EVTENSET */
<>	144:ef7eb2e8f9f7	5564	/* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */
<>	144:ef7eb2e8f9f7	5565
<>	144:ef7eb2e8f9f7	5566	/* Bit 19 : Enable routing to PPI of COMPARE[3] event. */
<>	144:ef7eb2e8f9f7	5567	#define RTC_EVTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
<>	144:ef7eb2e8f9f7	5568	#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
<>	144:ef7eb2e8f9f7	5569	#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /!< Event disabled. /
<>	144:ef7eb2e8f9f7	5570	#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /!< Event enabled. /
<>	144:ef7eb2e8f9f7	5571	#define RTC_EVTENSET_COMPARE3_Set (1UL) /!< Enable event on write. /
<>	144:ef7eb2e8f9f7	5572
<>	144:ef7eb2e8f9f7	5573	/* Bit 18 : Enable routing to PPI of COMPARE[2] event. */
<>	144:ef7eb2e8f9f7	5574	#define RTC_EVTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
<>	144:ef7eb2e8f9f7	5575	#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
<>	144:ef7eb2e8f9f7	5576	#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /!< Event disabled. /
<>	144:ef7eb2e8f9f7	5577	#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /!< Event enabled. /
<>	144:ef7eb2e8f9f7	5578	#define RTC_EVTENSET_COMPARE2_Set (1UL) /!< Enable event on write. /
<>	144:ef7eb2e8f9f7	5579
<>	144:ef7eb2e8f9f7	5580	/* Bit 17 : Enable routing to PPI of COMPARE[1] event. */
<>	144:ef7eb2e8f9f7	5581	#define RTC_EVTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
<>	144:ef7eb2e8f9f7	5582	#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
<>	144:ef7eb2e8f9f7	5583	#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /!< Event disabled. /
<>	144:ef7eb2e8f9f7	5584	#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /!< Event enabled. /
<>	144:ef7eb2e8f9f7	5585	#define RTC_EVTENSET_COMPARE1_Set (1UL) /!< Enable event on write. /
<>	144:ef7eb2e8f9f7	5586
<>	144:ef7eb2e8f9f7	5587	/* Bit 16 : Enable routing to PPI of COMPARE[0] event. */
<>	144:ef7eb2e8f9f7	5588	#define RTC_EVTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
<>	144:ef7eb2e8f9f7	5589	#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
<>	144:ef7eb2e8f9f7	5590	#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /!< Event disabled. /
<>	144:ef7eb2e8f9f7	5591	#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /!< Event enabled. /
<>	144:ef7eb2e8f9f7	5592	#define RTC_EVTENSET_COMPARE0_Set (1UL) /!< Enable event on write. /
<>	144:ef7eb2e8f9f7	5593
<>	144:ef7eb2e8f9f7	5594	/* Bit 1 : Enable routing to PPI of OVRFLW event. */
<>	144:ef7eb2e8f9f7	5595	#define RTC_EVTENSET_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
<>	144:ef7eb2e8f9f7	5596	#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
<>	144:ef7eb2e8f9f7	5597	#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /!< Event disabled. /
<>	144:ef7eb2e8f9f7	5598	#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /!< Event enabled. /
<>	144:ef7eb2e8f9f7	5599	#define RTC_EVTENSET_OVRFLW_Set (1UL) /!< Enable event on write. /
<>	144:ef7eb2e8f9f7	5600
<>	144:ef7eb2e8f9f7	5601	/* Bit 0 : Enable routing to PPI of TICK event. */
<>	144:ef7eb2e8f9f7	5602	#define RTC_EVTENSET_TICK_Pos (0UL) /!< Position of TICK field. /
<>	144:ef7eb2e8f9f7	5603	#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /!< Bit mask of TICK field. /
<>	144:ef7eb2e8f9f7	5604	#define RTC_EVTENSET_TICK_Disabled (0UL) /!< Event disabled. /
<>	144:ef7eb2e8f9f7	5605	#define RTC_EVTENSET_TICK_Enabled (1UL) /!< Event enabled. /
<>	144:ef7eb2e8f9f7	5606	#define RTC_EVTENSET_TICK_Set (1UL) /!< Enable event on write. /
<>	144:ef7eb2e8f9f7	5607
<>	144:ef7eb2e8f9f7	5608	/* Register: RTC_EVTENCLR */
<>	144:ef7eb2e8f9f7	5609	/* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */
<>	144:ef7eb2e8f9f7	5610
<>	144:ef7eb2e8f9f7	5611	/* Bit 19 : Disable routing to PPI of COMPARE[3] event. */
<>	144:ef7eb2e8f9f7	5612	#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
<>	144:ef7eb2e8f9f7	5613	#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
<>	144:ef7eb2e8f9f7	5614	#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /!< Event disabled. /
<>	144:ef7eb2e8f9f7	5615	#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /!< Event enabled. /
<>	144:ef7eb2e8f9f7	5616	#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /!< Disable event on write. /
<>	144:ef7eb2e8f9f7	5617
<>	144:ef7eb2e8f9f7	5618	/* Bit 18 : Disable routing to PPI of COMPARE[2] event. */
<>	144:ef7eb2e8f9f7	5619	#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
<>	144:ef7eb2e8f9f7	5620	#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
<>	144:ef7eb2e8f9f7	5621	#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /!< Event disabled. /
<>	144:ef7eb2e8f9f7	5622	#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /!< Event enabled. /
<>	144:ef7eb2e8f9f7	5623	#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /!< Disable event on write. /
<>	144:ef7eb2e8f9f7	5624
<>	144:ef7eb2e8f9f7	5625	/* Bit 17 : Disable routing to PPI of COMPARE[1] event. */
<>	144:ef7eb2e8f9f7	5626	#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
<>	144:ef7eb2e8f9f7	5627	#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
<>	144:ef7eb2e8f9f7	5628	#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /!< Event disabled. /
<>	144:ef7eb2e8f9f7	5629	#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /!< Event enabled. /
<>	144:ef7eb2e8f9f7	5630	#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /!< Disable event on write. /
<>	144:ef7eb2e8f9f7	5631
<>	144:ef7eb2e8f9f7	5632	/* Bit 16 : Disable routing to PPI of COMPARE[0] event. */
<>	144:ef7eb2e8f9f7	5633	#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
<>	144:ef7eb2e8f9f7	5634	#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
<>	144:ef7eb2e8f9f7	5635	#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /!< Event disabled. /
<>	144:ef7eb2e8f9f7	5636	#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /!< Event enabled. /
<>	144:ef7eb2e8f9f7	5637	#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /!< Disable event on write. /
<>	144:ef7eb2e8f9f7	5638
<>	144:ef7eb2e8f9f7	5639	/* Bit 1 : Disable routing to PPI of OVRFLW event. */
<>	144:ef7eb2e8f9f7	5640	#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
<>	144:ef7eb2e8f9f7	5641	#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
<>	144:ef7eb2e8f9f7	5642	#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /!< Event disabled. /
<>	144:ef7eb2e8f9f7	5643	#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /!< Event enabled. /
<>	144:ef7eb2e8f9f7	5644	#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /!< Disable event on write. /
<>	144:ef7eb2e8f9f7	5645
<>	144:ef7eb2e8f9f7	5646	/* Bit 0 : Disable routing to PPI of TICK event. */
<>	144:ef7eb2e8f9f7	5647	#define RTC_EVTENCLR_TICK_Pos (0UL) /!< Position of TICK field. /
<>	144:ef7eb2e8f9f7	5648	#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /!< Bit mask of TICK field. /
<>	144:ef7eb2e8f9f7	5649	#define RTC_EVTENCLR_TICK_Disabled (0UL) /!< Event disabled. /
<>	144:ef7eb2e8f9f7	5650	#define RTC_EVTENCLR_TICK_Enabled (1UL) /!< Event enabled. /
<>	144:ef7eb2e8f9f7	5651	#define RTC_EVTENCLR_TICK_Clear (1UL) /!< Disable event on write. /
<>	144:ef7eb2e8f9f7	5652
<>	144:ef7eb2e8f9f7	5653	/* Register: RTC_COUNTER */
<>	144:ef7eb2e8f9f7	5654	/* Description: Current COUNTER value. */
<>	144:ef7eb2e8f9f7	5655
<>	144:ef7eb2e8f9f7	5656	/* Bits 23..0 : Counter value. */
<>	144:ef7eb2e8f9f7	5657	#define RTC_COUNTER_COUNTER_Pos (0UL) /!< Position of COUNTER field. /
<>	144:ef7eb2e8f9f7	5658	#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /!< Bit mask of COUNTER field. /
<>	144:ef7eb2e8f9f7	5659
<>	144:ef7eb2e8f9f7	5660	/* Register: RTC_PRESCALER */
<>	144:ef7eb2e8f9f7	5661	/* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */
<>	144:ef7eb2e8f9f7	5662
<>	144:ef7eb2e8f9f7	5663	/* Bits 11..0 : RTC PRESCALER value. */
<>	144:ef7eb2e8f9f7	5664	#define RTC_PRESCALER_PRESCALER_Pos (0UL) /!< Position of PRESCALER field. /
<>	144:ef7eb2e8f9f7	5665	#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /!< Bit mask of PRESCALER field. /
<>	144:ef7eb2e8f9f7	5666
<>	144:ef7eb2e8f9f7	5667	/* Register: RTC_CC */
<>	144:ef7eb2e8f9f7	5668	/* Description: Capture/compare registers. */
<>	144:ef7eb2e8f9f7	5669
<>	144:ef7eb2e8f9f7	5670	/* Bits 23..0 : Compare value. */
<>	144:ef7eb2e8f9f7	5671	#define RTC_CC_COMPARE_Pos (0UL) /!< Position of COMPARE field. /
<>	144:ef7eb2e8f9f7	5672	#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /!< Bit mask of COMPARE field. /
<>	144:ef7eb2e8f9f7	5673
<>	144:ef7eb2e8f9f7	5674	/* Register: RTC_POWER */
<>	144:ef7eb2e8f9f7	5675	/* Description: Peripheral power control. */
<>	144:ef7eb2e8f9f7	5676
<>	144:ef7eb2e8f9f7	5677	/* Bit 0 : Peripheral power control. */
<>	144:ef7eb2e8f9f7	5678	#define RTC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
<>	144:ef7eb2e8f9f7	5679	#define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
<>	144:ef7eb2e8f9f7	5680	#define RTC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
<>	144:ef7eb2e8f9f7	5681	#define RTC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
<>	144:ef7eb2e8f9f7	5682
<>	144:ef7eb2e8f9f7	5683
<>	144:ef7eb2e8f9f7	5684	/* Peripheral: SPI */
<>	144:ef7eb2e8f9f7	5685	/* Description: SPI master 0. */
<>	144:ef7eb2e8f9f7	5686
<>	144:ef7eb2e8f9f7	5687	/* Register: SPI_INTENSET */
<>	144:ef7eb2e8f9f7	5688	/* Description: Interrupt enable set register. */
<>	144:ef7eb2e8f9f7	5689
<>	144:ef7eb2e8f9f7	5690	/* Bit 2 : Enable interrupt on READY event. */
<>	144:ef7eb2e8f9f7	5691	#define SPI_INTENSET_READY_Pos (2UL) /!< Position of READY field. /
<>	144:ef7eb2e8f9f7	5692	#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /!< Bit mask of READY field. /
<>	144:ef7eb2e8f9f7	5693	#define SPI_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	5694	#define SPI_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	5695	#define SPI_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	5696
<>	144:ef7eb2e8f9f7	5697	/* Register: SPI_INTENCLR */
<>	144:ef7eb2e8f9f7	5698	/* Description: Interrupt enable clear register. */
<>	144:ef7eb2e8f9f7	5699
<>	144:ef7eb2e8f9f7	5700	/* Bit 2 : Disable interrupt on READY event. */
<>	144:ef7eb2e8f9f7	5701	#define SPI_INTENCLR_READY_Pos (2UL) /!< Position of READY field. /
<>	144:ef7eb2e8f9f7	5702	#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
<>	144:ef7eb2e8f9f7	5703	#define SPI_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	5704	#define SPI_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	5705	#define SPI_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	5706
<>	144:ef7eb2e8f9f7	5707	/* Register: SPI_ENABLE */
<>	144:ef7eb2e8f9f7	5708	/* Description: Enable SPI. */
<>	144:ef7eb2e8f9f7	5709
<>	144:ef7eb2e8f9f7	5710	/* Bits 2..0 : Enable or disable SPI. */
<>	144:ef7eb2e8f9f7	5711	#define SPI_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
<>	144:ef7eb2e8f9f7	5712	#define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
<>	144:ef7eb2e8f9f7	5713	#define SPI_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPI. /
<>	144:ef7eb2e8f9f7	5714	#define SPI_ENABLE_ENABLE_Enabled (0x01UL) /!< Enable SPI. /
<>	144:ef7eb2e8f9f7	5715
<>	144:ef7eb2e8f9f7	5716	/* Register: SPI_RXD */
<>	144:ef7eb2e8f9f7	5717	/* Description: RX data. */
<>	144:ef7eb2e8f9f7	5718
<>	144:ef7eb2e8f9f7	5719	/* Bits 7..0 : RX data from last transfer. */
<>	144:ef7eb2e8f9f7	5720	#define SPI_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
<>	144:ef7eb2e8f9f7	5721	#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /!< Bit mask of RXD field. /
<>	144:ef7eb2e8f9f7	5722
<>	144:ef7eb2e8f9f7	5723	/* Register: SPI_TXD */
<>	144:ef7eb2e8f9f7	5724	/* Description: TX data. */
<>	144:ef7eb2e8f9f7	5725
<>	144:ef7eb2e8f9f7	5726	/* Bits 7..0 : TX data for next transfer. */
<>	144:ef7eb2e8f9f7	5727	#define SPI_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
<>	144:ef7eb2e8f9f7	5728	#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /!< Bit mask of TXD field. /
<>	144:ef7eb2e8f9f7	5729
<>	144:ef7eb2e8f9f7	5730	/* Register: SPI_FREQUENCY */
<>	144:ef7eb2e8f9f7	5731	/* Description: SPI frequency */
<>	144:ef7eb2e8f9f7	5732
<>	144:ef7eb2e8f9f7	5733	/* Bits 31..0 : SPI data rate. */
<>	144:ef7eb2e8f9f7	5734	#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
<>	144:ef7eb2e8f9f7	5735	#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
<>	144:ef7eb2e8f9f7	5736	#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /!< 125kbps. /
<>	144:ef7eb2e8f9f7	5737	#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250kbps. /
<>	144:ef7eb2e8f9f7	5738	#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /!< 500kbps. /
<>	144:ef7eb2e8f9f7	5739	#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /!< 1Mbps. /
<>	144:ef7eb2e8f9f7	5740	#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /!< 2Mbps. /
<>	144:ef7eb2e8f9f7	5741	#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /!< 4Mbps. /
<>	144:ef7eb2e8f9f7	5742	#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /!< 8Mbps. /
<>	144:ef7eb2e8f9f7	5743
<>	144:ef7eb2e8f9f7	5744	/* Register: SPI_CONFIG */
<>	144:ef7eb2e8f9f7	5745	/* Description: Configuration register. */
<>	144:ef7eb2e8f9f7	5746
<>	144:ef7eb2e8f9f7	5747	/* Bit 2 : Serial clock (SCK) polarity. */
<>	144:ef7eb2e8f9f7	5748	#define SPI_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
<>	144:ef7eb2e8f9f7	5749	#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
<>	144:ef7eb2e8f9f7	5750	#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
<>	144:ef7eb2e8f9f7	5751	#define SPI_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
<>	144:ef7eb2e8f9f7	5752
<>	144:ef7eb2e8f9f7	5753	/* Bit 1 : Serial clock (SCK) phase. */
<>	144:ef7eb2e8f9f7	5754	#define SPI_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
<>	144:ef7eb2e8f9f7	5755	#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
<>	144:ef7eb2e8f9f7	5756	#define SPI_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
<>	144:ef7eb2e8f9f7	5757	#define SPI_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
<>	144:ef7eb2e8f9f7	5758
<>	144:ef7eb2e8f9f7	5759	/* Bit 0 : Bit order. */
<>	144:ef7eb2e8f9f7	5760	#define SPI_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
<>	144:ef7eb2e8f9f7	5761	#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
<>	144:ef7eb2e8f9f7	5762	#define SPI_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
<>	144:ef7eb2e8f9f7	5763	#define SPI_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
<>	144:ef7eb2e8f9f7	5764
<>	144:ef7eb2e8f9f7	5765	/* Register: SPI_POWER */
<>	144:ef7eb2e8f9f7	5766	/* Description: Peripheral power control. */
<>	144:ef7eb2e8f9f7	5767
<>	144:ef7eb2e8f9f7	5768	/* Bit 0 : Peripheral power control. */
<>	144:ef7eb2e8f9f7	5769	#define SPI_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
<>	144:ef7eb2e8f9f7	5770	#define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /!< Bit mask of POWER field. /
<>	144:ef7eb2e8f9f7	5771	#define SPI_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
<>	144:ef7eb2e8f9f7	5772	#define SPI_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
<>	144:ef7eb2e8f9f7	5773
<>	144:ef7eb2e8f9f7	5774
<>	144:ef7eb2e8f9f7	5775	/* Peripheral: SPIM */
<>	144:ef7eb2e8f9f7	5776	/* Description: SPI master with easyDMA 1. */
<>	144:ef7eb2e8f9f7	5777
<>	144:ef7eb2e8f9f7	5778	/* Register: SPIM_INTENSET */
<>	144:ef7eb2e8f9f7	5779	/* Description: Interrupt enable set register. */
<>	144:ef7eb2e8f9f7	5780
<>	144:ef7eb2e8f9f7	5781	/* Bit 19 : Enable interrupt on STARTED event. */
<>	144:ef7eb2e8f9f7	5782	#define SPIM_INTENSET_STARTED_Pos (19UL) /!< Position of STARTED field. /
<>	144:ef7eb2e8f9f7	5783	#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /!< Bit mask of STARTED field. /
<>	144:ef7eb2e8f9f7	5784	#define SPIM_INTENSET_STARTED_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	5785	#define SPIM_INTENSET_STARTED_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	5786	#define SPIM_INTENSET_STARTED_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	5787
<>	144:ef7eb2e8f9f7	5788	/* Bit 8 : Enable interrupt on ENDTX event. */
<>	144:ef7eb2e8f9f7	5789	#define SPIM_INTENSET_ENDTX_Pos (8UL) /!< Position of ENDTX field. /
<>	144:ef7eb2e8f9f7	5790	#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /!< Bit mask of ENDTX field. /
<>	144:ef7eb2e8f9f7	5791	#define SPIM_INTENSET_ENDTX_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	5792	#define SPIM_INTENSET_ENDTX_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	5793	#define SPIM_INTENSET_ENDTX_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	5794
<>	144:ef7eb2e8f9f7	5795	/* Bit 4 : Enable interrupt on ENDRX event. */
<>	144:ef7eb2e8f9f7	5796	#define SPIM_INTENSET_ENDRX_Pos (4UL) /!< Position of ENDRX field. /
<>	144:ef7eb2e8f9f7	5797	#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /!< Bit mask of ENDRX field. /
<>	144:ef7eb2e8f9f7	5798	#define SPIM_INTENSET_ENDRX_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	5799	#define SPIM_INTENSET_ENDRX_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	5800	#define SPIM_INTENSET_ENDRX_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	5801
<>	144:ef7eb2e8f9f7	5802	/* Bit 1 : Enable interrupt on STOPPED event. */
<>	144:ef7eb2e8f9f7	5803	#define SPIM_INTENSET_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
<>	144:ef7eb2e8f9f7	5804	#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /!< Bit mask of STOPPED field. /
<>	144:ef7eb2e8f9f7	5805	#define SPIM_INTENSET_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	5806	#define SPIM_INTENSET_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	5807	#define SPIM_INTENSET_STOPPED_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	5808
<>	144:ef7eb2e8f9f7	5809	/* Register: SPIM_INTENCLR */
<>	144:ef7eb2e8f9f7	5810	/* Description: Interrupt enable clear register. */
<>	144:ef7eb2e8f9f7	5811
<>	144:ef7eb2e8f9f7	5812	/* Bit 19 : Disable interrupt on STARTED event. */
<>	144:ef7eb2e8f9f7	5813	#define SPIM_INTENCLR_STARTED_Pos (19UL) /!< Position of STARTED field. /
<>	144:ef7eb2e8f9f7	5814	#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /!< Bit mask of STARTED field. /
<>	144:ef7eb2e8f9f7	5815	#define SPIM_INTENCLR_STARTED_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	5816	#define SPIM_INTENCLR_STARTED_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	5817	#define SPIM_INTENCLR_STARTED_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	5818
<>	144:ef7eb2e8f9f7	5819	/* Bit 8 : Disable interrupt on ENDTX event. */
<>	144:ef7eb2e8f9f7	5820	#define SPIM_INTENCLR_ENDTX_Pos (8UL) /!< Position of ENDTX field. /
<>	144:ef7eb2e8f9f7	5821	#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /!< Bit mask of ENDTX field. /
<>	144:ef7eb2e8f9f7	5822	#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	5823	#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	5824	#define SPIM_INTENCLR_ENDTX_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	5825
<>	144:ef7eb2e8f9f7	5826	/* Bit 4 : Disable interrupt on ENDRX event. */
<>	144:ef7eb2e8f9f7	5827	#define SPIM_INTENCLR_ENDRX_Pos (4UL) /!< Position of ENDRX field. /
<>	144:ef7eb2e8f9f7	5828	#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /!< Bit mask of ENDRX field. /
<>	144:ef7eb2e8f9f7	5829	#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	5830	#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	5831	#define SPIM_INTENCLR_ENDRX_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	5832
<>	144:ef7eb2e8f9f7	5833	/* Bit 1 : Disable interrupt on STOPPED event. */
<>	144:ef7eb2e8f9f7	5834	#define SPIM_INTENCLR_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
<>	144:ef7eb2e8f9f7	5835	#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /!< Bit mask of STOPPED field. /
<>	144:ef7eb2e8f9f7	5836	#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	5837	#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	5838	#define SPIM_INTENCLR_STOPPED_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	5839
<>	144:ef7eb2e8f9f7	5840	/* Register: SPIM_ENABLE */
<>	144:ef7eb2e8f9f7	5841	/* Description: Enable SPIM. */
<>	144:ef7eb2e8f9f7	5842
<>	144:ef7eb2e8f9f7	5843	/* Bits 3..0 : Enable or disable SPIM. */
<>	144:ef7eb2e8f9f7	5844	#define SPIM_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
<>	144:ef7eb2e8f9f7	5845	#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
<>	144:ef7eb2e8f9f7	5846	#define SPIM_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPIM. /
<>	144:ef7eb2e8f9f7	5847	#define SPIM_ENABLE_ENABLE_Enabled (0x07UL) /!< Enable SPIM. /
<>	144:ef7eb2e8f9f7	5848
<>	144:ef7eb2e8f9f7	5849	/* Register: SPIM_FREQUENCY */
<>	144:ef7eb2e8f9f7	5850	/* Description: SPI frequency. */
<>	144:ef7eb2e8f9f7	5851
<>	144:ef7eb2e8f9f7	5852	/* Bits 31..0 : SPI master data rate. */
<>	144:ef7eb2e8f9f7	5853	#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
<>	144:ef7eb2e8f9f7	5854	#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
<>	144:ef7eb2e8f9f7	5855	#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /!< 125 kbps. /
<>	144:ef7eb2e8f9f7	5856	#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250 kbps. /
<>	144:ef7eb2e8f9f7	5857	#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /!< 500 kbps. /
<>	144:ef7eb2e8f9f7	5858	#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /!< 1 Mbps. /
<>	144:ef7eb2e8f9f7	5859	#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /!< 2 Mbps. /
<>	144:ef7eb2e8f9f7	5860	#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /!< 4 Mbps. /
<>	144:ef7eb2e8f9f7	5861	#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /!< 8 Mbps. /
<>	144:ef7eb2e8f9f7	5862
<>	144:ef7eb2e8f9f7	5863	/* Register: SPIM_RXD_PTR */
<>	144:ef7eb2e8f9f7	5864	/* Description: Data pointer. */
<>	144:ef7eb2e8f9f7	5865
<>	144:ef7eb2e8f9f7	5866	/* Bits 31..0 : Data pointer. */
<>	144:ef7eb2e8f9f7	5867	#define SPIM_RXD_PTR_PTR_Pos (0UL) /!< Position of PTR field. /
<>	144:ef7eb2e8f9f7	5868	#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /!< Bit mask of PTR field. /
<>	144:ef7eb2e8f9f7	5869
<>	144:ef7eb2e8f9f7	5870	/* Register: SPIM_RXD_MAXCNT */
<>	144:ef7eb2e8f9f7	5871	/* Description: Maximum number of buffer bytes to receive. */
<>	144:ef7eb2e8f9f7	5872
<>	144:ef7eb2e8f9f7	5873	/* Bits 7..0 : Maximum number of buffer bytes to receive. */
<>	144:ef7eb2e8f9f7	5874	#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /!< Position of MAXCNT field. /
<>	144:ef7eb2e8f9f7	5875	#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /!< Bit mask of MAXCNT field. /
<>	144:ef7eb2e8f9f7	5876
<>	144:ef7eb2e8f9f7	5877	/* Register: SPIM_RXD_AMOUNT */
<>	144:ef7eb2e8f9f7	5878	/* Description: Number of bytes received in the last transaction. */
<>	144:ef7eb2e8f9f7	5879
<>	144:ef7eb2e8f9f7	5880	/* Bits 7..0 : Number of bytes received in the last transaction. */
<>	144:ef7eb2e8f9f7	5881	#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /!< Position of AMOUNT field. /
<>	144:ef7eb2e8f9f7	5882	#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /!< Bit mask of AMOUNT field. /
<>	144:ef7eb2e8f9f7	5883
<>	144:ef7eb2e8f9f7	5884	/* Register: SPIM_TXD_PTR */
<>	144:ef7eb2e8f9f7	5885	/* Description: Data pointer. */
<>	144:ef7eb2e8f9f7	5886
<>	144:ef7eb2e8f9f7	5887	/* Bits 31..0 : Data pointer. */
<>	144:ef7eb2e8f9f7	5888	#define SPIM_TXD_PTR_PTR_Pos (0UL) /!< Position of PTR field. /
<>	144:ef7eb2e8f9f7	5889	#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /!< Bit mask of PTR field. /
<>	144:ef7eb2e8f9f7	5890
<>	144:ef7eb2e8f9f7	5891	/* Register: SPIM_TXD_MAXCNT */
<>	144:ef7eb2e8f9f7	5892	/* Description: Maximum number of buffer bytes to send. */
<>	144:ef7eb2e8f9f7	5893
<>	144:ef7eb2e8f9f7	5894	/* Bits 7..0 : Maximum number of buffer bytes to send. */
<>	144:ef7eb2e8f9f7	5895	#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /!< Position of MAXCNT field. /
<>	144:ef7eb2e8f9f7	5896	#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /!< Bit mask of MAXCNT field. /
<>	144:ef7eb2e8f9f7	5897
<>	144:ef7eb2e8f9f7	5898	/* Register: SPIM_TXD_AMOUNT */
<>	144:ef7eb2e8f9f7	5899	/* Description: Number of bytes sent in the last transaction. */
<>	144:ef7eb2e8f9f7	5900
<>	144:ef7eb2e8f9f7	5901	/* Bits 7..0 : Number of bytes sent in the last transaction. */
<>	144:ef7eb2e8f9f7	5902	#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /!< Position of AMOUNT field. /
<>	144:ef7eb2e8f9f7	5903	#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /!< Bit mask of AMOUNT field. /
<>	144:ef7eb2e8f9f7	5904
<>	144:ef7eb2e8f9f7	5905	/* Register: SPIM_CONFIG */
<>	144:ef7eb2e8f9f7	5906	/* Description: Configuration register. */
<>	144:ef7eb2e8f9f7	5907
<>	144:ef7eb2e8f9f7	5908	/* Bit 2 : Serial clock (SCK) polarity. */
<>	144:ef7eb2e8f9f7	5909	#define SPIM_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
<>	144:ef7eb2e8f9f7	5910	#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
<>	144:ef7eb2e8f9f7	5911	#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
<>	144:ef7eb2e8f9f7	5912	#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
<>	144:ef7eb2e8f9f7	5913
<>	144:ef7eb2e8f9f7	5914	/* Bit 1 : Serial clock (SCK) phase. */
<>	144:ef7eb2e8f9f7	5915	#define SPIM_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
<>	144:ef7eb2e8f9f7	5916	#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
<>	144:ef7eb2e8f9f7	5917	#define SPIM_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
<>	144:ef7eb2e8f9f7	5918	#define SPIM_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
<>	144:ef7eb2e8f9f7	5919
<>	144:ef7eb2e8f9f7	5920	/* Bit 0 : Bit order. */
<>	144:ef7eb2e8f9f7	5921	#define SPIM_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
<>	144:ef7eb2e8f9f7	5922	#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
<>	144:ef7eb2e8f9f7	5923	#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
<>	144:ef7eb2e8f9f7	5924	#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
<>	144:ef7eb2e8f9f7	5925
<>	144:ef7eb2e8f9f7	5926	/* Register: SPIM_ORC */
<>	144:ef7eb2e8f9f7	5927	/* Description: Over-read character. */
<>	144:ef7eb2e8f9f7	5928
<>	144:ef7eb2e8f9f7	5929	/* Bits 7..0 : Over-read character. */
<>	144:ef7eb2e8f9f7	5930	#define SPIM_ORC_ORC_Pos (0UL) /!< Position of ORC field. /
<>	144:ef7eb2e8f9f7	5931	#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /!< Bit mask of ORC field. /
<>	144:ef7eb2e8f9f7	5932
<>	144:ef7eb2e8f9f7	5933	/* Register: SPIM_POWER */
<>	144:ef7eb2e8f9f7	5934	/* Description: Peripheral power control. */
<>	144:ef7eb2e8f9f7	5935
<>	144:ef7eb2e8f9f7	5936	/* Bit 0 : Peripheral power control. */
<>	144:ef7eb2e8f9f7	5937	#define SPIM_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
<>	144:ef7eb2e8f9f7	5938	#define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos) /!< Bit mask of POWER field. /
<>	144:ef7eb2e8f9f7	5939	#define SPIM_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
<>	144:ef7eb2e8f9f7	5940	#define SPIM_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
<>	144:ef7eb2e8f9f7	5941
<>	144:ef7eb2e8f9f7	5942
<>	144:ef7eb2e8f9f7	5943	/* Peripheral: SPIS */
<>	144:ef7eb2e8f9f7	5944	/* Description: SPI slave 1. */
<>	144:ef7eb2e8f9f7	5945
<>	144:ef7eb2e8f9f7	5946	/* Register: SPIS_SHORTS */
<>	144:ef7eb2e8f9f7	5947	/* Description: Shortcuts for SPIS. */
<>	144:ef7eb2e8f9f7	5948
<>	144:ef7eb2e8f9f7	5949	/* Bit 2 : Shortcut between END event and the ACQUIRE task. */
<>	144:ef7eb2e8f9f7	5950	#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /!< Position of END_ACQUIRE field. /
<>	144:ef7eb2e8f9f7	5951	#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /!< Bit mask of END_ACQUIRE field. /
<>	144:ef7eb2e8f9f7	5952	#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /!< Shortcut disabled. /
<>	144:ef7eb2e8f9f7	5953	#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /!< Shortcut enabled. /
<>	144:ef7eb2e8f9f7	5954
<>	144:ef7eb2e8f9f7	5955	/* Register: SPIS_INTENSET */
<>	144:ef7eb2e8f9f7	5956	/* Description: Interrupt enable set register. */
<>	144:ef7eb2e8f9f7	5957
<>	144:ef7eb2e8f9f7	5958	/* Bit 10 : Enable interrupt on ACQUIRED event. */
<>	144:ef7eb2e8f9f7	5959	#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /!< Position of ACQUIRED field. /
<>	144:ef7eb2e8f9f7	5960	#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /!< Bit mask of ACQUIRED field. /
<>	144:ef7eb2e8f9f7	5961	#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	5962	#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	5963	#define SPIS_INTENSET_ACQUIRED_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	5964
<>	144:ef7eb2e8f9f7	5965	/* Bit 4 : enable interrupt on ENDRX event. */
<>	144:ef7eb2e8f9f7	5966	#define SPIS_INTENSET_ENDRX_Pos (4UL) /!< Position of ENDRX field. /
<>	144:ef7eb2e8f9f7	5967	#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /!< Bit mask of ENDRX field. /
<>	144:ef7eb2e8f9f7	5968	#define SPIS_INTENSET_ENDRX_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	5969	#define SPIS_INTENSET_ENDRX_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	5970	#define SPIS_INTENSET_ENDRX_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	5971
<>	144:ef7eb2e8f9f7	5972	/* Bit 1 : Enable interrupt on END event. */
<>	144:ef7eb2e8f9f7	5973	#define SPIS_INTENSET_END_Pos (1UL) /!< Position of END field. /
<>	144:ef7eb2e8f9f7	5974	#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /!< Bit mask of END field. /
<>	144:ef7eb2e8f9f7	5975	#define SPIS_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	5976	#define SPIS_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	5977	#define SPIS_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	5978
<>	144:ef7eb2e8f9f7	5979	/* Register: SPIS_INTENCLR */
<>	144:ef7eb2e8f9f7	5980	/* Description: Interrupt enable clear register. */
<>	144:ef7eb2e8f9f7	5981
<>	144:ef7eb2e8f9f7	5982	/* Bit 10 : Disable interrupt on ACQUIRED event. */
<>	144:ef7eb2e8f9f7	5983	#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /!< Position of ACQUIRED field. /
<>	144:ef7eb2e8f9f7	5984	#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /!< Bit mask of ACQUIRED field. /
<>	144:ef7eb2e8f9f7	5985	#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	5986	#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	5987	#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	5988
<>	144:ef7eb2e8f9f7	5989	/* Bit 4 : Disable interrupt on ENDRX event. */
<>	144:ef7eb2e8f9f7	5990	#define SPIS_INTENCLR_ENDRX_Pos (4UL) /!< Position of ENDRX field. /
<>	144:ef7eb2e8f9f7	5991	#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /!< Bit mask of ENDRX field. /
<>	144:ef7eb2e8f9f7	5992	#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	5993	#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	5994	#define SPIS_INTENCLR_ENDRX_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	5995
<>	144:ef7eb2e8f9f7	5996	/* Bit 1 : Disable interrupt on END event. */
<>	144:ef7eb2e8f9f7	5997	#define SPIS_INTENCLR_END_Pos (1UL) /!< Position of END field. /
<>	144:ef7eb2e8f9f7	5998	#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /!< Bit mask of END field. /
<>	144:ef7eb2e8f9f7	5999	#define SPIS_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6000	#define SPIS_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6001	#define SPIS_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	6002
<>	144:ef7eb2e8f9f7	6003	/* Register: SPIS_SEMSTAT */
<>	144:ef7eb2e8f9f7	6004	/* Description: Semaphore status. */
<>	144:ef7eb2e8f9f7	6005
<>	144:ef7eb2e8f9f7	6006	/* Bits 1..0 : Semaphore status. */
<>	144:ef7eb2e8f9f7	6007	#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /!< Position of SEMSTAT field. /
<>	144:ef7eb2e8f9f7	6008	#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /!< Bit mask of SEMSTAT field. /
<>	144:ef7eb2e8f9f7	6009	#define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /!< Semaphore is free. /
<>	144:ef7eb2e8f9f7	6010	#define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /!< Semaphore is assigned to the CPU. /
<>	144:ef7eb2e8f9f7	6011	#define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /!< Semaphore is assigned to the SPIS. /
<>	144:ef7eb2e8f9f7	6012	#define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. /
<>	144:ef7eb2e8f9f7	6013
<>	144:ef7eb2e8f9f7	6014	/* Register: SPIS_STATUS */
<>	144:ef7eb2e8f9f7	6015	/* Description: Status from last transaction. */
<>	144:ef7eb2e8f9f7	6016
<>	144:ef7eb2e8f9f7	6017	/* Bit 1 : RX buffer overflow detected, and prevented. */
<>	144:ef7eb2e8f9f7	6018	#define SPIS_STATUS_OVERFLOW_Pos (1UL) /!< Position of OVERFLOW field. /
<>	144:ef7eb2e8f9f7	6019	#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /!< Bit mask of OVERFLOW field. /
<>	144:ef7eb2e8f9f7	6020	#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /!< Error not present. /
<>	144:ef7eb2e8f9f7	6021	#define SPIS_STATUS_OVERFLOW_Present (1UL) /!< Error present. /
<>	144:ef7eb2e8f9f7	6022	#define SPIS_STATUS_OVERFLOW_Clear (1UL) /!< Clear on write. /
<>	144:ef7eb2e8f9f7	6023
<>	144:ef7eb2e8f9f7	6024	/* Bit 0 : TX buffer overread detected, and prevented. */
<>	144:ef7eb2e8f9f7	6025	#define SPIS_STATUS_OVERREAD_Pos (0UL) /!< Position of OVERREAD field. /
<>	144:ef7eb2e8f9f7	6026	#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /!< Bit mask of OVERREAD field. /
<>	144:ef7eb2e8f9f7	6027	#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /!< Error not present. /
<>	144:ef7eb2e8f9f7	6028	#define SPIS_STATUS_OVERREAD_Present (1UL) /!< Error present. /
<>	144:ef7eb2e8f9f7	6029	#define SPIS_STATUS_OVERREAD_Clear (1UL) /!< Clear on write. /
<>	144:ef7eb2e8f9f7	6030
<>	144:ef7eb2e8f9f7	6031	/* Register: SPIS_ENABLE */
<>	144:ef7eb2e8f9f7	6032	/* Description: Enable SPIS. */
<>	144:ef7eb2e8f9f7	6033
<>	144:ef7eb2e8f9f7	6034	/* Bits 2..0 : Enable or disable SPIS. */
<>	144:ef7eb2e8f9f7	6035	#define SPIS_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
<>	144:ef7eb2e8f9f7	6036	#define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
<>	144:ef7eb2e8f9f7	6037	#define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPIS. /
<>	144:ef7eb2e8f9f7	6038	#define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /!< Enable SPIS. /
<>	144:ef7eb2e8f9f7	6039
<>	144:ef7eb2e8f9f7	6040	/* Register: SPIS_MAXRX */
<>	144:ef7eb2e8f9f7	6041	/* Description: Maximum number of bytes in the receive buffer. */
<>	144:ef7eb2e8f9f7	6042
<>	144:ef7eb2e8f9f7	6043	/* Bits 7..0 : Maximum number of bytes in the receive buffer. */
<>	144:ef7eb2e8f9f7	6044	#define SPIS_MAXRX_MAXRX_Pos (0UL) /!< Position of MAXRX field. /
<>	144:ef7eb2e8f9f7	6045	#define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /!< Bit mask of MAXRX field. /
<>	144:ef7eb2e8f9f7	6046
<>	144:ef7eb2e8f9f7	6047	/* Register: SPIS_AMOUNTRX */
<>	144:ef7eb2e8f9f7	6048	/* Description: Number of bytes received in last granted transaction. */
<>	144:ef7eb2e8f9f7	6049
<>	144:ef7eb2e8f9f7	6050	/* Bits 7..0 : Number of bytes received in last granted transaction. */
<>	144:ef7eb2e8f9f7	6051	#define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /!< Position of AMOUNTRX field. /
<>	144:ef7eb2e8f9f7	6052	#define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /!< Bit mask of AMOUNTRX field. /
<>	144:ef7eb2e8f9f7	6053
<>	144:ef7eb2e8f9f7	6054	/* Register: SPIS_MAXTX */
<>	144:ef7eb2e8f9f7	6055	/* Description: Maximum number of bytes in the transmit buffer. */
<>	144:ef7eb2e8f9f7	6056
<>	144:ef7eb2e8f9f7	6057	/* Bits 7..0 : Maximum number of bytes in the transmit buffer. */
<>	144:ef7eb2e8f9f7	6058	#define SPIS_MAXTX_MAXTX_Pos (0UL) /!< Position of MAXTX field. /
<>	144:ef7eb2e8f9f7	6059	#define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /!< Bit mask of MAXTX field. /
<>	144:ef7eb2e8f9f7	6060
<>	144:ef7eb2e8f9f7	6061	/* Register: SPIS_AMOUNTTX */
<>	144:ef7eb2e8f9f7	6062	/* Description: Number of bytes transmitted in last granted transaction. */
<>	144:ef7eb2e8f9f7	6063
<>	144:ef7eb2e8f9f7	6064	/* Bits 7..0 : Number of bytes transmitted in last granted transaction. */
<>	144:ef7eb2e8f9f7	6065	#define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /!< Position of AMOUNTTX field. /
<>	144:ef7eb2e8f9f7	6066	#define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /!< Bit mask of AMOUNTTX field. /
<>	144:ef7eb2e8f9f7	6067
<>	144:ef7eb2e8f9f7	6068	/* Register: SPIS_CONFIG */
<>	144:ef7eb2e8f9f7	6069	/* Description: Configuration register. */
<>	144:ef7eb2e8f9f7	6070
<>	144:ef7eb2e8f9f7	6071	/* Bit 2 : Serial clock (SCK) polarity. */
<>	144:ef7eb2e8f9f7	6072	#define SPIS_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
<>	144:ef7eb2e8f9f7	6073	#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
<>	144:ef7eb2e8f9f7	6074	#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
<>	144:ef7eb2e8f9f7	6075	#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
<>	144:ef7eb2e8f9f7	6076
<>	144:ef7eb2e8f9f7	6077	/* Bit 1 : Serial clock (SCK) phase. */
<>	144:ef7eb2e8f9f7	6078	#define SPIS_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
<>	144:ef7eb2e8f9f7	6079	#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
<>	144:ef7eb2e8f9f7	6080	#define SPIS_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
<>	144:ef7eb2e8f9f7	6081	#define SPIS_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
<>	144:ef7eb2e8f9f7	6082
<>	144:ef7eb2e8f9f7	6083	/* Bit 0 : Bit order. */
<>	144:ef7eb2e8f9f7	6084	#define SPIS_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
<>	144:ef7eb2e8f9f7	6085	#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
<>	144:ef7eb2e8f9f7	6086	#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
<>	144:ef7eb2e8f9f7	6087	#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
<>	144:ef7eb2e8f9f7	6088
<>	144:ef7eb2e8f9f7	6089	/* Register: SPIS_DEF */
<>	144:ef7eb2e8f9f7	6090	/* Description: Default character. */
<>	144:ef7eb2e8f9f7	6091
<>	144:ef7eb2e8f9f7	6092	/* Bits 7..0 : Default character. */
<>	144:ef7eb2e8f9f7	6093	#define SPIS_DEF_DEF_Pos (0UL) /!< Position of DEF field. /
<>	144:ef7eb2e8f9f7	6094	#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /!< Bit mask of DEF field. /
<>	144:ef7eb2e8f9f7	6095
<>	144:ef7eb2e8f9f7	6096	/* Register: SPIS_ORC */
<>	144:ef7eb2e8f9f7	6097	/* Description: Over-read character. */
<>	144:ef7eb2e8f9f7	6098
<>	144:ef7eb2e8f9f7	6099	/* Bits 7..0 : Over-read character. */
<>	144:ef7eb2e8f9f7	6100	#define SPIS_ORC_ORC_Pos (0UL) /!< Position of ORC field. /
<>	144:ef7eb2e8f9f7	6101	#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /!< Bit mask of ORC field. /
<>	144:ef7eb2e8f9f7	6102
<>	144:ef7eb2e8f9f7	6103	/* Register: SPIS_POWER */
<>	144:ef7eb2e8f9f7	6104	/* Description: Peripheral power control. */
<>	144:ef7eb2e8f9f7	6105
<>	144:ef7eb2e8f9f7	6106	/* Bit 0 : Peripheral power control. */
<>	144:ef7eb2e8f9f7	6107	#define SPIS_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
<>	144:ef7eb2e8f9f7	6108	#define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /!< Bit mask of POWER field. /
<>	144:ef7eb2e8f9f7	6109	#define SPIS_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
<>	144:ef7eb2e8f9f7	6110	#define SPIS_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
<>	144:ef7eb2e8f9f7	6111
<>	144:ef7eb2e8f9f7	6112
<>	144:ef7eb2e8f9f7	6113	/* Peripheral: TEMP */
<>	144:ef7eb2e8f9f7	6114	/* Description: Temperature Sensor. */
<>	144:ef7eb2e8f9f7	6115
<>	144:ef7eb2e8f9f7	6116	/* Register: TEMP_INTENSET */
<>	144:ef7eb2e8f9f7	6117	/* Description: Interrupt enable set register. */
<>	144:ef7eb2e8f9f7	6118
<>	144:ef7eb2e8f9f7	6119	/* Bit 0 : Enable interrupt on DATARDY event. */
<>	144:ef7eb2e8f9f7	6120	#define TEMP_INTENSET_DATARDY_Pos (0UL) /!< Position of DATARDY field. /
<>	144:ef7eb2e8f9f7	6121	#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /!< Bit mask of DATARDY field. /
<>	144:ef7eb2e8f9f7	6122	#define TEMP_INTENSET_DATARDY_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6123	#define TEMP_INTENSET_DATARDY_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6124	#define TEMP_INTENSET_DATARDY_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	6125
<>	144:ef7eb2e8f9f7	6126	/* Register: TEMP_INTENCLR */
<>	144:ef7eb2e8f9f7	6127	/* Description: Interrupt enable clear register. */
<>	144:ef7eb2e8f9f7	6128
<>	144:ef7eb2e8f9f7	6129	/* Bit 0 : Disable interrupt on DATARDY event. */
<>	144:ef7eb2e8f9f7	6130	#define TEMP_INTENCLR_DATARDY_Pos (0UL) /!< Position of DATARDY field. /
<>	144:ef7eb2e8f9f7	6131	#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /!< Bit mask of DATARDY field. /
<>	144:ef7eb2e8f9f7	6132	#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6133	#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6134	#define TEMP_INTENCLR_DATARDY_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	6135
<>	144:ef7eb2e8f9f7	6136	/* Register: TEMP_POWER */
<>	144:ef7eb2e8f9f7	6137	/* Description: Peripheral power control. */
<>	144:ef7eb2e8f9f7	6138
<>	144:ef7eb2e8f9f7	6139	/* Bit 0 : Peripheral power control. */
<>	144:ef7eb2e8f9f7	6140	#define TEMP_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
<>	144:ef7eb2e8f9f7	6141	#define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /!< Bit mask of POWER field. /
<>	144:ef7eb2e8f9f7	6142	#define TEMP_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
<>	144:ef7eb2e8f9f7	6143	#define TEMP_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
<>	144:ef7eb2e8f9f7	6144
<>	144:ef7eb2e8f9f7	6145
<>	144:ef7eb2e8f9f7	6146	/* Peripheral: TIMER */
<>	144:ef7eb2e8f9f7	6147	/* Description: Timer 0. */
<>	144:ef7eb2e8f9f7	6148
<>	144:ef7eb2e8f9f7	6149	/* Register: TIMER_SHORTS */
<>	144:ef7eb2e8f9f7	6150	/* Description: Shortcuts for Timer. */
<>	144:ef7eb2e8f9f7	6151
<>	144:ef7eb2e8f9f7	6152	/* Bit 11 : Shortcut between CC[3] event and the STOP task. */
<>	144:ef7eb2e8f9f7	6153	#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /!< Position of COMPARE3_STOP field. /
<>	144:ef7eb2e8f9f7	6154	#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /!< Bit mask of COMPARE3_STOP field. /
<>	144:ef7eb2e8f9f7	6155	#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /!< Shortcut disabled. /
<>	144:ef7eb2e8f9f7	6156	#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /!< Shortcut enabled. /
<>	144:ef7eb2e8f9f7	6157
<>	144:ef7eb2e8f9f7	6158	/* Bit 10 : Shortcut between CC[2] event and the STOP task. */
<>	144:ef7eb2e8f9f7	6159	#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /!< Position of COMPARE2_STOP field. /
<>	144:ef7eb2e8f9f7	6160	#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /!< Bit mask of COMPARE2_STOP field. /
<>	144:ef7eb2e8f9f7	6161	#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /!< Shortcut disabled. /
<>	144:ef7eb2e8f9f7	6162	#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /!< Shortcut enabled. /
<>	144:ef7eb2e8f9f7	6163
<>	144:ef7eb2e8f9f7	6164	/* Bit 9 : Shortcut between CC[1] event and the STOP task. */
<>	144:ef7eb2e8f9f7	6165	#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /!< Position of COMPARE1_STOP field. /
<>	144:ef7eb2e8f9f7	6166	#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /!< Bit mask of COMPARE1_STOP field. /
<>	144:ef7eb2e8f9f7	6167	#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /!< Shortcut disabled. /
<>	144:ef7eb2e8f9f7	6168	#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /!< Shortcut enabled. /
<>	144:ef7eb2e8f9f7	6169
<>	144:ef7eb2e8f9f7	6170	/* Bit 8 : Shortcut between CC[0] event and the STOP task. */
<>	144:ef7eb2e8f9f7	6171	#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /!< Position of COMPARE0_STOP field. /
<>	144:ef7eb2e8f9f7	6172	#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /!< Bit mask of COMPARE0_STOP field. /
<>	144:ef7eb2e8f9f7	6173	#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /!< Shortcut disabled. /
<>	144:ef7eb2e8f9f7	6174	#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /!< Shortcut enabled. /
<>	144:ef7eb2e8f9f7	6175
<>	144:ef7eb2e8f9f7	6176	/* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */
<>	144:ef7eb2e8f9f7	6177	#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /!< Position of COMPARE3_CLEAR field. /
<>	144:ef7eb2e8f9f7	6178	#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /!< Bit mask of COMPARE3_CLEAR field. /
<>	144:ef7eb2e8f9f7	6179	#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
<>	144:ef7eb2e8f9f7	6180	#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
<>	144:ef7eb2e8f9f7	6181
<>	144:ef7eb2e8f9f7	6182	/* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */
<>	144:ef7eb2e8f9f7	6183	#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /!< Position of COMPARE2_CLEAR field. /
<>	144:ef7eb2e8f9f7	6184	#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /!< Bit mask of COMPARE2_CLEAR field. /
<>	144:ef7eb2e8f9f7	6185	#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
<>	144:ef7eb2e8f9f7	6186	#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
<>	144:ef7eb2e8f9f7	6187
<>	144:ef7eb2e8f9f7	6188	/* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */
<>	144:ef7eb2e8f9f7	6189	#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /!< Position of COMPARE1_CLEAR field. /
<>	144:ef7eb2e8f9f7	6190	#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /!< Bit mask of COMPARE1_CLEAR field. /
<>	144:ef7eb2e8f9f7	6191	#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
<>	144:ef7eb2e8f9f7	6192	#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
<>	144:ef7eb2e8f9f7	6193
<>	144:ef7eb2e8f9f7	6194	/* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */
<>	144:ef7eb2e8f9f7	6195	#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /!< Position of COMPARE0_CLEAR field. /
<>	144:ef7eb2e8f9f7	6196	#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /!< Bit mask of COMPARE0_CLEAR field. /
<>	144:ef7eb2e8f9f7	6197	#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
<>	144:ef7eb2e8f9f7	6198	#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
<>	144:ef7eb2e8f9f7	6199
<>	144:ef7eb2e8f9f7	6200	/* Register: TIMER_INTENSET */
<>	144:ef7eb2e8f9f7	6201	/* Description: Interrupt enable set register. */
<>	144:ef7eb2e8f9f7	6202
<>	144:ef7eb2e8f9f7	6203	/* Bit 19 : Enable interrupt on COMPARE[3] */
<>	144:ef7eb2e8f9f7	6204	#define TIMER_INTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
<>	144:ef7eb2e8f9f7	6205	#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
<>	144:ef7eb2e8f9f7	6206	#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6207	#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6208	#define TIMER_INTENSET_COMPARE3_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	6209
<>	144:ef7eb2e8f9f7	6210	/* Bit 18 : Enable interrupt on COMPARE[2] */
<>	144:ef7eb2e8f9f7	6211	#define TIMER_INTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
<>	144:ef7eb2e8f9f7	6212	#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
<>	144:ef7eb2e8f9f7	6213	#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6214	#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6215	#define TIMER_INTENSET_COMPARE2_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	6216
<>	144:ef7eb2e8f9f7	6217	/* Bit 17 : Enable interrupt on COMPARE[1] */
<>	144:ef7eb2e8f9f7	6218	#define TIMER_INTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
<>	144:ef7eb2e8f9f7	6219	#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
<>	144:ef7eb2e8f9f7	6220	#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6221	#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6222	#define TIMER_INTENSET_COMPARE1_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	6223
<>	144:ef7eb2e8f9f7	6224	/* Bit 16 : Enable interrupt on COMPARE[0] */
<>	144:ef7eb2e8f9f7	6225	#define TIMER_INTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
<>	144:ef7eb2e8f9f7	6226	#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
<>	144:ef7eb2e8f9f7	6227	#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6228	#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6229	#define TIMER_INTENSET_COMPARE0_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	6230
<>	144:ef7eb2e8f9f7	6231	/* Register: TIMER_INTENCLR */
<>	144:ef7eb2e8f9f7	6232	/* Description: Interrupt enable clear register. */
<>	144:ef7eb2e8f9f7	6233
<>	144:ef7eb2e8f9f7	6234	/* Bit 19 : Disable interrupt on COMPARE[3] */
<>	144:ef7eb2e8f9f7	6235	#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
<>	144:ef7eb2e8f9f7	6236	#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
<>	144:ef7eb2e8f9f7	6237	#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6238	#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6239	#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	6240
<>	144:ef7eb2e8f9f7	6241	/* Bit 18 : Disable interrupt on COMPARE[2] */
<>	144:ef7eb2e8f9f7	6242	#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
<>	144:ef7eb2e8f9f7	6243	#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
<>	144:ef7eb2e8f9f7	6244	#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6245	#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6246	#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	6247
<>	144:ef7eb2e8f9f7	6248	/* Bit 17 : Disable interrupt on COMPARE[1] */
<>	144:ef7eb2e8f9f7	6249	#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
<>	144:ef7eb2e8f9f7	6250	#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
<>	144:ef7eb2e8f9f7	6251	#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6252	#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6253	#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	6254
<>	144:ef7eb2e8f9f7	6255	/* Bit 16 : Disable interrupt on COMPARE[0] */
<>	144:ef7eb2e8f9f7	6256	#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
<>	144:ef7eb2e8f9f7	6257	#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
<>	144:ef7eb2e8f9f7	6258	#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6259	#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6260	#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	6261
<>	144:ef7eb2e8f9f7	6262	/* Register: TIMER_MODE */
<>	144:ef7eb2e8f9f7	6263	/* Description: Timer Mode selection. */
<>	144:ef7eb2e8f9f7	6264
<>	144:ef7eb2e8f9f7	6265	/* Bit 0 : Select Normal or Counter mode. */
<>	144:ef7eb2e8f9f7	6266	#define TIMER_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
<>	144:ef7eb2e8f9f7	6267	#define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /!< Bit mask of MODE field. /
<>	144:ef7eb2e8f9f7	6268	#define TIMER_MODE_MODE_Timer (0UL) /!< Timer in Normal mode. /
<>	144:ef7eb2e8f9f7	6269	#define TIMER_MODE_MODE_Counter (1UL) /!< Timer in Counter mode. /
<>	144:ef7eb2e8f9f7	6270
<>	144:ef7eb2e8f9f7	6271	/* Register: TIMER_BITMODE */
<>	144:ef7eb2e8f9f7	6272	/* Description: Sets timer behaviour. */
<>	144:ef7eb2e8f9f7	6273
<>	144:ef7eb2e8f9f7	6274	/* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */
<>	144:ef7eb2e8f9f7	6275	#define TIMER_BITMODE_BITMODE_Pos (0UL) /!< Position of BITMODE field. /
<>	144:ef7eb2e8f9f7	6276	#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /!< Bit mask of BITMODE field. /
<>	144:ef7eb2e8f9f7	6277	#define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /!< 16-bit timer behaviour. /
<>	144:ef7eb2e8f9f7	6278	#define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /!< 8-bit timer behaviour. /
<>	144:ef7eb2e8f9f7	6279	#define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /!< 24-bit timer behaviour. /
<>	144:ef7eb2e8f9f7	6280	#define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /!< 32-bit timer behaviour. /
<>	144:ef7eb2e8f9f7	6281
<>	144:ef7eb2e8f9f7	6282	/* Register: TIMER_PRESCALER */
<>	144:ef7eb2e8f9f7	6283	/* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */
<>	144:ef7eb2e8f9f7	6284
<>	144:ef7eb2e8f9f7	6285	/* Bits 3..0 : Timer PRESCALER value. Max value is 9. */
<>	144:ef7eb2e8f9f7	6286	#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /!< Position of PRESCALER field. /
<>	144:ef7eb2e8f9f7	6287	#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /!< Bit mask of PRESCALER field. /
<>	144:ef7eb2e8f9f7	6288
<>	144:ef7eb2e8f9f7	6289	/* Register: TIMER_POWER */
<>	144:ef7eb2e8f9f7	6290	/* Description: Peripheral power control. */
<>	144:ef7eb2e8f9f7	6291
<>	144:ef7eb2e8f9f7	6292	/* Bit 0 : Peripheral power control. */
<>	144:ef7eb2e8f9f7	6293	#define TIMER_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
<>	144:ef7eb2e8f9f7	6294	#define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /!< Bit mask of POWER field. /
<>	144:ef7eb2e8f9f7	6295	#define TIMER_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
<>	144:ef7eb2e8f9f7	6296	#define TIMER_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
<>	144:ef7eb2e8f9f7	6297
<>	144:ef7eb2e8f9f7	6298
<>	144:ef7eb2e8f9f7	6299	/* Peripheral: TWI */
<>	144:ef7eb2e8f9f7	6300	/* Description: Two-wire interface master 0. */
<>	144:ef7eb2e8f9f7	6301
<>	144:ef7eb2e8f9f7	6302	/* Register: TWI_SHORTS */
<>	144:ef7eb2e8f9f7	6303	/* Description: Shortcuts for TWI. */
<>	144:ef7eb2e8f9f7	6304
<>	144:ef7eb2e8f9f7	6305	/* Bit 1 : Shortcut between BB event and the STOP task. */
<>	144:ef7eb2e8f9f7	6306	#define TWI_SHORTS_BB_STOP_Pos (1UL) /!< Position of BB_STOP field. /
<>	144:ef7eb2e8f9f7	6307	#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /!< Bit mask of BB_STOP field. /
<>	144:ef7eb2e8f9f7	6308	#define TWI_SHORTS_BB_STOP_Disabled (0UL) /!< Shortcut disabled. /
<>	144:ef7eb2e8f9f7	6309	#define TWI_SHORTS_BB_STOP_Enabled (1UL) /!< Shortcut enabled. /
<>	144:ef7eb2e8f9f7	6310
<>	144:ef7eb2e8f9f7	6311	/* Bit 0 : Shortcut between BB event and the SUSPEND task. */
<>	144:ef7eb2e8f9f7	6312	#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /!< Position of BB_SUSPEND field. /
<>	144:ef7eb2e8f9f7	6313	#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /!< Bit mask of BB_SUSPEND field. /
<>	144:ef7eb2e8f9f7	6314	#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /!< Shortcut disabled. /
<>	144:ef7eb2e8f9f7	6315	#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /!< Shortcut enabled. /
<>	144:ef7eb2e8f9f7	6316
<>	144:ef7eb2e8f9f7	6317	/* Register: TWI_INTENSET */
<>	144:ef7eb2e8f9f7	6318	/* Description: Interrupt enable set register. */
<>	144:ef7eb2e8f9f7	6319
<>	144:ef7eb2e8f9f7	6320	/* Bit 18 : Enable interrupt on SUSPENDED event. */
<>	144:ef7eb2e8f9f7	6321	#define TWI_INTENSET_SUSPENDED_Pos (18UL) /!< Position of SUSPENDED field. /
<>	144:ef7eb2e8f9f7	6322	#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /!< Bit mask of SUSPENDED field. /
<>	144:ef7eb2e8f9f7	6323	#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6324	#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6325	#define TWI_INTENSET_SUSPENDED_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	6326
<>	144:ef7eb2e8f9f7	6327	/* Bit 14 : Enable interrupt on BB event. */
<>	144:ef7eb2e8f9f7	6328	#define TWI_INTENSET_BB_Pos (14UL) /!< Position of BB field. /
<>	144:ef7eb2e8f9f7	6329	#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /!< Bit mask of BB field. /
<>	144:ef7eb2e8f9f7	6330	#define TWI_INTENSET_BB_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6331	#define TWI_INTENSET_BB_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6332	#define TWI_INTENSET_BB_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	6333
<>	144:ef7eb2e8f9f7	6334	/* Bit 9 : Enable interrupt on ERROR event. */
<>	144:ef7eb2e8f9f7	6335	#define TWI_INTENSET_ERROR_Pos (9UL) /!< Position of ERROR field. /
<>	144:ef7eb2e8f9f7	6336	#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
<>	144:ef7eb2e8f9f7	6337	#define TWI_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6338	#define TWI_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6339	#define TWI_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	6340
<>	144:ef7eb2e8f9f7	6341	/* Bit 7 : Enable interrupt on TXDSENT event. */
<>	144:ef7eb2e8f9f7	6342	#define TWI_INTENSET_TXDSENT_Pos (7UL) /!< Position of TXDSENT field. /
<>	144:ef7eb2e8f9f7	6343	#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /!< Bit mask of TXDSENT field. /
<>	144:ef7eb2e8f9f7	6344	#define TWI_INTENSET_TXDSENT_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6345	#define TWI_INTENSET_TXDSENT_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6346	#define TWI_INTENSET_TXDSENT_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	6347
<>	144:ef7eb2e8f9f7	6348	/* Bit 2 : Enable interrupt on READY event. */
<>	144:ef7eb2e8f9f7	6349	#define TWI_INTENSET_RXDREADY_Pos (2UL) /!< Position of RXDREADY field. /
<>	144:ef7eb2e8f9f7	6350	#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /!< Bit mask of RXDREADY field. /
<>	144:ef7eb2e8f9f7	6351	#define TWI_INTENSET_RXDREADY_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6352	#define TWI_INTENSET_RXDREADY_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6353	#define TWI_INTENSET_RXDREADY_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	6354
<>	144:ef7eb2e8f9f7	6355	/* Bit 1 : Enable interrupt on STOPPED event. */
<>	144:ef7eb2e8f9f7	6356	#define TWI_INTENSET_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
<>	144:ef7eb2e8f9f7	6357	#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /!< Bit mask of STOPPED field. /
<>	144:ef7eb2e8f9f7	6358	#define TWI_INTENSET_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6359	#define TWI_INTENSET_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6360	#define TWI_INTENSET_STOPPED_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	6361
<>	144:ef7eb2e8f9f7	6362	/* Register: TWI_INTENCLR */
<>	144:ef7eb2e8f9f7	6363	/* Description: Interrupt enable clear register. */
<>	144:ef7eb2e8f9f7	6364
<>	144:ef7eb2e8f9f7	6365	/* Bit 18 : Disable interrupt on SUSPENDED event. */
<>	144:ef7eb2e8f9f7	6366	#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /!< Position of SUSPENDED field. /
<>	144:ef7eb2e8f9f7	6367	#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /!< Bit mask of SUSPENDED field. /
<>	144:ef7eb2e8f9f7	6368	#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6369	#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6370	#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	6371
<>	144:ef7eb2e8f9f7	6372	/* Bit 14 : Disable interrupt on BB event. */
<>	144:ef7eb2e8f9f7	6373	#define TWI_INTENCLR_BB_Pos (14UL) /!< Position of BB field. /
<>	144:ef7eb2e8f9f7	6374	#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /!< Bit mask of BB field. /
<>	144:ef7eb2e8f9f7	6375	#define TWI_INTENCLR_BB_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6376	#define TWI_INTENCLR_BB_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6377	#define TWI_INTENCLR_BB_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	6378
<>	144:ef7eb2e8f9f7	6379	/* Bit 9 : Disable interrupt on ERROR event. */
<>	144:ef7eb2e8f9f7	6380	#define TWI_INTENCLR_ERROR_Pos (9UL) /!< Position of ERROR field. /
<>	144:ef7eb2e8f9f7	6381	#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
<>	144:ef7eb2e8f9f7	6382	#define TWI_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6383	#define TWI_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6384	#define TWI_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	6385
<>	144:ef7eb2e8f9f7	6386	/* Bit 7 : Disable interrupt on TXDSENT event. */
<>	144:ef7eb2e8f9f7	6387	#define TWI_INTENCLR_TXDSENT_Pos (7UL) /!< Position of TXDSENT field. /
<>	144:ef7eb2e8f9f7	6388	#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /!< Bit mask of TXDSENT field. /
<>	144:ef7eb2e8f9f7	6389	#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6390	#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6391	#define TWI_INTENCLR_TXDSENT_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	6392
<>	144:ef7eb2e8f9f7	6393	/* Bit 2 : Disable interrupt on RXDREADY event. */
<>	144:ef7eb2e8f9f7	6394	#define TWI_INTENCLR_RXDREADY_Pos (2UL) /!< Position of RXDREADY field. /
<>	144:ef7eb2e8f9f7	6395	#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /!< Bit mask of RXDREADY field. /
<>	144:ef7eb2e8f9f7	6396	#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6397	#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6398	#define TWI_INTENCLR_RXDREADY_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	6399
<>	144:ef7eb2e8f9f7	6400	/* Bit 1 : Disable interrupt on STOPPED event. */
<>	144:ef7eb2e8f9f7	6401	#define TWI_INTENCLR_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
<>	144:ef7eb2e8f9f7	6402	#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /!< Bit mask of STOPPED field. /
<>	144:ef7eb2e8f9f7	6403	#define TWI_INTENCLR_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6404	#define TWI_INTENCLR_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6405	#define TWI_INTENCLR_STOPPED_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	6406
<>	144:ef7eb2e8f9f7	6407	/* Register: TWI_ERRORSRC */
<>	144:ef7eb2e8f9f7	6408	/* Description: Two-wire error source. Write error field to 1 to clear error. */
<>	144:ef7eb2e8f9f7	6409
<>	144:ef7eb2e8f9f7	6410	/* Bit 2 : NACK received after sending a data byte. */
<>	144:ef7eb2e8f9f7	6411	#define TWI_ERRORSRC_DNACK_Pos (2UL) /!< Position of DNACK field. /
<>	144:ef7eb2e8f9f7	6412	#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /!< Bit mask of DNACK field. /
<>	144:ef7eb2e8f9f7	6413	#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /!< Error not present. /
<>	144:ef7eb2e8f9f7	6414	#define TWI_ERRORSRC_DNACK_Present (1UL) /!< Error present. /
<>	144:ef7eb2e8f9f7	6415	#define TWI_ERRORSRC_DNACK_Clear (1UL) /!< Clear error on write. /
<>	144:ef7eb2e8f9f7	6416
<>	144:ef7eb2e8f9f7	6417	/* Bit 1 : NACK received after sending the address. */
<>	144:ef7eb2e8f9f7	6418	#define TWI_ERRORSRC_ANACK_Pos (1UL) /!< Position of ANACK field. /
<>	144:ef7eb2e8f9f7	6419	#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /!< Bit mask of ANACK field. /
<>	144:ef7eb2e8f9f7	6420	#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /!< Error not present. /
<>	144:ef7eb2e8f9f7	6421	#define TWI_ERRORSRC_ANACK_Present (1UL) /!< Error present. /
<>	144:ef7eb2e8f9f7	6422	#define TWI_ERRORSRC_ANACK_Clear (1UL) /!< Clear error on write. /
<>	144:ef7eb2e8f9f7	6423
<>	144:ef7eb2e8f9f7	6424	/* Bit 0 : Byte received in RXD register before read of the last received byte (data loss). */
<>	144:ef7eb2e8f9f7	6425	#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /!< Position of OVERRUN field. /
<>	144:ef7eb2e8f9f7	6426	#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /!< Bit mask of OVERRUN field. /
<>	144:ef7eb2e8f9f7	6427	#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /!< Error not present. /
<>	144:ef7eb2e8f9f7	6428	#define TWI_ERRORSRC_OVERRUN_Present (1UL) /!< Error present. /
<>	144:ef7eb2e8f9f7	6429	#define TWI_ERRORSRC_OVERRUN_Clear (1UL) /!< Clear error on write. /
<>	144:ef7eb2e8f9f7	6430
<>	144:ef7eb2e8f9f7	6431	/* Register: TWI_ENABLE */
<>	144:ef7eb2e8f9f7	6432	/* Description: Enable two-wire master. */
<>	144:ef7eb2e8f9f7	6433
<>	144:ef7eb2e8f9f7	6434	/* Bits 2..0 : Enable or disable W2M */
<>	144:ef7eb2e8f9f7	6435	#define TWI_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
<>	144:ef7eb2e8f9f7	6436	#define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
<>	144:ef7eb2e8f9f7	6437	#define TWI_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled. /
<>	144:ef7eb2e8f9f7	6438	#define TWI_ENABLE_ENABLE_Enabled (0x05UL) /!< Enabled. /
<>	144:ef7eb2e8f9f7	6439
<>	144:ef7eb2e8f9f7	6440	/* Register: TWI_RXD */
<>	144:ef7eb2e8f9f7	6441	/* Description: RX data register. */
<>	144:ef7eb2e8f9f7	6442
<>	144:ef7eb2e8f9f7	6443	/* Bits 7..0 : RX data from last transfer. */
<>	144:ef7eb2e8f9f7	6444	#define TWI_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
<>	144:ef7eb2e8f9f7	6445	#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /!< Bit mask of RXD field. /
<>	144:ef7eb2e8f9f7	6446
<>	144:ef7eb2e8f9f7	6447	/* Register: TWI_TXD */
<>	144:ef7eb2e8f9f7	6448	/* Description: TX data register. */
<>	144:ef7eb2e8f9f7	6449
<>	144:ef7eb2e8f9f7	6450	/* Bits 7..0 : TX data for next transfer. */
<>	144:ef7eb2e8f9f7	6451	#define TWI_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
<>	144:ef7eb2e8f9f7	6452	#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /!< Bit mask of TXD field. /
<>	144:ef7eb2e8f9f7	6453
<>	144:ef7eb2e8f9f7	6454	/* Register: TWI_FREQUENCY */
<>	144:ef7eb2e8f9f7	6455	/* Description: Two-wire frequency. */
<>	144:ef7eb2e8f9f7	6456
<>	144:ef7eb2e8f9f7	6457	/* Bits 31..0 : Two-wire master clock frequency. */
<>	144:ef7eb2e8f9f7	6458	#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
<>	144:ef7eb2e8f9f7	6459	#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
<>	144:ef7eb2e8f9f7	6460	#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /!< 100 kbps. /
<>	144:ef7eb2e8f9f7	6461	#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250 kbps. /
<>	144:ef7eb2e8f9f7	6462	#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /!< 400 kbps. /
<>	144:ef7eb2e8f9f7	6463
<>	144:ef7eb2e8f9f7	6464	/* Register: TWI_ADDRESS */
<>	144:ef7eb2e8f9f7	6465	/* Description: Address used in the two-wire transfer. */
<>	144:ef7eb2e8f9f7	6466
<>	144:ef7eb2e8f9f7	6467	/* Bits 6..0 : Two-wire address. */
<>	144:ef7eb2e8f9f7	6468	#define TWI_ADDRESS_ADDRESS_Pos (0UL) /!< Position of ADDRESS field. /
<>	144:ef7eb2e8f9f7	6469	#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
<>	144:ef7eb2e8f9f7	6470
<>	144:ef7eb2e8f9f7	6471	/* Register: TWI_POWER */
<>	144:ef7eb2e8f9f7	6472	/* Description: Peripheral power control. */
<>	144:ef7eb2e8f9f7	6473
<>	144:ef7eb2e8f9f7	6474	/* Bit 0 : Peripheral power control. */
<>	144:ef7eb2e8f9f7	6475	#define TWI_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
<>	144:ef7eb2e8f9f7	6476	#define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /!< Bit mask of POWER field. /
<>	144:ef7eb2e8f9f7	6477	#define TWI_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
<>	144:ef7eb2e8f9f7	6478	#define TWI_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
<>	144:ef7eb2e8f9f7	6479
<>	144:ef7eb2e8f9f7	6480
<>	144:ef7eb2e8f9f7	6481	/* Peripheral: UART */
<>	144:ef7eb2e8f9f7	6482	/* Description: Universal Asynchronous Receiver/Transmitter. */
<>	144:ef7eb2e8f9f7	6483
<>	144:ef7eb2e8f9f7	6484	/* Register: UART_SHORTS */
<>	144:ef7eb2e8f9f7	6485	/* Description: Shortcuts for UART. */
<>	144:ef7eb2e8f9f7	6486
<>	144:ef7eb2e8f9f7	6487	/* Bit 4 : Shortcut between NCTS event and STOPRX task. */
<>	144:ef7eb2e8f9f7	6488	#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /!< Position of NCTS_STOPRX field. /
<>	144:ef7eb2e8f9f7	6489	#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /!< Bit mask of NCTS_STOPRX field. /
<>	144:ef7eb2e8f9f7	6490	#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /!< Shortcut disabled. /
<>	144:ef7eb2e8f9f7	6491	#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /!< Shortcut enabled. /
<>	144:ef7eb2e8f9f7	6492
<>	144:ef7eb2e8f9f7	6493	/* Bit 3 : Shortcut between CTS event and STARTRX task. */
<>	144:ef7eb2e8f9f7	6494	#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /!< Position of CTS_STARTRX field. /
<>	144:ef7eb2e8f9f7	6495	#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /!< Bit mask of CTS_STARTRX field. /
<>	144:ef7eb2e8f9f7	6496	#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /!< Shortcut disabled. /
<>	144:ef7eb2e8f9f7	6497	#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /!< Shortcut enabled. /
<>	144:ef7eb2e8f9f7	6498
<>	144:ef7eb2e8f9f7	6499	/* Register: UART_INTENSET */
<>	144:ef7eb2e8f9f7	6500	/* Description: Interrupt enable set register. */
<>	144:ef7eb2e8f9f7	6501
<>	144:ef7eb2e8f9f7	6502	/* Bit 17 : Enable interrupt on RXTO event. */
<>	144:ef7eb2e8f9f7	6503	#define UART_INTENSET_RXTO_Pos (17UL) /!< Position of RXTO field. /
<>	144:ef7eb2e8f9f7	6504	#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /!< Bit mask of RXTO field. /
<>	144:ef7eb2e8f9f7	6505	#define UART_INTENSET_RXTO_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6506	#define UART_INTENSET_RXTO_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6507	#define UART_INTENSET_RXTO_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	6508
<>	144:ef7eb2e8f9f7	6509	/* Bit 9 : Enable interrupt on ERROR event. */
<>	144:ef7eb2e8f9f7	6510	#define UART_INTENSET_ERROR_Pos (9UL) /!< Position of ERROR field. /
<>	144:ef7eb2e8f9f7	6511	#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
<>	144:ef7eb2e8f9f7	6512	#define UART_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6513	#define UART_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6514	#define UART_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	6515
<>	144:ef7eb2e8f9f7	6516	/* Bit 7 : Enable interrupt on TXRDY event. */
<>	144:ef7eb2e8f9f7	6517	#define UART_INTENSET_TXDRDY_Pos (7UL) /!< Position of TXDRDY field. /
<>	144:ef7eb2e8f9f7	6518	#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /!< Bit mask of TXDRDY field. /
<>	144:ef7eb2e8f9f7	6519	#define UART_INTENSET_TXDRDY_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6520	#define UART_INTENSET_TXDRDY_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6521	#define UART_INTENSET_TXDRDY_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	6522
<>	144:ef7eb2e8f9f7	6523	/* Bit 2 : Enable interrupt on RXRDY event. */
<>	144:ef7eb2e8f9f7	6524	#define UART_INTENSET_RXDRDY_Pos (2UL) /!< Position of RXDRDY field. /
<>	144:ef7eb2e8f9f7	6525	#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /!< Bit mask of RXDRDY field. /
<>	144:ef7eb2e8f9f7	6526	#define UART_INTENSET_RXDRDY_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6527	#define UART_INTENSET_RXDRDY_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6528	#define UART_INTENSET_RXDRDY_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	6529
<>	144:ef7eb2e8f9f7	6530	/* Bit 1 : Enable interrupt on NCTS event. */
<>	144:ef7eb2e8f9f7	6531	#define UART_INTENSET_NCTS_Pos (1UL) /!< Position of NCTS field. /
<>	144:ef7eb2e8f9f7	6532	#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /!< Bit mask of NCTS field. /
<>	144:ef7eb2e8f9f7	6533	#define UART_INTENSET_NCTS_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6534	#define UART_INTENSET_NCTS_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6535	#define UART_INTENSET_NCTS_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	6536
<>	144:ef7eb2e8f9f7	6537	/* Bit 0 : Enable interrupt on CTS event. */
<>	144:ef7eb2e8f9f7	6538	#define UART_INTENSET_CTS_Pos (0UL) /!< Position of CTS field. /
<>	144:ef7eb2e8f9f7	6539	#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /!< Bit mask of CTS field. /
<>	144:ef7eb2e8f9f7	6540	#define UART_INTENSET_CTS_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6541	#define UART_INTENSET_CTS_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6542	#define UART_INTENSET_CTS_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	6543
<>	144:ef7eb2e8f9f7	6544	/* Register: UART_INTENCLR */
<>	144:ef7eb2e8f9f7	6545	/* Description: Interrupt enable clear register. */
<>	144:ef7eb2e8f9f7	6546
<>	144:ef7eb2e8f9f7	6547	/* Bit 17 : Disable interrupt on RXTO event. */
<>	144:ef7eb2e8f9f7	6548	#define UART_INTENCLR_RXTO_Pos (17UL) /!< Position of RXTO field. /
<>	144:ef7eb2e8f9f7	6549	#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /!< Bit mask of RXTO field. /
<>	144:ef7eb2e8f9f7	6550	#define UART_INTENCLR_RXTO_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6551	#define UART_INTENCLR_RXTO_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6552	#define UART_INTENCLR_RXTO_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	6553
<>	144:ef7eb2e8f9f7	6554	/* Bit 9 : Disable interrupt on ERROR event. */
<>	144:ef7eb2e8f9f7	6555	#define UART_INTENCLR_ERROR_Pos (9UL) /!< Position of ERROR field. /
<>	144:ef7eb2e8f9f7	6556	#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
<>	144:ef7eb2e8f9f7	6557	#define UART_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6558	#define UART_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6559	#define UART_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	6560
<>	144:ef7eb2e8f9f7	6561	/* Bit 7 : Disable interrupt on TXRDY event. */
<>	144:ef7eb2e8f9f7	6562	#define UART_INTENCLR_TXDRDY_Pos (7UL) /!< Position of TXDRDY field. /
<>	144:ef7eb2e8f9f7	6563	#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /!< Bit mask of TXDRDY field. /
<>	144:ef7eb2e8f9f7	6564	#define UART_INTENCLR_TXDRDY_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6565	#define UART_INTENCLR_TXDRDY_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6566	#define UART_INTENCLR_TXDRDY_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	6567
<>	144:ef7eb2e8f9f7	6568	/* Bit 2 : Disable interrupt on RXRDY event. */
<>	144:ef7eb2e8f9f7	6569	#define UART_INTENCLR_RXDRDY_Pos (2UL) /!< Position of RXDRDY field. /
<>	144:ef7eb2e8f9f7	6570	#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /!< Bit mask of RXDRDY field. /
<>	144:ef7eb2e8f9f7	6571	#define UART_INTENCLR_RXDRDY_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6572	#define UART_INTENCLR_RXDRDY_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6573	#define UART_INTENCLR_RXDRDY_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	6574
<>	144:ef7eb2e8f9f7	6575	/* Bit 1 : Disable interrupt on NCTS event. */
<>	144:ef7eb2e8f9f7	6576	#define UART_INTENCLR_NCTS_Pos (1UL) /!< Position of NCTS field. /
<>	144:ef7eb2e8f9f7	6577	#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /!< Bit mask of NCTS field. /
<>	144:ef7eb2e8f9f7	6578	#define UART_INTENCLR_NCTS_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6579	#define UART_INTENCLR_NCTS_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6580	#define UART_INTENCLR_NCTS_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	6581
<>	144:ef7eb2e8f9f7	6582	/* Bit 0 : Disable interrupt on CTS event. */
<>	144:ef7eb2e8f9f7	6583	#define UART_INTENCLR_CTS_Pos (0UL) /!< Position of CTS field. /
<>	144:ef7eb2e8f9f7	6584	#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /!< Bit mask of CTS field. /
<>	144:ef7eb2e8f9f7	6585	#define UART_INTENCLR_CTS_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6586	#define UART_INTENCLR_CTS_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6587	#define UART_INTENCLR_CTS_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	6588
<>	144:ef7eb2e8f9f7	6589	/* Register: UART_ERRORSRC */
<>	144:ef7eb2e8f9f7	6590	/* Description: Error source. Write error field to 1 to clear error. */
<>	144:ef7eb2e8f9f7	6591
<>	144:ef7eb2e8f9f7	6592	/* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */
<>	144:ef7eb2e8f9f7	6593	#define UART_ERRORSRC_BREAK_Pos (3UL) /!< Position of BREAK field. /
<>	144:ef7eb2e8f9f7	6594	#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /!< Bit mask of BREAK field. /
<>	144:ef7eb2e8f9f7	6595	#define UART_ERRORSRC_BREAK_NotPresent (0UL) /!< Error not present. /
<>	144:ef7eb2e8f9f7	6596	#define UART_ERRORSRC_BREAK_Present (1UL) /!< Error present. /
<>	144:ef7eb2e8f9f7	6597	#define UART_ERRORSRC_BREAK_Clear (1UL) /!< Clear error on write. /
<>	144:ef7eb2e8f9f7	6598
<>	144:ef7eb2e8f9f7	6599	/* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */
<>	144:ef7eb2e8f9f7	6600	#define UART_ERRORSRC_FRAMING_Pos (2UL) /!< Position of FRAMING field. /
<>	144:ef7eb2e8f9f7	6601	#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /!< Bit mask of FRAMING field. /
<>	144:ef7eb2e8f9f7	6602	#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /!< Error not present. /
<>	144:ef7eb2e8f9f7	6603	#define UART_ERRORSRC_FRAMING_Present (1UL) /!< Error present. /
<>	144:ef7eb2e8f9f7	6604	#define UART_ERRORSRC_FRAMING_Clear (1UL) /!< Clear error on write. /
<>	144:ef7eb2e8f9f7	6605
<>	144:ef7eb2e8f9f7	6606	/* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */
<>	144:ef7eb2e8f9f7	6607	#define UART_ERRORSRC_PARITY_Pos (1UL) /!< Position of PARITY field. /
<>	144:ef7eb2e8f9f7	6608	#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /!< Bit mask of PARITY field. /
<>	144:ef7eb2e8f9f7	6609	#define UART_ERRORSRC_PARITY_NotPresent (0UL) /!< Error not present. /
<>	144:ef7eb2e8f9f7	6610	#define UART_ERRORSRC_PARITY_Present (1UL) /!< Error present. /
<>	144:ef7eb2e8f9f7	6611	#define UART_ERRORSRC_PARITY_Clear (1UL) /!< Clear error on write. /
<>	144:ef7eb2e8f9f7	6612
<>	144:ef7eb2e8f9f7	6613	/* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */
<>	144:ef7eb2e8f9f7	6614	#define UART_ERRORSRC_OVERRUN_Pos (0UL) /!< Position of OVERRUN field. /
<>	144:ef7eb2e8f9f7	6615	#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /!< Bit mask of OVERRUN field. /
<>	144:ef7eb2e8f9f7	6616	#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /!< Error not present. /
<>	144:ef7eb2e8f9f7	6617	#define UART_ERRORSRC_OVERRUN_Present (1UL) /!< Error present. /
<>	144:ef7eb2e8f9f7	6618	#define UART_ERRORSRC_OVERRUN_Clear (1UL) /!< Clear error on write. /
<>	144:ef7eb2e8f9f7	6619
<>	144:ef7eb2e8f9f7	6620	/* Register: UART_ENABLE */
<>	144:ef7eb2e8f9f7	6621	/* Description: Enable UART and acquire IOs. */
<>	144:ef7eb2e8f9f7	6622
<>	144:ef7eb2e8f9f7	6623	/* Bits 2..0 : Enable or disable UART and acquire IOs. */
<>	144:ef7eb2e8f9f7	6624	#define UART_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
<>	144:ef7eb2e8f9f7	6625	#define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
<>	144:ef7eb2e8f9f7	6626	#define UART_ENABLE_ENABLE_Disabled (0x00UL) /!< UART disabled. /
<>	144:ef7eb2e8f9f7	6627	#define UART_ENABLE_ENABLE_Enabled (0x04UL) /!< UART enabled. /
<>	144:ef7eb2e8f9f7	6628
<>	144:ef7eb2e8f9f7	6629	/* Register: UART_RXD */
<>	144:ef7eb2e8f9f7	6630	/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */
<>	144:ef7eb2e8f9f7	6631
<>	144:ef7eb2e8f9f7	6632	/* Bits 7..0 : RX data from previous transfer. Double buffered. */
<>	144:ef7eb2e8f9f7	6633	#define UART_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
<>	144:ef7eb2e8f9f7	6634	#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /!< Bit mask of RXD field. /
<>	144:ef7eb2e8f9f7	6635
<>	144:ef7eb2e8f9f7	6636	/* Register: UART_TXD */
<>	144:ef7eb2e8f9f7	6637	/* Description: TXD register. */
<>	144:ef7eb2e8f9f7	6638
<>	144:ef7eb2e8f9f7	6639	/* Bits 7..0 : TX data for transfer. */
<>	144:ef7eb2e8f9f7	6640	#define UART_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
<>	144:ef7eb2e8f9f7	6641	#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /!< Bit mask of TXD field. /
<>	144:ef7eb2e8f9f7	6642
<>	144:ef7eb2e8f9f7	6643	/* Register: UART_BAUDRATE */
<>	144:ef7eb2e8f9f7	6644	/* Description: UART Baudrate. */
<>	144:ef7eb2e8f9f7	6645
<>	144:ef7eb2e8f9f7	6646	/* Bits 31..0 : UART baudrate. */
<>	144:ef7eb2e8f9f7	6647	#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /!< Position of BAUDRATE field. /
<>	144:ef7eb2e8f9f7	6648	#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /!< Bit mask of BAUDRATE field. /
<>	144:ef7eb2e8f9f7	6649	#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /!< 1200 baud. /
<>	144:ef7eb2e8f9f7	6650	#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /!< 2400 baud. /
<>	144:ef7eb2e8f9f7	6651	#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /!< 4800 baud. /
<>	144:ef7eb2e8f9f7	6652	#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /!< 9600 baud. /
<>	144:ef7eb2e8f9f7	6653	#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /!< 14400 baud. /
<>	144:ef7eb2e8f9f7	6654	#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /!< 19200 baud. /
<>	144:ef7eb2e8f9f7	6655	#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /!< 28800 baud. /
<>	144:ef7eb2e8f9f7	6656	#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /!< 38400 baud. /
<>	144:ef7eb2e8f9f7	6657	#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /!< 57600 baud. /
<>	144:ef7eb2e8f9f7	6658	#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /!< 76800 baud. /
<>	144:ef7eb2e8f9f7	6659	#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /!< 115200 baud. /
<>	144:ef7eb2e8f9f7	6660	#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /!< 230400 baud. /
<>	144:ef7eb2e8f9f7	6661	#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /!< 250000 baud. /
<>	144:ef7eb2e8f9f7	6662	#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /!< 460800 baud. /
<>	144:ef7eb2e8f9f7	6663	#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /!< 921600 baud. /
<>	144:ef7eb2e8f9f7	6664	#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /!< 1M baud. /
<>	144:ef7eb2e8f9f7	6665
<>	144:ef7eb2e8f9f7	6666	/* Register: UART_CONFIG */
<>	144:ef7eb2e8f9f7	6667	/* Description: Configuration of parity and hardware flow control register. */
<>	144:ef7eb2e8f9f7	6668
<>	144:ef7eb2e8f9f7	6669	/* Bits 3..1 : Include parity bit. */
<>	144:ef7eb2e8f9f7	6670	#define UART_CONFIG_PARITY_Pos (1UL) /!< Position of PARITY field. /
<>	144:ef7eb2e8f9f7	6671	#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /!< Bit mask of PARITY field. /
<>	144:ef7eb2e8f9f7	6672	#define UART_CONFIG_PARITY_Excluded (0UL) /!< Parity bit excluded. /
<>	144:ef7eb2e8f9f7	6673	#define UART_CONFIG_PARITY_Included (7UL) /!< Parity bit included. /
<>	144:ef7eb2e8f9f7	6674
<>	144:ef7eb2e8f9f7	6675	/* Bit 0 : Hardware flow control. */
<>	144:ef7eb2e8f9f7	6676	#define UART_CONFIG_HWFC_Pos (0UL) /!< Position of HWFC field. /
<>	144:ef7eb2e8f9f7	6677	#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /!< Bit mask of HWFC field. /
<>	144:ef7eb2e8f9f7	6678	#define UART_CONFIG_HWFC_Disabled (0UL) /!< Hardware flow control disabled. /
<>	144:ef7eb2e8f9f7	6679	#define UART_CONFIG_HWFC_Enabled (1UL) /!< Hardware flow control enabled. /
<>	144:ef7eb2e8f9f7	6680
<>	144:ef7eb2e8f9f7	6681	/* Register: UART_POWER */
<>	144:ef7eb2e8f9f7	6682	/* Description: Peripheral power control. */
<>	144:ef7eb2e8f9f7	6683
<>	144:ef7eb2e8f9f7	6684	/* Bit 0 : Peripheral power control. */
<>	144:ef7eb2e8f9f7	6685	#define UART_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
<>	144:ef7eb2e8f9f7	6686	#define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /!< Bit mask of POWER field. /
<>	144:ef7eb2e8f9f7	6687	#define UART_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
<>	144:ef7eb2e8f9f7	6688	#define UART_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
<>	144:ef7eb2e8f9f7	6689
<>	144:ef7eb2e8f9f7	6690
<>	144:ef7eb2e8f9f7	6691	/* Peripheral: UICR */
<>	144:ef7eb2e8f9f7	6692	/* Description: User Information Configuration. */
<>	144:ef7eb2e8f9f7	6693
<>	144:ef7eb2e8f9f7	6694	/* Register: UICR_RBPCONF */
<>	144:ef7eb2e8f9f7	6695	/* Description: Readback protection configuration. */
<>	144:ef7eb2e8f9f7	6696
<>	144:ef7eb2e8f9f7	6697	/* Bits 15..8 : Readback protect all code in the device. */
<>	144:ef7eb2e8f9f7	6698	#define UICR_RBPCONF_PALL_Pos (8UL) /!< Position of PALL field. /
<>	144:ef7eb2e8f9f7	6699	#define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /!< Bit mask of PALL field. /
<>	144:ef7eb2e8f9f7	6700	#define UICR_RBPCONF_PALL_Enabled (0x00UL) /!< Enabled. /
<>	144:ef7eb2e8f9f7	6701	#define UICR_RBPCONF_PALL_Disabled (0xFFUL) /!< Disabled. /
<>	144:ef7eb2e8f9f7	6702
<>	144:ef7eb2e8f9f7	6703	/* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */
<>	144:ef7eb2e8f9f7	6704	#define UICR_RBPCONF_PR0_Pos (0UL) /!< Position of PR0 field. /
<>	144:ef7eb2e8f9f7	6705	#define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /!< Bit mask of PR0 field. /
<>	144:ef7eb2e8f9f7	6706	#define UICR_RBPCONF_PR0_Enabled (0x00UL) /!< Enabled. /
<>	144:ef7eb2e8f9f7	6707	#define UICR_RBPCONF_PR0_Disabled (0xFFUL) /!< Disabled. /
<>	144:ef7eb2e8f9f7	6708
<>	144:ef7eb2e8f9f7	6709	/* Register: UICR_XTALFREQ */
<>	144:ef7eb2e8f9f7	6710	/* Description: Reset value for CLOCK XTALFREQ register. */
<>	144:ef7eb2e8f9f7	6711
<>	144:ef7eb2e8f9f7	6712	/* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */
<>	144:ef7eb2e8f9f7	6713	#define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /!< Position of XTALFREQ field. /
<>	144:ef7eb2e8f9f7	6714	#define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /!< Bit mask of XTALFREQ field. /
<>	144:ef7eb2e8f9f7	6715	#define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /!< 32MHz Xtal is used. /
<>	144:ef7eb2e8f9f7	6716	#define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /!< 16MHz Xtal is used. /
<>	144:ef7eb2e8f9f7	6717
<>	144:ef7eb2e8f9f7	6718	/* Register: UICR_FWID */
<>	144:ef7eb2e8f9f7	6719	/* Description: Firmware ID. */
<>	144:ef7eb2e8f9f7	6720
<>	144:ef7eb2e8f9f7	6721	/* Bits 15..0 : Identification number for the firmware loaded into the chip. */
<>	144:ef7eb2e8f9f7	6722	#define UICR_FWID_FWID_Pos (0UL) /!< Position of FWID field. /
<>	144:ef7eb2e8f9f7	6723	#define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /!< Bit mask of FWID field. /
<>	144:ef7eb2e8f9f7	6724
<>	144:ef7eb2e8f9f7	6725
<>	144:ef7eb2e8f9f7	6726	/* Peripheral: WDT */
<>	144:ef7eb2e8f9f7	6727	/* Description: Watchdog Timer. */
<>	144:ef7eb2e8f9f7	6728
<>	144:ef7eb2e8f9f7	6729	/* Register: WDT_INTENSET */
<>	144:ef7eb2e8f9f7	6730	/* Description: Interrupt enable set register. */
<>	144:ef7eb2e8f9f7	6731
<>	144:ef7eb2e8f9f7	6732	/* Bit 0 : Enable interrupt on TIMEOUT event. */
<>	144:ef7eb2e8f9f7	6733	#define WDT_INTENSET_TIMEOUT_Pos (0UL) /!< Position of TIMEOUT field. /
<>	144:ef7eb2e8f9f7	6734	#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /!< Bit mask of TIMEOUT field. /
<>	144:ef7eb2e8f9f7	6735	#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6736	#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6737	#define WDT_INTENSET_TIMEOUT_Set (1UL) /!< Enable interrupt on write. /
<>	144:ef7eb2e8f9f7	6738
<>	144:ef7eb2e8f9f7	6739	/* Register: WDT_INTENCLR */
<>	144:ef7eb2e8f9f7	6740	/* Description: Interrupt enable clear register. */
<>	144:ef7eb2e8f9f7	6741
<>	144:ef7eb2e8f9f7	6742	/* Bit 0 : Disable interrupt on TIMEOUT event. */
<>	144:ef7eb2e8f9f7	6743	#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /!< Position of TIMEOUT field. /
<>	144:ef7eb2e8f9f7	6744	#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /!< Bit mask of TIMEOUT field. /
<>	144:ef7eb2e8f9f7	6745	#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /!< Interrupt disabled. /
<>	144:ef7eb2e8f9f7	6746	#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /!< Interrupt enabled. /
<>	144:ef7eb2e8f9f7	6747	#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /!< Disable interrupt on write. /
<>	144:ef7eb2e8f9f7	6748
<>	144:ef7eb2e8f9f7	6749	/* Register: WDT_RUNSTATUS */
<>	144:ef7eb2e8f9f7	6750	/* Description: Watchdog running status. */
<>	144:ef7eb2e8f9f7	6751
<>	144:ef7eb2e8f9f7	6752	/* Bit 0 : Watchdog running status. */
<>	144:ef7eb2e8f9f7	6753	#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /!< Position of RUNSTATUS field. /
<>	144:ef7eb2e8f9f7	6754	#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /!< Bit mask of RUNSTATUS field. /
<>	144:ef7eb2e8f9f7	6755	#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /!< Watchdog timer is not running. /
<>	144:ef7eb2e8f9f7	6756	#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /!< Watchdog timer is running. /
<>	144:ef7eb2e8f9f7	6757
<>	144:ef7eb2e8f9f7	6758	/* Register: WDT_REQSTATUS */
<>	144:ef7eb2e8f9f7	6759	/* Description: Request status. */
<>	144:ef7eb2e8f9f7	6760
<>	144:ef7eb2e8f9f7	6761	/* Bit 7 : Request status for RR[7]. */
<>	144:ef7eb2e8f9f7	6762	#define WDT_REQSTATUS_RR7_Pos (7UL) /!< Position of RR7 field. /
<>	144:ef7eb2e8f9f7	6763	#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /!< Bit mask of RR7 field. /
<>	144:ef7eb2e8f9f7	6764	#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /!< RR[7] register is not enabled or has already requested reload. /
<>	144:ef7eb2e8f9f7	6765	#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /!< RR[7] register is enabled and has not jet requested. /
<>	144:ef7eb2e8f9f7	6766
<>	144:ef7eb2e8f9f7	6767	/* Bit 6 : Request status for RR[6]. */
<>	144:ef7eb2e8f9f7	6768	#define WDT_REQSTATUS_RR6_Pos (6UL) /!< Position of RR6 field. /
<>	144:ef7eb2e8f9f7	6769	#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /!< Bit mask of RR6 field. /
<>	144:ef7eb2e8f9f7	6770	#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /!< RR[6] register is not enabled or has already requested reload. /
<>	144:ef7eb2e8f9f7	6771	#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /!< RR[6] register is enabled and has not jet requested. /
<>	144:ef7eb2e8f9f7	6772
<>	144:ef7eb2e8f9f7	6773	/* Bit 5 : Request status for RR[5]. */
<>	144:ef7eb2e8f9f7	6774	#define WDT_REQSTATUS_RR5_Pos (5UL) /!< Position of RR5 field. /
<>	144:ef7eb2e8f9f7	6775	#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /!< Bit mask of RR5 field. /
<>	144:ef7eb2e8f9f7	6776	#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /!< RR[5] register is not enabled or has already requested reload. /
<>	144:ef7eb2e8f9f7	6777	#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /!< RR[5] register is enabled and has not jet requested. /
<>	144:ef7eb2e8f9f7	6778
<>	144:ef7eb2e8f9f7	6779	/* Bit 4 : Request status for RR[4]. */
<>	144:ef7eb2e8f9f7	6780	#define WDT_REQSTATUS_RR4_Pos (4UL) /!< Position of RR4 field. /
<>	144:ef7eb2e8f9f7	6781	#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /!< Bit mask of RR4 field. /
<>	144:ef7eb2e8f9f7	6782	#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /!< RR[4] register is not enabled or has already requested reload. /
<>	144:ef7eb2e8f9f7	6783	#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /!< RR[4] register is enabled and has not jet requested. /
<>	144:ef7eb2e8f9f7	6784
<>	144:ef7eb2e8f9f7	6785	/* Bit 3 : Request status for RR[3]. */
<>	144:ef7eb2e8f9f7	6786	#define WDT_REQSTATUS_RR3_Pos (3UL) /!< Position of RR3 field. /
<>	144:ef7eb2e8f9f7	6787	#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /!< Bit mask of RR3 field. /
<>	144:ef7eb2e8f9f7	6788	#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /!< RR[3] register is not enabled or has already requested reload. /
<>	144:ef7eb2e8f9f7	6789	#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /!< RR[3] register is enabled and has not jet requested. /
<>	144:ef7eb2e8f9f7	6790
<>	144:ef7eb2e8f9f7	6791	/* Bit 2 : Request status for RR[2]. */
<>	144:ef7eb2e8f9f7	6792	#define WDT_REQSTATUS_RR2_Pos (2UL) /!< Position of RR2 field. /
<>	144:ef7eb2e8f9f7	6793	#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /!< Bit mask of RR2 field. /
<>	144:ef7eb2e8f9f7	6794	#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /!< RR[2] register is not enabled or has already requested reload. /
<>	144:ef7eb2e8f9f7	6795	#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /!< RR[2] register is enabled and has not jet requested. /
<>	144:ef7eb2e8f9f7	6796
<>	144:ef7eb2e8f9f7	6797	/* Bit 1 : Request status for RR[1]. */
<>	144:ef7eb2e8f9f7	6798	#define WDT_REQSTATUS_RR1_Pos (1UL) /!< Position of RR1 field. /
<>	144:ef7eb2e8f9f7	6799	#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /!< Bit mask of RR1 field. /
<>	144:ef7eb2e8f9f7	6800	#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /!< RR[1] register is not enabled or has already requested reload. /
<>	144:ef7eb2e8f9f7	6801	#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /!< RR[1] register is enabled and has not jet requested. /
<>	144:ef7eb2e8f9f7	6802
<>	144:ef7eb2e8f9f7	6803	/* Bit 0 : Request status for RR[0]. */
<>	144:ef7eb2e8f9f7	6804	#define WDT_REQSTATUS_RR0_Pos (0UL) /!< Position of RR0 field. /
<>	144:ef7eb2e8f9f7	6805	#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /!< Bit mask of RR0 field. /
<>	144:ef7eb2e8f9f7	6806	#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /!< RR[0] register is not enabled or has already requested reload. /
<>	144:ef7eb2e8f9f7	6807	#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /!< RR[0] register is enabled and has not jet requested. /
<>	144:ef7eb2e8f9f7	6808
<>	144:ef7eb2e8f9f7	6809	/* Register: WDT_RREN */
<>	144:ef7eb2e8f9f7	6810	/* Description: Reload request enable. */
<>	144:ef7eb2e8f9f7	6811
<>	144:ef7eb2e8f9f7	6812	/* Bit 7 : Enable or disable RR[7] register. */
<>	144:ef7eb2e8f9f7	6813	#define WDT_RREN_RR7_Pos (7UL) /!< Position of RR7 field. /
<>	144:ef7eb2e8f9f7	6814	#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /!< Bit mask of RR7 field. /
<>	144:ef7eb2e8f9f7	6815	#define WDT_RREN_RR7_Disabled (0UL) /!< RR[7] register is disabled. /
<>	144:ef7eb2e8f9f7	6816	#define WDT_RREN_RR7_Enabled (1UL) /!< RR[7] register is enabled. /
<>	144:ef7eb2e8f9f7	6817
<>	144:ef7eb2e8f9f7	6818	/* Bit 6 : Enable or disable RR[6] register. */
<>	144:ef7eb2e8f9f7	6819	#define WDT_RREN_RR6_Pos (6UL) /!< Position of RR6 field. /
<>	144:ef7eb2e8f9f7	6820	#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /!< Bit mask of RR6 field. /
<>	144:ef7eb2e8f9f7	6821	#define WDT_RREN_RR6_Disabled (0UL) /!< RR[6] register is disabled. /
<>	144:ef7eb2e8f9f7	6822	#define WDT_RREN_RR6_Enabled (1UL) /!< RR[6] register is enabled. /
<>	144:ef7eb2e8f9f7	6823
<>	144:ef7eb2e8f9f7	6824	/* Bit 5 : Enable or disable RR[5] register. */
<>	144:ef7eb2e8f9f7	6825	#define WDT_RREN_RR5_Pos (5UL) /!< Position of RR5 field. /
<>	144:ef7eb2e8f9f7	6826	#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /!< Bit mask of RR5 field. /
<>	144:ef7eb2e8f9f7	6827	#define WDT_RREN_RR5_Disabled (0UL) /!< RR[5] register is disabled. /
<>	144:ef7eb2e8f9f7	6828	#define WDT_RREN_RR5_Enabled (1UL) /!< RR[5] register is enabled. /
<>	144:ef7eb2e8f9f7	6829
<>	144:ef7eb2e8f9f7	6830	/* Bit 4 : Enable or disable RR[4] register. */
<>	144:ef7eb2e8f9f7	6831	#define WDT_RREN_RR4_Pos (4UL) /!< Position of RR4 field. /
<>	144:ef7eb2e8f9f7	6832	#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /!< Bit mask of RR4 field. /
<>	144:ef7eb2e8f9f7	6833	#define WDT_RREN_RR4_Disabled (0UL) /!< RR[4] register is disabled. /
<>	144:ef7eb2e8f9f7	6834	#define WDT_RREN_RR4_Enabled (1UL) /!< RR[4] register is enabled. /
<>	144:ef7eb2e8f9f7	6835
<>	144:ef7eb2e8f9f7	6836	/* Bit 3 : Enable or disable RR[3] register. */
<>	144:ef7eb2e8f9f7	6837	#define WDT_RREN_RR3_Pos (3UL) /!< Position of RR3 field. /
<>	144:ef7eb2e8f9f7	6838	#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /!< Bit mask of RR3 field. /
<>	144:ef7eb2e8f9f7	6839	#define WDT_RREN_RR3_Disabled (0UL) /!< RR[3] register is disabled. /
<>	144:ef7eb2e8f9f7	6840	#define WDT_RREN_RR3_Enabled (1UL) /!< RR[3] register is enabled. /
<>	144:ef7eb2e8f9f7	6841
<>	144:ef7eb2e8f9f7	6842	/* Bit 2 : Enable or disable RR[2] register. */
<>	144:ef7eb2e8f9f7	6843	#define WDT_RREN_RR2_Pos (2UL) /!< Position of RR2 field. /
<>	144:ef7eb2e8f9f7	6844	#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /!< Bit mask of RR2 field. /
<>	144:ef7eb2e8f9f7	6845	#define WDT_RREN_RR2_Disabled (0UL) /!< RR[2] register is disabled. /
<>	144:ef7eb2e8f9f7	6846	#define WDT_RREN_RR2_Enabled (1UL) /!< RR[2] register is enabled. /
<>	144:ef7eb2e8f9f7	6847
<>	144:ef7eb2e8f9f7	6848	/* Bit 1 : Enable or disable RR[1] register. */
<>	144:ef7eb2e8f9f7	6849	#define WDT_RREN_RR1_Pos (1UL) /!< Position of RR1 field. /
<>	144:ef7eb2e8f9f7	6850	#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /!< Bit mask of RR1 field. /
<>	144:ef7eb2e8f9f7	6851	#define WDT_RREN_RR1_Disabled (0UL) /!< RR[1] register is disabled. /
<>	144:ef7eb2e8f9f7	6852	#define WDT_RREN_RR1_Enabled (1UL) /!< RR[1] register is enabled. /
<>	144:ef7eb2e8f9f7	6853
<>	144:ef7eb2e8f9f7	6854	/* Bit 0 : Enable or disable RR[0] register. */
<>	144:ef7eb2e8f9f7	6855	#define WDT_RREN_RR0_Pos (0UL) /!< Position of RR0 field. /
<>	144:ef7eb2e8f9f7	6856	#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /!< Bit mask of RR0 field. /
<>	144:ef7eb2e8f9f7	6857	#define WDT_RREN_RR0_Disabled (0UL) /!< RR[0] register is disabled. /
<>	144:ef7eb2e8f9f7	6858	#define WDT_RREN_RR0_Enabled (1UL) /!< RR[0] register is enabled. /
<>	144:ef7eb2e8f9f7	6859
<>	144:ef7eb2e8f9f7	6860	/* Register: WDT_CONFIG */
<>	144:ef7eb2e8f9f7	6861	/* Description: Configuration register. */
<>	144:ef7eb2e8f9f7	6862
<>	144:ef7eb2e8f9f7	6863	/* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */
<>	144:ef7eb2e8f9f7	6864	#define WDT_CONFIG_HALT_Pos (3UL) /!< Position of HALT field. /
<>	144:ef7eb2e8f9f7	6865	#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /!< Bit mask of HALT field. /
<>	144:ef7eb2e8f9f7	6866	#define WDT_CONFIG_HALT_Pause (0UL) /!< Pause watchdog while the CPU is halted by the debugger. /
<>	144:ef7eb2e8f9f7	6867	#define WDT_CONFIG_HALT_Run (1UL) /!< Do not pause watchdog while the CPU is halted by the debugger. /
<>	144:ef7eb2e8f9f7	6868
<>	144:ef7eb2e8f9f7	6869	/* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */
<>	144:ef7eb2e8f9f7	6870	#define WDT_CONFIG_SLEEP_Pos (0UL) /!< Position of SLEEP field. /
<>	144:ef7eb2e8f9f7	6871	#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /!< Bit mask of SLEEP field. /
<>	144:ef7eb2e8f9f7	6872	#define WDT_CONFIG_SLEEP_Pause (0UL) /!< Pause watchdog while the CPU is asleep. /
<>	144:ef7eb2e8f9f7	6873	#define WDT_CONFIG_SLEEP_Run (1UL) /!< Do not pause watchdog while the CPU is asleep. /
<>	144:ef7eb2e8f9f7	6874
<>	144:ef7eb2e8f9f7	6875	/* Register: WDT_RR */
<>	144:ef7eb2e8f9f7	6876	/* Description: Reload requests registers. */
<>	144:ef7eb2e8f9f7	6877
<>	144:ef7eb2e8f9f7	6878	/* Bits 31..0 : Reload register. */
<>	144:ef7eb2e8f9f7	6879	#define WDT_RR_RR_Pos (0UL) /!< Position of RR field. /
<>	144:ef7eb2e8f9f7	6880	#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /!< Bit mask of RR field. /
<>	144:ef7eb2e8f9f7	6881	#define WDT_RR_RR_Reload (0x6E524635UL) /!< Value to request a reload of the watchdog timer. /
<>	144:ef7eb2e8f9f7	6882
<>	144:ef7eb2e8f9f7	6883	/* Register: WDT_POWER */
<>	144:ef7eb2e8f9f7	6884	/* Description: Peripheral power control. */
<>	144:ef7eb2e8f9f7	6885
<>	144:ef7eb2e8f9f7	6886	/* Bit 0 : Peripheral power control. */
<>	144:ef7eb2e8f9f7	6887	#define WDT_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
<>	144:ef7eb2e8f9f7	6888	#define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /!< Bit mask of POWER field. /
<>	144:ef7eb2e8f9f7	6889	#define WDT_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
<>	144:ef7eb2e8f9f7	6890	#define WDT_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
<>	144:ef7eb2e8f9f7	6891
<>	144:ef7eb2e8f9f7	6892
<>	144:ef7eb2e8f9f7	6893	/lint --flb "Leave library region" /
<>	144:ef7eb2e8f9f7	6894	#endif

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Type:	Library
Created:	11 Apr 2017
Imports:	0
Forks:	1
Commits:	164
Dependents:	1
Dependencies:	0
Followers:	1

targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/nrf51_bitfields.h@163:1d4c9d0af1e9, 2017-04-11 (annotated)

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