Claudio Citterio / RomeLib

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EncoderCounter.cpp@0:df3d4b033d11, 2019-02-27 (annotated)

Committer:
cittecla
Date:
Wed Feb 27 15:14:27 2019 +0000
Revision:
0:df3d4b033d11
P1 finished

Who changed what in which revision?

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cittecla 0:df3d4b033d11 1 /*
cittecla 0:df3d4b033d11 2 * EncoderCounter.cpp
cittecla 0:df3d4b033d11 3 * Copyright (c) 2019, ZHAW
cittecla 0:df3d4b033d11 4 * All rights reserved.
cittecla 0:df3d4b033d11 5 */
cittecla 0:df3d4b033d11 6
cittecla 0:df3d4b033d11 7 #include "EncoderCounter.h"
cittecla 0:df3d4b033d11 8
cittecla 0:df3d4b033d11 9 using namespace std;
cittecla 0:df3d4b033d11 10
cittecla 0:df3d4b033d11 11 /**
cittecla 0:df3d4b033d11 12 * Creates and initializes the driver to read the quadrature
cittecla 0:df3d4b033d11 13 * encoder counter of the STM32 microcontroller.
cittecla 0:df3d4b033d11 14 * @param a the input pin for the channel A.
cittecla 0:df3d4b033d11 15 * @param b the input pin for the channel B.
cittecla 0:df3d4b033d11 16 */
cittecla 0:df3d4b033d11 17 EncoderCounter::EncoderCounter(PinName a, PinName b) {
cittecla 0:df3d4b033d11 18
cittecla 0:df3d4b033d11 19 // check pins
cittecla 0:df3d4b033d11 20
cittecla 0:df3d4b033d11 21 if ((a == PA_0) && (b == PA_1)) {
cittecla 0:df3d4b033d11 22
cittecla 0:df3d4b033d11 23 // pinmap OK for TIM2 CH1 and CH2
cittecla 0:df3d4b033d11 24
cittecla 0:df3d4b033d11 25 TIM = TIM2;
cittecla 0:df3d4b033d11 26
cittecla 0:df3d4b033d11 27 // configure general purpose I/O registers
cittecla 0:df3d4b033d11 28
cittecla 0:df3d4b033d11 29 GPIOA->MODER &= ~GPIO_MODER_MODER0; // reset port A0
cittecla 0:df3d4b033d11 30 GPIOA->MODER |= GPIO_MODER_MODER0_1; // set alternate mode of port A0
cittecla 0:df3d4b033d11 31 GPIOA->PUPDR &= ~GPIO_PUPDR_PUPDR0; // reset pull-up/pull-down on port A0
cittecla 0:df3d4b033d11 32 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR0_1; // set input as pull-down
cittecla 0:df3d4b033d11 33 GPIOA->AFR[0] &= ~(0xF << 4*0); // reset alternate function of port A0
cittecla 0:df3d4b033d11 34 GPIOA->AFR[0] |= 1 << 4*0; // set alternate funtion 1 of port A0
cittecla 0:df3d4b033d11 35
cittecla 0:df3d4b033d11 36 GPIOA->MODER &= ~GPIO_MODER_MODER1; // reset port A1
cittecla 0:df3d4b033d11 37 GPIOA->MODER |= GPIO_MODER_MODER1_1; // set alternate mode of port A1
cittecla 0:df3d4b033d11 38 GPIOA->PUPDR &= ~GPIO_PUPDR_PUPDR1; // reset pull-up/pull-down on port A1
cittecla 0:df3d4b033d11 39 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR1_1; // set input as pull-down
cittecla 0:df3d4b033d11 40 GPIOA->AFR[0] &= ~(0xF << 4*1); // reset alternate function of port A1
cittecla 0:df3d4b033d11 41 GPIOA->AFR[0] |= 1 << 4*1; // set alternate funtion 1 of port A1
cittecla 0:df3d4b033d11 42
cittecla 0:df3d4b033d11 43 // configure reset and clock control registers
cittecla 0:df3d4b033d11 44
cittecla 0:df3d4b033d11 45 RCC->APB1RSTR |= RCC_APB1RSTR_TIM2RST; //reset TIM2 controller
cittecla 0:df3d4b033d11 46 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM2RST;
cittecla 0:df3d4b033d11 47
cittecla 0:df3d4b033d11 48 RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; // TIM2 clock enable
cittecla 0:df3d4b033d11 49
cittecla 0:df3d4b033d11 50 } else if ((a == PA_6) && (b == PC_7)) {
cittecla 0:df3d4b033d11 51
cittecla 0:df3d4b033d11 52 // pinmap OK for TIM3 CH1 and CH2
cittecla 0:df3d4b033d11 53
cittecla 0:df3d4b033d11 54 TIM = TIM3;
cittecla 0:df3d4b033d11 55
cittecla 0:df3d4b033d11 56 // configure reset and clock control registers
cittecla 0:df3d4b033d11 57
cittecla 0:df3d4b033d11 58 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN; // manually enable port C (port A enabled by mbed library)
cittecla 0:df3d4b033d11 59
cittecla 0:df3d4b033d11 60 // configure general purpose I/O registers
cittecla 0:df3d4b033d11 61
cittecla 0:df3d4b033d11 62 GPIOA->MODER &= ~GPIO_MODER_MODER6; // reset port A6
cittecla 0:df3d4b033d11 63 GPIOA->MODER |= GPIO_MODER_MODER6_1; // set alternate mode of port A6
cittecla 0:df3d4b033d11 64 GPIOA->PUPDR &= ~GPIO_PUPDR_PUPDR6; // reset pull-up/pull-down on port A6
cittecla 0:df3d4b033d11 65 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR6_1; // set input as pull-down
cittecla 0:df3d4b033d11 66 GPIOA->AFR[0] &= ~(0xF << 4*6); // reset alternate function of port A6
cittecla 0:df3d4b033d11 67 GPIOA->AFR[0] |= 2 << 4*6; // set alternate funtion 2 of port A6
cittecla 0:df3d4b033d11 68
cittecla 0:df3d4b033d11 69 GPIOC->MODER &= ~GPIO_MODER_MODER7; // reset port C7
cittecla 0:df3d4b033d11 70 GPIOC->MODER |= GPIO_MODER_MODER7_1; // set alternate mode of port C7
cittecla 0:df3d4b033d11 71 GPIOC->PUPDR &= ~GPIO_PUPDR_PUPDR7; // reset pull-up/pull-down on port C7
cittecla 0:df3d4b033d11 72 GPIOC->PUPDR |= GPIO_PUPDR_PUPDR7_1; // set input as pull-down
cittecla 0:df3d4b033d11 73 GPIOC->AFR[0] &= ~0xF0000000; // reset alternate function of port C7
cittecla 0:df3d4b033d11 74 GPIOC->AFR[0] |= 2 << 4*7; // set alternate funtion 2 of port C7
cittecla 0:df3d4b033d11 75
cittecla 0:df3d4b033d11 76 // configure reset and clock control registers
cittecla 0:df3d4b033d11 77
cittecla 0:df3d4b033d11 78 RCC->APB1RSTR |= RCC_APB1RSTR_TIM3RST; //reset TIM3 controller
cittecla 0:df3d4b033d11 79 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM3RST;
cittecla 0:df3d4b033d11 80
cittecla 0:df3d4b033d11 81 RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; // TIM3 clock enable
cittecla 0:df3d4b033d11 82
cittecla 0:df3d4b033d11 83 } else if ((a == PB_6) && (b == PB_7)) {
cittecla 0:df3d4b033d11 84
cittecla 0:df3d4b033d11 85 // pinmap OK for TIM4 CH1 and CH2
cittecla 0:df3d4b033d11 86
cittecla 0:df3d4b033d11 87 TIM = TIM4;
cittecla 0:df3d4b033d11 88
cittecla 0:df3d4b033d11 89 // configure reset and clock control registers
cittecla 0:df3d4b033d11 90
cittecla 0:df3d4b033d11 91 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN; // manually enable port B (port A enabled by mbed library)
cittecla 0:df3d4b033d11 92
cittecla 0:df3d4b033d11 93 // configure general purpose I/O registers
cittecla 0:df3d4b033d11 94
cittecla 0:df3d4b033d11 95 GPIOB->MODER &= ~GPIO_MODER_MODER6; // reset port B6
cittecla 0:df3d4b033d11 96 GPIOB->MODER |= GPIO_MODER_MODER6_1; // set alternate mode of port B6
cittecla 0:df3d4b033d11 97 GPIOB->PUPDR &= ~GPIO_PUPDR_PUPDR6; // reset pull-up/pull-down on port B6
cittecla 0:df3d4b033d11 98 GPIOB->PUPDR |= GPIO_PUPDR_PUPDR6_1; // set input as pull-down
cittecla 0:df3d4b033d11 99 GPIOB->AFR[0] &= ~(0xF << 4*6); // reset alternate function of port B6
cittecla 0:df3d4b033d11 100 GPIOB->AFR[0] |= 2 << 4*6; // set alternate funtion 2 of port B6
cittecla 0:df3d4b033d11 101
cittecla 0:df3d4b033d11 102 GPIOB->MODER &= ~GPIO_MODER_MODER7; // reset port B7
cittecla 0:df3d4b033d11 103 GPIOB->MODER |= GPIO_MODER_MODER7_1; // set alternate mode of port B7
cittecla 0:df3d4b033d11 104 GPIOB->PUPDR &= ~GPIO_PUPDR_PUPDR7; // reset pull-up/pull-down on port B7
cittecla 0:df3d4b033d11 105 GPIOB->PUPDR |= GPIO_PUPDR_PUPDR7_1; // set input as pull-down
cittecla 0:df3d4b033d11 106 GPIOB->AFR[0] &= ~0xF0000000; // reset alternate function of port B7
cittecla 0:df3d4b033d11 107 GPIOB->AFR[0] |= 2 << 4*7; // set alternate funtion 2 of port B7
cittecla 0:df3d4b033d11 108
cittecla 0:df3d4b033d11 109 // configure reset and clock control registers
cittecla 0:df3d4b033d11 110
cittecla 0:df3d4b033d11 111 RCC->APB1RSTR |= RCC_APB1RSTR_TIM4RST; //reset TIM4 controller
cittecla 0:df3d4b033d11 112 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM4RST;
cittecla 0:df3d4b033d11 113
cittecla 0:df3d4b033d11 114 RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; // TIM4 clock enable
cittecla 0:df3d4b033d11 115
cittecla 0:df3d4b033d11 116 } else {
cittecla 0:df3d4b033d11 117
cittecla 0:df3d4b033d11 118 printf("pinmap not found for peripheral\n");
cittecla 0:df3d4b033d11 119 }
cittecla 0:df3d4b033d11 120
cittecla 0:df3d4b033d11 121 // configure general purpose timer 3 or 4
cittecla 0:df3d4b033d11 122
cittecla 0:df3d4b033d11 123 TIM->CR1 = 0x0000; // counter disable
cittecla 0:df3d4b033d11 124 TIM->CR2 = 0x0000; // reset master mode selection
cittecla 0:df3d4b033d11 125 TIM->SMCR = TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0; // counting on both TI1 & TI2 edges
cittecla 0:df3d4b033d11 126 TIM->CCMR1 = TIM_CCMR1_CC2S_0 | TIM_CCMR1_CC1S_0;
cittecla 0:df3d4b033d11 127 TIM->CCMR2 = 0x0000; // reset capture mode register 2
cittecla 0:df3d4b033d11 128 TIM->CCER = TIM_CCER_CC2E | TIM_CCER_CC1E;
cittecla 0:df3d4b033d11 129 TIM->CNT = 0x0000; // reset counter value
cittecla 0:df3d4b033d11 130 TIM->ARR = 0xFFFF; // auto reload register
cittecla 0:df3d4b033d11 131 TIM->CR1 = TIM_CR1_CEN; // counter enable
cittecla 0:df3d4b033d11 132 }
cittecla 0:df3d4b033d11 133
cittecla 0:df3d4b033d11 134 EncoderCounter::~EncoderCounter() {}
cittecla 0:df3d4b033d11 135
cittecla 0:df3d4b033d11 136 /**
cittecla 0:df3d4b033d11 137 * Resets the counter value to zero.
cittecla 0:df3d4b033d11 138 */
cittecla 0:df3d4b033d11 139 void EncoderCounter::reset() {
cittecla 0:df3d4b033d11 140
cittecla 0:df3d4b033d11 141 TIM->CNT = 0x0000;
cittecla 0:df3d4b033d11 142 }
cittecla 0:df3d4b033d11 143
cittecla 0:df3d4b033d11 144 /**
cittecla 0:df3d4b033d11 145 * Resets the counter value to a given offset value.
cittecla 0:df3d4b033d11 146 * @param offset the offset value to reset the counter to.
cittecla 0:df3d4b033d11 147 */
cittecla 0:df3d4b033d11 148 void EncoderCounter::reset(short offset) {
cittecla 0:df3d4b033d11 149
cittecla 0:df3d4b033d11 150 TIM->CNT = -offset;
cittecla 0:df3d4b033d11 151 }
cittecla 0:df3d4b033d11 152
cittecla 0:df3d4b033d11 153 /**
cittecla 0:df3d4b033d11 154 * Reads the quadrature encoder counter value.
cittecla 0:df3d4b033d11 155 * @return the quadrature encoder counter as a signed 16-bit integer value.
cittecla 0:df3d4b033d11 156 */
cittecla 0:df3d4b033d11 157 short EncoderCounter::read() {
cittecla 0:df3d4b033d11 158
cittecla 0:df3d4b033d11 159 return (short)(-TIM->CNT);
cittecla 0:df3d4b033d11 160 }
cittecla 0:df3d4b033d11 161
cittecla 0:df3d4b033d11 162 /**
cittecla 0:df3d4b033d11 163 * The empty operator is a shorthand notation of the <code>read()</code> method.
cittecla 0:df3d4b033d11 164 */
cittecla 0:df3d4b033d11 165 EncoderCounter::operator short() {
cittecla 0:df3d4b033d11 166
cittecla 0:df3d4b033d11 167 return read();
cittecla 0:df3d4b033d11 168 }