Lucas Citolin
MBED experiment.
Autoline/ios.h@2:d1c24eae74d5, 2018-09-16 (annotated)
- Committer:
- citolin
- Date:
- Sun Sep 16 17:28:48 2018 +0000
- Revision:
- 2:d1c24eae74d5
- Parent:
- 1:cca3a4e419dd
Added a mutex in the state memory space. Also added a example for power supply station.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| citolin | 1:cca3a4e419dd | 1 | #ifndef AUTOLINE_IOS_H_ |
| citolin | 1:cca3a4e419dd | 2 | #define AUTOLINE_IOS_H_ |
| citolin | 1:cca3a4e419dd | 3 | |
| citolin | 1:cca3a4e419dd | 4 | |
| citolin | 1:cca3a4e419dd | 5 | /* |
| citolin | 1:cca3a4e419dd | 6 | ======================= ======= ======================= |
| citolin | 1:cca3a4e419dd | 7 | ======================= Sensors ======================= |
| citolin | 1:cca3a4e419dd | 8 | ======================= ======= ======================= |
| citolin | 1:cca3a4e419dd | 9 | */ |
| citolin | 1:cca3a4e419dd | 10 | // INPUT ELEVATOR |
| citolin | 1:cca3a4e419dd | 11 | #define SUPP_IE 0x00 |
| citolin | 1:cca3a4e419dd | 12 | #define IP_IE 0x01 |
| citolin | 1:cca3a4e419dd | 13 | #define DWS_IP 0x02 |
| citolin | 1:cca3a4e419dd | 14 | #define UPS_IE 0x03 |
| citolin | 1:cca3a4e419dd | 15 | #define SSTOP_IE 0x04 |
| citolin | 1:cca3a4e419dd | 16 | #define DWS_DES_iE 0x05 |
| citolin | 1:cca3a4e419dd | 17 | #define UPS_DES_DE 0x06 |
| citolin | 1:cca3a4e419dd | 18 | // OUTPUT ELEVATOR |
| citolin | 1:cca3a4e419dd | 19 | #define IP_OE 0x07 |
| citolin | 1:cca3a4e419dd | 20 | #define OP_OE 0x37 |
| citolin | 1:cca3a4e419dd | 21 | #define DWS_OE 0x08 |
| citolin | 1:cca3a4e419dd | 22 | #define UPS_OE 0x09 |
| citolin | 1:cca3a4e419dd | 23 | #define DWS_DES_OE 0x0A |
| citolin | 1:cca3a4e419dd | 24 | #define UPS_DES_OE 0x0B |
| citolin | 1:cca3a4e419dd | 25 | // POWER STATION |
| citolin | 1:cca3a4e419dd | 26 | #define PS_SUPP 0x0E |
| citolin | 1:cca3a4e419dd | 27 | #define SSTOP_SUPP 0x0F |
| citolin | 1:cca3a4e419dd | 28 | #define BT_GO_SUPP 0x0C |
| citolin | 1:cca3a4e419dd | 29 | #define MAN_AUT 0X0D |
| citolin | 1:cca3a4e419dd | 30 | // WAIT HIPOT |
| citolin | 1:cca3a4e419dd | 31 | #define PS_WT_HIP 0X10 |
| citolin | 1:cca3a4e419dd | 32 | #define SSTOP_WT_HIP 0x11 |
| citolin | 1:cca3a4e419dd | 33 | // HIPOT |
| citolin | 1:cca3a4e419dd | 34 | #define PS_HIP 0x12 |
| citolin | 1:cca3a4e419dd | 35 | #define END_DC_HIP 0x13 |
| citolin | 1:cca3a4e419dd | 36 | #define ST_DC_HIP 0x14 |
| citolin | 1:cca3a4e419dd | 37 | #define END_AC_HIP 0x15 |
| citolin | 1:cca3a4e419dd | 38 | #define ST_AC_HIP 0x16 |
| citolin | 1:cca3a4e419dd | 39 | #define SSTOP_HIP 0x17 |
| citolin | 1:cca3a4e419dd | 40 | // PF |
| citolin | 1:cca3a4e419dd | 41 | #define PS_PF 0x18 |
| citolin | 1:cca3a4e419dd | 42 | #define END_DC_PF 0x19 |
| citolin | 1:cca3a4e419dd | 43 | #define ST_DC_PF 0x1A |
| citolin | 1:cca3a4e419dd | 44 | #define END_AC_PF 0x1B |
| citolin | 1:cca3a4e419dd | 45 | #define ST_AC_PF 0x1C |
| citolin | 1:cca3a4e419dd | 46 | #define SSTOP_PF 0x1D |
| citolin | 1:cca3a4e419dd | 47 | // WAIT ATE |
| citolin | 1:cca3a4e419dd | 48 | #define PS_WT_ATE1 0x1E |
| citolin | 1:cca3a4e419dd | 49 | #define SSTOP_WT_ATE1 0x1F |
| citolin | 1:cca3a4e419dd | 50 | // ATE1 |
| citolin | 1:cca3a4e419dd | 51 | #define PS_ATE1 0x20 |
| citolin | 1:cca3a4e419dd | 52 | #define GAV1_ATE1 0x21 |
| citolin | 1:cca3a4e419dd | 53 | #define SSTOP_ATE1 0x22 |
| citolin | 1:cca3a4e419dd | 54 | #define UPS_ATE1 0x23 |
| citolin | 1:cca3a4e419dd | 55 | #define DWS_ATE1 0x24 |
| citolin | 1:cca3a4e419dd | 56 | #define END_DC_ATE1 0x25 |
| citolin | 1:cca3a4e419dd | 57 | #define ST_DC_ATE1 0x26 |
| citolin | 1:cca3a4e419dd | 58 | #define END_DC_AC_ATE1 0x27 |
| citolin | 1:cca3a4e419dd | 59 | #define ST_AC_ATE1 0x28 |
| citolin | 1:cca3a4e419dd | 60 | // ATE2 |
| citolin | 1:cca3a4e419dd | 61 | #define PS_ATE2 0x29 |
| citolin | 1:cca3a4e419dd | 62 | #define GAV2_ATE2 0x2A |
| citolin | 1:cca3a4e419dd | 63 | #define SSTOP_ATE2 0x2B |
| citolin | 1:cca3a4e419dd | 64 | #define UPS_ATE2 0x2C |
| citolin | 1:cca3a4e419dd | 65 | #define DWS_ATE2 0x2D |
| citolin | 1:cca3a4e419dd | 66 | #define END_DC_ATE2 0x2E |
| citolin | 1:cca3a4e419dd | 67 | #define ST_DC_ATE2 0x2F |
| citolin | 1:cca3a4e419dd | 68 | #define END_AC_ATE2 0x30 |
| citolin | 1:cca3a4e419dd | 69 | #define ST_AC_ATE2 0x31 |
| citolin | 1:cca3a4e419dd | 70 | // EPROM |
| citolin | 1:cca3a4e419dd | 71 | #define PS_ROM 0x32 |
| citolin | 1:cca3a4e419dd | 72 | #define SSTOP_ROM 0x35 |
| citolin | 1:cca3a4e419dd | 73 | #define ST_DC_ROM 0x38 |
| citolin | 1:cca3a4e419dd | 74 | #define END_DC_ROM 0x39 |
| citolin | 1:cca3a4e419dd | 75 | // REMOVAL |
| citolin | 1:cca3a4e419dd | 76 | #define PS_RE 0x33 |
| citolin | 1:cca3a4e419dd | 77 | #define SSTOP_RE 0x34 |
| citolin | 1:cca3a4e419dd | 78 | #define ST_DC_RE 0x3A |
| citolin | 1:cca3a4e419dd | 79 | #define END_DC_RE 0x3B |
| citolin | 1:cca3a4e419dd | 80 | |
| citolin | 1:cca3a4e419dd | 81 | |
| citolin | 1:cca3a4e419dd | 82 | |
| citolin | 1:cca3a4e419dd | 83 | /* |
| citolin | 1:cca3a4e419dd | 84 | ======================= ========= ======================= |
| citolin | 1:cca3a4e419dd | 85 | ======================= Actuators ======================= |
| citolin | 1:cca3a4e419dd | 86 | ======================= ========= ======================= |
| citolin | 1:cca3a4e419dd | 87 | */ |
| citolin | 1:cca3a4e419dd | 88 | // It sums 0x50 because the OUTPUT I/Os in the bitset start at index 80. |
| citolin | 1:cca3a4e419dd | 89 | |
| citolin | 1:cca3a4e419dd | 90 | // INPUT ELEVATOR |
| citolin | 1:cca3a4e419dd | 91 | #define STOP_IE 0x00 + 0x50 |
| citolin | 1:cca3a4e419dd | 92 | #define MT1_FW_IE 0x01 + 0x50 |
| citolin | 1:cca3a4e419dd | 93 | #define MT1_REV_IE 0x3C + 0x50 |
| citolin | 1:cca3a4e419dd | 94 | #define MT2_DW_IE 0x03 + 0x50 |
| citolin | 1:cca3a4e419dd | 95 | #define MT2_UP_IE 0x04 + 0x50 |
| citolin | 1:cca3a4e419dd | 96 | #define FRMT_IE 0x05 + 0x50 |
| citolin | 1:cca3a4e419dd | 97 | // OUTPUT ELEVATOR |
| citolin | 1:cca3a4e419dd | 98 | #define MT1_FW_OE 0x06 + 0x50 |
| citolin | 1:cca3a4e419dd | 99 | #define MT1_REV_OE 0x07 + 0x50 |
| citolin | 1:cca3a4e419dd | 100 | #define MT2_DW_OE 0x08 + 0x50 |
| citolin | 1:cca3a4e419dd | 101 | #define MT2_UP_OE 0x09 + 0x50 |
| citolin | 1:cca3a4e419dd | 102 | #define FRMT_OE 0x0A + 0x50 |
| citolin | 1:cca3a4e419dd | 103 | // POWER STATION |
| citolin | 1:cca3a4e419dd | 104 | #define STOP_SUPP 0x0B + 0x50 |
| citolin | 1:cca3a4e419dd | 105 | // WAIT HIPOT |
| citolin | 1:cca3a4e419dd | 106 | #define STOP_WT_HIP 0x0C + 0x50 |
| citolin | 1:cca3a4e419dd | 107 | // HIPOT |
| citolin | 1:cca3a4e419dd | 108 | #define SOL_DC_HIP 0x0D + 0x50 |
| citolin | 1:cca3a4e419dd | 109 | #define SOL_AC_HIP 0x0E + 0x50 |
| citolin | 1:cca3a4e419dd | 110 | #define STOP_HIP 0x0F + 0x50 |
| citolin | 1:cca3a4e419dd | 111 | // PF |
| citolin | 1:cca3a4e419dd | 112 | #define SOL_DC_PF 0x10 + 0x50 |
| citolin | 1:cca3a4e419dd | 113 | #define SOL_AC_PF 0x11 + 0x50 |
| citolin | 1:cca3a4e419dd | 114 | #define STOP_PF 0x12 + 0x50 |
| citolin | 1:cca3a4e419dd | 115 | // WAIT ATE |
| citolin | 1:cca3a4e419dd | 116 | #define STOP_WT_ATE1 0x13 + 0x50 |
| citolin | 1:cca3a4e419dd | 117 | // RELAY ATE |
| citolin | 1:cca3a4e419dd | 118 | #define RLADP1_ATE1_2 0x18 + 0x50 // It could be: RLADP1_ATE |
| citolin | 1:cca3a4e419dd | 119 | #define RLADP2_ATE1_2 0x19 + 0x50 // It could be: RLADP2_ATE |
| citolin | 1:cca3a4e419dd | 120 | // ATE1 |
| citolin | 1:cca3a4e419dd | 121 | #define SOL_DC_ATE1 0x14 + 0x50 |
| citolin | 1:cca3a4e419dd | 122 | #define SOL_AC_ATE1 0x15 + 0x50 |
| citolin | 1:cca3a4e419dd | 123 | #define STOP_ATE1 0x16 + 0x50 |
| citolin | 1:cca3a4e419dd | 124 | #define SOL1_ELEV_ATE1 0x17 + 0x50 |
| citolin | 1:cca3a4e419dd | 125 | #define MTGAV1_FW_ATE1 0x19 + 0x50 |
| citolin | 1:cca3a4e419dd | 126 | #define MTGAV1_REV_ATE1 0x1A + 0x50 |
| citolin | 1:cca3a4e419dd | 127 | #define MTST_FW_ATE1 0x1B + 0x50 |
| citolin | 1:cca3a4e419dd | 128 | #define MTST_REV_ATE1 0x1C + 0x50 |
| citolin | 1:cca3a4e419dd | 129 | // ATE2 |
| citolin | 1:cca3a4e419dd | 130 | #define SOL_DC_ATE2 0x1D + 0x50 |
| citolin | 1:cca3a4e419dd | 131 | #define SOL_AC_ATE2 0x1E + 0x50 |
| citolin | 1:cca3a4e419dd | 132 | #define STOP_ATE2 0x1F + 0x50 |
| citolin | 1:cca3a4e419dd | 133 | #define SOL1_ELEV_ATE2 0x20 + 0x50 |
| citolin | 1:cca3a4e419dd | 134 | #define MTGAV2_FW_ATE2 0x38 + 0x50 |
| citolin | 1:cca3a4e419dd | 135 | #define MTGAV2_REV_ATE2 0x39 + 0x50 |
| citolin | 1:cca3a4e419dd | 136 | #define MTST_FW_ATE2 0x3A + 0x50 |
| citolin | 1:cca3a4e419dd | 137 | #define MTST_REV_ATE2 0x3B + 0x50 |
| citolin | 1:cca3a4e419dd | 138 | // EPROM |
| citolin | 1:cca3a4e419dd | 139 | #define STOP_ROM 0x3D + 0x50 |
| citolin | 1:cca3a4e419dd | 140 | #define SOL_ROM 0x3E + 0x50 |
| citolin | 1:cca3a4e419dd | 141 | // Removal |
| citolin | 1:cca3a4e419dd | 142 | #define STOP_RE 0x30 + 0x50 |
| citolin | 1:cca3a4e419dd | 143 | #define SOL_RE 0x31 + 0x50 |
| citolin | 1:cca3a4e419dd | 144 | // Coneyor |
| citolin | 1:cca3a4e419dd | 145 | #define MTST_TOP_FW 0x32 + 0x50 |
| citolin | 1:cca3a4e419dd | 146 | #define MTST_BOT_REV 0x33 + 0x50 |
| citolin | 1:cca3a4e419dd | 147 | |
| citolin | 1:cca3a4e419dd | 148 | #endif |