charles macneill
Initial release. Mbed library for VL53L1CB
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vl53l1_register_map.h
00001 00002 /******************************************************************************* 00003 * Copyright (c) 2020, STMicroelectronics - All Rights Reserved 00004 00005 This file is part of VL53L1 Core and is dual licensed, 00006 either 'STMicroelectronics 00007 Proprietary license' 00008 or 'BSD 3-clause "New" or "Revised" License' , at your option. 00009 00010 ******************************************************************************** 00011 00012 'STMicroelectronics Proprietary license' 00013 00014 ******************************************************************************** 00015 00016 License terms: STMicroelectronics Proprietary in accordance with licensing 00017 terms at www.st.com/sla0081 00018 00019 STMicroelectronics confidential 00020 Reproduction and Communication of this document is strictly prohibited unless 00021 specifically authorized in writing by STMicroelectronics. 00022 00023 00024 ******************************************************************************** 00025 00026 Alternatively, VL53L1 Core may be distributed under the terms of 00027 'BSD 3-clause "New" or "Revised" License', in which case the following 00028 provisions apply instead of the ones 00029 mentioned above : 00030 00031 ******************************************************************************** 00032 00033 License terms: BSD 3-clause "New" or "Revised" License. 00034 00035 Redistribution and use in source and binary forms, with or without 00036 modification, are permitted provided that the following conditions are met: 00037 00038 1. Redistributions of source code must retain the above copyright notice, this 00039 list of conditions and the following disclaimer. 00040 00041 2. Redistributions in binary form must reproduce the above copyright notice, 00042 this list of conditions and the following disclaimer in the documentation 00043 and/or other materials provided with the distribution. 00044 00045 3. Neither the name of the copyright holder nor the names of its contributors 00046 may be used to endorse or promote products derived from this software 00047 without specific prior written permission. 00048 00049 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00050 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00051 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00052 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00053 FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00054 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00055 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00056 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00057 OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00058 OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00059 00060 00061 ******************************************************************************** 00062 00063 */ 00064 00065 00066 00067 00068 #ifndef _VL53L1_REGISTER_MAP_H_ 00069 #define _VL53L1_REGISTER_MAP_H_ 00070 00071 00072 00073 #define VL53L1_SOFT_RESET 0x0000 00074 00075 #define VL53L1_I2C_SLAVE__DEVICE_ADDRESS 0x0001 00076 00077 #define VL53L1_ANA_CONFIG__VHV_REF_SEL_VDDPIX 0x0002 00078 00079 #define VL53L1_ANA_CONFIG__VHV_REF_SEL_VQUENCH 0x0003 00080 00081 #define VL53L1_ANA_CONFIG__REG_AVDD1V2_SEL 0x0004 00082 00083 #define VL53L1_ANA_CONFIG__FAST_OSC__TRIM 0x0005 00084 00085 #define VL53L1_OSC_MEASURED__FAST_OSC__FREQUENCY 0x0006 00086 00087 #define VL53L1_OSC_MEASURED__FAST_OSC__FREQUENCY_HI 0x0006 00088 00089 #define VL53L1_OSC_MEASURED__FAST_OSC__FREQUENCY_LO 0x0007 00090 00091 #define VL53L1_VHV_CONFIG__TIMEOUT_MACROP_LOOP_BOUND 0x0008 00092 00093 #define VL53L1_VHV_CONFIG__COUNT_THRESH 0x0009 00094 00095 #define VL53L1_VHV_CONFIG__OFFSET 0x000A 00096 00097 #define VL53L1_VHV_CONFIG__INIT 0x000B 00098 00099 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_REF_0 0x000D 00100 00101 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_REF_1 0x000E 00102 00103 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_REF_2 0x000F 00104 00105 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_REF_3 0x0010 00106 00107 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_REF_4 0x0011 00108 00109 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_REF_5 0x0012 00110 00111 #define VL53L1_GLOBAL_CONFIG__REF_EN_START_SELECT 0x0013 00112 00113 #define VL53L1_REF_SPAD_MAN__NUM_REQUESTED_REF_SPADS 0x0014 00114 00115 #define VL53L1_REF_SPAD_MAN__REF_LOCATION 0x0015 00116 00117 #define VL53L1_ALGO__CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS 0x0016 00118 00119 #define VL53L1_ALGO__CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS_HI 0x0016 00120 00121 #define VL53L1_ALGO__CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS_LO 0x0017 00122 00123 #define VL53L1_ALGO__CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS 0x0018 00124 00125 #define VL53L1_ALGO__CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS_HI 0x0018 00126 00127 #define VL53L1_ALGO__CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS_LO 0x0019 00128 00129 #define VL53L1_ALGO__CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS 0x001A 00130 00131 #define VL53L1_ALGO__CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS_HI 0x001A 00132 00133 #define VL53L1_ALGO__CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS_LO 0x001B 00134 00135 #define VL53L1_REF_SPAD_CHAR__TOTAL_RATE_TARGET_MCPS 0x001C 00136 00137 #define VL53L1_REF_SPAD_CHAR__TOTAL_RATE_TARGET_MCPS_HI 0x001C 00138 00139 #define VL53L1_REF_SPAD_CHAR__TOTAL_RATE_TARGET_MCPS_LO 0x001D 00140 00141 #define VL53L1_ALGO__PART_TO_PART_RANGE_OFFSET_MM 0x001E 00142 00143 #define VL53L1_ALGO__PART_TO_PART_RANGE_OFFSET_MM_HI 0x001E 00144 00145 #define VL53L1_ALGO__PART_TO_PART_RANGE_OFFSET_MM_LO 0x001F 00146 00147 #define VL53L1_MM_CONFIG__INNER_OFFSET_MM 0x0020 00148 00149 #define VL53L1_MM_CONFIG__INNER_OFFSET_MM_HI 0x0020 00150 00151 #define VL53L1_MM_CONFIG__INNER_OFFSET_MM_LO 0x0021 00152 00153 #define VL53L1_MM_CONFIG__OUTER_OFFSET_MM 0x0022 00154 00155 #define VL53L1_MM_CONFIG__OUTER_OFFSET_MM_HI 0x0022 00156 00157 #define VL53L1_MM_CONFIG__OUTER_OFFSET_MM_LO 0x0023 00158 00159 #define VL53L1_DSS_CONFIG__TARGET_TOTAL_RATE_MCPS 0x0024 00160 00161 #define VL53L1_DSS_CONFIG__TARGET_TOTAL_RATE_MCPS_HI 0x0024 00162 00163 #define VL53L1_DSS_CONFIG__TARGET_TOTAL_RATE_MCPS_LO 0x0025 00164 00165 #define VL53L1_DEBUG__CTRL 0x0026 00166 00167 #define VL53L1_TEST_MODE__CTRL 0x0027 00168 00169 #define VL53L1_CLK_GATING__CTRL 0x0028 00170 00171 #define VL53L1_NVM_BIST__CTRL 0x0029 00172 00173 #define VL53L1_NVM_BIST__NUM_NVM_WORDS 0x002A 00174 00175 #define VL53L1_NVM_BIST__START_ADDRESS 0x002B 00176 00177 #define VL53L1_HOST_IF__STATUS 0x002C 00178 00179 #define VL53L1_PAD_I2C_HV__CONFIG 0x002D 00180 00181 #define VL53L1_PAD_I2C_HV__EXTSUP_CONFIG 0x002E 00182 00183 #define VL53L1_GPIO_HV_PAD__CTRL 0x002F 00184 00185 #define VL53L1_GPIO_HV_MUX__CTRL 0x0030 00186 00187 #define VL53L1_GPIO__TIO_HV_STATUS 0x0031 00188 00189 #define VL53L1_GPIO__FIO_HV_STATUS 0x0032 00190 00191 #define VL53L1_ANA_CONFIG__SPAD_SEL_PSWIDTH 0x0033 00192 00193 #define VL53L1_ANA_CONFIG__VCSEL_PULSE_WIDTH_OFFSET 0x0034 00194 00195 #define VL53L1_ANA_CONFIG__FAST_OSC__CONFIG_CTRL 0x0035 00196 00197 #define VL53L1_SIGMA_ESTIMATOR__EFFECTIVE_PULSE_WIDTH_NS 0x0036 00198 00199 #define VL53L1_SIGMA_ESTIMATOR__EFFECTIVE_AMBIENT_WIDTH_NS 0x0037 00200 00201 #define VL53L1_SIGMA_ESTIMATOR__SIGMA_REF_MM 0x0038 00202 00203 #define VL53L1_ALGO__CROSSTALK_COMPENSATION_VALID_HEIGHT_MM 0x0039 00204 00205 #define VL53L1_SPARE_HOST_CONFIG__STATIC_CONFIG_SPARE_0 0x003A 00206 00207 #define VL53L1_SPARE_HOST_CONFIG__STATIC_CONFIG_SPARE_1 0x003B 00208 00209 #define VL53L1_ALGO__RANGE_IGNORE_THRESHOLD_MCPS 0x003C 00210 00211 #define VL53L1_ALGO__RANGE_IGNORE_THRESHOLD_MCPS_HI 0x003C 00212 00213 #define VL53L1_ALGO__RANGE_IGNORE_THRESHOLD_MCPS_LO 0x003D 00214 00215 #define VL53L1_ALGO__RANGE_IGNORE_VALID_HEIGHT_MM 0x003E 00216 00217 #define VL53L1_ALGO__RANGE_MIN_CLIP 0x003F 00218 00219 #define VL53L1_ALGO__CONSISTENCY_CHECK__TOLERANCE 0x0040 00220 00221 #define VL53L1_SPARE_HOST_CONFIG__STATIC_CONFIG_SPARE_2 0x0041 00222 00223 #define VL53L1_SD_CONFIG__RESET_STAGES_MSB 0x0042 00224 00225 #define VL53L1_SD_CONFIG__RESET_STAGES_LSB 0x0043 00226 00227 #define VL53L1_GPH_CONFIG__STREAM_COUNT_UPDATE_VALUE 0x0044 00228 00229 #define VL53L1_GLOBAL_CONFIG__STREAM_DIVIDER 0x0045 00230 00231 #define VL53L1_SYSTEM__INTERRUPT_CONFIG_GPIO 0x0046 00232 00233 #define VL53L1_CAL_CONFIG__VCSEL_START 0x0047 00234 00235 #define VL53L1_CAL_CONFIG__REPEAT_RATE 0x0048 00236 00237 #define VL53L1_CAL_CONFIG__REPEAT_RATE_HI 0x0048 00238 00239 #define VL53L1_CAL_CONFIG__REPEAT_RATE_LO 0x0049 00240 00241 #define VL53L1_GLOBAL_CONFIG__VCSEL_WIDTH 0x004A 00242 00243 #define VL53L1_PHASECAL_CONFIG__TIMEOUT_MACROP 0x004B 00244 00245 #define VL53L1_PHASECAL_CONFIG__TARGET 0x004C 00246 00247 #define VL53L1_PHASECAL_CONFIG__OVERRIDE 0x004D 00248 00249 #define VL53L1_DSS_CONFIG__ROI_MODE_CONTROL 0x004F 00250 00251 #define VL53L1_SYSTEM__THRESH_RATE_HIGH 0x0050 00252 00253 #define VL53L1_SYSTEM__THRESH_RATE_HIGH_HI 0x0050 00254 00255 #define VL53L1_SYSTEM__THRESH_RATE_HIGH_LO 0x0051 00256 00257 #define VL53L1_SYSTEM__THRESH_RATE_LOW 0x0052 00258 00259 #define VL53L1_SYSTEM__THRESH_RATE_LOW_HI 0x0052 00260 00261 #define VL53L1_SYSTEM__THRESH_RATE_LOW_LO 0x0053 00262 00263 #define VL53L1_DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT 0x0054 00264 00265 #define VL53L1_DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT_HI 0x0054 00266 00267 #define VL53L1_DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT_LO 0x0055 00268 00269 #define VL53L1_DSS_CONFIG__MANUAL_BLOCK_SELECT 0x0056 00270 00271 #define VL53L1_DSS_CONFIG__APERTURE_ATTENUATION 0x0057 00272 00273 #define VL53L1_DSS_CONFIG__MAX_SPADS_LIMIT 0x0058 00274 00275 #define VL53L1_DSS_CONFIG__MIN_SPADS_LIMIT 0x0059 00276 00277 #define VL53L1_MM_CONFIG__TIMEOUT_MACROP_A_HI 0x005A 00278 00279 #define VL53L1_MM_CONFIG__TIMEOUT_MACROP_A_LO 0x005B 00280 00281 #define VL53L1_MM_CONFIG__TIMEOUT_MACROP_B_HI 0x005C 00282 00283 #define VL53L1_MM_CONFIG__TIMEOUT_MACROP_B_LO 0x005D 00284 00285 #define VL53L1_RANGE_CONFIG__TIMEOUT_MACROP_A_HI 0x005E 00286 00287 #define VL53L1_RANGE_CONFIG__TIMEOUT_MACROP_A_LO 0x005F 00288 00289 #define VL53L1_RANGE_CONFIG__VCSEL_PERIOD_A 0x0060 00290 00291 #define VL53L1_RANGE_CONFIG__TIMEOUT_MACROP_B_HI 0x0061 00292 00293 #define VL53L1_RANGE_CONFIG__TIMEOUT_MACROP_B_LO 0x0062 00294 00295 #define VL53L1_RANGE_CONFIG__VCSEL_PERIOD_B 0x0063 00296 00297 #define VL53L1_RANGE_CONFIG__SIGMA_THRESH 0x0064 00298 00299 #define VL53L1_RANGE_CONFIG__SIGMA_THRESH_HI 0x0064 00300 00301 #define VL53L1_RANGE_CONFIG__SIGMA_THRESH_LO 0x0065 00302 00303 #define VL53L1_RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS 0x0066 00304 00305 #define VL53L1_RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS_HI 0x0066 00306 00307 #define VL53L1_RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS_LO 0x0067 00308 00309 #define VL53L1_RANGE_CONFIG__VALID_PHASE_LOW 0x0068 00310 00311 #define VL53L1_RANGE_CONFIG__VALID_PHASE_HIGH 0x0069 00312 00313 #define VL53L1_SYSTEM__INTERMEASUREMENT_PERIOD 0x006C 00314 00315 #define VL53L1_SYSTEM__INTERMEASUREMENT_PERIOD_3 0x006C 00316 00317 #define VL53L1_SYSTEM__INTERMEASUREMENT_PERIOD_2 0x006D 00318 00319 #define VL53L1_SYSTEM__INTERMEASUREMENT_PERIOD_1 0x006E 00320 00321 #define VL53L1_SYSTEM__INTERMEASUREMENT_PERIOD_0 0x006F 00322 00323 #define VL53L1_SYSTEM__FRACTIONAL_ENABLE 0x0070 00324 00325 #define VL53L1_SYSTEM__GROUPED_PARAMETER_HOLD_0 0x0071 00326 00327 #define VL53L1_SYSTEM__THRESH_HIGH 0x0072 00328 00329 #define VL53L1_SYSTEM__THRESH_HIGH_HI 0x0072 00330 00331 #define VL53L1_SYSTEM__THRESH_HIGH_LO 0x0073 00332 00333 #define VL53L1_SYSTEM__THRESH_LOW 0x0074 00334 00335 #define VL53L1_SYSTEM__THRESH_LOW_HI 0x0074 00336 00337 #define VL53L1_SYSTEM__THRESH_LOW_LO 0x0075 00338 00339 #define VL53L1_SYSTEM__ENABLE_XTALK_PER_QUADRANT 0x0076 00340 00341 #define VL53L1_SYSTEM__SEED_CONFIG 0x0077 00342 00343 #define VL53L1_SD_CONFIG__WOI_SD0 0x0078 00344 00345 #define VL53L1_SD_CONFIG__WOI_SD1 0x0079 00346 00347 #define VL53L1_SD_CONFIG__INITIAL_PHASE_SD0 0x007A 00348 00349 #define VL53L1_SD_CONFIG__INITIAL_PHASE_SD1 0x007B 00350 00351 #define VL53L1_SYSTEM__GROUPED_PARAMETER_HOLD_1 0x007C 00352 00353 #define VL53L1_SD_CONFIG__FIRST_ORDER_SELECT 0x007D 00354 00355 #define VL53L1_SD_CONFIG__QUANTIFIER 0x007E 00356 00357 #define VL53L1_ROI_CONFIG__USER_ROI_CENTRE_SPAD 0x007F 00358 00359 #define VL53L1_ROI_CONFIG__USER_ROI_REQUESTED_GLOBAL_XY_SIZE 0x0080 00360 00361 #define VL53L1_SYSTEM__SEQUENCE_CONFIG 0x0081 00362 00363 #define VL53L1_SYSTEM__GROUPED_PARAMETER_HOLD 0x0082 00364 00365 #define VL53L1_POWER_MANAGEMENT__GO1_POWER_FORCE 0x0083 00366 00367 #define VL53L1_SYSTEM__STREAM_COUNT_CTRL 0x0084 00368 00369 #define VL53L1_FIRMWARE__ENABLE 0x0085 00370 00371 #define VL53L1_SYSTEM__INTERRUPT_CLEAR 0x0086 00372 00373 #define VL53L1_SYSTEM__MODE_START 0x0087 00374 00375 #define VL53L1_RESULT__INTERRUPT_STATUS 0x0088 00376 00377 #define VL53L1_RESULT__RANGE_STATUS 0x0089 00378 00379 #define VL53L1_RESULT__REPORT_STATUS 0x008A 00380 00381 #define VL53L1_RESULT__STREAM_COUNT 0x008B 00382 00383 #define VL53L1_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0 0x008C 00384 00385 #define VL53L1_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x008C 00386 00387 #define VL53L1_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x008D 00388 00389 #define VL53L1_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0 0x008E 00390 00391 #define VL53L1_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x008E 00392 00393 #define VL53L1_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x008F 00394 00395 #define VL53L1_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0 0x0090 00396 00397 #define VL53L1_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_HI 0x0090 00398 00399 #define VL53L1_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_LO 0x0091 00400 00401 #define VL53L1_RESULT__SIGMA_SD0 0x0092 00402 00403 #define VL53L1_RESULT__SIGMA_SD0_HI 0x0092 00404 00405 #define VL53L1_RESULT__SIGMA_SD0_LO 0x0093 00406 00407 #define VL53L1_RESULT__PHASE_SD0 0x0094 00408 00409 #define VL53L1_RESULT__PHASE_SD0_HI 0x0094 00410 00411 #define VL53L1_RESULT__PHASE_SD0_LO 0x0095 00412 00413 #define VL53L1_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0 0x0096 00414 00415 #define VL53L1_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_HI 0x0096 00416 00417 #define VL53L1_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_LO 0x0097 00418 00419 #define VL53L1_PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0 0x0098 00420 00421 #define VL53L1__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_HI 0x0098 00422 00423 #define VL53L1___PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_LO 0x0099 00424 00425 #define VL53L1_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0 0x009A 00426 00427 #define VL53L1_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x009A 00428 00429 #define VL53L1_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x009B 00430 00431 #define VL53L1_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0 0x009C 00432 00433 #define VL53L1_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x009C 00434 00435 #define VL53L1_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x009D 00436 00437 #define VL53L1_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0 0x009E 00438 00439 #define VL53L1_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x009E 00440 00441 #define VL53L1_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x009F 00442 00443 #define VL53L1_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1 0x00A0 00444 00445 #define VL53L1_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_HI 0x00A0 00446 00447 #define VL53L1_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_LO 0x00A1 00448 00449 #define VL53L1_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1 0x00A2 00450 00451 #define VL53L1_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_HI 0x00A2 00452 00453 #define VL53L1_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_LO 0x00A3 00454 00455 #define VL53L1_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1 0x00A4 00456 00457 #define VL53L1_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_HI 0x00A4 00458 00459 #define VL53L1_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_LO 0x00A5 00460 00461 #define VL53L1_RESULT__SIGMA_SD1 0x00A6 00462 00463 #define VL53L1_RESULT__SIGMA_SD1_HI 0x00A6 00464 00465 #define VL53L1_RESULT__SIGMA_SD1_LO 0x00A7 00466 00467 #define VL53L1_RESULT__PHASE_SD1 0x00A8 00468 00469 #define VL53L1_RESULT__PHASE_SD1_HI 0x00A8 00470 00471 #define VL53L1_RESULT__PHASE_SD1_LO 0x00A9 00472 00473 #define VL53L1_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1 0x00AA 00474 00475 #define VL53L1_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_HI 0x00AA 00476 00477 #define VL53L1_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_LO 0x00AB 00478 00479 #define VL53L1_RESULT__SPARE_0_SD1 0x00AC 00480 00481 #define VL53L1_RESULT__SPARE_0_SD1_HI 0x00AC 00482 00483 #define VL53L1_RESULT__SPARE_0_SD1_LO 0x00AD 00484 00485 #define VL53L1_RESULT__SPARE_1_SD1 0x00AE 00486 00487 #define VL53L1_RESULT__SPARE_1_SD1_HI 0x00AE 00488 00489 #define VL53L1_RESULT__SPARE_1_SD1_LO 0x00AF 00490 00491 #define VL53L1_RESULT__SPARE_2_SD1 0x00B0 00492 00493 #define VL53L1_RESULT__SPARE_2_SD1_HI 0x00B0 00494 00495 #define VL53L1_RESULT__SPARE_2_SD1_LO 0x00B1 00496 00497 #define VL53L1_RESULT__SPARE_3_SD1 0x00B2 00498 00499 #define VL53L1_RESULT__THRESH_INFO 0x00B3 00500 00501 #define VL53L1_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0 0x00B4 00502 00503 #define VL53L1_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_3 0x00B4 00504 00505 #define VL53L1_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_2 0x00B5 00506 00507 #define VL53L1_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_1 0x00B6 00508 00509 #define VL53L1_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_0 0x00B7 00510 00511 #define VL53L1_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0 0x00B8 00512 00513 #define VL53L1_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_3 0x00B8 00514 00515 #define VL53L1_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_2 0x00B9 00516 00517 #define VL53L1_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_1 0x00BA 00518 00519 #define VL53L1_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_0 0x00BB 00520 00521 #define VL53L1_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0 0x00BC 00522 00523 #define VL53L1_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_3 0x00BC 00524 00525 #define VL53L1_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_2 0x00BD 00526 00527 #define VL53L1_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_1 0x00BE 00528 00529 #define VL53L1_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_0 0x00BF 00530 00531 #define VL53L1_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0 0x00C0 00532 00533 #define VL53L1_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_3 0x00C0 00534 00535 #define VL53L1_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_2 0x00C1 00536 00537 #define VL53L1_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_1 0x00C2 00538 00539 #define VL53L1_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_0 0x00C3 00540 00541 #define VL53L1_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1 0x00C4 00542 00543 #define VL53L1_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_3 0x00C4 00544 00545 #define VL53L1_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_2 0x00C5 00546 00547 #define VL53L1_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_1 0x00C6 00548 00549 #define VL53L1_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_0 0x00C7 00550 00551 #define VL53L1_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1 0x00C8 00552 00553 #define VL53L1_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_3 0x00C8 00554 00555 #define VL53L1_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_2 0x00C9 00556 00557 #define VL53L1_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_1 0x00CA 00558 00559 #define VL53L1_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_0 0x00CB 00560 00561 #define VL53L1_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1 0x00CC 00562 00563 #define VL53L1_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_3 0x00CC 00564 00565 #define VL53L1_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_2 0x00CD 00566 00567 #define VL53L1_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_1 0x00CE 00568 00569 #define VL53L1_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_0 0x00CF 00570 00571 #define VL53L1_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1 0x00D0 00572 00573 #define VL53L1_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_3 0x00D0 00574 00575 #define VL53L1_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_2 0x00D1 00576 00577 #define VL53L1_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_1 0x00D2 00578 00579 #define VL53L1_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_0 0x00D3 00580 00581 #define VL53L1_RESULT_CORE__SPARE_0 0x00D4 00582 00583 #define VL53L1_PHASECAL_RESULT__REFERENCE_PHASE 0x00D6 00584 00585 #define VL53L1_PHASECAL_RESULT__REFERENCE_PHASE_HI 0x00D6 00586 00587 #define VL53L1_PHASECAL_RESULT__REFERENCE_PHASE_LO 0x00D7 00588 00589 #define VL53L1_PHASECAL_RESULT__VCSEL_START 0x00D8 00590 00591 #define VL53L1_REF_SPAD_CHAR_RESULT__NUM_ACTUAL_REF_SPADS 0x00D9 00592 00593 #define VL53L1_REF_SPAD_CHAR_RESULT__REF_LOCATION 0x00DA 00594 00595 #define VL53L1_VHV_RESULT__COLDBOOT_STATUS 0x00DB 00596 00597 #define VL53L1_VHV_RESULT__SEARCH_RESULT 0x00DC 00598 00599 #define VL53L1_VHV_RESULT__LATEST_SETTING 0x00DD 00600 00601 #define VL53L1_RESULT__OSC_CALIBRATE_VAL 0x00DE 00602 00603 #define VL53L1_RESULT__OSC_CALIBRATE_VAL_HI 0x00DE 00604 00605 #define VL53L1_RESULT__OSC_CALIBRATE_VAL_LO 0x00DF 00606 00607 #define VL53L1_ANA_CONFIG__POWERDOWN_GO1 0x00E0 00608 00609 #define VL53L1_ANA_CONFIG__REF_BG_CTRL 0x00E1 00610 00611 #define VL53L1_ANA_CONFIG__REGDVDD1V2_CTRL 0x00E2 00612 00613 #define VL53L1_ANA_CONFIG__OSC_SLOW_CTRL 0x00E3 00614 00615 #define VL53L1_TEST_MODE__STATUS 0x00E4 00616 00617 #define VL53L1_FIRMWARE__SYSTEM_STATUS 0x00E5 00618 00619 #define VL53L1_FIRMWARE__MODE_STATUS 0x00E6 00620 00621 #define VL53L1_FIRMWARE__SECONDARY_MODE_STATUS 0x00E7 00622 00623 #define VL53L1_FIRMWARE__CAL_REPEAT_RATE_COUNTER 0x00E8 00624 00625 #define VL53L1_FIRMWARE__CAL_REPEAT_RATE_COUNTER_HI 0x00E8 00626 00627 #define VL53L1_FIRMWARE__CAL_REPEAT_RATE_COUNTER_LO 0x00E9 00628 00629 #define VL53L1_FIRMWARE__HISTOGRAM_BIN 0x00EA 00630 00631 #define VL53L1_GPH__SYSTEM__THRESH_HIGH 0x00EC 00632 00633 #define VL53L1_GPH__SYSTEM__THRESH_HIGH_HI 0x00EC 00634 00635 #define VL53L1_GPH__SYSTEM__THRESH_HIGH_LO 0x00ED 00636 00637 #define VL53L1_GPH__SYSTEM__THRESH_LOW 0x00EE 00638 00639 #define VL53L1_GPH__SYSTEM__THRESH_LOW_HI 0x00EE 00640 00641 #define VL53L1_GPH__SYSTEM__THRESH_LOW_LO 0x00EF 00642 00643 #define VL53L1_GPH__SYSTEM__ENABLE_XTALK_PER_QUADRANT 0x00F0 00644 00645 #define VL53L1_GPH__SPARE_0 0x00F1 00646 00647 #define VL53L1_GPH__SD_CONFIG__WOI_SD0 0x00F2 00648 00649 #define VL53L1_GPH__SD_CONFIG__WOI_SD1 0x00F3 00650 00651 #define VL53L1_GPH__SD_CONFIG__INITIAL_PHASE_SD0 0x00F4 00652 00653 #define VL53L1_GPH__SD_CONFIG__INITIAL_PHASE_SD1 0x00F5 00654 00655 #define VL53L1_GPH__SD_CONFIG__FIRST_ORDER_SELECT 0x00F6 00656 00657 #define VL53L1_GPH__SD_CONFIG__QUANTIFIER 0x00F7 00658 00659 #define VL53L1_GPH__ROI_CONFIG__USER_ROI_CENTRE_SPAD 0x00F8 00660 00661 #define VL53L1_GPH__ROI_CONFIG__USER_ROI_REQUESTED_GLOBAL_XY_SIZE 0x00F9 00662 00663 #define VL53L1_GPH__SYSTEM__SEQUENCE_CONFIG 0x00FA 00664 00665 #define VL53L1_GPH__GPH_ID 0x00FB 00666 00667 #define VL53L1_SYSTEM__INTERRUPT_SET 0x00FC 00668 00669 #define VL53L1_INTERRUPT_MANAGER__ENABLES 0x00FD 00670 00671 #define VL53L1_INTERRUPT_MANAGER__CLEAR 0x00FE 00672 00673 #define VL53L1_INTERRUPT_MANAGER__STATUS 0x00FF 00674 00675 #define VL53L1_MCU_TO_HOST_BANK__WR_ACCESS_EN 0x0100 00676 00677 #define VL53L1_POWER_MANAGEMENT__GO1_RESET_STATUS 0x0101 00678 00679 #define VL53L1_PAD_STARTUP_MODE__VALUE_RO 0x0102 00680 00681 #define VL53L1_PAD_STARTUP_MODE__VALUE_CTRL 0x0103 00682 00683 #define VL53L1_PLL_PERIOD_US 0x0104 00684 00685 #define VL53L1_PLL_PERIOD_US_3 0x0104 00686 00687 #define VL53L1_PLL_PERIOD_US_2 0x0105 00688 00689 #define VL53L1_PLL_PERIOD_US_1 0x0106 00690 00691 #define VL53L1_PLL_PERIOD_US_0 0x0107 00692 00693 #define VL53L1_INTERRUPT_SCHEDULER__DATA_OUT 0x0108 00694 00695 #define VL53L1_INTERRUPT_SCHEDULER__DATA_OUT_3 0x0108 00696 00697 #define VL53L1_INTERRUPT_SCHEDULER__DATA_OUT_2 0x0109 00698 00699 #define VL53L1_INTERRUPT_SCHEDULER__DATA_OUT_1 0x010A 00700 00701 #define VL53L1_INTERRUPT_SCHEDULER__DATA_OUT_0 0x010B 00702 00703 #define VL53L1_NVM_BIST__COMPLETE 0x010C 00704 00705 #define VL53L1_NVM_BIST__STATUS 0x010D 00706 00707 #define VL53L1_IDENTIFICATION__MODEL_ID 0x010F 00708 00709 #define VL53L1_IDENTIFICATION__MODULE_TYPE 0x0110 00710 00711 #define VL53L1_IDENTIFICATION__REVISION_ID 0x0111 00712 00713 #define VL53L1_IDENTIFICATION__MODULE_ID 0x0112 00714 00715 #define VL53L1_IDENTIFICATION__MODULE_ID_HI 0x0112 00716 00717 #define VL53L1_IDENTIFICATION__MODULE_ID_LO 0x0113 00718 00719 #define VL53L1_ANA_CONFIG__FAST_OSC__TRIM_MAX 0x0114 00720 00721 #define VL53L1_ANA_CONFIG__FAST_OSC__FREQ_SET 0x0115 00722 00723 #define VL53L1_ANA_CONFIG__VCSEL_TRIM 0x0116 00724 00725 #define VL53L1_ANA_CONFIG__VCSEL_SELION 0x0117 00726 00727 #define VL53L1_ANA_CONFIG__VCSEL_SELION_MAX 0x0118 00728 00729 #define VL53L1_PROTECTED_LASER_SAFETY__LOCK_BIT 0x0119 00730 00731 #define VL53L1_LASER_SAFETY__KEY 0x011A 00732 00733 #define VL53L1_LASER_SAFETY__KEY_RO 0x011B 00734 00735 #define VL53L1_LASER_SAFETY__CLIP 0x011C 00736 00737 #define VL53L1_LASER_SAFETY__MULT 0x011D 00738 00739 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_0 0x011E 00740 00741 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_1 0x011F 00742 00743 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_2 0x0120 00744 00745 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_3 0x0121 00746 00747 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_4 0x0122 00748 00749 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_5 0x0123 00750 00751 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_6 0x0124 00752 00753 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_7 0x0125 00754 00755 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_8 0x0126 00756 00757 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_9 0x0127 00758 00759 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_10 0x0128 00760 00761 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_11 0x0129 00762 00763 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_12 0x012A 00764 00765 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_13 0x012B 00766 00767 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_14 0x012C 00768 00769 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_15 0x012D 00770 00771 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_16 0x012E 00772 00773 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_17 0x012F 00774 00775 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_18 0x0130 00776 00777 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_19 0x0131 00778 00779 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_20 0x0132 00780 00781 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_21 0x0133 00782 00783 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_22 0x0134 00784 00785 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_23 0x0135 00786 00787 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_24 0x0136 00788 00789 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_25 0x0137 00790 00791 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_26 0x0138 00792 00793 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_27 0x0139 00794 00795 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_28 0x013A 00796 00797 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_29 0x013B 00798 00799 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_30 0x013C 00800 00801 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_31 0x013D 00802 00803 #define VL53L1_ROI_CONFIG__MODE_ROI_CENTRE_SPAD 0x013E 00804 00805 #define VL53L1_ROI_CONFIG__MODE_ROI_XY_SIZE 0x013F 00806 00807 #define VL53L1_GO2_HOST_BANK_ACCESS__OVERRIDE 0x0300 00808 00809 #define VL53L1_MCU_UTIL_MULTIPLIER__MULTIPLICAND 0x0400 00810 00811 #define VL53L1_MCU_UTIL_MULTIPLIER__MULTIPLICAND_3 0x0400 00812 00813 #define VL53L1_MCU_UTIL_MULTIPLIER__MULTIPLICAND_2 0x0401 00814 00815 #define VL53L1_MCU_UTIL_MULTIPLIER__MULTIPLICAND_1 0x0402 00816 00817 #define VL53L1_MCU_UTIL_MULTIPLIER__MULTIPLICAND_0 0x0403 00818 00819 #define VL53L1_MCU_UTIL_MULTIPLIER__MULTIPLIER 0x0404 00820 00821 #define VL53L1_MCU_UTIL_MULTIPLIER__MULTIPLIER_3 0x0404 00822 00823 #define VL53L1_MCU_UTIL_MULTIPLIER__MULTIPLIER_2 0x0405 00824 00825 #define VL53L1_MCU_UTIL_MULTIPLIER__MULTIPLIER_1 0x0406 00826 00827 #define VL53L1_MCU_UTIL_MULTIPLIER__MULTIPLIER_0 0x0407 00828 00829 #define VL53L1_MCU_UTIL_MULTIPLIER__PRODUCT_HI 0x0408 00830 00831 #define VL53L1_MCU_UTIL_MULTIPLIER__PRODUCT_HI_3 0x0408 00832 00833 #define VL53L1_MCU_UTIL_MULTIPLIER__PRODUCT_HI_2 0x0409 00834 00835 #define VL53L1_MCU_UTIL_MULTIPLIER__PRODUCT_HI_1 0x040A 00836 00837 #define VL53L1_MCU_UTIL_MULTIPLIER__PRODUCT_HI_0 0x040B 00838 00839 #define VL53L1_MCU_UTIL_MULTIPLIER__PRODUCT_LO 0x040C 00840 00841 #define VL53L1_MCU_UTIL_MULTIPLIER__PRODUCT_LO_3 0x040C 00842 00843 #define VL53L1_MCU_UTIL_MULTIPLIER__PRODUCT_LO_2 0x040D 00844 00845 #define VL53L1_MCU_UTIL_MULTIPLIER__PRODUCT_LO_1 0x040E 00846 00847 #define VL53L1_MCU_UTIL_MULTIPLIER__PRODUCT_LO_0 0x040F 00848 00849 #define VL53L1_MCU_UTIL_MULTIPLIER__START 0x0410 00850 00851 #define VL53L1_MCU_UTIL_MULTIPLIER__STATUS 0x0411 00852 00853 #define VL53L1_MCU_UTIL_DIVIDER__START 0x0412 00854 00855 #define VL53L1_MCU_UTIL_DIVIDER__STATUS 0x0413 00856 00857 #define VL53L1_MCU_UTIL_DIVIDER__DIVIDEND 0x0414 00858 00859 #define VL53L1_MCU_UTIL_DIVIDER__DIVIDEND_3 0x0414 00860 00861 #define VL53L1_MCU_UTIL_DIVIDER__DIVIDEND_2 0x0415 00862 00863 #define VL53L1_MCU_UTIL_DIVIDER__DIVIDEND_1 0x0416 00864 00865 #define VL53L1_MCU_UTIL_DIVIDER__DIVIDEND_0 0x0417 00866 00867 #define VL53L1_MCU_UTIL_DIVIDER__DIVISOR 0x0418 00868 00869 #define VL53L1_MCU_UTIL_DIVIDER__DIVISOR_3 0x0418 00870 00871 #define VL53L1_MCU_UTIL_DIVIDER__DIVISOR_2 0x0419 00872 00873 #define VL53L1_MCU_UTIL_DIVIDER__DIVISOR_1 0x041A 00874 00875 #define VL53L1_MCU_UTIL_DIVIDER__DIVISOR_0 0x041B 00876 00877 #define VL53L1_MCU_UTIL_DIVIDER__QUOTIENT 0x041C 00878 00879 #define VL53L1_MCU_UTIL_DIVIDER__QUOTIENT_3 0x041C 00880 00881 #define VL53L1_MCU_UTIL_DIVIDER__QUOTIENT_2 0x041D 00882 00883 #define VL53L1_MCU_UTIL_DIVIDER__QUOTIENT_1 0x041E 00884 00885 #define VL53L1_MCU_UTIL_DIVIDER__QUOTIENT_0 0x041F 00886 00887 #define VL53L1_TIMER0__VALUE_IN 0x0420 00888 00889 #define VL53L1_TIMER0__VALUE_IN_3 0x0420 00890 00891 #define VL53L1_TIMER0__VALUE_IN_2 0x0421 00892 00893 #define VL53L1_TIMER0__VALUE_IN_1 0x0422 00894 00895 #define VL53L1_TIMER0__VALUE_IN_0 0x0423 00896 00897 #define VL53L1_TIMER1__VALUE_IN 0x0424 00898 00899 #define VL53L1_TIMER1__VALUE_IN_3 0x0424 00900 00901 #define VL53L1_TIMER1__VALUE_IN_2 0x0425 00902 00903 #define VL53L1_TIMER1__VALUE_IN_1 0x0426 00904 00905 #define VL53L1_TIMER1__VALUE_IN_0 0x0427 00906 00907 #define VL53L1_TIMER0__CTRL 0x0428 00908 00909 #define VL53L1_TIMER1__CTRL 0x0429 00910 00911 #define VL53L1_MCU_GENERAL_PURPOSE__GP_0 0x042C 00912 00913 #define VL53L1_MCU_GENERAL_PURPOSE__GP_1 0x042D 00914 00915 #define VL53L1_MCU_GENERAL_PURPOSE__GP_2 0x042E 00916 00917 #define VL53L1_MCU_GENERAL_PURPOSE__GP_3 0x042F 00918 00919 #define VL53L1_MCU_RANGE_CALC__CONFIG 0x0430 00920 00921 #define VL53L1_MCU_RANGE_CALC__OFFSET_CORRECTED_RANGE 0x0432 00922 00923 #define VL53L1_MCU_RANGE_CALC__OFFSET_CORRECTED_RANGE_HI 0x0432 00924 00925 #define VL53L1_MCU_RANGE_CALC__OFFSET_CORRECTED_RANGE_LO 0x0433 00926 00927 #define VL53L1_MCU_RANGE_CALC__SPARE_4 0x0434 00928 00929 #define VL53L1_MCU_RANGE_CALC__SPARE_4_3 0x0434 00930 00931 #define VL53L1_MCU_RANGE_CALC__SPARE_4_2 0x0435 00932 00933 #define VL53L1_MCU_RANGE_CALC__SPARE_4_1 0x0436 00934 00935 #define VL53L1_MCU_RANGE_CALC__SPARE_4_0 0x0437 00936 00937 #define VL53L1_MCU_RANGE_CALC__AMBIENT_DURATION_PRE_CALC 0x0438 00938 00939 #define VL53L1_MCU_RANGE_CALC__AMBIENT_DURATION_PRE_CALC_HI 0x0438 00940 00941 #define VL53L1_MCU_RANGE_CALC__AMBIENT_DURATION_PRE_CALC_LO 0x0439 00942 00943 #define VL53L1_MCU_RANGE_CALC__ALGO_VCSEL_PERIOD 0x043C 00944 00945 #define VL53L1_MCU_RANGE_CALC__SPARE_5 0x043D 00946 00947 #define VL53L1_MCU_RANGE_CALC__ALGO_TOTAL_PERIODS 0x043E 00948 00949 #define VL53L1_MCU_RANGE_CALC__ALGO_TOTAL_PERIODS_HI 0x043E 00950 00951 #define VL53L1_MCU_RANGE_CALC__ALGO_TOTAL_PERIODS_LO 0x043F 00952 00953 #define VL53L1_MCU_RANGE_CALC__ALGO_ACCUM_PHASE 0x0440 00954 00955 #define VL53L1_MCU_RANGE_CALC__ALGO_ACCUM_PHASE_3 0x0440 00956 00957 #define VL53L1_MCU_RANGE_CALC__ALGO_ACCUM_PHASE_2 0x0441 00958 00959 #define VL53L1_MCU_RANGE_CALC__ALGO_ACCUM_PHASE_1 0x0442 00960 00961 #define VL53L1_MCU_RANGE_CALC__ALGO_ACCUM_PHASE_0 0x0443 00962 00963 #define VL53L1_MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS 0x0444 00964 00965 #define VL53L1_MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS_3 0x0444 00966 00967 #define VL53L1_MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS_2 0x0445 00968 00969 #define VL53L1_MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS_1 0x0446 00970 00971 #define VL53L1_MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS_0 0x0447 00972 00973 #define VL53L1_MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS 0x0448 00974 00975 #define VL53L1_MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS_3 0x0448 00976 00977 #define VL53L1_MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS_2 0x0449 00978 00979 #define VL53L1_MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS_1 0x044A 00980 00981 #define VL53L1_MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS_0 0x044B 00982 00983 #define VL53L1_MCU_RANGE_CALC__SPARE_6 0x044C 00984 00985 #define VL53L1_MCU_RANGE_CALC__SPARE_6_HI 0x044C 00986 00987 #define VL53L1_MCU_RANGE_CALC__SPARE_6_LO 0x044D 00988 00989 #define VL53L1_MCU_RANGE_CALC__ALGO_ADJUST_VCSEL_PERIOD 0x044E 00990 00991 #define VL53L1_MCU_RANGE_CALC__ALGO_ADJUST_VCSEL_PERIOD_HI 0x044E 00992 00993 #define VL53L1_MCU_RANGE_CALC__ALGO_ADJUST_VCSEL_PERIOD_LO 0x044F 00994 00995 #define VL53L1_MCU_RANGE_CALC__NUM_SPADS 0x0450 00996 00997 #define VL53L1_MCU_RANGE_CALC__NUM_SPADS_HI 0x0450 00998 00999 #define VL53L1_MCU_RANGE_CALC__NUM_SPADS_LO 0x0451 01000 01001 #define VL53L1_MCU_RANGE_CALC__PHASE_OUTPUT 0x0452 01002 01003 #define VL53L1_MCU_RANGE_CALC__PHASE_OUTPUT_HI 0x0452 01004 01005 #define VL53L1_MCU_RANGE_CALC__PHASE_OUTPUT_LO 0x0453 01006 01007 #define VL53L1_MCU_RANGE_CALC__RATE_PER_SPAD_MCPS 0x0454 01008 01009 #define VL53L1_MCU_RANGE_CALC__RATE_PER_SPAD_MCPS_3 0x0454 01010 01011 #define VL53L1_MCU_RANGE_CALC__RATE_PER_SPAD_MCPS_2 0x0455 01012 01013 #define VL53L1_MCU_RANGE_CALC__RATE_PER_SPAD_MCPS_1 0x0456 01014 01015 #define VL53L1_MCU_RANGE_CALC__RATE_PER_SPAD_MCPS_0 0x0457 01016 01017 #define VL53L1_MCU_RANGE_CALC__SPARE_7 0x0458 01018 01019 #define VL53L1_MCU_RANGE_CALC__SPARE_8 0x0459 01020 01021 #define VL53L1_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_MCPS 0x045A 01022 01023 #define VL53L1_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_MCPS_HI 0x045A 01024 01025 #define VL53L1_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_MCPS_LO 0x045B 01026 01027 #define VL53L1_MCU_RANGE_CALC__AVG_SIGNAL_RATE_MCPS 0x045C 01028 01029 #define VL53L1_MCU_RANGE_CALC__AVG_SIGNAL_RATE_MCPS_HI 0x045C 01030 01031 #define VL53L1_MCU_RANGE_CALC__AVG_SIGNAL_RATE_MCPS_LO 0x045D 01032 01033 #define VL53L1_MCU_RANGE_CALC__AMBIENT_RATE_MCPS 0x045E 01034 01035 #define VL53L1_MCU_RANGE_CALC__AMBIENT_RATE_MCPS_HI 0x045E 01036 01037 #define VL53L1_MCU_RANGE_CALC__AMBIENT_RATE_MCPS_LO 0x045F 01038 01039 #define VL53L1_MCU_RANGE_CALC__XTALK 0x0460 01040 01041 #define VL53L1_MCU_RANGE_CALC__XTALK_HI 0x0460 01042 01043 #define VL53L1_MCU_RANGE_CALC__XTALK_LO 0x0461 01044 01045 #define VL53L1_MCU_RANGE_CALC__CALC_STATUS 0x0462 01046 01047 #define VL53L1_MCU_RANGE_CALC__DEBUG 0x0463 01048 01049 #define VL53L1_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_XTALK_CORR_MCPS 0x0464 01050 01051 #define VL53L1_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_XTALK_CORR_MCPS_HI 0x0464 01052 01053 #define VL53L1_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_XTALK_CORR_MCPS_LO 0x0465 01054 01055 #define VL53L1_MCU_RANGE_CALC__SPARE_0 0x0468 01056 01057 #define VL53L1_MCU_RANGE_CALC__SPARE_1 0x0469 01058 01059 #define VL53L1_MCU_RANGE_CALC__SPARE_2 0x046A 01060 01061 #define VL53L1_MCU_RANGE_CALC__SPARE_3 0x046B 01062 01063 #define VL53L1_PATCH__CTRL 0x0470 01064 01065 #define VL53L1_PATCH__JMP_ENABLES 0x0472 01066 01067 #define VL53L1_PATCH__JMP_ENABLES_HI 0x0472 01068 01069 #define VL53L1_PATCH__JMP_ENABLES_LO 0x0473 01070 01071 #define VL53L1_PATCH__DATA_ENABLES 0x0474 01072 01073 #define VL53L1_PATCH__DATA_ENABLES_HI 0x0474 01074 01075 #define VL53L1_PATCH__DATA_ENABLES_LO 0x0475 01076 01077 #define VL53L1_PATCH__OFFSET_0 0x0476 01078 01079 #define VL53L1_PATCH__OFFSET_0_HI 0x0476 01080 01081 #define VL53L1_PATCH__OFFSET_0_LO 0x0477 01082 01083 #define VL53L1_PATCH__OFFSET_1 0x0478 01084 01085 #define VL53L1_PATCH__OFFSET_1_HI 0x0478 01086 01087 #define VL53L1_PATCH__OFFSET_1_LO 0x0479 01088 01089 #define VL53L1_PATCH__OFFSET_2 0x047A 01090 01091 #define VL53L1_PATCH__OFFSET_2_HI 0x047A 01092 01093 #define VL53L1_PATCH__OFFSET_2_LO 0x047B 01094 01095 #define VL53L1_PATCH__OFFSET_3 0x047C 01096 01097 #define VL53L1_PATCH__OFFSET_3_HI 0x047C 01098 01099 #define VL53L1_PATCH__OFFSET_3_LO 0x047D 01100 01101 #define VL53L1_PATCH__OFFSET_4 0x047E 01102 01103 #define VL53L1_PATCH__OFFSET_4_HI 0x047E 01104 01105 #define VL53L1_PATCH__OFFSET_4_LO 0x047F 01106 01107 #define VL53L1_PATCH__OFFSET_5 0x0480 01108 01109 #define VL53L1_PATCH__OFFSET_5_HI 0x0480 01110 01111 #define VL53L1_PATCH__OFFSET_5_LO 0x0481 01112 01113 #define VL53L1_PATCH__OFFSET_6 0x0482 01114 01115 #define VL53L1_PATCH__OFFSET_6_HI 0x0482 01116 01117 #define VL53L1_PATCH__OFFSET_6_LO 0x0483 01118 01119 #define VL53L1_PATCH__OFFSET_7 0x0484 01120 01121 #define VL53L1_PATCH__OFFSET_7_HI 0x0484 01122 01123 #define VL53L1_PATCH__OFFSET_7_LO 0x0485 01124 01125 #define VL53L1_PATCH__OFFSET_8 0x0486 01126 01127 #define VL53L1_PATCH__OFFSET_8_HI 0x0486 01128 01129 #define VL53L1_PATCH__OFFSET_8_LO 0x0487 01130 01131 #define VL53L1_PATCH__OFFSET_9 0x0488 01132 01133 #define VL53L1_PATCH__OFFSET_9_HI 0x0488 01134 01135 #define VL53L1_PATCH__OFFSET_9_LO 0x0489 01136 01137 #define VL53L1_PATCH__OFFSET_10 0x048A 01138 01139 #define VL53L1_PATCH__OFFSET_10_HI 0x048A 01140 01141 #define VL53L1_PATCH__OFFSET_10_LO 0x048B 01142 01143 #define VL53L1_PATCH__OFFSET_11 0x048C 01144 01145 #define VL53L1_PATCH__OFFSET_11_HI 0x048C 01146 01147 #define VL53L1_PATCH__OFFSET_11_LO 0x048D 01148 01149 #define VL53L1_PATCH__OFFSET_12 0x048E 01150 01151 #define VL53L1_PATCH__OFFSET_12_HI 0x048E 01152 01153 #define VL53L1_PATCH__OFFSET_12_LO 0x048F 01154 01155 #define VL53L1_PATCH__OFFSET_13 0x0490 01156 01157 #define VL53L1_PATCH__OFFSET_13_HI 0x0490 01158 01159 #define VL53L1_PATCH__OFFSET_13_LO 0x0491 01160 01161 #define VL53L1_PATCH__OFFSET_14 0x0492 01162 01163 #define VL53L1_PATCH__OFFSET_14_HI 0x0492 01164 01165 #define VL53L1_PATCH__OFFSET_14_LO 0x0493 01166 01167 #define VL53L1_PATCH__OFFSET_15 0x0494 01168 01169 #define VL53L1_PATCH__OFFSET_15_HI 0x0494 01170 01171 #define VL53L1_PATCH__OFFSET_15_LO 0x0495 01172 01173 #define VL53L1_PATCH__ADDRESS_0 0x0496 01174 01175 #define VL53L1_PATCH__ADDRESS_0_HI 0x0496 01176 01177 #define VL53L1_PATCH__ADDRESS_0_LO 0x0497 01178 01179 #define VL53L1_PATCH__ADDRESS_1 0x0498 01180 01181 #define VL53L1_PATCH__ADDRESS_1_HI 0x0498 01182 01183 #define VL53L1_PATCH__ADDRESS_1_LO 0x0499 01184 01185 #define VL53L1_PATCH__ADDRESS_2 0x049A 01186 01187 #define VL53L1_PATCH__ADDRESS_2_HI 0x049A 01188 01189 #define VL53L1_PATCH__ADDRESS_2_LO 0x049B 01190 01191 #define VL53L1_PATCH__ADDRESS_3 0x049C 01192 01193 #define VL53L1_PATCH__ADDRESS_3_HI 0x049C 01194 01195 #define VL53L1_PATCH__ADDRESS_3_LO 0x049D 01196 01197 #define VL53L1_PATCH__ADDRESS_4 0x049E 01198 01199 #define VL53L1_PATCH__ADDRESS_4_HI 0x049E 01200 01201 #define VL53L1_PATCH__ADDRESS_4_LO 0x049F 01202 01203 #define VL53L1_PATCH__ADDRESS_5 0x04A0 01204 01205 #define VL53L1_PATCH__ADDRESS_5_HI 0x04A0 01206 01207 #define VL53L1_PATCH__ADDRESS_5_LO 0x04A1 01208 01209 #define VL53L1_PATCH__ADDRESS_6 0x04A2 01210 01211 #define VL53L1_PATCH__ADDRESS_6_HI 0x04A2 01212 01213 #define VL53L1_PATCH__ADDRESS_6_LO 0x04A3 01214 01215 #define VL53L1_PATCH__ADDRESS_7 0x04A4 01216 01217 #define VL53L1_PATCH__ADDRESS_7_HI 0x04A4 01218 01219 #define VL53L1_PATCH__ADDRESS_7_LO 0x04A5 01220 01221 #define VL53L1_PATCH__ADDRESS_8 0x04A6 01222 01223 #define VL53L1_PATCH__ADDRESS_8_HI 0x04A6 01224 01225 #define VL53L1_PATCH__ADDRESS_8_LO 0x04A7 01226 01227 #define VL53L1_PATCH__ADDRESS_9 0x04A8 01228 01229 #define VL53L1_PATCH__ADDRESS_9_HI 0x04A8 01230 01231 #define VL53L1_PATCH__ADDRESS_9_LO 0x04A9 01232 01233 #define VL53L1_PATCH__ADDRESS_10 0x04AA 01234 01235 #define VL53L1_PATCH__ADDRESS_10_HI 0x04AA 01236 01237 #define VL53L1_PATCH__ADDRESS_10_LO 0x04AB 01238 01239 #define VL53L1_PATCH__ADDRESS_11 0x04AC 01240 01241 #define VL53L1_PATCH__ADDRESS_11_HI 0x04AC 01242 01243 #define VL53L1_PATCH__ADDRESS_11_LO 0x04AD 01244 01245 #define VL53L1_PATCH__ADDRESS_12 0x04AE 01246 01247 #define VL53L1_PATCH__ADDRESS_12_HI 0x04AE 01248 01249 #define VL53L1_PATCH__ADDRESS_12_LO 0x04AF 01250 01251 #define VL53L1_PATCH__ADDRESS_13 0x04B0 01252 01253 #define VL53L1_PATCH__ADDRESS_13_HI 0x04B0 01254 01255 #define VL53L1_PATCH__ADDRESS_13_LO 0x04B1 01256 01257 #define VL53L1_PATCH__ADDRESS_14 0x04B2 01258 01259 #define VL53L1_PATCH__ADDRESS_14_HI 0x04B2 01260 01261 #define VL53L1_PATCH__ADDRESS_14_LO 0x04B3 01262 01263 #define VL53L1_PATCH__ADDRESS_15 0x04B4 01264 01265 #define VL53L1_PATCH__ADDRESS_15_HI 0x04B4 01266 01267 #define VL53L1_PATCH__ADDRESS_15_LO 0x04B5 01268 01269 #define VL53L1_SPI_ASYNC_MUX__CTRL 0x04C0 01270 01271 #define VL53L1_CLK__CONFIG 0x04C4 01272 01273 #define VL53L1_GPIO_LV_MUX__CTRL 0x04CC 01274 01275 #define VL53L1_GPIO_LV_PAD__CTRL 0x04CD 01276 01277 #define VL53L1_PAD_I2C_LV__CONFIG 0x04D0 01278 01279 #define VL53L1_PAD_STARTUP_MODE__VALUE_RO_GO1 0x04D4 01280 01281 #define VL53L1_HOST_IF__STATUS_GO1 0x04D5 01282 01283 #define VL53L1_MCU_CLK_GATING__CTRL 0x04D8 01284 01285 #define VL53L1_TEST__BIST_ROM_CTRL 0x04E0 01286 01287 #define VL53L1_TEST__BIST_ROM_RESULT 0x04E1 01288 01289 #define VL53L1_TEST__BIST_ROM_MCU_SIG 0x04E2 01290 01291 #define VL53L1_TEST__BIST_ROM_MCU_SIG_HI 0x04E2 01292 01293 #define VL53L1_TEST__BIST_ROM_MCU_SIG_LO 0x04E3 01294 01295 #define VL53L1_TEST__BIST_RAM_CTRL 0x04E4 01296 01297 #define VL53L1_TEST__BIST_RAM_RESULT 0x04E5 01298 01299 #define VL53L1_TEST__TMC 0x04E8 01300 01301 #define VL53L1_TEST__PLL_BIST_MIN_THRESHOLD 0x04F0 01302 01303 #define VL53L1_TEST__PLL_BIST_MIN_THRESHOLD_HI 0x04F0 01304 01305 #define VL53L1_TEST__PLL_BIST_MIN_THRESHOLD_LO 0x04F1 01306 01307 #define VL53L1_TEST__PLL_BIST_MAX_THRESHOLD 0x04F2 01308 01309 #define VL53L1_TEST__PLL_BIST_MAX_THRESHOLD_HI 0x04F2 01310 01311 #define VL53L1_TEST__PLL_BIST_MAX_THRESHOLD_LO 0x04F3 01312 01313 #define VL53L1_TEST__PLL_BIST_COUNT_OUT 0x04F4 01314 01315 #define VL53L1_TEST__PLL_BIST_COUNT_OUT_HI 0x04F4 01316 01317 #define VL53L1_TEST__PLL_BIST_COUNT_OUT_LO 0x04F5 01318 01319 #define VL53L1_TEST__PLL_BIST_GONOGO 0x04F6 01320 01321 #define VL53L1_TEST__PLL_BIST_CTRL 0x04F7 01322 01323 #define VL53L1_RANGING_CORE__DEVICE_ID 0x0680 01324 01325 #define VL53L1_RANGING_CORE__REVISION_ID 0x0681 01326 01327 #define VL53L1_RANGING_CORE__CLK_CTRL1 0x0683 01328 01329 #define VL53L1_RANGING_CORE__CLK_CTRL2 0x0684 01330 01331 #define VL53L1_RANGING_CORE__WOI_1 0x0685 01332 01333 #define VL53L1_RANGING_CORE__WOI_REF_1 0x0686 01334 01335 #define VL53L1_RANGING_CORE__START_RANGING 0x0687 01336 01337 #define VL53L1_RANGING_CORE__LOW_LIMIT_1 0x0690 01338 01339 #define VL53L1_RANGING_CORE__HIGH_LIMIT_1 0x0691 01340 01341 #define VL53L1_RANGING_CORE__LOW_LIMIT_REF_1 0x0692 01342 01343 #define VL53L1_RANGING_CORE__HIGH_LIMIT_REF_1 0x0693 01344 01345 #define VL53L1_RANGING_CORE__QUANTIFIER_1_MSB 0x0694 01346 01347 #define VL53L1_RANGING_CORE__QUANTIFIER_1_LSB 0x0695 01348 01349 #define VL53L1_RANGING_CORE__QUANTIFIER_REF_1_MSB 0x0696 01350 01351 #define VL53L1_RANGING_CORE__QUANTIFIER_REF_1_LSB 0x0697 01352 01353 #define VL53L1_RANGING_CORE__AMBIENT_OFFSET_1_MSB 0x0698 01354 01355 #define VL53L1_RANGING_CORE__AMBIENT_OFFSET_1_LSB 0x0699 01356 01357 #define VL53L1_RANGING_CORE__AMBIENT_OFFSET_REF_1_MSB 0x069A 01358 01359 #define VL53L1_RANGING_CORE__AMBIENT_OFFSET_REF_1_LSB 0x069B 01360 01361 #define VL53L1_RANGING_CORE__FILTER_STRENGTH_1 0x069C 01362 01363 #define VL53L1_RANGING_CORE__FILTER_STRENGTH_REF_1 0x069D 01364 01365 #define VL53L1_RANGING_CORE__SIGNAL_EVENT_LIMIT_1_MSB 0x069E 01366 01367 #define VL53L1_RANGING_CORE__SIGNAL_EVENT_LIMIT_1_LSB 0x069F 01368 01369 #define VL53L1_RANGING_CORE__SIGNAL_EVENT_LIMIT_REF_1_MSB 0x06A0 01370 01371 #define VL53L1_RANGING_CORE__SIGNAL_EVENT_LIMIT_REF_1_LSB 0x06A1 01372 01373 #define VL53L1_RANGING_CORE__TIMEOUT_OVERALL_PERIODS_MSB 0x06A4 01374 01375 #define VL53L1_RANGING_CORE__TIMEOUT_OVERALL_PERIODS_LSB 0x06A5 01376 01377 #define VL53L1_RANGING_CORE__INVERT_HW 0x06A6 01378 01379 #define VL53L1_RANGING_CORE__FORCE_HW 0x06A7 01380 01381 #define VL53L1_RANGING_CORE__STATIC_HW_VALUE 0x06A8 01382 01383 #define VL53L1_RANGING_CORE__FORCE_CONTINUOUS_AMBIENT 0x06A9 01384 01385 #define VL53L1_RANGING_CORE__TEST_PHASE_SELECT_TO_FILTER 0x06AA 01386 01387 #define VL53L1_RANGING_CORE__TEST_PHASE_SELECT_TO_TIMING_GEN 0x06AB 01388 01389 #define VL53L1_RANGING_CORE__INITIAL_PHASE_VALUE_1 0x06AC 01390 01391 #define VL53L1_RANGING_CORE__INITIAL_PHASE_VALUE_REF_1 0x06AD 01392 01393 #define VL53L1_RANGING_CORE__FORCE_UP_IN 0x06AE 01394 01395 #define VL53L1_RANGING_CORE__FORCE_DN_IN 0x06AF 01396 01397 #define VL53L1_RANGING_CORE__STATIC_UP_VALUE_1 0x06B0 01398 01399 #define VL53L1_RANGING_CORE__STATIC_UP_VALUE_REF_1 0x06B1 01400 01401 #define VL53L1_RANGING_CORE__STATIC_DN_VALUE_1 0x06B2 01402 01403 #define VL53L1_RANGING_CORE__STATIC_DN_VALUE_REF_1 0x06B3 01404 01405 #define VL53L1_RANGING_CORE__MONITOR_UP_DN 0x06B4 01406 01407 #define VL53L1_RANGING_CORE__INVERT_UP_DN 0x06B5 01408 01409 #define VL53L1_RANGING_CORE__CPUMP_1 0x06B6 01410 01411 #define VL53L1_RANGING_CORE__CPUMP_2 0x06B7 01412 01413 #define VL53L1_RANGING_CORE__CPUMP_3 0x06B8 01414 01415 #define VL53L1_RANGING_CORE__OSC_1 0x06B9 01416 01417 #define VL53L1_RANGING_CORE__PLL_1 0x06BB 01418 01419 #define VL53L1_RANGING_CORE__PLL_2 0x06BC 01420 01421 #define VL53L1_RANGING_CORE__REFERENCE_1 0x06BD 01422 01423 #define VL53L1_RANGING_CORE__REFERENCE_3 0x06BF 01424 01425 #define VL53L1_RANGING_CORE__REFERENCE_4 0x06C0 01426 01427 #define VL53L1_RANGING_CORE__REFERENCE_5 0x06C1 01428 01429 #define VL53L1_RANGING_CORE__REGAVDD1V2 0x06C3 01430 01431 #define VL53L1_RANGING_CORE__CALIB_1 0x06C4 01432 01433 #define VL53L1_RANGING_CORE__CALIB_2 0x06C5 01434 01435 #define VL53L1_RANGING_CORE__CALIB_3 0x06C6 01436 01437 #define VL53L1_RANGING_CORE__TST_MUX_SEL1 0x06C9 01438 01439 #define VL53L1_RANGING_CORE__TST_MUX_SEL2 0x06CA 01440 01441 #define VL53L1_RANGING_CORE__TST_MUX 0x06CB 01442 01443 #define VL53L1_RANGING_CORE__GPIO_OUT_TESTMUX 0x06CC 01444 01445 #define VL53L1_RANGING_CORE__CUSTOM_FE 0x06CD 01446 01447 #define VL53L1_RANGING_CORE__CUSTOM_FE_2 0x06CE 01448 01449 #define VL53L1_RANGING_CORE__SPAD_READOUT 0x06CF 01450 01451 #define VL53L1_RANGING_CORE__SPAD_READOUT_1 0x06D0 01452 01453 #define VL53L1_RANGING_CORE__SPAD_READOUT_2 0x06D1 01454 01455 #define VL53L1_RANGING_CORE__SPAD_PS 0x06D2 01456 01457 #define VL53L1_RANGING_CORE__LASER_SAFETY_2 0x06D4 01458 01459 #define VL53L1_RANGING_CORE__NVM_CTRL__MODE 0x0780 01460 01461 #define VL53L1_RANGING_CORE__NVM_CTRL__PDN 0x0781 01462 01463 #define VL53L1_RANGING_CORE__NVM_CTRL__PROGN 0x0782 01464 01465 #define VL53L1_RANGING_CORE__NVM_CTRL__READN 0x0783 01466 01467 #define VL53L1_RANGING_CORE__NVM_CTRL__PULSE_WIDTH_MSB 0x0784 01468 01469 #define VL53L1_RANGING_CORE__NVM_CTRL__PULSE_WIDTH_LSB 0x0785 01470 01471 #define VL53L1_RANGING_CORE__NVM_CTRL__HV_RISE_MSB 0x0786 01472 01473 #define VL53L1_RANGING_CORE__NVM_CTRL__HV_RISE_LSB 0x0787 01474 01475 #define VL53L1_RANGING_CORE__NVM_CTRL__HV_FALL_MSB 0x0788 01476 01477 #define VL53L1_RANGING_CORE__NVM_CTRL__HV_FALL_LSB 0x0789 01478 01479 #define VL53L1_RANGING_CORE__NVM_CTRL__TST 0x078A 01480 01481 #define VL53L1_RANGING_CORE__NVM_CTRL__TESTREAD 0x078B 01482 01483 #define VL53L1_RANGING_CORE__NVM_CTRL__DATAIN_MMM 0x078C 01484 01485 #define VL53L1_RANGING_CORE__NVM_CTRL__DATAIN_LMM 0x078D 01486 01487 #define VL53L1_RANGING_CORE__NVM_CTRL__DATAIN_LLM 0x078E 01488 01489 #define VL53L1_RANGING_CORE__NVM_CTRL__DATAIN_LLL 0x078F 01490 01491 #define VL53L1_RANGING_CORE__NVM_CTRL__DATAOUT_MMM 0x0790 01492 01493 #define VL53L1_RANGING_CORE__NVM_CTRL__DATAOUT_LMM 0x0791 01494 01495 #define VL53L1_RANGING_CORE__NVM_CTRL__DATAOUT_LLM 0x0792 01496 01497 #define VL53L1_RANGING_CORE__NVM_CTRL__DATAOUT_LLL 0x0793 01498 01499 #define VL53L1_RANGING_CORE__NVM_CTRL__ADDR 0x0794 01500 01501 #define VL53L1_RANGING_CORE__NVM_CTRL__DATAOUT_ECC 0x0795 01502 01503 #define VL53L1_RANGING_CORE__RET_SPAD_EN_0 0x0796 01504 01505 #define VL53L1_RANGING_CORE__RET_SPAD_EN_1 0x0797 01506 01507 #define VL53L1_RANGING_CORE__RET_SPAD_EN_2 0x0798 01508 01509 #define VL53L1_RANGING_CORE__RET_SPAD_EN_3 0x0799 01510 01511 #define VL53L1_RANGING_CORE__RET_SPAD_EN_4 0x079A 01512 01513 #define VL53L1_RANGING_CORE__RET_SPAD_EN_5 0x079B 01514 01515 #define VL53L1_RANGING_CORE__RET_SPAD_EN_6 0x079C 01516 01517 #define VL53L1_RANGING_CORE__RET_SPAD_EN_7 0x079D 01518 01519 #define VL53L1_RANGING_CORE__RET_SPAD_EN_8 0x079E 01520 01521 #define VL53L1_RANGING_CORE__RET_SPAD_EN_9 0x079F 01522 01523 #define VL53L1_RANGING_CORE__RET_SPAD_EN_10 0x07A0 01524 01525 #define VL53L1_RANGING_CORE__RET_SPAD_EN_11 0x07A1 01526 01527 #define VL53L1_RANGING_CORE__RET_SPAD_EN_12 0x07A2 01528 01529 #define VL53L1_RANGING_CORE__RET_SPAD_EN_13 0x07A3 01530 01531 #define VL53L1_RANGING_CORE__RET_SPAD_EN_14 0x07A4 01532 01533 #define VL53L1_RANGING_CORE__RET_SPAD_EN_15 0x07A5 01534 01535 #define VL53L1_RANGING_CORE__RET_SPAD_EN_16 0x07A6 01536 01537 #define VL53L1_RANGING_CORE__RET_SPAD_EN_17 0x07A7 01538 01539 #define VL53L1_RANGING_CORE__SPAD_SHIFT_EN 0x07BA 01540 01541 #define VL53L1_RANGING_CORE__SPAD_DISABLE_CTRL 0x07BB 01542 01543 #define VL53L1_RANGING_CORE__SPAD_EN_SHIFT_OUT_DEBUG 0x07BC 01544 01545 #define VL53L1_RANGING_CORE__SPI_MODE 0x07BD 01546 01547 #define VL53L1_RANGING_CORE__GPIO_DIR 0x07BE 01548 01549 #define VL53L1_RANGING_CORE__VCSEL_PERIOD 0x0880 01550 01551 #define VL53L1_RANGING_CORE__VCSEL_START 0x0881 01552 01553 #define VL53L1_RANGING_CORE__VCSEL_STOP 0x0882 01554 01555 #define VL53L1_RANGING_CORE__VCSEL_1 0x0885 01556 01557 #define VL53L1_RANGING_CORE__VCSEL_STATUS 0x088D 01558 01559 #define VL53L1_RANGING_CORE__STATUS 0x0980 01560 01561 #define VL53L1_RANGING_CORE__LASER_CONTINUITY_STATE 0x0981 01562 01563 #define VL53L1_RANGING_CORE__RANGE_1_MMM 0x0982 01564 01565 #define VL53L1_RANGING_CORE__RANGE_1_LMM 0x0983 01566 01567 #define VL53L1_RANGING_CORE__RANGE_1_LLM 0x0984 01568 01569 #define VL53L1_RANGING_CORE__RANGE_1_LLL 0x0985 01570 01571 #define VL53L1_RANGING_CORE__RANGE_REF_1_MMM 0x0986 01572 01573 #define VL53L1_RANGING_CORE__RANGE_REF_1_LMM 0x0987 01574 01575 #define VL53L1_RANGING_CORE__RANGE_REF_1_LLM 0x0988 01576 01577 #define VL53L1_RANGING_CORE__RANGE_REF_1_LLL 0x0989 01578 01579 #define VL53L1_RANGING_CORE__AMBIENT_WINDOW_EVENTS_1_MMM 0x098A 01580 01581 #define VL53L1_RANGING_CORE__AMBIENT_WINDOW_EVENTS_1_LMM 0x098B 01582 01583 #define VL53L1_RANGING_CORE__AMBIENT_WINDOW_EVENTS_1_LLM 0x098C 01584 01585 #define VL53L1_RANGING_CORE__AMBIENT_WINDOW_EVENTS_1_LLL 0x098D 01586 01587 #define VL53L1_RANGING_CORE__RANGING_TOTAL_EVENTS_1_MMM 0x098E 01588 01589 #define VL53L1_RANGING_CORE__RANGING_TOTAL_EVENTS_1_LMM 0x098F 01590 01591 #define VL53L1_RANGING_CORE__RANGING_TOTAL_EVENTS_1_LLM 0x0990 01592 01593 #define VL53L1_RANGING_CORE__RANGING_TOTAL_EVENTS_1_LLL 0x0991 01594 01595 #define VL53L1_RANGING_CORE__SIGNAL_TOTAL_EVENTS_1_MMM 0x0992 01596 01597 #define VL53L1_RANGING_CORE__SIGNAL_TOTAL_EVENTS_1_LMM 0x0993 01598 01599 #define VL53L1_RANGING_CORE__SIGNAL_TOTAL_EVENTS_1_LLM 0x0994 01600 01601 #define VL53L1_RANGING_CORE__SIGNAL_TOTAL_EVENTS_1_LLL 0x0995 01602 01603 #define VL53L1_RANGING_CORE__TOTAL_PERIODS_ELAPSED_1_MM 0x0996 01604 01605 #define VL53L1_RANGING_CORE__TOTAL_PERIODS_ELAPSED_1_LM 0x0997 01606 01607 #define VL53L1_RANGING_CORE__TOTAL_PERIODS_ELAPSED_1_LL 0x0998 01608 01609 #define VL53L1_RANGING_CORE__AMBIENT_MISMATCH_MM 0x0999 01610 01611 #define VL53L1_RANGING_CORE__AMBIENT_MISMATCH_LM 0x099A 01612 01613 #define VL53L1_RANGING_CORE__AMBIENT_MISMATCH_LL 0x099B 01614 01615 #define VL53L1_RANGING_CORE__AMBIENT_WINDOW_EVENTS_REF_1_MMM 0x099C 01616 01617 #define VL53L1_RANGING_CORE__AMBIENT_WINDOW_EVENTS_REF_1_LMM 0x099D 01618 01619 #define VL53L1_RANGING_CORE__AMBIENT_WINDOW_EVENTS_REF_1_LLM 0x099E 01620 01621 #define VL53L1_RANGING_CORE__AMBIENT_WINDOW_EVENTS_REF_1_LLL 0x099F 01622 01623 #define VL53L1_RANGING_CORE__RANGING_TOTAL_EVENTS_REF_1_MMM 0x09A0 01624 01625 #define VL53L1_RANGING_CORE__RANGING_TOTAL_EVENTS_REF_1_LMM 0x09A1 01626 01627 #define VL53L1_RANGING_CORE__RANGING_TOTAL_EVENTS_REF_1_LLM 0x09A2 01628 01629 #define VL53L1_RANGING_CORE__RANGING_TOTAL_EVENTS_REF_1_LLL 0x09A3 01630 01631 #define VL53L1_RANGING_CORE__SIGNAL_TOTAL_EVENTS_REF_1_MMM 0x09A4 01632 01633 #define VL53L1_RANGING_CORE__SIGNAL_TOTAL_EVENTS_REF_1_LMM 0x09A5 01634 01635 #define VL53L1_RANGING_CORE__SIGNAL_TOTAL_EVENTS_REF_1_LLM 0x09A6 01636 01637 #define VL53L1_RANGING_CORE__SIGNAL_TOTAL_EVENTS_REF_1_LLL 0x09A7 01638 01639 #define VL53L1_RANGING_CORE__TOTAL_PERIODS_ELAPSED_REF_1_MM 0x09A8 01640 01641 #define VL53L1_RANGING_CORE__TOTAL_PERIODS_ELAPSED_REF_1_LM 0x09A9 01642 01643 #define VL53L1_RANGING_CORE__TOTAL_PERIODS_ELAPSED_REF_1_LL 0x09AA 01644 01645 #define VL53L1_RANGING_CORE__AMBIENT_MISMATCH_REF_MM 0x09AB 01646 01647 #define VL53L1_RANGING_CORE__AMBIENT_MISMATCH_REF_LM 0x09AC 01648 01649 #define VL53L1_RANGING_CORE__AMBIENT_MISMATCH_REF_LL 0x09AD 01650 01651 #define VL53L1_RANGING_CORE__GPIO_CONFIG__A0 0x0A00 01652 01653 #define VL53L1_RANGING_CORE__RESET_CONTROL__A0 0x0A01 01654 01655 #define VL53L1_RANGING_CORE__INTR_MANAGER__A0 0x0A02 01656 01657 #define VL53L1_RANGING_CORE__POWER_FSM_TIME_OSC__A0 0x0A06 01658 01659 #define VL53L1_RANGING_CORE__VCSEL_ATEST__A0 0x0A07 01660 01661 #define VL53L1_RANGING_CORE__VCSEL_PERIOD_CLIPPED__A0 0x0A08 01662 01663 #define VL53L1_RANGING_CORE__VCSEL_STOP_CLIPPED__A0 0x0A09 01664 01665 #define VL53L1_RANGING_CORE__CALIB_2__A0 0x0A0A 01666 01667 #define VL53L1_RANGING_CORE__STOP_CONDITION__A0 0x0A0B 01668 01669 #define VL53L1_RANGING_CORE__STATUS_RESET__A0 0x0A0C 01670 01671 #define VL53L1_RANGING_CORE__READOUT_CFG__A0 0x0A0D 01672 01673 #define VL53L1_RANGING_CORE__WINDOW_SETTING__A0 0x0A0E 01674 01675 #define VL53L1_RANGING_CORE__VCSEL_DELAY__A0 0x0A1A 01676 01677 #define VL53L1_RANGING_CORE__REFERENCE_2__A0 0x0A1B 01678 01679 #define VL53L1_RANGING_CORE__REGAVDD1V2__A0 0x0A1D 01680 01681 #define VL53L1_RANGING_CORE__TST_MUX__A0 0x0A1F 01682 01683 #define VL53L1_RANGING_CORE__CUSTOM_FE_2__A0 0x0A20 01684 01685 #define VL53L1_RANGING_CORE__SPAD_READOUT__A0 0x0A21 01686 01687 #define VL53L1_RANGING_CORE__CPUMP_1__A0 0x0A22 01688 01689 #define VL53L1_RANGING_CORE__SPARE_REGISTER__A0 0x0A23 01690 01691 #define VL53L1_RANGING_CORE__VCSEL_CONT_STAGE5_BYPASS__A0 0x0A24 01692 01693 #define VL53L1_RANGING_CORE__RET_SPAD_EN_18 0x0A25 01694 01695 #define VL53L1_RANGING_CORE__RET_SPAD_EN_19 0x0A26 01696 01697 #define VL53L1_RANGING_CORE__RET_SPAD_EN_20 0x0A27 01698 01699 #define VL53L1_RANGING_CORE__RET_SPAD_EN_21 0x0A28 01700 01701 #define VL53L1_RANGING_CORE__RET_SPAD_EN_22 0x0A29 01702 01703 #define VL53L1_RANGING_CORE__RET_SPAD_EN_23 0x0A2A 01704 01705 #define VL53L1_RANGING_CORE__RET_SPAD_EN_24 0x0A2B 01706 01707 #define VL53L1_RANGING_CORE__RET_SPAD_EN_25 0x0A2C 01708 01709 #define VL53L1_RANGING_CORE__RET_SPAD_EN_26 0x0A2D 01710 01711 #define VL53L1_RANGING_CORE__RET_SPAD_EN_27 0x0A2E 01712 01713 #define VL53L1_RANGING_CORE__RET_SPAD_EN_28 0x0A2F 01714 01715 #define VL53L1_RANGING_CORE__RET_SPAD_EN_29 0x0A30 01716 01717 #define VL53L1_RANGING_CORE__RET_SPAD_EN_30 0x0A31 01718 01719 #define VL53L1_RANGING_CORE__RET_SPAD_EN_31 0x0A32 01720 01721 #define VL53L1_RANGING_CORE__REF_SPAD_EN_0__EWOK 0x0A33 01722 01723 #define VL53L1_RANGING_CORE__REF_SPAD_EN_1__EWOK 0x0A34 01724 01725 #define VL53L1_RANGING_CORE__REF_SPAD_EN_2__EWOK 0x0A35 01726 01727 #define VL53L1_RANGING_CORE__REF_SPAD_EN_3__EWOK 0x0A36 01728 01729 #define VL53L1_RANGING_CORE__REF_SPAD_EN_4__EWOK 0x0A37 01730 01731 #define VL53L1_RANGING_CORE__REF_SPAD_EN_5__EWOK 0x0A38 01732 01733 #define VL53L1_RANGING_CORE__REF_EN_START_SELECT 0x0A39 01734 01735 #define VL53L1_RANGING_CORE__REGDVDD1V2_ATEST__EWOK 0x0A41 01736 01737 #define VL53L1_SOFT_RESET_GO1 0x0B00 01738 01739 #define VL53L1_PRIVATE__PATCH_BASE_ADDR_RSLV 0x0E00 01740 01741 #define VL53L1_PREV_SHADOW_RESULT__INTERRUPT_STATUS 0x0ED0 01742 01743 #define VL53L1_PREV_SHADOW_RESULT__RANGE_STATUS 0x0ED1 01744 01745 #define VL53L1_PREV_SHADOW_RESULT__REPORT_STATUS 0x0ED2 01746 01747 #define VL53L1_PREV_SHADOW_RESULT__STREAM_COUNT 0x0ED3 01748 01749 #define VL53L1_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0 0x0ED4 01750 01751 #define VL53L1_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0ED4 01752 01753 #define VL53L1_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0ED5 01754 01755 #define VL53L1_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0 0x0ED6 01756 01757 #define VL53L1_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x0ED6 01758 01759 #define VL53L1_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x0ED7 01760 01761 #define VL53L1_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0 0x0ED8 01762 01763 #define VL53L1_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_HI 0x0ED8 01764 01765 #define VL53L1_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_LO 0x0ED9 01766 01767 #define VL53L1_PREV_SHADOW_RESULT__SIGMA_SD0 0x0EDA 01768 01769 #define VL53L1_PREV_SHADOW_RESULT__SIGMA_SD0_HI 0x0EDA 01770 01771 #define VL53L1_PREV_SHADOW_RESULT__SIGMA_SD0_LO 0x0EDB 01772 01773 #define VL53L1_PREV_SHADOW_RESULT__PHASE_SD0 0x0EDC 01774 01775 #define VL53L1_PREV_SHADOW_RESULT__PHASE_SD0_HI 0x0EDC 01776 01777 #define VL53L1_PREV_SHADOW_RESULT__PHASE_SD0_LO 0x0EDD 01778 01779 #define VL53L1_PREV_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0 0x0EDE 01780 01781 #define VL53L1_PREV__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_HI 0x0EDE 01782 01783 #define VL53L1_PREV__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_LO 0x0EDF 01784 01785 #define VL53L1_PREV__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0 0x0EE0 01786 01787 #define VL53L1_PPEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_HI 0x0EE0 01788 01789 #define VL53L1_PPEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_LO 0x0EE1 01790 01791 #define VL53L1_PREV_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0 0x0EE2 01792 01793 #define VL53L1_PREV_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0EE2 01794 01795 #define VL53L1_PREV_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0EE3 01796 01797 #define VL53L1_PREV_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0 0x0EE4 01798 01799 #define VL53L1_PREV_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0EE4 01800 01801 #define VL53L1_PREV_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0EE5 01802 01803 #define VL53L1_PREV_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0 0x0EE6 01804 01805 #define VL53L1_PREV_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x0EE6 01806 01807 #define VL53L1_PREV_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x0EE7 01808 01809 #define VL53L1_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1 0x0EE8 01810 01811 #define VL53L1_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_HI 0x0EE8 01812 01813 #define VL53L1_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_LO 0x0EE9 01814 01815 #define VL53L1_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1 0x0EEA 01816 01817 #define VL53L1_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_HI 0x0EEA 01818 01819 #define VL53L1_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_LO 0x0EEB 01820 01821 #define VL53L1_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1 0x0EEC 01822 01823 #define VL53L1_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_HI 0x0EEC 01824 01825 #define VL53L1_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_LO 0x0EED 01826 01827 #define VL53L1_PREV_SHADOW_RESULT__SIGMA_SD1 0x0EEE 01828 01829 #define VL53L1_PREV_SHADOW_RESULT__SIGMA_SD1_HI 0x0EEE 01830 01831 #define VL53L1_PREV_SHADOW_RESULT__SIGMA_SD1_LO 0x0EEF 01832 01833 #define VL53L1_PREV_SHADOW_RESULT__PHASE_SD1 0x0EF0 01834 01835 #define VL53L1_PREV_SHADOW_RESULT__PHASE_SD1_HI 0x0EF0 01836 01837 #define VL53L1_PREV_SHADOW_RESULT__PHASE_SD1_LO 0x0EF1 01838 01839 #define VL53L1_PREV_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1 0x0EF2 01840 01841 #define VL53L1_PFINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_HI 0x0EF2 01842 01843 #define VL53L1_PFINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_LO 0x0EF3 01844 01845 #define VL53L1_PREV_SHADOW_RESULT__SPARE_0_SD1 0x0EF4 01846 01847 #define VL53L1_PREV_SHADOW_RESULT__SPARE_0_SD1_HI 0x0EF4 01848 01849 #define VL53L1_PREV_SHADOW_RESULT__SPARE_0_SD1_LO 0x0EF5 01850 01851 #define VL53L1_PREV_SHADOW_RESULT__SPARE_1_SD1 0x0EF6 01852 01853 #define VL53L1_PREV_SHADOW_RESULT__SPARE_1_SD1_HI 0x0EF6 01854 01855 #define VL53L1_PREV_SHADOW_RESULT__SPARE_1_SD1_LO 0x0EF7 01856 01857 #define VL53L1_PREV_SHADOW_RESULT__SPARE_2_SD1 0x0EF8 01858 01859 #define VL53L1_PREV_SHADOW_RESULT__SPARE_2_SD1_HI 0x0EF8 01860 01861 #define VL53L1_PREV_SHADOW_RESULT__SPARE_2_SD1_LO 0x0EF9 01862 01863 #define VL53L1_PREV_SHADOW_RESULT__SPARE_3_SD1 0x0EFA 01864 01865 #define VL53L1_PREV_SHADOW_RESULT__SPARE_3_SD1_HI 0x0EFA 01866 01867 #define VL53L1_PREV_SHADOW_RESULT__SPARE_3_SD1_LO 0x0EFB 01868 01869 #define VL53L1_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0 0x0EFC 01870 01871 #define VL53L1_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_3 0x0EFC 01872 01873 #define VL53L1_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_2 0x0EFD 01874 01875 #define VL53L1_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_1 0x0EFE 01876 01877 #define VL53L1_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_0 0x0EFF 01878 01879 #define VL53L1_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0 0x0F00 01880 01881 #define VL53L1_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_3 0x0F00 01882 01883 #define VL53L1_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_2 0x0F01 01884 01885 #define VL53L1_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_1 0x0F02 01886 01887 #define VL53L1_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_0 0x0F03 01888 01889 #define VL53L1_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0 0x0F04 01890 01891 #define VL53L1_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_3 0x0F04 01892 01893 #define VL53L1_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_2 0x0F05 01894 01895 #define VL53L1_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_1 0x0F06 01896 01897 #define VL53L1_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_0 0x0F07 01898 01899 #define VL53L1_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0 0x0F08 01900 01901 #define VL53L1_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_3 0x0F08 01902 01903 #define VL53L1_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_2 0x0F09 01904 01905 #define VL53L1_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_1 0x0F0A 01906 01907 #define VL53L1_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_0 0x0F0B 01908 01909 #define VL53L1_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1 0x0F0C 01910 01911 #define VL53L1_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_3 0x0F0C 01912 01913 #define VL53L1_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_2 0x0F0D 01914 01915 #define VL53L1_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_1 0x0F0E 01916 01917 #define VL53L1_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_0 0x0F0F 01918 01919 #define VL53L1_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1 0x0F10 01920 01921 #define VL53L1_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_3 0x0F10 01922 01923 #define VL53L1_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_2 0x0F11 01924 01925 #define VL53L1_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_1 0x0F12 01926 01927 #define VL53L1_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_0 0x0F13 01928 01929 #define VL53L1_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1 0x0F14 01930 01931 #define VL53L1_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_3 0x0F14 01932 01933 #define VL53L1_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_2 0x0F15 01934 01935 #define VL53L1_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_1 0x0F16 01936 01937 #define VL53L1_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_0 0x0F17 01938 01939 #define VL53L1_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1 0x0F18 01940 01941 #define VL53L1_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_3 0x0F18 01942 01943 #define VL53L1_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_2 0x0F19 01944 01945 #define VL53L1_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_1 0x0F1A 01946 01947 #define VL53L1_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_0 0x0F1B 01948 01949 #define VL53L1_PREV_SHADOW_RESULT_CORE__SPARE_0 0x0F1C 01950 01951 #define VL53L1_RESULT__DEBUG_STATUS 0x0F20 01952 01953 #define VL53L1_RESULT__DEBUG_STAGE 0x0F21 01954 01955 #define VL53L1_GPH__SYSTEM__THRESH_RATE_HIGH 0x0F24 01956 01957 #define VL53L1_GPH__SYSTEM__THRESH_RATE_HIGH_HI 0x0F24 01958 01959 #define VL53L1_GPH__SYSTEM__THRESH_RATE_HIGH_LO 0x0F25 01960 01961 #define VL53L1_GPH__SYSTEM__THRESH_RATE_LOW 0x0F26 01962 01963 #define VL53L1_GPH__SYSTEM__THRESH_RATE_LOW_HI 0x0F26 01964 01965 #define VL53L1_GPH__SYSTEM__THRESH_RATE_LOW_LO 0x0F27 01966 01967 #define VL53L1_GPH__SYSTEM__INTERRUPT_CONFIG_GPIO 0x0F28 01968 01969 #define VL53L1_GPH__DSS_CONFIG__ROI_MODE_CONTROL 0x0F2F 01970 01971 #define VL53L1_GPH__DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT 0x0F30 01972 01973 #define VL53L1_GPH__DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT_HI 0x0F30 01974 01975 #define VL53L1_GPH__DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT_LO 0x0F31 01976 01977 #define VL53L1_GPH__DSS_CONFIG__MANUAL_BLOCK_SELECT 0x0F32 01978 01979 #define VL53L1_GPH__DSS_CONFIG__MAX_SPADS_LIMIT 0x0F33 01980 01981 #define VL53L1_GPH__DSS_CONFIG__MIN_SPADS_LIMIT 0x0F34 01982 01983 #define VL53L1_GPH__MM_CONFIG__TIMEOUT_MACROP_A_HI 0x0F36 01984 01985 #define VL53L1_GPH__MM_CONFIG__TIMEOUT_MACROP_A_LO 0x0F37 01986 01987 #define VL53L1_GPH__MM_CONFIG__TIMEOUT_MACROP_B_HI 0x0F38 01988 01989 #define VL53L1_GPH__MM_CONFIG__TIMEOUT_MACROP_B_LO 0x0F39 01990 01991 #define VL53L1_GPH__RANGE_CONFIG__TIMEOUT_MACROP_A_HI 0x0F3A 01992 01993 #define VL53L1_GPH__RANGE_CONFIG__TIMEOUT_MACROP_A_LO 0x0F3B 01994 01995 #define VL53L1_GPH__RANGE_CONFIG__VCSEL_PERIOD_A 0x0F3C 01996 01997 #define VL53L1_GPH__RANGE_CONFIG__VCSEL_PERIOD_B 0x0F3D 01998 01999 #define VL53L1_GPH__RANGE_CONFIG__TIMEOUT_MACROP_B_HI 0x0F3E 02000 02001 #define VL53L1_GPH__RANGE_CONFIG__TIMEOUT_MACROP_B_LO 0x0F3F 02002 02003 #define VL53L1_GPH__RANGE_CONFIG__SIGMA_THRESH 0x0F40 02004 02005 #define VL53L1_GPH__RANGE_CONFIG__SIGMA_THRESH_HI 0x0F40 02006 02007 #define VL53L1_GPH__RANGE_CONFIG__SIGMA_THRESH_LO 0x0F41 02008 02009 #define VL53L1_GPH__RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS 0x0F42 02010 02011 #define VL53L1_GPH__RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS_HI 0x0F42 02012 02013 #define VL53L1_GPH__RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS_LO 0x0F43 02014 02015 #define VL53L1_GPH__RANGE_CONFIG__VALID_PHASE_LOW 0x0F44 02016 02017 #define VL53L1_GPH__RANGE_CONFIG__VALID_PHASE_HIGH 0x0F45 02018 02019 #define VL53L1_FIRMWARE__INTERNAL_STREAM_COUNT_DIV 0x0F46 02020 02021 #define VL53L1_FIRMWARE__INTERNAL_STREAM_COUNTER_VAL 0x0F47 02022 02023 #define VL53L1_DSS_CALC__ROI_CTRL 0x0F54 02024 02025 #define VL53L1_DSS_CALC__SPARE_1 0x0F55 02026 02027 #define VL53L1_DSS_CALC__SPARE_2 0x0F56 02028 02029 #define VL53L1_DSS_CALC__SPARE_3 0x0F57 02030 02031 #define VL53L1_DSS_CALC__SPARE_4 0x0F58 02032 02033 #define VL53L1_DSS_CALC__SPARE_5 0x0F59 02034 02035 #define VL53L1_DSS_CALC__SPARE_6 0x0F5A 02036 02037 #define VL53L1_DSS_CALC__SPARE_7 0x0F5B 02038 02039 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_0 0x0F5C 02040 02041 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_1 0x0F5D 02042 02043 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_2 0x0F5E 02044 02045 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_3 0x0F5F 02046 02047 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_4 0x0F60 02048 02049 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_5 0x0F61 02050 02051 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_6 0x0F62 02052 02053 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_7 0x0F63 02054 02055 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_8 0x0F64 02056 02057 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_9 0x0F65 02058 02059 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_10 0x0F66 02060 02061 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_11 0x0F67 02062 02063 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_12 0x0F68 02064 02065 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_13 0x0F69 02066 02067 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_14 0x0F6A 02068 02069 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_15 0x0F6B 02070 02071 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_16 0x0F6C 02072 02073 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_17 0x0F6D 02074 02075 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_18 0x0F6E 02076 02077 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_19 0x0F6F 02078 02079 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_20 0x0F70 02080 02081 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_21 0x0F71 02082 02083 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_22 0x0F72 02084 02085 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_23 0x0F73 02086 02087 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_24 0x0F74 02088 02089 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_25 0x0F75 02090 02091 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_26 0x0F76 02092 02093 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_27 0x0F77 02094 02095 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_28 0x0F78 02096 02097 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_29 0x0F79 02098 02099 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_30 0x0F7A 02100 02101 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_31 0x0F7B 02102 02103 #define VL53L1_DSS_CALC__USER_ROI_0 0x0F7C 02104 02105 #define VL53L1_DSS_CALC__USER_ROI_1 0x0F7D 02106 02107 #define VL53L1_DSS_CALC__MODE_ROI_0 0x0F7E 02108 02109 #define VL53L1_DSS_CALC__MODE_ROI_1 0x0F7F 02110 02111 #define VL53L1_SIGMA_ESTIMATOR_CALC__SPARE_0 0x0F80 02112 02113 #define VL53L1_VHV_RESULT__PEAK_SIGNAL_RATE_MCPS 0x0F82 02114 02115 #define VL53L1_VHV_RESULT__PEAK_SIGNAL_RATE_MCPS_HI 0x0F82 02116 02117 #define VL53L1_VHV_RESULT__PEAK_SIGNAL_RATE_MCPS_LO 0x0F83 02118 02119 #define VL53L1_VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF 0x0F84 02120 02121 #define VL53L1_VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF_3 0x0F84 02122 02123 #define VL53L1_VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF_2 0x0F85 02124 02125 #define VL53L1_VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF_1 0x0F86 02126 02127 #define VL53L1_VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF_0 0x0F87 02128 02129 #define VL53L1_PHASECAL_RESULT__PHASE_OUTPUT_REF 0x0F88 02130 02131 #define VL53L1_PHASECAL_RESULT__PHASE_OUTPUT_REF_HI 0x0F88 02132 02133 #define VL53L1_PHASECAL_RESULT__PHASE_OUTPUT_REF_LO 0x0F89 02134 02135 #define VL53L1_DSS_RESULT__TOTAL_RATE_PER_SPAD 0x0F8A 02136 02137 #define VL53L1_DSS_RESULT__TOTAL_RATE_PER_SPAD_HI 0x0F8A 02138 02139 #define VL53L1_DSS_RESULT__TOTAL_RATE_PER_SPAD_LO 0x0F8B 02140 02141 #define VL53L1_DSS_RESULT__ENABLED_BLOCKS 0x0F8C 02142 02143 #define VL53L1_DSS_RESULT__NUM_REQUESTED_SPADS 0x0F8E 02144 02145 #define VL53L1_DSS_RESULT__NUM_REQUESTED_SPADS_HI 0x0F8E 02146 02147 #define VL53L1_DSS_RESULT__NUM_REQUESTED_SPADS_LO 0x0F8F 02148 02149 #define VL53L1_MM_RESULT__INNER_INTERSECTION_RATE 0x0F92 02150 02151 #define VL53L1_MM_RESULT__INNER_INTERSECTION_RATE_HI 0x0F92 02152 02153 #define VL53L1_MM_RESULT__INNER_INTERSECTION_RATE_LO 0x0F93 02154 02155 #define VL53L1_MM_RESULT__OUTER_COMPLEMENT_RATE 0x0F94 02156 02157 #define VL53L1_MM_RESULT__OUTER_COMPLEMENT_RATE_HI 0x0F94 02158 02159 #define VL53L1_MM_RESULT__OUTER_COMPLEMENT_RATE_LO 0x0F95 02160 02161 #define VL53L1_MM_RESULT__TOTAL_OFFSET 0x0F96 02162 02163 #define VL53L1_MM_RESULT__TOTAL_OFFSET_HI 0x0F96 02164 02165 #define VL53L1_MM_RESULT__TOTAL_OFFSET_LO 0x0F97 02166 02167 #define VL53L1_XTALK_CALC__XTALK_FOR_ENABLED_SPADS 0x0F98 02168 02169 #define VL53L1_XTALK_CALC__XTALK_FOR_ENABLED_SPADS_3 0x0F98 02170 02171 #define VL53L1_XTALK_CALC__XTALK_FOR_ENABLED_SPADS_2 0x0F99 02172 02173 #define VL53L1_XTALK_CALC__XTALK_FOR_ENABLED_SPADS_1 0x0F9A 02174 02175 #define VL53L1_XTALK_CALC__XTALK_FOR_ENABLED_SPADS_0 0x0F9B 02176 02177 #define VL53L1_XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS 0x0F9C 02178 02179 #define VL53L1_XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS_3 0x0F9C 02180 02181 #define VL53L1_XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS_2 0x0F9D 02182 02183 #define VL53L1_XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS_1 0x0F9E 02184 02185 #define VL53L1_XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS_0 0x0F9F 02186 02187 #define VL53L1_XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS 0x0FA0 02188 02189 #define VL53L1_XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS_3 0x0FA0 02190 02191 #define VL53L1_XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS_2 0x0FA1 02192 02193 #define VL53L1_XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS_1 0x0FA2 02194 02195 #define VL53L1_XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS_0 0x0FA3 02196 02197 #define VL53L1_XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS 0x0FA4 02198 02199 #define VL53L1_XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS_3 0x0FA4 02200 02201 #define VL53L1_XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS_2 0x0FA5 02202 02203 #define VL53L1_XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS_1 0x0FA6 02204 02205 #define VL53L1_XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS_0 0x0FA7 02206 02207 #define VL53L1_RANGE_RESULT__ACCUM_PHASE 0x0FA8 02208 02209 #define VL53L1_RANGE_RESULT__ACCUM_PHASE_3 0x0FA8 02210 02211 #define VL53L1_RANGE_RESULT__ACCUM_PHASE_2 0x0FA9 02212 02213 #define VL53L1_RANGE_RESULT__ACCUM_PHASE_1 0x0FAA 02214 02215 #define VL53L1_RANGE_RESULT__ACCUM_PHASE_0 0x0FAB 02216 02217 #define VL53L1_RANGE_RESULT__OFFSET_CORRECTED_RANGE 0x0FAC 02218 02219 #define VL53L1_RANGE_RESULT__OFFSET_CORRECTED_RANGE_HI 0x0FAC 02220 02221 #define VL53L1_RANGE_RESULT__OFFSET_CORRECTED_RANGE_LO 0x0FAD 02222 02223 #define VL53L1_SHADOW_PHASECAL_RESULT__VCSEL_START 0x0FAE 02224 02225 #define VL53L1_SHADOW_RESULT__INTERRUPT_STATUS 0x0FB0 02226 02227 #define VL53L1_SHADOW_RESULT__RANGE_STATUS 0x0FB1 02228 02229 #define VL53L1_SHADOW_RESULT__REPORT_STATUS 0x0FB2 02230 02231 #define VL53L1_SHADOW_RESULT__STREAM_COUNT 0x0FB3 02232 02233 #define VL53L1_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0 0x0FB4 02234 02235 #define VL53L1_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0FB4 02236 02237 #define VL53L1_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0FB5 02238 02239 #define VL53L1_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0 0x0FB6 02240 02241 #define VL53L1_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x0FB6 02242 02243 #define VL53L1_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x0FB7 02244 02245 #define VL53L1_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0 0x0FB8 02246 02247 #define VL53L1_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_HI 0x0FB8 02248 02249 #define VL53L1_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_LO 0x0FB9 02250 02251 #define VL53L1_SHADOW_RESULT__SIGMA_SD0 0x0FBA 02252 02253 #define VL53L1_SHADOW_RESULT__SIGMA_SD0_HI 0x0FBA 02254 02255 #define VL53L1_SHADOW_RESULT__SIGMA_SD0_LO 0x0FBB 02256 02257 #define VL53L1_SHADOW_RESULT__PHASE_SD0 0x0FBC 02258 02259 #define VL53L1_SHADOW_RESULT__PHASE_SD0_HI 0x0FBC 02260 02261 #define VL53L1_SHADOW_RESULT__PHASE_SD0_LO 0x0FBD 02262 02263 #define VL53L1_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0 0x0FBE 02264 02265 #define VL53L1_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_HI 0x0FBE 02266 02267 #define VL53L1_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_LO 0x0FBF 02268 02269 #define VL53L1_SHPEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0 0x0FC0 02270 02271 #define VL53L1_SHPEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_HI 0x0FC0 02272 02273 #define VL53L1_SHPEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_LO 0x0FC1 02274 02275 #define VL53L1_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0 0x0FC2 02276 02277 #define VL53L1_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0FC2 02278 02279 #define VL53L1_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0FC3 02280 02281 #define VL53L1_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0 0x0FC4 02282 02283 #define VL53L1_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0FC4 02284 02285 #define VL53L1_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0FC5 02286 02287 #define VL53L1_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0 0x0FC6 02288 02289 #define VL53L1_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x0FC6 02290 02291 #define VL53L1_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x0FC7 02292 02293 #define VL53L1_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1 0x0FC8 02294 02295 #define VL53L1_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_HI 0x0FC8 02296 02297 #define VL53L1_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_LO 0x0FC9 02298 02299 #define VL53L1_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1 0x0FCA 02300 02301 #define VL53L1_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_HI 0x0FCA 02302 02303 #define VL53L1_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_LO 0x0FCB 02304 02305 #define VL53L1_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1 0x0FCC 02306 02307 #define VL53L1_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_HI 0x0FCC 02308 02309 #define VL53L1_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_LO 0x0FCD 02310 02311 #define VL53L1_SHADOW_RESULT__SIGMA_SD1 0x0FCE 02312 02313 #define VL53L1_SHADOW_RESULT__SIGMA_SD1_HI 0x0FCE 02314 02315 #define VL53L1_SHADOW_RESULT__SIGMA_SD1_LO 0x0FCF 02316 02317 #define VL53L1_SHADOW_RESULT__PHASE_SD1 0x0FD0 02318 02319 #define VL53L1_SHADOW_RESULT__PHASE_SD1_HI 0x0FD0 02320 02321 #define VL53L1_SHADOW_RESULT__PHASE_SD1_LO 0x0FD1 02322 02323 #define VL53L1_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1 0x0FD2 02324 02325 #define VL53L1_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_HI 0x0FD2 02326 02327 #define VL53L1_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_LO 0x0FD3 02328 02329 #define VL53L1_SHADOW_RESULT__SPARE_0_SD1 0x0FD4 02330 02331 #define VL53L1_SHADOW_RESULT__SPARE_0_SD1_HI 0x0FD4 02332 02333 #define VL53L1_SHADOW_RESULT__SPARE_0_SD1_LO 0x0FD5 02334 02335 #define VL53L1_SHADOW_RESULT__SPARE_1_SD1 0x0FD6 02336 02337 #define VL53L1_SHADOW_RESULT__SPARE_1_SD1_HI 0x0FD6 02338 02339 #define VL53L1_SHADOW_RESULT__SPARE_1_SD1_LO 0x0FD7 02340 02341 #define VL53L1_SHADOW_RESULT__SPARE_2_SD1 0x0FD8 02342 02343 #define VL53L1_SHADOW_RESULT__SPARE_2_SD1_HI 0x0FD8 02344 02345 #define VL53L1_SHADOW_RESULT__SPARE_2_SD1_LO 0x0FD9 02346 02347 #define VL53L1_SHADOW_RESULT__SPARE_3_SD1 0x0FDA 02348 02349 #define VL53L1_SHADOW_RESULT__THRESH_INFO 0x0FDB 02350 02351 #define VL53L1_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0 0x0FDC 02352 02353 #define VL53L1_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_3 0x0FDC 02354 02355 #define VL53L1_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_2 0x0FDD 02356 02357 #define VL53L1_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_1 0x0FDE 02358 02359 #define VL53L1_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_0 0x0FDF 02360 02361 #define VL53L1_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0 0x0FE0 02362 02363 #define VL53L1_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_3 0x0FE0 02364 02365 #define VL53L1_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_2 0x0FE1 02366 02367 #define VL53L1_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_1 0x0FE2 02368 02369 #define VL53L1_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_0 0x0FE3 02370 02371 #define VL53L1_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0 0x0FE4 02372 02373 #define VL53L1_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_3 0x0FE4 02374 02375 #define VL53L1_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_2 0x0FE5 02376 02377 #define VL53L1_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_1 0x0FE6 02378 02379 #define VL53L1_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_0 0x0FE7 02380 02381 #define VL53L1_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0 0x0FE8 02382 02383 #define VL53L1_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_3 0x0FE8 02384 02385 #define VL53L1_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_2 0x0FE9 02386 02387 #define VL53L1_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_1 0x0FEA 02388 02389 #define VL53L1_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_0 0x0FEB 02390 02391 #define VL53L1_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1 0x0FEC 02392 02393 #define VL53L1_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_3 0x0FEC 02394 02395 #define VL53L1_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_2 0x0FED 02396 02397 #define VL53L1_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_1 0x0FEE 02398 02399 #define VL53L1_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_0 0x0FEF 02400 02401 #define VL53L1_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1 0x0FF0 02402 02403 #define VL53L1_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_3 0x0FF0 02404 02405 #define VL53L1_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_2 0x0FF1 02406 02407 #define VL53L1_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_1 0x0FF2 02408 02409 #define VL53L1_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_0 0x0FF3 02410 02411 #define VL53L1_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1 0x0FF4 02412 02413 #define VL53L1_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_3 0x0FF4 02414 02415 #define VL53L1_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_2 0x0FF5 02416 02417 #define VL53L1_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_1 0x0FF6 02418 02419 #define VL53L1_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_0 0x0FF7 02420 02421 #define VL53L1_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1 0x0FF8 02422 02423 #define VL53L1_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_3 0x0FF8 02424 02425 #define VL53L1_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_2 0x0FF9 02426 02427 #define VL53L1_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_1 0x0FFA 02428 02429 #define VL53L1_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_0 0x0FFB 02430 02431 #define VL53L1_SHADOW_RESULT_CORE__SPARE_0 0x0FFC 02432 02433 #define VL53L1_SHADOW_PHASECAL_RESULT__REFERENCE_PHASE_HI 0x0FFE 02434 02435 #define VL53L1_SHADOW_PHASECAL_RESULT__REFERENCE_PHASE_LO 0x0FFF 02436 02437 02438 02439 02440 02441 #endif 02442 02443 02444
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