charles macneill
Initial release. Mbed library for VL53L1CB
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vl53l1_api_preset_modes.c
00001 00002 /******************************************************************************* 00003 * Copyright (c) 2020, STMicroelectronics - All Rights Reserved 00004 00005 This file is part of VL53L1 Core and is dual licensed, 00006 either 'STMicroelectronics 00007 Proprietary license' 00008 or 'BSD 3-clause "New" or "Revised" License' , at your option. 00009 00010 ******************************************************************************** 00011 00012 'STMicroelectronics Proprietary license' 00013 00014 ******************************************************************************** 00015 00016 License terms: STMicroelectronics Proprietary in accordance with licensing 00017 terms at www.st.com/sla0081 00018 00019 STMicroelectronics confidential 00020 Reproduction and Communication of this document is strictly prohibited unless 00021 specifically authorized in writing by STMicroelectronics. 00022 00023 00024 ******************************************************************************** 00025 00026 Alternatively, VL53L1 Core may be distributed under the terms of 00027 'BSD 3-clause "New" or "Revised" License', in which case the following 00028 provisions apply instead of the ones 00029 mentioned above : 00030 00031 ******************************************************************************** 00032 00033 License terms: BSD 3-clause "New" or "Revised" License. 00034 00035 Redistribution and use in source and binary forms, with or without 00036 modification, are permitted provided that the following conditions are met: 00037 00038 1. Redistributions of source code must retain the above copyright notice, this 00039 list of conditions and the following disclaimer. 00040 00041 2. Redistributions in binary form must reproduce the above copyright notice, 00042 this list of conditions and the following disclaimer in the documentation 00043 and/or other materials provided with the distribution. 00044 00045 3. Neither the name of the copyright holder nor the names of its contributors 00046 may be used to endorse or promote products derived from this software 00047 without specific prior written permission. 00048 00049 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00050 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00051 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00052 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00053 FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00054 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00055 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00056 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00057 OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00058 OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00059 00060 00061 ******************************************************************************** 00062 00063 */ 00064 00065 00066 00067 00068 #include "vl53l1_ll_def.h" 00069 #include "vl53l1_platform_log.h" 00070 #include "vl53l1_register_structs.h" 00071 #include "vl53l1_register_settings.h" 00072 #include "vl53l1_hist_structs.h" 00073 #include "vl53l1_zone_presets.h" 00074 #include "vl53l1_core.h" 00075 #include "vl53l1_api_preset_modes.h" 00076 #include "vl53l1_tuning_parm_defaults.h" 00077 00078 00079 #define LOG_FUNCTION_START(fmt, ...) \ 00080 _LOG_FUNCTION_START(VL53L1_TRACE_MODULE_API, fmt, ##__VA_ARGS__) 00081 #define LOG_FUNCTION_END(status, ...) \ 00082 _LOG_FUNCTION_END(VL53L1_TRACE_MODULE_API, status, ##__VA_ARGS__) 00083 #define LOG_FUNCTION_END_FMT(status, fmt, ...) \ 00084 _LOG_FUNCTION_END_FMT(VL53L1_TRACE_MODULE_API,\ 00085 status, fmt, ##__VA_ARGS__) 00086 00087 00088 VL53L1_Error VL53L1_init_refspadchar_config_struct( 00089 VL53L1_refspadchar_config_t *pdata) 00090 { 00091 00092 00093 VL53L1_Error status = VL53L1_ERROR_NONE; 00094 00095 LOG_FUNCTION_START(""); 00096 00097 00098 00099 pdata->device_test_mode = 00100 VL53L1_TUNINGPARM_REFSPADCHAR_DEVICE_TEST_MODE_DEFAULT; 00101 pdata->VL53L1_p_009 = 00102 VL53L1_TUNINGPARM_REFSPADCHAR_VCSEL_PERIOD_DEFAULT; 00103 pdata->timeout_us = 00104 VL53L1_TUNINGPARM_REFSPADCHAR_PHASECAL_TIMEOUT_US_DEFAULT; 00105 pdata->target_count_rate_mcps = 00106 VL53L1_TUNINGPARM_REFSPADCHAR_TARGET_COUNT_RATE_MCPS_DEFAULT; 00107 pdata->min_count_rate_limit_mcps = 00108 VL53L1_TUNINGPARM_REFSPADCHAR_MIN_COUNTRATE_LIMIT_MCPS_DEFAULT; 00109 pdata->max_count_rate_limit_mcps = 00110 VL53L1_TUNINGPARM_REFSPADCHAR_MAX_COUNTRATE_LIMIT_MCPS_DEFAULT; 00111 00112 LOG_FUNCTION_END(status); 00113 00114 return status; 00115 } 00116 00117 00118 VL53L1_Error VL53L1_init_ssc_config_struct( 00119 VL53L1_ssc_config_t *pdata) 00120 { 00121 00122 00123 VL53L1_Error status = VL53L1_ERROR_NONE; 00124 00125 LOG_FUNCTION_START(""); 00126 00127 00128 00129 00130 pdata->array_select = VL53L1_DEVICESSCARRAY_RTN; 00131 00132 00133 pdata->VL53L1_p_009 = 00134 VL53L1_TUNINGPARM_SPADMAP_VCSEL_PERIOD_DEFAULT; 00135 00136 00137 pdata->vcsel_start = 00138 VL53L1_TUNINGPARM_SPADMAP_VCSEL_START_DEFAULT; 00139 00140 00141 pdata->vcsel_width = 0x02; 00142 00143 00144 pdata->timeout_us = 36000; 00145 00146 00147 pdata->rate_limit_mcps = 00148 VL53L1_TUNINGPARM_SPADMAP_RATE_LIMIT_MCPS_DEFAULT; 00149 00150 LOG_FUNCTION_END(status); 00151 00152 return status; 00153 } 00154 00155 00156 VL53L1_Error VL53L1_init_xtalk_config_struct( 00157 VL53L1_customer_nvm_managed_t *pnvm, 00158 VL53L1_xtalk_config_t *pdata) 00159 { 00160 00161 00162 VL53L1_Error status = VL53L1_ERROR_NONE; 00163 00164 LOG_FUNCTION_START(""); 00165 00166 00167 00168 00169 00170 pdata->algo__crosstalk_compensation_plane_offset_kcps = 00171 pnvm->algo__crosstalk_compensation_plane_offset_kcps; 00172 pdata->algo__crosstalk_compensation_x_plane_gradient_kcps = 00173 pnvm->algo__crosstalk_compensation_x_plane_gradient_kcps; 00174 pdata->algo__crosstalk_compensation_y_plane_gradient_kcps = 00175 pnvm->algo__crosstalk_compensation_y_plane_gradient_kcps; 00176 00177 00178 00179 pdata->nvm_default__crosstalk_compensation_plane_offset_kcps = 00180 (uint32_t)pnvm->algo__crosstalk_compensation_plane_offset_kcps; 00181 pdata->nvm_default__crosstalk_compensation_x_plane_gradient_kcps = 00182 pnvm->algo__crosstalk_compensation_x_plane_gradient_kcps; 00183 pdata->nvm_default__crosstalk_compensation_y_plane_gradient_kcps = 00184 pnvm->algo__crosstalk_compensation_y_plane_gradient_kcps; 00185 00186 pdata->histogram_mode_crosstalk_margin_kcps = 00187 VL53L1_TUNINGPARM_HIST_XTALK_MARGIN_KCPS_DEFAULT; 00188 pdata->lite_mode_crosstalk_margin_kcps = 00189 VL53L1_TUNINGPARM_LITE_XTALK_MARGIN_KCPS_DEFAULT; 00190 00191 00192 00193 pdata->crosstalk_range_ignore_threshold_mult = 00194 VL53L1_TUNINGPARM_LITE_RIT_MULT_DEFAULT; 00195 00196 if ((pdata->algo__crosstalk_compensation_plane_offset_kcps == 0x00) 00197 && (pdata->algo__crosstalk_compensation_x_plane_gradient_kcps 00198 == 0x00) 00199 && (pdata->algo__crosstalk_compensation_y_plane_gradient_kcps 00200 == 0x00)) 00201 pdata->global_crosstalk_compensation_enable = 0x00; 00202 else 00203 pdata->global_crosstalk_compensation_enable = 0x01; 00204 00205 00206 if ((status == VL53L1_ERROR_NONE) && 00207 (pdata->global_crosstalk_compensation_enable == 0x01)) { 00208 pdata->crosstalk_range_ignore_threshold_rate_mcps = 00209 VL53L1_calc_range_ignore_threshold( 00210 pdata->algo__crosstalk_compensation_plane_offset_kcps, 00211 pdata->algo__crosstalk_compensation_x_plane_gradient_kcps, 00212 pdata->algo__crosstalk_compensation_y_plane_gradient_kcps, 00213 pdata->crosstalk_range_ignore_threshold_mult); 00214 } else { 00215 pdata->crosstalk_range_ignore_threshold_rate_mcps = 0; 00216 } 00217 00218 00219 00220 00221 pdata->algo__crosstalk_detect_min_valid_range_mm = 00222 VL53L1_TUNINGPARM_XTALK_DETECT_MIN_VALID_RANGE_MM_DEFAULT; 00223 pdata->algo__crosstalk_detect_max_valid_range_mm = 00224 VL53L1_TUNINGPARM_XTALK_DETECT_MAX_VALID_RANGE_MM_DEFAULT; 00225 pdata->algo__crosstalk_detect_max_valid_rate_kcps = 00226 VL53L1_TUNINGPARM_XTALK_DETECT_MAX_VALID_RATE_KCPS_DEFAULT; 00227 pdata->algo__crosstalk_detect_max_sigma_mm = 00228 VL53L1_TUNINGPARM_XTALK_DETECT_MAX_SIGMA_MM_DEFAULT; 00229 00230 LOG_FUNCTION_END(status); 00231 00232 return status; 00233 } 00234 00235 VL53L1_Error VL53L1_init_xtalk_extract_config_struct( 00236 VL53L1_xtalkextract_config_t *pdata) 00237 { 00238 00239 00240 VL53L1_Error status = VL53L1_ERROR_NONE; 00241 00242 LOG_FUNCTION_START(""); 00243 00244 00245 00246 pdata->dss_config__target_total_rate_mcps = 00247 VL53L1_TUNINGPARM_XTALK_EXTRACT_DSS_RATE_MCPS_DEFAULT; 00248 00249 pdata->mm_config_timeout_us = 00250 VL53L1_TUNINGPARM_XTALK_EXTRACT_DSS_TIMEOUT_US_DEFAULT; 00251 00252 pdata->num_of_samples = 00253 VL53L1_TUNINGPARM_XTALK_EXTRACT_NUM_OF_SAMPLES_DEFAULT; 00254 00255 pdata->phasecal_config_timeout_us = 00256 VL53L1_TUNINGPARM_XTALK_EXTRACT_PHASECAL_TIMEOUT_US_DEFAULT; 00257 00258 pdata->range_config_timeout_us = 00259 VL53L1_TUNINGPARM_XTALK_EXTRACT_BIN_TIMEOUT_US_DEFAULT; 00260 00261 00262 00263 00264 pdata->algo__crosstalk_extract_min_valid_range_mm = 00265 VL53L1_TUNINGPARM_XTALK_EXTRACT_MIN_FILTER_THRESH_MM_DEFAULT; 00266 pdata->algo__crosstalk_extract_max_valid_range_mm = 00267 VL53L1_TUNINGPARM_XTALK_EXTRACT_MAX_FILTER_THRESH_MM_DEFAULT; 00268 pdata->algo__crosstalk_extract_max_valid_rate_kcps = 00269 VL53L1_TUNINGPARM_XTALK_EXTRACT_MAX_VALID_RATE_KCPS_DEFAULT; 00270 pdata->algo__crosstalk_extract_max_sigma_mm = 00271 VL53L1_TUNINGPARM_XTALK_EXTRACT_SIGMA_THRESHOLD_MM_DEFAULT; 00272 00273 00274 LOG_FUNCTION_END(status); 00275 00276 return status; 00277 } 00278 00279 00280 VL53L1_Error VL53L1_init_offset_cal_config_struct( 00281 VL53L1_offsetcal_config_t *pdata) 00282 { 00283 00284 00285 VL53L1_Error status = VL53L1_ERROR_NONE; 00286 00287 LOG_FUNCTION_START(""); 00288 00289 00290 00291 pdata->dss_config__target_total_rate_mcps = 00292 VL53L1_TUNINGPARM_OFFSET_CAL_DSS_RATE_MCPS_DEFAULT; 00293 00294 pdata->phasecal_config_timeout_us = 00295 VL53L1_TUNINGPARM_OFFSET_CAL_PHASECAL_TIMEOUT_US_DEFAULT; 00296 00297 pdata->range_config_timeout_us = 00298 VL53L1_TUNINGPARM_OFFSET_CAL_RANGE_TIMEOUT_US_DEFAULT; 00299 00300 pdata->mm_config_timeout_us = 00301 VL53L1_TUNINGPARM_OFFSET_CAL_MM_TIMEOUT_US_DEFAULT; 00302 00303 00304 00305 00306 pdata->pre_num_of_samples = 00307 VL53L1_TUNINGPARM_OFFSET_CAL_PRE_SAMPLES_DEFAULT; 00308 pdata->mm1_num_of_samples = 00309 VL53L1_TUNINGPARM_OFFSET_CAL_MM1_SAMPLES_DEFAULT; 00310 pdata->mm2_num_of_samples = 00311 VL53L1_TUNINGPARM_OFFSET_CAL_MM2_SAMPLES_DEFAULT; 00312 00313 LOG_FUNCTION_END(status); 00314 00315 return status; 00316 } 00317 00318 VL53L1_Error VL53L1_init_zone_cal_config_struct( 00319 VL53L1_zonecal_config_t *pdata) 00320 { 00321 00322 00323 VL53L1_Error status = VL53L1_ERROR_NONE; 00324 00325 LOG_FUNCTION_START(""); 00326 00327 00328 00329 pdata->dss_config__target_total_rate_mcps = 00330 VL53L1_TUNINGPARM_ZONE_CAL_DSS_RATE_MCPS_DEFAULT; 00331 00332 pdata->phasecal_config_timeout_us = 00333 VL53L1_TUNINGPARM_ZONE_CAL_PHASECAL_TIMEOUT_US_DEFAULT; 00334 00335 pdata->range_config_timeout_us = 00336 VL53L1_TUNINGPARM_ZONE_CAL_RANGE_TIMEOUT_US_DEFAULT; 00337 00338 pdata->mm_config_timeout_us = 00339 VL53L1_TUNINGPARM_ZONE_CAL_DSS_TIMEOUT_US_DEFAULT; 00340 00341 00342 00343 00344 pdata->phasecal_num_of_samples = 00345 VL53L1_TUNINGPARM_ZONE_CAL_PHASECAL_NUM_SAMPLES_DEFAULT; 00346 pdata->zone_num_of_samples = 00347 VL53L1_TUNINGPARM_ZONE_CAL_ZONE_NUM_SAMPLES_DEFAULT; 00348 00349 LOG_FUNCTION_END(status); 00350 00351 return status; 00352 } 00353 00354 00355 VL53L1_Error VL53L1_init_hist_post_process_config_struct( 00356 uint8_t xtalk_compensation_enable, 00357 VL53L1_hist_post_process_config_t *pdata) 00358 { 00359 00360 00361 VL53L1_Error status = VL53L1_ERROR_NONE; 00362 00363 LOG_FUNCTION_START(""); 00364 00365 00366 00367 pdata->hist_algo_select = 00368 VL53L1_TUNINGPARM_HIST_ALGO_SELECT_DEFAULT; 00369 00370 00371 00372 pdata->hist_target_order = 00373 VL53L1_TUNINGPARM_HIST_TARGET_ORDER_DEFAULT; 00374 00375 00376 00377 pdata->filter_woi0 = 00378 VL53L1_TUNINGPARM_HIST_FILTER_WOI_0_DEFAULT; 00379 pdata->filter_woi1 = 00380 VL53L1_TUNINGPARM_HIST_FILTER_WOI_1_DEFAULT; 00381 00382 00383 pdata->hist_amb_est_method = 00384 VL53L1_TUNINGPARM_HIST_AMB_EST_METHOD_DEFAULT; 00385 00386 pdata->ambient_thresh_sigma0 = 00387 VL53L1_TUNINGPARM_HIST_AMB_THRESH_SIGMA_0_DEFAULT; 00388 pdata->ambient_thresh_sigma1 = 00389 VL53L1_TUNINGPARM_HIST_AMB_THRESH_SIGMA_1_DEFAULT; 00390 00391 00392 pdata->ambient_thresh_events_scaler = 00393 VL53L1_TUNINGPARM_HIST_AMB_EVENTS_SCALER_DEFAULT; 00394 00395 00396 pdata->min_ambient_thresh_events = 00397 VL53L1_TUNINGPARM_HIST_MIN_AMB_THRESH_EVENTS_DEFAULT; 00398 00399 pdata->noise_threshold = 00400 VL53L1_TUNINGPARM_HIST_NOISE_THRESHOLD_DEFAULT; 00401 00402 pdata->signal_total_events_limit = 00403 VL53L1_TUNINGPARM_HIST_SIGNAL_TOTAL_EVENTS_LIMIT_DEFAULT; 00404 pdata->sigma_estimator__sigma_ref_mm = 00405 VL53L1_TUNINGPARM_HIST_SIGMA_EST_REF_MM_DEFAULT; 00406 00407 00408 pdata->sigma_thresh = 00409 VL53L1_TUNINGPARM_HIST_SIGMA_THRESH_MM_DEFAULT; 00410 00411 pdata->range_offset_mm = 0; 00412 00413 pdata->gain_factor = 00414 VL53L1_TUNINGPARM_HIST_GAIN_FACTOR_DEFAULT; 00415 00416 00417 00418 pdata->valid_phase_low = 0x08; 00419 pdata->valid_phase_high = 0x88; 00420 00421 00422 00423 pdata->algo__consistency_check__phase_tolerance = 00424 VL53L1_TUNINGPARM_CONSISTENCY_HIST_PHASE_TOLERANCE_DEFAULT; 00425 00426 00427 00428 pdata->algo__consistency_check__event_sigma = 00429 VL53L1_TUNINGPARM_CONSISTENCY_HIST_EVENT_SIGMA_DEFAULT; 00430 00431 00432 pdata->algo__consistency_check__event_min_spad_count = 00433 VL53L1_TUNINGPARM_CONSISTENCY_HIST_EVENT_SIGMA_MIN_SPAD_LIMIT_DEFAULT; 00434 00435 00436 00437 pdata->algo__consistency_check__min_max_tolerance = 00438 VL53L1_TUNINGPARM_CONSISTENCY_HIST_MIN_MAX_TOLERANCE_MM_DEFAULT; 00439 00440 00441 pdata->algo__crosstalk_compensation_enable = xtalk_compensation_enable; 00442 00443 00444 pdata->algo__crosstalk_detect_min_valid_range_mm = 00445 VL53L1_TUNINGPARM_XTALK_DETECT_MIN_VALID_RANGE_MM_DEFAULT; 00446 pdata->algo__crosstalk_detect_max_valid_range_mm = 00447 VL53L1_TUNINGPARM_XTALK_DETECT_MAX_VALID_RANGE_MM_DEFAULT; 00448 pdata->algo__crosstalk_detect_max_valid_rate_kcps = 00449 VL53L1_TUNINGPARM_XTALK_DETECT_MAX_VALID_RATE_KCPS_DEFAULT; 00450 pdata->algo__crosstalk_detect_max_sigma_mm = 00451 VL53L1_TUNINGPARM_XTALK_DETECT_MAX_SIGMA_MM_DEFAULT; 00452 00453 00454 00455 00456 00457 pdata->algo__crosstalk_detect_event_sigma = 00458 VL53L1_TUNINGPARM_XTALK_DETECT_EVENT_SIGMA_DEFAULT; 00459 00460 00461 00462 pdata->algo__crosstalk_detect_min_max_tolerance = 00463 VL53L1_TUNINGPARM_XTALK_DETECT_MIN_MAX_TOLERANCE_DEFAULT; 00464 00465 00466 00467 LOG_FUNCTION_END(status); 00468 00469 return status; 00470 } 00471 00472 00473 VL53L1_Error VL53L1_init_dmax_calibration_data_struct( 00474 VL53L1_dmax_calibration_data_t *pdata) 00475 { 00476 00477 00478 VL53L1_Error status = VL53L1_ERROR_NONE; 00479 00480 LOG_FUNCTION_START(""); 00481 00482 00483 00484 00485 pdata->ref__actual_effective_spads = 0x5F2D; 00486 00487 pdata->ref__peak_signal_count_rate_mcps = 0x0844; 00488 00489 pdata->ref__distance_mm = 0x08A5; 00490 00491 00492 pdata->ref_reflectance_pc = 0x0014; 00493 00494 00495 pdata->coverglass_transmission = 0x0100; 00496 00497 LOG_FUNCTION_END(status); 00498 00499 return status; 00500 } 00501 00502 00503 VL53L1_Error VL53L1_init_tuning_parm_storage_struct( 00504 VL53L1_tuning_parm_storage_t *pdata) 00505 { 00506 00507 00508 VL53L1_Error status = VL53L1_ERROR_NONE; 00509 00510 LOG_FUNCTION_START(""); 00511 00512 00513 00514 pdata->tp_tuning_parm_version = 00515 VL53L1_TUNINGPARM_VERSION_DEFAULT; 00516 pdata->tp_tuning_parm_key_table_version = 00517 VL53L1_TUNINGPARM_KEY_TABLE_VERSION_DEFAULT; 00518 pdata->tp_tuning_parm_lld_version = 00519 VL53L1_TUNINGPARM_LLD_VERSION_DEFAULT; 00520 pdata->tp_init_phase_rtn_lite_long = 00521 VL53L1_TUNINGPARM_INITIAL_PHASE_RTN_LITE_LONG_RANGE_DEFAULT; 00522 pdata->tp_init_phase_rtn_lite_med = 00523 VL53L1_TUNINGPARM_INITIAL_PHASE_RTN_LITE_MED_RANGE_DEFAULT; 00524 pdata->tp_init_phase_rtn_lite_short = 00525 VL53L1_TUNINGPARM_INITIAL_PHASE_RTN_LITE_SHORT_RANGE_DEFAULT; 00526 pdata->tp_init_phase_ref_lite_long = 00527 VL53L1_TUNINGPARM_INITIAL_PHASE_REF_LITE_LONG_RANGE_DEFAULT; 00528 pdata->tp_init_phase_ref_lite_med = 00529 VL53L1_TUNINGPARM_INITIAL_PHASE_REF_LITE_MED_RANGE_DEFAULT; 00530 pdata->tp_init_phase_ref_lite_short = 00531 VL53L1_TUNINGPARM_INITIAL_PHASE_REF_LITE_SHORT_RANGE_DEFAULT; 00532 pdata->tp_init_phase_rtn_hist_long = 00533 VL53L1_TUNINGPARM_INITIAL_PHASE_RTN_HISTO_LONG_RANGE_DEFAULT; 00534 pdata->tp_init_phase_rtn_hist_med = 00535 VL53L1_TUNINGPARM_INITIAL_PHASE_RTN_HISTO_MED_RANGE_DEFAULT; 00536 pdata->tp_init_phase_rtn_hist_short = 00537 VL53L1_TUNINGPARM_INITIAL_PHASE_RTN_HISTO_SHORT_RANGE_DEFAULT; 00538 pdata->tp_init_phase_ref_hist_long = 00539 VL53L1_TUNINGPARM_INITIAL_PHASE_REF_HISTO_LONG_RANGE_DEFAULT; 00540 pdata->tp_init_phase_ref_hist_med = 00541 VL53L1_TUNINGPARM_INITIAL_PHASE_REF_HISTO_MED_RANGE_DEFAULT; 00542 pdata->tp_init_phase_ref_hist_short = 00543 VL53L1_TUNINGPARM_INITIAL_PHASE_REF_HISTO_SHORT_RANGE_DEFAULT; 00544 pdata->tp_consistency_lite_phase_tolerance = 00545 VL53L1_TUNINGPARM_CONSISTENCY_LITE_PHASE_TOLERANCE_DEFAULT; 00546 pdata->tp_phasecal_target = 00547 VL53L1_TUNINGPARM_PHASECAL_TARGET_DEFAULT; 00548 pdata->tp_cal_repeat_rate = 00549 VL53L1_TUNINGPARM_LITE_CAL_REPEAT_RATE_DEFAULT; 00550 pdata->tp_lite_min_clip = 00551 VL53L1_TUNINGPARM_LITE_MIN_CLIP_MM_DEFAULT; 00552 pdata->tp_lite_long_sigma_thresh_mm = 00553 VL53L1_TUNINGPARM_LITE_LONG_SIGMA_THRESH_MM_DEFAULT; 00554 pdata->tp_lite_med_sigma_thresh_mm = 00555 VL53L1_TUNINGPARM_LITE_MED_SIGMA_THRESH_MM_DEFAULT; 00556 pdata->tp_lite_short_sigma_thresh_mm = 00557 VL53L1_TUNINGPARM_LITE_SHORT_SIGMA_THRESH_MM_DEFAULT; 00558 pdata->tp_lite_long_min_count_rate_rtn_mcps = 00559 VL53L1_TUNINGPARM_LITE_LONG_MIN_COUNT_RATE_RTN_MCPS_DEFAULT; 00560 pdata->tp_lite_med_min_count_rate_rtn_mcps = 00561 VL53L1_TUNINGPARM_LITE_MED_MIN_COUNT_RATE_RTN_MCPS_DEFAULT; 00562 pdata->tp_lite_short_min_count_rate_rtn_mcps = 00563 VL53L1_TUNINGPARM_LITE_SHORT_MIN_COUNT_RATE_RTN_MCPS_DEFAULT; 00564 pdata->tp_lite_sigma_est_pulse_width_ns = 00565 VL53L1_TUNINGPARM_LITE_SIGMA_EST_PULSE_WIDTH_DEFAULT; 00566 pdata->tp_lite_sigma_est_amb_width_ns = 00567 VL53L1_TUNINGPARM_LITE_SIGMA_EST_AMB_WIDTH_NS_DEFAULT; 00568 pdata->tp_lite_sigma_ref_mm = 00569 VL53L1_TUNINGPARM_LITE_SIGMA_REF_MM_DEFAULT; 00570 pdata->tp_lite_seed_cfg = 00571 VL53L1_TUNINGPARM_LITE_SEED_CONFIG_DEFAULT; 00572 pdata->tp_timed_seed_cfg = 00573 VL53L1_TUNINGPARM_TIMED_SEED_CONFIG_DEFAULT; 00574 pdata->tp_lite_quantifier = 00575 VL53L1_TUNINGPARM_LITE_QUANTIFIER_DEFAULT; 00576 pdata->tp_lite_first_order_select = 00577 VL53L1_TUNINGPARM_LITE_FIRST_ORDER_SELECT_DEFAULT; 00578 00579 00580 00581 00582 pdata->tp_dss_target_lite_mcps = 00583 VL53L1_TUNINGPARM_LITE_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS_DEFAULT; 00584 pdata->tp_dss_target_histo_mcps = 00585 VL53L1_TUNINGPARM_RANGING_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS_DEFAULT; 00586 pdata->tp_dss_target_histo_mz_mcps = 00587 VL53L1_TUNINGPARM_MZ_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS_DEFAULT; 00588 pdata->tp_dss_target_timed_mcps = 00589 VL53L1_TUNINGPARM_TIMED_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS_DEFAULT; 00590 pdata->tp_phasecal_timeout_lite_us = 00591 VL53L1_TUNINGPARM_LITE_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT; 00592 pdata->tp_phasecal_timeout_hist_long_us = 00593 VL53L1_TUNINGPARM_RANGING_LONG_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT; 00594 pdata->tp_phasecal_timeout_hist_med_us = 00595 VL53L1_TUNINGPARM_RANGING_MED_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT; 00596 pdata->tp_phasecal_timeout_hist_short_us = 00597 VL53L1_TUNINGPARM_RANGING_SHORT_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT; 00598 pdata->tp_phasecal_timeout_mz_long_us = 00599 VL53L1_TUNINGPARM_MZ_LONG_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT; 00600 pdata->tp_phasecal_timeout_mz_med_us = 00601 VL53L1_TUNINGPARM_MZ_MED_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT; 00602 pdata->tp_phasecal_timeout_mz_short_us = 00603 VL53L1_TUNINGPARM_MZ_SHORT_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT; 00604 pdata->tp_phasecal_timeout_timed_us = 00605 VL53L1_TUNINGPARM_TIMED_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT; 00606 pdata->tp_mm_timeout_lite_us = 00607 VL53L1_TUNINGPARM_LITE_MM_CONFIG_TIMEOUT_US_DEFAULT; 00608 pdata->tp_mm_timeout_histo_us = 00609 VL53L1_TUNINGPARM_RANGING_MM_CONFIG_TIMEOUT_US_DEFAULT; 00610 pdata->tp_mm_timeout_mz_us = 00611 VL53L1_TUNINGPARM_MZ_MM_CONFIG_TIMEOUT_US_DEFAULT; 00612 pdata->tp_mm_timeout_timed_us = 00613 VL53L1_TUNINGPARM_TIMED_MM_CONFIG_TIMEOUT_US_DEFAULT; 00614 pdata->tp_range_timeout_lite_us = 00615 VL53L1_TUNINGPARM_LITE_RANGE_CONFIG_TIMEOUT_US_DEFAULT; 00616 pdata->tp_range_timeout_histo_us = 00617 VL53L1_TUNINGPARM_RANGING_RANGE_CONFIG_TIMEOUT_US_DEFAULT; 00618 pdata->tp_range_timeout_mz_us = 00619 VL53L1_TUNINGPARM_MZ_RANGE_CONFIG_TIMEOUT_US_DEFAULT; 00620 pdata->tp_range_timeout_timed_us = 00621 VL53L1_TUNINGPARM_TIMED_RANGE_CONFIG_TIMEOUT_US_DEFAULT; 00622 00623 00624 00625 pdata->tp_mm_timeout_lpa_us = 00626 VL53L1_TUNINGPARM_LOWPOWERAUTO_MM_CONFIG_TIMEOUT_US_DEFAULT; 00627 pdata->tp_range_timeout_lpa_us = 00628 VL53L1_TUNINGPARM_LOWPOWERAUTO_RANGE_CONFIG_TIMEOUT_US_DEFAULT; 00629 00630 pdata->tp_dss_target_very_short_mcps = 00631 VL53L1_TUNINGPARM_VERY_SHORT_DSS_RATE_MCPS_DEFAULT; 00632 00633 pdata->tp_phasecal_patch_power = 00634 VL53L1_TUNINGPARM_PHASECAL_PATCH_POWER_DEFAULT; 00635 00636 pdata->tp_hist_merge = 00637 VL53L1_TUNINGPARM_HIST_MERGE_DEFAULT; 00638 00639 pdata->tp_reset_merge_threshold = 00640 VL53L1_TUNINGPARM_RESET_MERGE_THRESHOLD_DEFAULT; 00641 00642 pdata->tp_hist_merge_max_size = 00643 VL53L1_TUNINGPARM_HIST_MERGE_MAX_SIZE_DEFAULT; 00644 00645 pdata->tp_uwr_enable = 00646 VL53L1_TUNINGPARM_UWR_ENABLE_DEFAULT; 00647 pdata->tp_uwr_med_z_1_min = 00648 VL53L1_TUNINGPARM_UWR_MEDIUM_ZONE_1_MIN_DEFAULT; 00649 pdata->tp_uwr_med_z_1_max = 00650 VL53L1_TUNINGPARM_UWR_MEDIUM_ZONE_1_MAX_DEFAULT; 00651 pdata->tp_uwr_med_z_2_min = 00652 VL53L1_TUNINGPARM_UWR_MEDIUM_ZONE_2_MIN_DEFAULT; 00653 pdata->tp_uwr_med_z_2_max = 00654 VL53L1_TUNINGPARM_UWR_MEDIUM_ZONE_2_MAX_DEFAULT; 00655 pdata->tp_uwr_med_z_3_min = 00656 VL53L1_TUNINGPARM_UWR_MEDIUM_ZONE_3_MIN_DEFAULT; 00657 pdata->tp_uwr_med_z_3_max = 00658 VL53L1_TUNINGPARM_UWR_MEDIUM_ZONE_3_MAX_DEFAULT; 00659 pdata->tp_uwr_med_z_4_min = 00660 VL53L1_TUNINGPARM_UWR_MEDIUM_ZONE_4_MIN_DEFAULT; 00661 pdata->tp_uwr_med_z_4_max = 00662 VL53L1_TUNINGPARM_UWR_MEDIUM_ZONE_4_MAX_DEFAULT; 00663 pdata->tp_uwr_med_z_5_min = 00664 VL53L1_TUNINGPARM_UWR_MEDIUM_ZONE_5_MIN_DEFAULT; 00665 pdata->tp_uwr_med_z_5_max = 00666 VL53L1_TUNINGPARM_UWR_MEDIUM_ZONE_5_MAX_DEFAULT; 00667 pdata->tp_uwr_med_z_6_min = 00668 VL53L1_TUNINGPARM_UWR_MEDIUM_ZONE_6_MIN_DEFAULT; 00669 pdata->tp_uwr_med_z_6_max = 00670 VL53L1_TUNINGPARM_UWR_MEDIUM_ZONE_6_MAX_DEFAULT; 00671 pdata->tp_uwr_med_corr_z_1_rangea = 00672 VL53L1_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_1_RANGEA_DEFAULT; 00673 pdata->tp_uwr_med_corr_z_1_rangeb = 00674 VL53L1_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_1_RANGEB_DEFAULT; 00675 pdata->tp_uwr_med_corr_z_2_rangea = 00676 VL53L1_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_2_RANGEA_DEFAULT; 00677 pdata->tp_uwr_med_corr_z_2_rangeb = 00678 VL53L1_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_2_RANGEB_DEFAULT; 00679 pdata->tp_uwr_med_corr_z_3_rangea = 00680 VL53L1_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_3_RANGEA_DEFAULT; 00681 pdata->tp_uwr_med_corr_z_3_rangeb = 00682 VL53L1_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_3_RANGEB_DEFAULT; 00683 pdata->tp_uwr_med_corr_z_4_rangea = 00684 VL53L1_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_4_RANGEA_DEFAULT; 00685 pdata->tp_uwr_med_corr_z_4_rangeb = 00686 VL53L1_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_4_RANGEB_DEFAULT; 00687 pdata->tp_uwr_med_corr_z_5_rangea = 00688 VL53L1_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_5_RANGEA_DEFAULT; 00689 pdata->tp_uwr_med_corr_z_5_rangeb = 00690 VL53L1_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_5_RANGEB_DEFAULT; 00691 pdata->tp_uwr_med_corr_z_6_rangea = 00692 VL53L1_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_6_RANGEA_DEFAULT; 00693 pdata->tp_uwr_med_corr_z_6_rangeb = 00694 VL53L1_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_6_RANGEB_DEFAULT; 00695 pdata->tp_uwr_lng_z_1_min = 00696 VL53L1_TUNINGPARM_UWR_LONG_ZONE_1_MIN_DEFAULT; 00697 pdata->tp_uwr_lng_z_1_max = 00698 VL53L1_TUNINGPARM_UWR_LONG_ZONE_1_MAX_DEFAULT; 00699 pdata->tp_uwr_lng_z_2_min = 00700 VL53L1_TUNINGPARM_UWR_LONG_ZONE_2_MIN_DEFAULT; 00701 pdata->tp_uwr_lng_z_2_max = 00702 VL53L1_TUNINGPARM_UWR_LONG_ZONE_2_MAX_DEFAULT; 00703 pdata->tp_uwr_lng_z_3_min = 00704 VL53L1_TUNINGPARM_UWR_LONG_ZONE_3_MIN_DEFAULT; 00705 pdata->tp_uwr_lng_z_3_max = 00706 VL53L1_TUNINGPARM_UWR_LONG_ZONE_3_MAX_DEFAULT; 00707 pdata->tp_uwr_lng_z_4_min = 00708 VL53L1_TUNINGPARM_UWR_LONG_ZONE_4_MIN_DEFAULT; 00709 pdata->tp_uwr_lng_z_4_max = 00710 VL53L1_TUNINGPARM_UWR_LONG_ZONE_4_MAX_DEFAULT; 00711 pdata->tp_uwr_lng_z_5_min = 00712 VL53L1_TUNINGPARM_UWR_LONG_ZONE_5_MIN_DEFAULT; 00713 pdata->tp_uwr_lng_z_5_max = 00714 VL53L1_TUNINGPARM_UWR_LONG_ZONE_5_MAX_DEFAULT; 00715 pdata->tp_uwr_lng_corr_z_1_rangea = 00716 VL53L1_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_1_RANGEA_DEFAULT; 00717 pdata->tp_uwr_lng_corr_z_1_rangeb = 00718 VL53L1_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_1_RANGEB_DEFAULT; 00719 pdata->tp_uwr_lng_corr_z_2_rangea = 00720 VL53L1_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_2_RANGEA_DEFAULT; 00721 pdata->tp_uwr_lng_corr_z_2_rangeb = 00722 VL53L1_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_2_RANGEB_DEFAULT; 00723 pdata->tp_uwr_lng_corr_z_3_rangea = 00724 VL53L1_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_3_RANGEA_DEFAULT; 00725 pdata->tp_uwr_lng_corr_z_3_rangeb = 00726 VL53L1_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_3_RANGEB_DEFAULT; 00727 pdata->tp_uwr_lng_corr_z_4_rangea = 00728 VL53L1_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_4_RANGEA_DEFAULT; 00729 pdata->tp_uwr_lng_corr_z_4_rangeb = 00730 VL53L1_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_4_RANGEB_DEFAULT; 00731 pdata->tp_uwr_lng_corr_z_5_rangea = 00732 VL53L1_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_5_RANGEA_DEFAULT; 00733 pdata->tp_uwr_lng_corr_z_5_rangeb = 00734 VL53L1_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_5_RANGEB_DEFAULT; 00735 00736 LOG_FUNCTION_END(status); 00737 00738 return status; 00739 } 00740 00741 00742 VL53L1_Error VL53L1_init_hist_gen3_dmax_config_struct( 00743 VL53L1_hist_gen3_dmax_config_t *pdata) 00744 { 00745 00746 00747 VL53L1_Error status = VL53L1_ERROR_NONE; 00748 00749 LOG_FUNCTION_START(""); 00750 00751 00752 pdata->dss_config__target_total_rate_mcps = 0x1400; 00753 pdata->dss_config__aperture_attenuation = 0x38; 00754 00755 pdata->signal_thresh_sigma = 00756 VL53L1_TUNINGPARM_DMAX_CFG_SIGNAL_THRESH_SIGMA_DEFAULT; 00757 pdata->ambient_thresh_sigma = 0x70; 00758 pdata->min_ambient_thresh_events = 16; 00759 pdata->signal_total_events_limit = 100; 00760 pdata->max_effective_spads = 0xFFFF; 00761 00762 00763 00764 pdata->target_reflectance_for_dmax_calc[0] = 00765 VL53L1_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_0_DEFAULT; 00766 pdata->target_reflectance_for_dmax_calc[1] = 00767 VL53L1_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_1_DEFAULT; 00768 pdata->target_reflectance_for_dmax_calc[2] = 00769 VL53L1_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_2_DEFAULT; 00770 pdata->target_reflectance_for_dmax_calc[3] = 00771 VL53L1_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_3_DEFAULT; 00772 pdata->target_reflectance_for_dmax_calc[4] = 00773 VL53L1_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_4_DEFAULT; 00774 00775 LOG_FUNCTION_END(status); 00776 00777 return status; 00778 } 00779 00780 00781 VL53L1_Error VL53L1_preset_mode_standard_ranging( 00782 VL53L1_static_config_t *pstatic, 00783 VL53L1_histogram_config_t *phistogram, 00784 VL53L1_general_config_t *pgeneral, 00785 VL53L1_timing_config_t *ptiming, 00786 VL53L1_dynamic_config_t *pdynamic, 00787 VL53L1_system_control_t *psystem, 00788 VL53L1_tuning_parm_storage_t *ptuning_parms, 00789 VL53L1_zone_config_t *pzone_cfg) 00790 { 00791 00792 00793 VL53L1_Error status = VL53L1_ERROR_NONE; 00794 00795 LOG_FUNCTION_START(""); 00796 00797 00798 00799 00800 pstatic->dss_config__target_total_rate_mcps = 0x0A00; 00801 pstatic->debug__ctrl = 0x00; 00802 pstatic->test_mode__ctrl = 0x00; 00803 pstatic->clk_gating__ctrl = 0x00; 00804 pstatic->nvm_bist__ctrl = 0x00; 00805 pstatic->nvm_bist__num_nvm_words = 0x00; 00806 pstatic->nvm_bist__start_address = 0x00; 00807 pstatic->host_if__status = 0x00; 00808 pstatic->pad_i2c_hv__config = 0x00; 00809 pstatic->pad_i2c_hv__extsup_config = 0x00; 00810 00811 00812 pstatic->gpio_hv_pad__ctrl = 0x00; 00813 00814 00815 pstatic->gpio_hv_mux__ctrl = 00816 VL53L1_DEVICEINTERRUPTPOLARITY_ACTIVE_LOW | 00817 VL53L1_DEVICEGPIOMODE_OUTPUT_RANGE_AND_ERROR_INTERRUPTS; 00818 00819 pstatic->gpio__tio_hv_status = 0x02; 00820 pstatic->gpio__fio_hv_status = 0x00; 00821 pstatic->ana_config__spad_sel_pswidth = 0x02; 00822 pstatic->ana_config__vcsel_pulse_width_offset = 0x08; 00823 pstatic->ana_config__fast_osc__config_ctrl = 0x00; 00824 00825 pstatic->sigma_estimator__effective_pulse_width_ns = 00826 ptuning_parms->tp_lite_sigma_est_pulse_width_ns; 00827 pstatic->sigma_estimator__effective_ambient_width_ns = 00828 ptuning_parms->tp_lite_sigma_est_amb_width_ns; 00829 pstatic->sigma_estimator__sigma_ref_mm = 00830 ptuning_parms->tp_lite_sigma_ref_mm; 00831 00832 pstatic->algo__crosstalk_compensation_valid_height_mm = 0x01; 00833 pstatic->spare_host_config__static_config_spare_0 = 0x00; 00834 pstatic->spare_host_config__static_config_spare_1 = 0x00; 00835 00836 pstatic->algo__range_ignore_threshold_mcps = 0x0000; 00837 00838 00839 pstatic->algo__range_ignore_valid_height_mm = 0xff; 00840 pstatic->algo__range_min_clip = 00841 ptuning_parms->tp_lite_min_clip; 00842 00843 pstatic->algo__consistency_check__tolerance = 00844 ptuning_parms->tp_consistency_lite_phase_tolerance; 00845 pstatic->spare_host_config__static_config_spare_2 = 0x00; 00846 pstatic->sd_config__reset_stages_msb = 0x00; 00847 pstatic->sd_config__reset_stages_lsb = 0x00; 00848 00849 pgeneral->gph_config__stream_count_update_value = 0x00; 00850 pgeneral->global_config__stream_divider = 0x00; 00851 pgeneral->system__interrupt_config_gpio = 00852 VL53L1_INTERRUPT_CONFIG_NEW_SAMPLE_READY; 00853 pgeneral->cal_config__vcsel_start = 0x0B; 00854 00855 00856 pgeneral->cal_config__repeat_rate = 00857 ptuning_parms->tp_cal_repeat_rate; 00858 pgeneral->global_config__vcsel_width = 0x02; 00859 00860 pgeneral->phasecal_config__timeout_macrop = 0x0D; 00861 00862 pgeneral->phasecal_config__target = 00863 ptuning_parms->tp_phasecal_target; 00864 pgeneral->phasecal_config__override = 0x00; 00865 pgeneral->dss_config__roi_mode_control = 00866 VL53L1_DEVICEDSSMODE__TARGET_RATE; 00867 00868 pgeneral->system__thresh_rate_high = 0x0000; 00869 pgeneral->system__thresh_rate_low = 0x0000; 00870 00871 pgeneral->dss_config__manual_effective_spads_select = 0x8C00; 00872 pgeneral->dss_config__manual_block_select = 0x00; 00873 00874 00875 pgeneral->dss_config__aperture_attenuation = 0x38; 00876 pgeneral->dss_config__max_spads_limit = 0xFF; 00877 pgeneral->dss_config__min_spads_limit = 0x01; 00878 00879 00880 00881 00882 ptiming->mm_config__timeout_macrop_a_hi = 0x00; 00883 ptiming->mm_config__timeout_macrop_a_lo = 0x1a; 00884 ptiming->mm_config__timeout_macrop_b_hi = 0x00; 00885 ptiming->mm_config__timeout_macrop_b_lo = 0x20; 00886 00887 ptiming->range_config__timeout_macrop_a_hi = 0x01; 00888 ptiming->range_config__timeout_macrop_a_lo = 0xCC; 00889 00890 ptiming->range_config__vcsel_period_a = 0x0B; 00891 00892 ptiming->range_config__timeout_macrop_b_hi = 0x01; 00893 ptiming->range_config__timeout_macrop_b_lo = 0xF5; 00894 00895 ptiming->range_config__vcsel_period_b = 0x09; 00896 00897 ptiming->range_config__sigma_thresh = 00898 ptuning_parms->tp_lite_med_sigma_thresh_mm; 00899 00900 ptiming->range_config__min_count_rate_rtn_limit_mcps = 00901 ptuning_parms->tp_lite_med_min_count_rate_rtn_mcps; 00902 00903 00904 ptiming->range_config__valid_phase_low = 0x08; 00905 ptiming->range_config__valid_phase_high = 0x78; 00906 ptiming->system__intermeasurement_period = 0x00000000; 00907 ptiming->system__fractional_enable = 0x00; 00908 00909 00910 00911 phistogram->histogram_config__low_amb_even_bin_0_1 = 0x07; 00912 phistogram->histogram_config__low_amb_even_bin_2_3 = 0x21; 00913 phistogram->histogram_config__low_amb_even_bin_4_5 = 0x43; 00914 00915 phistogram->histogram_config__low_amb_odd_bin_0_1 = 0x10; 00916 phistogram->histogram_config__low_amb_odd_bin_2_3 = 0x32; 00917 phistogram->histogram_config__low_amb_odd_bin_4_5 = 0x54; 00918 00919 phistogram->histogram_config__mid_amb_even_bin_0_1 = 0x07; 00920 phistogram->histogram_config__mid_amb_even_bin_2_3 = 0x21; 00921 phistogram->histogram_config__mid_amb_even_bin_4_5 = 0x43; 00922 00923 phistogram->histogram_config__mid_amb_odd_bin_0_1 = 0x10; 00924 phistogram->histogram_config__mid_amb_odd_bin_2 = 0x02; 00925 phistogram->histogram_config__mid_amb_odd_bin_3_4 = 0x43; 00926 phistogram->histogram_config__mid_amb_odd_bin_5 = 0x05; 00927 00928 phistogram->histogram_config__user_bin_offset = 0x00; 00929 00930 phistogram->histogram_config__high_amb_even_bin_0_1 = 0x07; 00931 phistogram->histogram_config__high_amb_even_bin_2_3 = 0x21; 00932 phistogram->histogram_config__high_amb_even_bin_4_5 = 0x43; 00933 00934 phistogram->histogram_config__high_amb_odd_bin_0_1 = 0x10; 00935 phistogram->histogram_config__high_amb_odd_bin_2_3 = 0x32; 00936 phistogram->histogram_config__high_amb_odd_bin_4_5 = 0x54; 00937 00938 phistogram->histogram_config__amb_thresh_low = 0xFFFF; 00939 phistogram->histogram_config__amb_thresh_high = 0xFFFF; 00940 00941 phistogram->histogram_config__spad_array_selection = 0x00; 00942 00943 00944 pzone_cfg->max_zones = VL53L1_MAX_USER_ZONES; 00945 pzone_cfg->active_zones = 0x00; 00946 pzone_cfg->user_zones[0].height = 0x0f; 00947 pzone_cfg->user_zones[0].width = 0x0f; 00948 pzone_cfg->user_zones[0].x_centre = 0x08; 00949 pzone_cfg->user_zones[0].y_centre = 0x08; 00950 00951 00952 00953 pdynamic->system__grouped_parameter_hold_0 = 0x01; 00954 00955 pdynamic->system__thresh_high = 0x0000; 00956 pdynamic->system__thresh_low = 0x0000; 00957 pdynamic->system__enable_xtalk_per_quadrant = 0x00; 00958 pdynamic->system__seed_config = 00959 ptuning_parms->tp_lite_seed_cfg; 00960 00961 00962 pdynamic->sd_config__woi_sd0 = 0x0B; 00963 00964 pdynamic->sd_config__woi_sd1 = 0x09; 00965 00966 pdynamic->sd_config__initial_phase_sd0 = 00967 ptuning_parms->tp_init_phase_rtn_lite_med; 00968 pdynamic->sd_config__initial_phase_sd1 = 00969 ptuning_parms->tp_init_phase_ref_lite_med; 00970 00971 pdynamic->system__grouped_parameter_hold_1 = 0x01; 00972 00973 00974 00975 pdynamic->sd_config__first_order_select = 00976 ptuning_parms->tp_lite_first_order_select; 00977 pdynamic->sd_config__quantifier = 00978 ptuning_parms->tp_lite_quantifier; 00979 00980 00981 pdynamic->roi_config__user_roi_centre_spad = 0xC7; 00982 00983 pdynamic->roi_config__user_roi_requested_global_xy_size = 0xFF; 00984 00985 00986 pdynamic->system__sequence_config = 00987 VL53L1_SEQUENCE_VHV_EN | 00988 VL53L1_SEQUENCE_PHASECAL_EN | 00989 VL53L1_SEQUENCE_DSS1_EN | 00990 VL53L1_SEQUENCE_DSS2_EN | 00991 VL53L1_SEQUENCE_MM2_EN | 00992 VL53L1_SEQUENCE_RANGE_EN; 00993 00994 pdynamic->system__grouped_parameter_hold = 0x02; 00995 00996 00997 00998 00999 psystem->system__stream_count_ctrl = 0x00; 01000 psystem->firmware__enable = 0x01; 01001 psystem->system__interrupt_clear = 01002 VL53L1_CLEAR_RANGE_INT; 01003 01004 psystem->system__mode_start = 01005 VL53L1_DEVICESCHEDULERMODE_STREAMING | 01006 VL53L1_DEVICEREADOUTMODE_SINGLE_SD | 01007 VL53L1_DEVICEMEASUREMENTMODE_BACKTOBACK; 01008 01009 LOG_FUNCTION_END(status); 01010 01011 return status; 01012 } 01013 01014 01015 VL53L1_Error VL53L1_preset_mode_standard_ranging_short_range( 01016 VL53L1_static_config_t *pstatic, 01017 VL53L1_histogram_config_t *phistogram, 01018 VL53L1_general_config_t *pgeneral, 01019 VL53L1_timing_config_t *ptiming, 01020 VL53L1_dynamic_config_t *pdynamic, 01021 VL53L1_system_control_t *psystem, 01022 VL53L1_tuning_parm_storage_t *ptuning_parms, 01023 VL53L1_zone_config_t *pzone_cfg) 01024 { 01025 01026 01027 VL53L1_Error status = VL53L1_ERROR_NONE; 01028 01029 LOG_FUNCTION_START(""); 01030 01031 01032 01033 status = VL53L1_preset_mode_standard_ranging( 01034 pstatic, 01035 phistogram, 01036 pgeneral, 01037 ptiming, 01038 pdynamic, 01039 psystem, 01040 ptuning_parms, 01041 pzone_cfg); 01042 01043 01044 01045 if (status == VL53L1_ERROR_NONE) { 01046 01047 01048 01049 ptiming->range_config__vcsel_period_a = 0x07; 01050 ptiming->range_config__vcsel_period_b = 0x05; 01051 ptiming->range_config__sigma_thresh = 01052 ptuning_parms->tp_lite_short_sigma_thresh_mm; 01053 ptiming->range_config__min_count_rate_rtn_limit_mcps = 01054 ptuning_parms->tp_lite_short_min_count_rate_rtn_mcps; 01055 ptiming->range_config__valid_phase_low = 0x08; 01056 ptiming->range_config__valid_phase_high = 0x38; 01057 01058 01059 01060 pdynamic->sd_config__woi_sd0 = 0x07; 01061 pdynamic->sd_config__woi_sd1 = 0x05; 01062 pdynamic->sd_config__initial_phase_sd0 = 01063 ptuning_parms->tp_init_phase_rtn_lite_short; 01064 pdynamic->sd_config__initial_phase_sd1 = 01065 ptuning_parms->tp_init_phase_ref_lite_short; 01066 } 01067 01068 LOG_FUNCTION_END(status); 01069 01070 return status; 01071 } 01072 01073 01074 VL53L1_Error VL53L1_preset_mode_standard_ranging_long_range( 01075 VL53L1_static_config_t *pstatic, 01076 VL53L1_histogram_config_t *phistogram, 01077 VL53L1_general_config_t *pgeneral, 01078 VL53L1_timing_config_t *ptiming, 01079 VL53L1_dynamic_config_t *pdynamic, 01080 VL53L1_system_control_t *psystem, 01081 VL53L1_tuning_parm_storage_t *ptuning_parms, 01082 VL53L1_zone_config_t *pzone_cfg) 01083 { 01084 01085 01086 VL53L1_Error status = VL53L1_ERROR_NONE; 01087 01088 LOG_FUNCTION_START(""); 01089 01090 01091 01092 status = VL53L1_preset_mode_standard_ranging( 01093 pstatic, 01094 phistogram, 01095 pgeneral, 01096 ptiming, 01097 pdynamic, 01098 psystem, 01099 ptuning_parms, 01100 pzone_cfg); 01101 01102 01103 01104 if (status == VL53L1_ERROR_NONE) { 01105 01106 01107 01108 ptiming->range_config__vcsel_period_a = 0x0F; 01109 ptiming->range_config__vcsel_period_b = 0x0D; 01110 ptiming->range_config__sigma_thresh = 01111 ptuning_parms->tp_lite_long_sigma_thresh_mm; 01112 ptiming->range_config__min_count_rate_rtn_limit_mcps = 01113 ptuning_parms->tp_lite_long_min_count_rate_rtn_mcps; 01114 ptiming->range_config__valid_phase_low = 0x08; 01115 ptiming->range_config__valid_phase_high = 0xB8; 01116 01117 01118 01119 pdynamic->sd_config__woi_sd0 = 0x0F; 01120 pdynamic->sd_config__woi_sd1 = 0x0D; 01121 pdynamic->sd_config__initial_phase_sd0 = 01122 ptuning_parms->tp_init_phase_rtn_lite_long; 01123 pdynamic->sd_config__initial_phase_sd1 = 01124 ptuning_parms->tp_init_phase_ref_lite_long; 01125 } 01126 01127 LOG_FUNCTION_END(status); 01128 01129 return status; 01130 } 01131 01132 01133 VL53L1_Error VL53L1_preset_mode_standard_ranging_mm1_cal( 01134 VL53L1_static_config_t *pstatic, 01135 VL53L1_histogram_config_t *phistogram, 01136 VL53L1_general_config_t *pgeneral, 01137 VL53L1_timing_config_t *ptiming, 01138 VL53L1_dynamic_config_t *pdynamic, 01139 VL53L1_system_control_t *psystem, 01140 VL53L1_tuning_parm_storage_t *ptuning_parms, 01141 VL53L1_zone_config_t *pzone_cfg) 01142 { 01143 01144 01145 VL53L1_Error status = VL53L1_ERROR_NONE; 01146 01147 LOG_FUNCTION_START(""); 01148 01149 01150 01151 status = VL53L1_preset_mode_standard_ranging( 01152 pstatic, 01153 phistogram, 01154 pgeneral, 01155 ptiming, 01156 pdynamic, 01157 psystem, 01158 ptuning_parms, 01159 pzone_cfg); 01160 01161 01162 01163 if (status == VL53L1_ERROR_NONE) { 01164 01165 pgeneral->dss_config__roi_mode_control = 01166 VL53L1_DEVICEDSSMODE__REQUESTED_EFFFECTIVE_SPADS; 01167 01168 pdynamic->system__sequence_config = 01169 VL53L1_SEQUENCE_VHV_EN | 01170 VL53L1_SEQUENCE_PHASECAL_EN | 01171 VL53L1_SEQUENCE_DSS1_EN | 01172 VL53L1_SEQUENCE_DSS2_EN | 01173 VL53L1_SEQUENCE_MM1_EN; 01174 } 01175 01176 LOG_FUNCTION_END(status); 01177 01178 return status; 01179 } 01180 01181 01182 VL53L1_Error VL53L1_preset_mode_standard_ranging_mm2_cal( 01183 VL53L1_static_config_t *pstatic, 01184 VL53L1_histogram_config_t *phistogram, 01185 VL53L1_general_config_t *pgeneral, 01186 VL53L1_timing_config_t *ptiming, 01187 VL53L1_dynamic_config_t *pdynamic, 01188 VL53L1_system_control_t *psystem, 01189 VL53L1_tuning_parm_storage_t *ptuning_parms, 01190 VL53L1_zone_config_t *pzone_cfg) 01191 { 01192 01193 01194 VL53L1_Error status = VL53L1_ERROR_NONE; 01195 01196 LOG_FUNCTION_START(""); 01197 01198 01199 01200 status = VL53L1_preset_mode_standard_ranging( 01201 pstatic, 01202 phistogram, 01203 pgeneral, 01204 ptiming, 01205 pdynamic, 01206 psystem, 01207 ptuning_parms, 01208 pzone_cfg); 01209 01210 01211 01212 if (status == VL53L1_ERROR_NONE) { 01213 01214 pgeneral->dss_config__roi_mode_control = 01215 VL53L1_DEVICEDSSMODE__REQUESTED_EFFFECTIVE_SPADS; 01216 01217 pdynamic->system__sequence_config = 01218 VL53L1_SEQUENCE_VHV_EN | 01219 VL53L1_SEQUENCE_PHASECAL_EN | 01220 VL53L1_SEQUENCE_DSS1_EN | 01221 VL53L1_SEQUENCE_DSS2_EN | 01222 VL53L1_SEQUENCE_MM2_EN; 01223 } 01224 01225 LOG_FUNCTION_END(status); 01226 01227 return status; 01228 } 01229 01230 01231 VL53L1_Error VL53L1_preset_mode_timed_ranging( 01232 01233 VL53L1_static_config_t *pstatic, 01234 VL53L1_histogram_config_t *phistogram, 01235 VL53L1_general_config_t *pgeneral, 01236 VL53L1_timing_config_t *ptiming, 01237 VL53L1_dynamic_config_t *pdynamic, 01238 VL53L1_system_control_t *psystem, 01239 VL53L1_tuning_parm_storage_t *ptuning_parms, 01240 VL53L1_zone_config_t *pzone_cfg) 01241 { 01242 01243 01244 VL53L1_Error status = VL53L1_ERROR_NONE; 01245 01246 LOG_FUNCTION_START(""); 01247 01248 01249 01250 status = VL53L1_preset_mode_standard_ranging( 01251 pstatic, 01252 phistogram, 01253 pgeneral, 01254 ptiming, 01255 pdynamic, 01256 psystem, 01257 ptuning_parms, 01258 pzone_cfg); 01259 01260 01261 01262 if (status == VL53L1_ERROR_NONE) { 01263 01264 01265 01266 01267 pdynamic->system__grouped_parameter_hold = 0x00; 01268 01269 01270 ptiming->range_config__timeout_macrop_a_hi = 0x00; 01271 ptiming->range_config__timeout_macrop_a_lo = 0xB1; 01272 01273 ptiming->range_config__timeout_macrop_b_hi = 0x00; 01274 ptiming->range_config__timeout_macrop_b_lo = 0xD4; 01275 01276 01277 01278 ptiming->system__intermeasurement_period = 0x00000600; 01279 pdynamic->system__seed_config = 01280 ptuning_parms->tp_timed_seed_cfg; 01281 01282 01283 01284 01285 psystem->system__mode_start = 01286 VL53L1_DEVICESCHEDULERMODE_PSEUDO_SOLO | 01287 VL53L1_DEVICEREADOUTMODE_SINGLE_SD | 01288 VL53L1_DEVICEMEASUREMENTMODE_TIMED; 01289 } 01290 01291 LOG_FUNCTION_END(status); 01292 01293 return status; 01294 } 01295 01296 VL53L1_Error VL53L1_preset_mode_timed_ranging_short_range( 01297 01298 VL53L1_static_config_t *pstatic, 01299 VL53L1_histogram_config_t *phistogram, 01300 VL53L1_general_config_t *pgeneral, 01301 VL53L1_timing_config_t *ptiming, 01302 VL53L1_dynamic_config_t *pdynamic, 01303 VL53L1_system_control_t *psystem, 01304 VL53L1_tuning_parm_storage_t *ptuning_parms, 01305 VL53L1_zone_config_t *pzone_cfg) 01306 { 01307 01308 01309 VL53L1_Error status = VL53L1_ERROR_NONE; 01310 01311 LOG_FUNCTION_START(""); 01312 01313 01314 01315 status = VL53L1_preset_mode_standard_ranging_short_range( 01316 pstatic, 01317 phistogram, 01318 pgeneral, 01319 ptiming, 01320 pdynamic, 01321 psystem, 01322 ptuning_parms, 01323 pzone_cfg); 01324 01325 01326 01327 if (status == VL53L1_ERROR_NONE) { 01328 01329 01330 01331 01332 pdynamic->system__grouped_parameter_hold = 0x00; 01333 01334 01335 01336 01337 01338 ptiming->range_config__timeout_macrop_a_hi = 0x01; 01339 ptiming->range_config__timeout_macrop_a_lo = 0x84; 01340 01341 ptiming->range_config__timeout_macrop_b_hi = 0x01; 01342 ptiming->range_config__timeout_macrop_b_lo = 0xB1; 01343 01344 ptiming->system__intermeasurement_period = 0x00000600; 01345 pdynamic->system__seed_config = 01346 ptuning_parms->tp_timed_seed_cfg; 01347 01348 01349 01350 01351 psystem->system__mode_start = 01352 VL53L1_DEVICESCHEDULERMODE_PSEUDO_SOLO | 01353 VL53L1_DEVICEREADOUTMODE_SINGLE_SD | 01354 VL53L1_DEVICEMEASUREMENTMODE_TIMED; 01355 } 01356 01357 LOG_FUNCTION_END(status); 01358 01359 return status; 01360 } 01361 01362 VL53L1_Error VL53L1_preset_mode_timed_ranging_long_range( 01363 01364 VL53L1_static_config_t *pstatic, 01365 VL53L1_histogram_config_t *phistogram, 01366 VL53L1_general_config_t *pgeneral, 01367 VL53L1_timing_config_t *ptiming, 01368 VL53L1_dynamic_config_t *pdynamic, 01369 VL53L1_system_control_t *psystem, 01370 VL53L1_tuning_parm_storage_t *ptuning_parms, 01371 VL53L1_zone_config_t *pzone_cfg) 01372 { 01373 01374 01375 VL53L1_Error status = VL53L1_ERROR_NONE; 01376 01377 LOG_FUNCTION_START(""); 01378 01379 01380 01381 status = VL53L1_preset_mode_standard_ranging_long_range( 01382 pstatic, 01383 phistogram, 01384 pgeneral, 01385 ptiming, 01386 pdynamic, 01387 psystem, 01388 ptuning_parms, 01389 pzone_cfg); 01390 01391 01392 01393 if (status == VL53L1_ERROR_NONE) { 01394 01395 01396 01397 01398 pdynamic->system__grouped_parameter_hold = 0x00; 01399 01400 01401 01402 01403 01404 ptiming->range_config__timeout_macrop_a_hi = 0x00; 01405 ptiming->range_config__timeout_macrop_a_lo = 0x97; 01406 01407 ptiming->range_config__timeout_macrop_b_hi = 0x00; 01408 ptiming->range_config__timeout_macrop_b_lo = 0xB1; 01409 01410 ptiming->system__intermeasurement_period = 0x00000600; 01411 pdynamic->system__seed_config = 01412 ptuning_parms->tp_timed_seed_cfg; 01413 01414 01415 01416 01417 psystem->system__mode_start = 01418 VL53L1_DEVICESCHEDULERMODE_PSEUDO_SOLO | 01419 VL53L1_DEVICEREADOUTMODE_SINGLE_SD | 01420 VL53L1_DEVICEMEASUREMENTMODE_TIMED; 01421 } 01422 01423 LOG_FUNCTION_END(status); 01424 01425 return status; 01426 } 01427 01428 01429 VL53L1_Error VL53L1_preset_mode_low_power_auto_ranging( 01430 01431 VL53L1_static_config_t *pstatic, 01432 VL53L1_histogram_config_t *phistogram, 01433 VL53L1_general_config_t *pgeneral, 01434 VL53L1_timing_config_t *ptiming, 01435 VL53L1_dynamic_config_t *pdynamic, 01436 VL53L1_system_control_t *psystem, 01437 VL53L1_tuning_parm_storage_t *ptuning_parms, 01438 VL53L1_zone_config_t *pzone_cfg, 01439 VL53L1_low_power_auto_data_t *plpadata) 01440 { 01441 01442 01443 VL53L1_Error status = VL53L1_ERROR_NONE; 01444 01445 LOG_FUNCTION_START(""); 01446 01447 01448 01449 status = VL53L1_preset_mode_timed_ranging( 01450 pstatic, 01451 phistogram, 01452 pgeneral, 01453 ptiming, 01454 pdynamic, 01455 psystem, 01456 ptuning_parms, 01457 pzone_cfg); 01458 01459 01460 01461 if (status == VL53L1_ERROR_NONE) { 01462 status = VL53L1_config_low_power_auto_mode( 01463 pgeneral, 01464 pdynamic, 01465 plpadata 01466 ); 01467 } 01468 01469 LOG_FUNCTION_END(status); 01470 01471 return status; 01472 } 01473 01474 VL53L1_Error VL53L1_preset_mode_low_power_auto_short_ranging( 01475 01476 VL53L1_static_config_t *pstatic, 01477 VL53L1_histogram_config_t *phistogram, 01478 VL53L1_general_config_t *pgeneral, 01479 VL53L1_timing_config_t *ptiming, 01480 VL53L1_dynamic_config_t *pdynamic, 01481 VL53L1_system_control_t *psystem, 01482 VL53L1_tuning_parm_storage_t *ptuning_parms, 01483 VL53L1_zone_config_t *pzone_cfg, 01484 VL53L1_low_power_auto_data_t *plpadata) 01485 { 01486 01487 01488 VL53L1_Error status = VL53L1_ERROR_NONE; 01489 01490 LOG_FUNCTION_START(""); 01491 01492 01493 01494 status = VL53L1_preset_mode_timed_ranging_short_range( 01495 pstatic, 01496 phistogram, 01497 pgeneral, 01498 ptiming, 01499 pdynamic, 01500 psystem, 01501 ptuning_parms, 01502 pzone_cfg); 01503 01504 01505 01506 if (status == VL53L1_ERROR_NONE) { 01507 status = VL53L1_config_low_power_auto_mode( 01508 pgeneral, 01509 pdynamic, 01510 plpadata 01511 ); 01512 } 01513 01514 LOG_FUNCTION_END(status); 01515 01516 return status; 01517 } 01518 01519 VL53L1_Error VL53L1_preset_mode_low_power_auto_long_ranging( 01520 01521 VL53L1_static_config_t *pstatic, 01522 VL53L1_histogram_config_t *phistogram, 01523 VL53L1_general_config_t *pgeneral, 01524 VL53L1_timing_config_t *ptiming, 01525 VL53L1_dynamic_config_t *pdynamic, 01526 VL53L1_system_control_t *psystem, 01527 VL53L1_tuning_parm_storage_t *ptuning_parms, 01528 VL53L1_zone_config_t *pzone_cfg, 01529 VL53L1_low_power_auto_data_t *plpadata) 01530 { 01531 01532 01533 VL53L1_Error status = VL53L1_ERROR_NONE; 01534 01535 LOG_FUNCTION_START(""); 01536 01537 01538 01539 status = VL53L1_preset_mode_timed_ranging_long_range( 01540 pstatic, 01541 phistogram, 01542 pgeneral, 01543 ptiming, 01544 pdynamic, 01545 psystem, 01546 ptuning_parms, 01547 pzone_cfg); 01548 01549 01550 01551 if (status == VL53L1_ERROR_NONE) { 01552 status = VL53L1_config_low_power_auto_mode( 01553 pgeneral, 01554 pdynamic, 01555 plpadata 01556 ); 01557 } 01558 01559 LOG_FUNCTION_END(status); 01560 01561 return status; 01562 } 01563 01564 01565 01566 VL53L1_Error VL53L1_preset_mode_singleshot_ranging( 01567 01568 VL53L1_static_config_t *pstatic, 01569 VL53L1_histogram_config_t *phistogram, 01570 VL53L1_general_config_t *pgeneral, 01571 VL53L1_timing_config_t *ptiming, 01572 VL53L1_dynamic_config_t *pdynamic, 01573 VL53L1_system_control_t *psystem, 01574 VL53L1_tuning_parm_storage_t *ptuning_parms, 01575 VL53L1_zone_config_t *pzone_cfg) 01576 { 01577 01578 01579 VL53L1_Error status = VL53L1_ERROR_NONE; 01580 01581 LOG_FUNCTION_START(""); 01582 01583 01584 01585 status = VL53L1_preset_mode_standard_ranging( 01586 pstatic, 01587 phistogram, 01588 pgeneral, 01589 ptiming, 01590 pdynamic, 01591 psystem, 01592 ptuning_parms, 01593 pzone_cfg); 01594 01595 01596 01597 if (status == VL53L1_ERROR_NONE) { 01598 01599 01600 01601 01602 pdynamic->system__grouped_parameter_hold = 0x00; 01603 01604 01605 01606 01607 ptiming->range_config__timeout_macrop_a_hi = 0x00; 01608 ptiming->range_config__timeout_macrop_a_lo = 0xB1; 01609 01610 ptiming->range_config__timeout_macrop_b_hi = 0x00; 01611 ptiming->range_config__timeout_macrop_b_lo = 0xD4; 01612 01613 pdynamic->system__seed_config = 01614 ptuning_parms->tp_timed_seed_cfg; 01615 01616 01617 01618 01619 psystem->system__mode_start = 01620 VL53L1_DEVICESCHEDULERMODE_PSEUDO_SOLO | 01621 VL53L1_DEVICEREADOUTMODE_SINGLE_SD | 01622 VL53L1_DEVICEMEASUREMENTMODE_SINGLESHOT; 01623 } 01624 01625 LOG_FUNCTION_END(status); 01626 01627 return status; 01628 } 01629 01630 01631 VL53L1_Error VL53L1_preset_mode_histogram_ranging( 01632 VL53L1_hist_post_process_config_t *phistpostprocess, 01633 VL53L1_static_config_t *pstatic, 01634 VL53L1_histogram_config_t *phistogram, 01635 VL53L1_general_config_t *pgeneral, 01636 VL53L1_timing_config_t *ptiming, 01637 VL53L1_dynamic_config_t *pdynamic, 01638 VL53L1_system_control_t *psystem, 01639 VL53L1_tuning_parm_storage_t *ptuning_parms, 01640 VL53L1_zone_config_t *pzone_cfg) 01641 { 01642 01643 01644 VL53L1_Error status = VL53L1_ERROR_NONE; 01645 01646 LOG_FUNCTION_START(""); 01647 01648 01649 01650 status = 01651 VL53L1_preset_mode_standard_ranging( 01652 pstatic, 01653 phistogram, 01654 pgeneral, 01655 ptiming, 01656 pdynamic, 01657 psystem, 01658 ptuning_parms, 01659 pzone_cfg); 01660 01661 01662 01663 if (status == VL53L1_ERROR_NONE) { 01664 01665 01666 01667 pstatic->dss_config__target_total_rate_mcps = 0x1400; 01668 01669 01670 01671 VL53L1_init_histogram_config_structure( 01672 7, 0, 1, 2, 3, 4, 01673 0, 1, 2, 3, 4, 5, 01674 phistogram); 01675 01676 01677 VL53L1_init_histogram_multizone_config_structure( 01678 7, 0, 1, 2, 3, 4, 01679 0, 1, 2, 3, 4, 5, 01680 &(pzone_cfg->multizone_hist_cfg)); 01681 01682 01683 01684 01685 ptiming->range_config__vcsel_period_a = 0x09; 01686 ptiming->range_config__vcsel_period_b = 0x0B; 01687 pdynamic->sd_config__woi_sd0 = 0x09; 01688 pdynamic->sd_config__woi_sd1 = 0x0B; 01689 01690 01691 01692 01693 ptiming->mm_config__timeout_macrop_a_hi = 0x00; 01694 ptiming->mm_config__timeout_macrop_a_lo = 0x20; 01695 ptiming->mm_config__timeout_macrop_b_hi = 0x00; 01696 ptiming->mm_config__timeout_macrop_b_lo = 0x1A; 01697 01698 01699 ptiming->range_config__timeout_macrop_a_hi = 0x00; 01700 ptiming->range_config__timeout_macrop_a_lo = 0x28; 01701 01702 01703 ptiming->range_config__timeout_macrop_b_hi = 0x00; 01704 ptiming->range_config__timeout_macrop_b_lo = 0x21; 01705 01706 01707 pgeneral->phasecal_config__timeout_macrop = 0xF5; 01708 01709 01710 01711 phistpostprocess->valid_phase_low = 0x08; 01712 phistpostprocess->valid_phase_high = 0x88; 01713 01714 01715 01716 VL53L1_copy_hist_cfg_to_static_cfg( 01717 phistogram, 01718 pstatic, 01719 pgeneral, 01720 ptiming, 01721 pdynamic); 01722 01723 01724 01725 01726 pdynamic->system__sequence_config = 01727 VL53L1_SEQUENCE_VHV_EN | 01728 VL53L1_SEQUENCE_PHASECAL_EN | 01729 VL53L1_SEQUENCE_DSS1_EN | 01730 VL53L1_SEQUENCE_DSS2_EN | 01731 01732 01733 VL53L1_SEQUENCE_RANGE_EN; 01734 01735 01736 01737 01738 psystem->system__mode_start = 01739 VL53L1_DEVICESCHEDULERMODE_HISTOGRAM | 01740 VL53L1_DEVICEREADOUTMODE_DUAL_SD | 01741 VL53L1_DEVICEMEASUREMENTMODE_BACKTOBACK; 01742 } 01743 01744 LOG_FUNCTION_END(status); 01745 01746 return status; 01747 } 01748 01749 01750 VL53L1_Error VL53L1_preset_mode_histogram_ranging_with_mm1( 01751 VL53L1_hist_post_process_config_t *phistpostprocess, 01752 VL53L1_static_config_t *pstatic, 01753 VL53L1_histogram_config_t *phistogram, 01754 VL53L1_general_config_t *pgeneral, 01755 VL53L1_timing_config_t *ptiming, 01756 VL53L1_dynamic_config_t *pdynamic, 01757 VL53L1_system_control_t *psystem, 01758 VL53L1_tuning_parm_storage_t *ptuning_parms, 01759 VL53L1_zone_config_t *pzone_cfg) 01760 { 01761 01762 01763 VL53L1_Error status = VL53L1_ERROR_NONE; 01764 01765 LOG_FUNCTION_START(""); 01766 01767 01768 01769 status = 01770 VL53L1_preset_mode_histogram_ranging( 01771 phistpostprocess, 01772 pstatic, 01773 phistogram, 01774 pgeneral, 01775 ptiming, 01776 pdynamic, 01777 psystem, 01778 ptuning_parms, 01779 pzone_cfg); 01780 01781 01782 01783 if (status == VL53L1_ERROR_NONE) { 01784 01785 01786 01787 VL53L1_init_histogram_config_structure( 01788 7, 0, 1, 2, 3, 4, 01789 8+0, 8+1, 8+2, 3, 4, 5, 01790 phistogram); 01791 01792 01793 VL53L1_init_histogram_multizone_config_structure( 01794 7, 0, 1, 2, 3, 4, 01795 8+0, 8+1, 8+2, 3, 4, 5, 01796 &(pzone_cfg->multizone_hist_cfg)); 01797 01798 01799 01800 VL53L1_copy_hist_cfg_to_static_cfg( 01801 phistogram, 01802 pstatic, 01803 pgeneral, 01804 ptiming, 01805 pdynamic); 01806 01807 01808 01809 pdynamic->system__sequence_config = 01810 VL53L1_SEQUENCE_VHV_EN | 01811 VL53L1_SEQUENCE_PHASECAL_EN | 01812 VL53L1_SEQUENCE_DSS1_EN | 01813 VL53L1_SEQUENCE_DSS2_EN | 01814 VL53L1_SEQUENCE_MM1_EN | 01815 VL53L1_SEQUENCE_RANGE_EN; 01816 01817 01818 01819 psystem->system__mode_start = 01820 VL53L1_DEVICESCHEDULERMODE_HISTOGRAM | 01821 VL53L1_DEVICEREADOUTMODE_DUAL_SD | 01822 VL53L1_DEVICEMEASUREMENTMODE_BACKTOBACK; 01823 } 01824 01825 LOG_FUNCTION_END(status); 01826 01827 return status; 01828 } 01829 01830 01831 VL53L1_Error VL53L1_preset_mode_histogram_ranging_with_mm2( 01832 VL53L1_hist_post_process_config_t *phistpostprocess, 01833 VL53L1_static_config_t *pstatic, 01834 VL53L1_histogram_config_t *phistogram, 01835 VL53L1_general_config_t *pgeneral, 01836 VL53L1_timing_config_t *ptiming, 01837 VL53L1_dynamic_config_t *pdynamic, 01838 VL53L1_system_control_t *psystem, 01839 VL53L1_tuning_parm_storage_t *ptuning_parms, 01840 VL53L1_zone_config_t *pzone_cfg) 01841 { 01842 01843 01844 VL53L1_Error status = VL53L1_ERROR_NONE; 01845 01846 LOG_FUNCTION_START(""); 01847 01848 01849 01850 status = 01851 VL53L1_preset_mode_histogram_ranging_with_mm1( 01852 phistpostprocess, 01853 pstatic, 01854 phistogram, 01855 pgeneral, 01856 ptiming, 01857 pdynamic, 01858 psystem, 01859 ptuning_parms, 01860 pzone_cfg); 01861 01862 01863 01864 if (status == VL53L1_ERROR_NONE) { 01865 01866 01867 01868 pdynamic->system__sequence_config = 01869 VL53L1_SEQUENCE_VHV_EN | 01870 VL53L1_SEQUENCE_PHASECAL_EN | 01871 VL53L1_SEQUENCE_DSS1_EN | 01872 VL53L1_SEQUENCE_DSS2_EN | 01873 VL53L1_SEQUENCE_MM2_EN | 01874 VL53L1_SEQUENCE_RANGE_EN; 01875 } 01876 01877 LOG_FUNCTION_END(status); 01878 01879 return status; 01880 } 01881 01882 01883 VL53L1_Error VL53L1_preset_mode_histogram_ranging_mm1_cal( 01884 VL53L1_hist_post_process_config_t *phistpostprocess, 01885 VL53L1_static_config_t *pstatic, 01886 VL53L1_histogram_config_t *phistogram, 01887 VL53L1_general_config_t *pgeneral, 01888 VL53L1_timing_config_t *ptiming, 01889 VL53L1_dynamic_config_t *pdynamic, 01890 VL53L1_system_control_t *psystem, 01891 VL53L1_tuning_parm_storage_t *ptuning_parms, 01892 VL53L1_zone_config_t *pzone_cfg) 01893 { 01894 01895 01896 VL53L1_Error status = VL53L1_ERROR_NONE; 01897 01898 LOG_FUNCTION_START(""); 01899 01900 01901 01902 status = 01903 VL53L1_preset_mode_histogram_ranging( 01904 phistpostprocess, 01905 pstatic, 01906 phistogram, 01907 pgeneral, 01908 ptiming, 01909 pdynamic, 01910 psystem, 01911 ptuning_parms, 01912 pzone_cfg); 01913 01914 01915 01916 if (status == VL53L1_ERROR_NONE) { 01917 01918 01919 01920 VL53L1_init_histogram_config_structure( 01921 7, 8+0, 8+1, 8+2, 8+3, 8+4, 01922 8+0, 8+1, 8+2, 8+3, 8+4, 8+5, 01923 phistogram); 01924 01925 01926 VL53L1_init_histogram_multizone_config_structure( 01927 7, 8+0, 8+1, 8+2, 8+3, 8+4, 01928 8+0, 8+1, 8+2, 8+3, 8+4, 8+5, 01929 &(pzone_cfg->multizone_hist_cfg)); 01930 01931 01932 01933 VL53L1_copy_hist_cfg_to_static_cfg( 01934 phistogram, 01935 pstatic, 01936 pgeneral, 01937 ptiming, 01938 pdynamic); 01939 01940 01941 01942 pgeneral->dss_config__roi_mode_control = 01943 VL53L1_DEVICEDSSMODE__REQUESTED_EFFFECTIVE_SPADS; 01944 01945 01946 01947 pdynamic->system__sequence_config = 01948 VL53L1_SEQUENCE_VHV_EN | 01949 VL53L1_SEQUENCE_PHASECAL_EN | 01950 VL53L1_SEQUENCE_DSS1_EN | 01951 VL53L1_SEQUENCE_DSS2_EN | 01952 VL53L1_SEQUENCE_MM1_EN | 01953 VL53L1_SEQUENCE_RANGE_EN; 01954 01955 } 01956 01957 LOG_FUNCTION_END(status); 01958 01959 return status; 01960 } 01961 01962 01963 VL53L1_Error VL53L1_preset_mode_histogram_ranging_mm2_cal( 01964 VL53L1_hist_post_process_config_t *phistpostprocess, 01965 VL53L1_static_config_t *pstatic, 01966 VL53L1_histogram_config_t *phistogram, 01967 VL53L1_general_config_t *pgeneral, 01968 VL53L1_timing_config_t *ptiming, 01969 VL53L1_dynamic_config_t *pdynamic, 01970 VL53L1_system_control_t *psystem, 01971 VL53L1_tuning_parm_storage_t *ptuning_parms, 01972 VL53L1_zone_config_t *pzone_cfg) 01973 { 01974 01975 01976 VL53L1_Error status = VL53L1_ERROR_NONE; 01977 01978 LOG_FUNCTION_START(""); 01979 01980 01981 01982 status = 01983 VL53L1_preset_mode_histogram_ranging_mm1_cal( 01984 phistpostprocess, 01985 pstatic, 01986 phistogram, 01987 pgeneral, 01988 ptiming, 01989 pdynamic, 01990 psystem, 01991 ptuning_parms, 01992 pzone_cfg); 01993 01994 if (status == VL53L1_ERROR_NONE) { 01995 01996 01997 01998 pdynamic->system__sequence_config = 01999 VL53L1_SEQUENCE_VHV_EN | 02000 VL53L1_SEQUENCE_PHASECAL_EN | 02001 VL53L1_SEQUENCE_DSS1_EN | 02002 VL53L1_SEQUENCE_DSS2_EN | 02003 VL53L1_SEQUENCE_MM2_EN | 02004 VL53L1_SEQUENCE_RANGE_EN; 02005 02006 } 02007 02008 LOG_FUNCTION_END(status); 02009 02010 return status; 02011 } 02012 02013 02014 VL53L1_Error VL53L1_preset_mode_histogram_ranging_short_timing( 02015 VL53L1_hist_post_process_config_t *phistpostprocess, 02016 VL53L1_static_config_t *pstatic, 02017 VL53L1_histogram_config_t *phistogram, 02018 VL53L1_general_config_t *pgeneral, 02019 VL53L1_timing_config_t *ptiming, 02020 VL53L1_dynamic_config_t *pdynamic, 02021 VL53L1_system_control_t *psystem, 02022 VL53L1_tuning_parm_storage_t *ptuning_parms, 02023 VL53L1_zone_config_t *pzone_cfg) 02024 { 02025 02026 02027 VL53L1_Error status = VL53L1_ERROR_NONE; 02028 02029 LOG_FUNCTION_START(""); 02030 02031 02032 02033 status = 02034 VL53L1_preset_mode_histogram_ranging( 02035 phistpostprocess, 02036 pstatic, 02037 phistogram, 02038 pgeneral, 02039 ptiming, 02040 pdynamic, 02041 psystem, 02042 ptuning_parms, 02043 pzone_cfg); 02044 02045 02046 02047 if (status == VL53L1_ERROR_NONE) { 02048 02049 02050 02051 pstatic->dss_config__target_total_rate_mcps = 0x1400; 02052 02053 02054 02055 VL53L1_init_histogram_config_structure( 02056 7, 0, 1, 2, 3, 4, 02057 7, 0, 1, 2, 3, 4, 02058 phistogram); 02059 02060 02061 VL53L1_init_histogram_multizone_config_structure( 02062 7, 0, 1, 2, 3, 4, 02063 7, 0, 1, 2, 3, 4, 02064 &(pzone_cfg->multizone_hist_cfg)); 02065 02066 02067 02068 VL53L1_copy_hist_cfg_to_static_cfg( 02069 phistogram, 02070 pstatic, 02071 pgeneral, 02072 ptiming, 02073 pdynamic); 02074 02075 02076 02077 ptiming->range_config__vcsel_period_a = 0x04; 02078 ptiming->range_config__vcsel_period_b = 0x03; 02079 ptiming->mm_config__timeout_macrop_a_hi = 0x00; 02080 ptiming->mm_config__timeout_macrop_a_lo = 0x42; 02081 ptiming->mm_config__timeout_macrop_b_hi = 0x00; 02082 ptiming->mm_config__timeout_macrop_b_lo = 0x42; 02083 ptiming->range_config__timeout_macrop_a_hi = 0x00; 02084 ptiming->range_config__timeout_macrop_a_lo = 0x52; 02085 ptiming->range_config__timeout_macrop_b_hi = 0x00; 02086 ptiming->range_config__timeout_macrop_b_lo = 0x66; 02087 02088 pgeneral->cal_config__vcsel_start = 0x04; 02089 02090 02091 02092 pgeneral->phasecal_config__timeout_macrop = 0xa4; 02093 02094 02095 02096 pdynamic->system__sequence_config = 02097 VL53L1_SEQUENCE_VHV_EN | 02098 VL53L1_SEQUENCE_PHASECAL_EN | 02099 VL53L1_SEQUENCE_DSS1_EN | 02100 VL53L1_SEQUENCE_DSS2_EN | 02101 02102 02103 VL53L1_SEQUENCE_RANGE_EN; 02104 02105 02106 02107 02108 psystem->system__mode_start = 02109 VL53L1_DEVICESCHEDULERMODE_HISTOGRAM | 02110 VL53L1_DEVICEREADOUTMODE_DUAL_SD | 02111 VL53L1_DEVICEMEASUREMENTMODE_BACKTOBACK; 02112 } 02113 02114 LOG_FUNCTION_END(status); 02115 02116 return status; 02117 } 02118 02119 02120 VL53L1_Error VL53L1_preset_mode_histogram_long_range( 02121 VL53L1_hist_post_process_config_t *phistpostprocess, 02122 VL53L1_static_config_t *pstatic, 02123 VL53L1_histogram_config_t *phistogram, 02124 VL53L1_general_config_t *pgeneral, 02125 VL53L1_timing_config_t *ptiming, 02126 VL53L1_dynamic_config_t *pdynamic, 02127 VL53L1_system_control_t *psystem, 02128 VL53L1_tuning_parm_storage_t *ptuning_parms, 02129 VL53L1_zone_config_t *pzone_cfg) 02130 { 02131 02132 02133 VL53L1_Error status = VL53L1_ERROR_NONE; 02134 02135 LOG_FUNCTION_START(""); 02136 02137 02138 02139 status = 02140 VL53L1_preset_mode_histogram_ranging( 02141 phistpostprocess, 02142 pstatic, 02143 phistogram, 02144 pgeneral, 02145 ptiming, 02146 pdynamic, 02147 psystem, 02148 ptuning_parms, 02149 pzone_cfg); 02150 02151 02152 02153 if (status == VL53L1_ERROR_NONE) { 02154 02155 02156 02157 02158 02159 VL53L1_init_histogram_config_structure( 02160 7, 0, 1, 2, 3, 4, 02161 0, 1, 2, 3, 4, 5, 02162 phistogram); 02163 02164 02165 VL53L1_init_histogram_multizone_config_structure( 02166 7, 0, 1, 2, 3, 4, 02167 0, 1, 2, 3, 4, 5, 02168 &(pzone_cfg->multizone_hist_cfg)); 02169 02170 02171 02172 VL53L1_copy_hist_cfg_to_static_cfg( 02173 phistogram, 02174 pstatic, 02175 pgeneral, 02176 ptiming, 02177 pdynamic); 02178 02179 02180 02181 ptiming->range_config__vcsel_period_a = 0x09; 02182 ptiming->range_config__vcsel_period_b = 0x0b; 02183 02184 02185 02186 ptiming->mm_config__timeout_macrop_a_hi = 0x00; 02187 ptiming->mm_config__timeout_macrop_a_lo = 0x21; 02188 ptiming->mm_config__timeout_macrop_b_hi = 0x00; 02189 ptiming->mm_config__timeout_macrop_b_lo = 0x1b; 02190 02191 02192 02193 ptiming->range_config__timeout_macrop_a_hi = 0x00; 02194 ptiming->range_config__timeout_macrop_a_lo = 0x29; 02195 ptiming->range_config__timeout_macrop_b_hi = 0x00; 02196 ptiming->range_config__timeout_macrop_b_lo = 0x22; 02197 02198 02199 02200 pgeneral->cal_config__vcsel_start = 0x09; 02201 02202 02203 02204 pgeneral->phasecal_config__timeout_macrop = 0xF5; 02205 02206 02207 02208 pdynamic->sd_config__woi_sd0 = 0x09; 02209 pdynamic->sd_config__woi_sd1 = 0x0B; 02210 pdynamic->sd_config__initial_phase_sd0 = 02211 ptuning_parms->tp_init_phase_rtn_hist_long; 02212 pdynamic->sd_config__initial_phase_sd1 = 02213 ptuning_parms->tp_init_phase_ref_hist_long; 02214 02215 02216 02217 phistpostprocess->valid_phase_low = 0x08; 02218 phistpostprocess->valid_phase_high = 0x88; 02219 02220 pdynamic->system__sequence_config = 02221 VL53L1_SEQUENCE_VHV_EN | 02222 VL53L1_SEQUENCE_PHASECAL_EN | 02223 VL53L1_SEQUENCE_DSS1_EN | 02224 VL53L1_SEQUENCE_DSS2_EN | 02225 VL53L1_SEQUENCE_RANGE_EN; 02226 02227 02228 02229 02230 psystem->system__mode_start = 02231 VL53L1_DEVICESCHEDULERMODE_HISTOGRAM | 02232 VL53L1_DEVICEREADOUTMODE_DUAL_SD | 02233 VL53L1_DEVICEMEASUREMENTMODE_BACKTOBACK; 02234 } 02235 02236 LOG_FUNCTION_END(status); 02237 02238 return status; 02239 } 02240 02241 02242 VL53L1_Error VL53L1_preset_mode_histogram_long_range_mm1( 02243 VL53L1_hist_post_process_config_t *phistpostprocess, 02244 VL53L1_static_config_t *pstatic, 02245 VL53L1_histogram_config_t *phistogram, 02246 VL53L1_general_config_t *pgeneral, 02247 VL53L1_timing_config_t *ptiming, 02248 VL53L1_dynamic_config_t *pdynamic, 02249 VL53L1_system_control_t *psystem, 02250 VL53L1_tuning_parm_storage_t *ptuning_parms, 02251 VL53L1_zone_config_t *pzone_cfg) 02252 { 02253 02254 02255 VL53L1_Error status = VL53L1_ERROR_NONE; 02256 02257 LOG_FUNCTION_START(""); 02258 02259 02260 02261 status = 02262 VL53L1_preset_mode_histogram_long_range( 02263 phistpostprocess, 02264 pstatic, 02265 phistogram, 02266 pgeneral, 02267 ptiming, 02268 pdynamic, 02269 psystem, 02270 ptuning_parms, 02271 pzone_cfg); 02272 02273 02274 02275 if (status == VL53L1_ERROR_NONE) { 02276 02277 02278 02279 02280 02281 VL53L1_init_histogram_config_structure( 02282 7, 0, 1, 2, 3, 4, 02283 8+0, 8+1, 8+2, 3, 4, 5, 02284 phistogram); 02285 02286 02287 VL53L1_init_histogram_multizone_config_structure( 02288 7, 0, 1, 2, 3, 4, 02289 8+0, 8+1, 8+2, 3, 4, 5, 02290 &(pzone_cfg->multizone_hist_cfg)); 02291 02292 02293 02294 VL53L1_copy_hist_cfg_to_static_cfg( 02295 phistogram, 02296 pstatic, 02297 pgeneral, 02298 ptiming, 02299 pdynamic); 02300 02301 02302 02303 pdynamic->system__sequence_config = 02304 VL53L1_SEQUENCE_VHV_EN | 02305 VL53L1_SEQUENCE_PHASECAL_EN | 02306 VL53L1_SEQUENCE_DSS1_EN | 02307 VL53L1_SEQUENCE_DSS2_EN | 02308 VL53L1_SEQUENCE_MM1_EN | 02309 VL53L1_SEQUENCE_RANGE_EN; 02310 } 02311 02312 LOG_FUNCTION_END(status); 02313 02314 return status; 02315 } 02316 02317 02318 VL53L1_Error VL53L1_preset_mode_histogram_long_range_mm2( 02319 VL53L1_hist_post_process_config_t *phistpostprocess, 02320 VL53L1_static_config_t *pstatic, 02321 VL53L1_histogram_config_t *phistogram, 02322 VL53L1_general_config_t *pgeneral, 02323 VL53L1_timing_config_t *ptiming, 02324 VL53L1_dynamic_config_t *pdynamic, 02325 VL53L1_system_control_t *psystem, 02326 VL53L1_tuning_parm_storage_t *ptuning_parms, 02327 VL53L1_zone_config_t *pzone_cfg) 02328 { 02329 02330 02331 VL53L1_Error status = VL53L1_ERROR_NONE; 02332 02333 LOG_FUNCTION_START(""); 02334 02335 02336 02337 status = 02338 VL53L1_preset_mode_histogram_long_range_mm1( 02339 phistpostprocess, 02340 pstatic, 02341 phistogram, 02342 pgeneral, 02343 ptiming, 02344 pdynamic, 02345 psystem, 02346 ptuning_parms, 02347 pzone_cfg); 02348 02349 02350 02351 if (status == VL53L1_ERROR_NONE) { 02352 02353 02354 02355 pdynamic->system__sequence_config = 02356 VL53L1_SEQUENCE_VHV_EN | 02357 VL53L1_SEQUENCE_PHASECAL_EN | 02358 VL53L1_SEQUENCE_DSS1_EN | 02359 VL53L1_SEQUENCE_DSS2_EN | 02360 VL53L1_SEQUENCE_MM2_EN | 02361 VL53L1_SEQUENCE_RANGE_EN; 02362 } 02363 02364 LOG_FUNCTION_END(status); 02365 02366 return status; 02367 } 02368 02369 02370 02371 VL53L1_Error VL53L1_preset_mode_histogram_medium_range( 02372 VL53L1_hist_post_process_config_t *phistpostprocess, 02373 VL53L1_static_config_t *pstatic, 02374 VL53L1_histogram_config_t *phistogram, 02375 VL53L1_general_config_t *pgeneral, 02376 VL53L1_timing_config_t *ptiming, 02377 VL53L1_dynamic_config_t *pdynamic, 02378 VL53L1_system_control_t *psystem, 02379 VL53L1_tuning_parm_storage_t *ptuning_parms, 02380 VL53L1_zone_config_t *pzone_cfg) 02381 { 02382 02383 02384 VL53L1_Error status = VL53L1_ERROR_NONE; 02385 02386 LOG_FUNCTION_START(""); 02387 02388 02389 02390 status = 02391 VL53L1_preset_mode_histogram_ranging( 02392 phistpostprocess, 02393 pstatic, 02394 phistogram, 02395 pgeneral, 02396 ptiming, 02397 pdynamic, 02398 psystem, 02399 ptuning_parms, 02400 pzone_cfg); 02401 02402 02403 02404 if (status == VL53L1_ERROR_NONE) { 02405 02406 02407 02408 02409 02410 VL53L1_init_histogram_config_structure( 02411 7, 0, 1, 1, 2, 2, 02412 0, 1, 2, 1, 2, 3, 02413 phistogram); 02414 02415 02416 VL53L1_init_histogram_multizone_config_structure( 02417 7, 0, 1, 1, 2, 2, 02418 0, 1, 2, 1, 2, 3, 02419 &(pzone_cfg->multizone_hist_cfg)); 02420 02421 02422 02423 VL53L1_copy_hist_cfg_to_static_cfg( 02424 phistogram, 02425 pstatic, 02426 pgeneral, 02427 ptiming, 02428 pdynamic); 02429 02430 02431 02432 ptiming->range_config__vcsel_period_a = 0x05; 02433 ptiming->range_config__vcsel_period_b = 0x07; 02434 02435 02436 02437 ptiming->mm_config__timeout_macrop_a_hi = 0x00; 02438 ptiming->mm_config__timeout_macrop_a_lo = 0x36; 02439 ptiming->mm_config__timeout_macrop_b_hi = 0x00; 02440 ptiming->mm_config__timeout_macrop_b_lo = 0x28; 02441 02442 02443 02444 ptiming->range_config__timeout_macrop_a_hi = 0x00; 02445 ptiming->range_config__timeout_macrop_a_lo = 0x44; 02446 ptiming->range_config__timeout_macrop_b_hi = 0x00; 02447 ptiming->range_config__timeout_macrop_b_lo = 0x33; 02448 02449 02450 02451 pgeneral->cal_config__vcsel_start = 0x05; 02452 02453 02454 02455 pgeneral->phasecal_config__timeout_macrop = 0xF5; 02456 02457 02458 02459 pdynamic->sd_config__woi_sd0 = 0x05; 02460 pdynamic->sd_config__woi_sd1 = 0x07; 02461 pdynamic->sd_config__initial_phase_sd0 = 02462 ptuning_parms->tp_init_phase_rtn_hist_med; 02463 pdynamic->sd_config__initial_phase_sd1 = 02464 ptuning_parms->tp_init_phase_ref_hist_med; 02465 02466 02467 02468 phistpostprocess->valid_phase_low = 0x08; 02469 phistpostprocess->valid_phase_high = 0x48; 02470 02471 pdynamic->system__sequence_config = 02472 VL53L1_SEQUENCE_VHV_EN | 02473 VL53L1_SEQUENCE_PHASECAL_EN | 02474 VL53L1_SEQUENCE_DSS1_EN | 02475 VL53L1_SEQUENCE_DSS2_EN | 02476 VL53L1_SEQUENCE_RANGE_EN; 02477 02478 02479 02480 02481 psystem->system__mode_start = 02482 VL53L1_DEVICESCHEDULERMODE_HISTOGRAM | 02483 VL53L1_DEVICEREADOUTMODE_DUAL_SD | 02484 VL53L1_DEVICEMEASUREMENTMODE_BACKTOBACK; 02485 } 02486 02487 LOG_FUNCTION_END(status); 02488 02489 return status; 02490 } 02491 02492 02493 VL53L1_Error VL53L1_preset_mode_histogram_medium_range_mm1( 02494 VL53L1_hist_post_process_config_t *phistpostprocess, 02495 VL53L1_static_config_t *pstatic, 02496 VL53L1_histogram_config_t *phistogram, 02497 VL53L1_general_config_t *pgeneral, 02498 VL53L1_timing_config_t *ptiming, 02499 VL53L1_dynamic_config_t *pdynamic, 02500 VL53L1_system_control_t *psystem, 02501 VL53L1_tuning_parm_storage_t *ptuning_parms, 02502 VL53L1_zone_config_t *pzone_cfg) 02503 { 02504 02505 02506 VL53L1_Error status = VL53L1_ERROR_NONE; 02507 02508 LOG_FUNCTION_START(""); 02509 02510 02511 02512 status = 02513 VL53L1_preset_mode_histogram_medium_range( 02514 phistpostprocess, 02515 pstatic, 02516 phistogram, 02517 pgeneral, 02518 ptiming, 02519 pdynamic, 02520 psystem, 02521 ptuning_parms, 02522 pzone_cfg); 02523 02524 02525 02526 if (status == VL53L1_ERROR_NONE) { 02527 02528 02529 02530 VL53L1_init_histogram_config_structure( 02531 7, 0, 1, 1, 2, 2, 02532 8+0, 8+1, 8+2, 1, 2, 3, 02533 phistogram); 02534 02535 02536 VL53L1_init_histogram_multizone_config_structure( 02537 7, 0, 1, 1, 2, 2, 02538 8+0, 8+1, 8+2, 1, 2, 3, 02539 &(pzone_cfg->multizone_hist_cfg)); 02540 02541 02542 02543 VL53L1_copy_hist_cfg_to_static_cfg( 02544 phistogram, 02545 pstatic, 02546 pgeneral, 02547 ptiming, 02548 pdynamic); 02549 02550 02551 02552 pdynamic->system__sequence_config = 02553 VL53L1_SEQUENCE_VHV_EN | 02554 VL53L1_SEQUENCE_PHASECAL_EN | 02555 VL53L1_SEQUENCE_DSS1_EN | 02556 VL53L1_SEQUENCE_DSS2_EN | 02557 VL53L1_SEQUENCE_MM1_EN | 02558 VL53L1_SEQUENCE_RANGE_EN; 02559 } 02560 02561 LOG_FUNCTION_END(status); 02562 02563 return status; 02564 } 02565 02566 02567 VL53L1_Error VL53L1_preset_mode_histogram_medium_range_mm2( 02568 VL53L1_hist_post_process_config_t *phistpostprocess, 02569 VL53L1_static_config_t *pstatic, 02570 VL53L1_histogram_config_t *phistogram, 02571 VL53L1_general_config_t *pgeneral, 02572 VL53L1_timing_config_t *ptiming, 02573 VL53L1_dynamic_config_t *pdynamic, 02574 VL53L1_system_control_t *psystem, 02575 VL53L1_tuning_parm_storage_t *ptuning_parms, 02576 VL53L1_zone_config_t *pzone_cfg) 02577 { 02578 02579 02580 VL53L1_Error status = VL53L1_ERROR_NONE; 02581 02582 LOG_FUNCTION_START(""); 02583 02584 02585 02586 status = 02587 VL53L1_preset_mode_histogram_medium_range_mm1( 02588 phistpostprocess, 02589 pstatic, 02590 phistogram, 02591 pgeneral, 02592 ptiming, 02593 pdynamic, 02594 psystem, 02595 ptuning_parms, 02596 pzone_cfg); 02597 02598 02599 02600 if (status == VL53L1_ERROR_NONE) { 02601 02602 02603 02604 pdynamic->system__sequence_config = 02605 VL53L1_SEQUENCE_VHV_EN | 02606 VL53L1_SEQUENCE_PHASECAL_EN | 02607 VL53L1_SEQUENCE_DSS1_EN | 02608 VL53L1_SEQUENCE_DSS2_EN | 02609 VL53L1_SEQUENCE_MM2_EN | 02610 VL53L1_SEQUENCE_RANGE_EN; 02611 } 02612 02613 LOG_FUNCTION_END(status); 02614 02615 return status; 02616 } 02617 02618 02619 VL53L1_Error VL53L1_preset_mode_histogram_short_range( 02620 VL53L1_hist_post_process_config_t *phistpostprocess, 02621 VL53L1_static_config_t *pstatic, 02622 VL53L1_histogram_config_t *phistogram, 02623 VL53L1_general_config_t *pgeneral, 02624 VL53L1_timing_config_t *ptiming, 02625 VL53L1_dynamic_config_t *pdynamic, 02626 VL53L1_system_control_t *psystem, 02627 VL53L1_tuning_parm_storage_t *ptuning_parms, 02628 VL53L1_zone_config_t *pzone_cfg) 02629 { 02630 02631 02632 VL53L1_Error status = VL53L1_ERROR_NONE; 02633 02634 LOG_FUNCTION_START(""); 02635 02636 02637 02638 status = 02639 VL53L1_preset_mode_histogram_ranging( 02640 phistpostprocess, 02641 pstatic, 02642 phistogram, 02643 pgeneral, 02644 ptiming, 02645 pdynamic, 02646 psystem, 02647 ptuning_parms, 02648 pzone_cfg); 02649 02650 02651 02652 if (status == VL53L1_ERROR_NONE) { 02653 02654 02655 02656 02657 02658 VL53L1_init_histogram_config_structure( 02659 7, 7, 0, 1, 1, 1, 02660 0, 1, 1, 1, 2, 2, 02661 phistogram); 02662 02663 02664 VL53L1_init_histogram_multizone_config_structure( 02665 7, 7, 0, 1, 1, 1, 02666 0, 1, 1, 1, 2, 2, 02667 &(pzone_cfg->multizone_hist_cfg)); 02668 02669 02670 02671 VL53L1_copy_hist_cfg_to_static_cfg( 02672 phistogram, 02673 pstatic, 02674 pgeneral, 02675 ptiming, 02676 pdynamic); 02677 02678 02679 02680 ptiming->range_config__vcsel_period_a = 0x03; 02681 ptiming->range_config__vcsel_period_b = 0x05; 02682 02683 02684 02685 ptiming->mm_config__timeout_macrop_a_hi = 0x00; 02686 ptiming->mm_config__timeout_macrop_a_lo = 0x52; 02687 ptiming->mm_config__timeout_macrop_b_hi = 0x00; 02688 ptiming->mm_config__timeout_macrop_b_lo = 0x37; 02689 02690 02691 02692 ptiming->range_config__timeout_macrop_a_hi = 0x00; 02693 ptiming->range_config__timeout_macrop_a_lo = 0x66; 02694 ptiming->range_config__timeout_macrop_b_hi = 0x00; 02695 ptiming->range_config__timeout_macrop_b_lo = 0x44; 02696 02697 02698 02699 pgeneral->cal_config__vcsel_start = 0x03; 02700 02701 02702 02703 pgeneral->phasecal_config__timeout_macrop = 0xF5; 02704 02705 02706 02707 pdynamic->sd_config__woi_sd0 = 0x03; 02708 pdynamic->sd_config__woi_sd1 = 0x05; 02709 pdynamic->sd_config__initial_phase_sd0 = 02710 ptuning_parms->tp_init_phase_rtn_hist_short; 02711 pdynamic->sd_config__initial_phase_sd1 = 02712 ptuning_parms->tp_init_phase_ref_hist_short; 02713 02714 02715 phistpostprocess->valid_phase_low = 0x08; 02716 phistpostprocess->valid_phase_high = 0x28; 02717 02718 pdynamic->system__sequence_config = 02719 VL53L1_SEQUENCE_VHV_EN | 02720 VL53L1_SEQUENCE_PHASECAL_EN | 02721 VL53L1_SEQUENCE_DSS1_EN | 02722 VL53L1_SEQUENCE_DSS2_EN | 02723 VL53L1_SEQUENCE_MM1_EN | 02724 02725 VL53L1_SEQUENCE_RANGE_EN; 02726 02727 02728 02729 02730 psystem->system__mode_start = 02731 VL53L1_DEVICESCHEDULERMODE_HISTOGRAM | 02732 VL53L1_DEVICEREADOUTMODE_DUAL_SD | 02733 VL53L1_DEVICEMEASUREMENTMODE_BACKTOBACK; 02734 } 02735 02736 LOG_FUNCTION_END(status); 02737 02738 return status; 02739 } 02740 02741 02742 02743 VL53L1_Error VL53L1_preset_mode_special_histogram_short_range( 02744 VL53L1_hist_post_process_config_t *phistpostprocess, 02745 VL53L1_static_config_t *pstatic, 02746 VL53L1_histogram_config_t *phistogram, 02747 VL53L1_general_config_t *pgeneral, 02748 VL53L1_timing_config_t *ptiming, 02749 VL53L1_dynamic_config_t *pdynamic, 02750 VL53L1_system_control_t *psystem, 02751 VL53L1_tuning_parm_storage_t *ptuning_parms, 02752 VL53L1_zone_config_t *pzone_cfg) 02753 { 02754 02755 02756 VL53L1_Error status = VL53L1_ERROR_NONE; 02757 02758 LOG_FUNCTION_START(""); 02759 02760 02761 02762 status = 02763 VL53L1_preset_mode_histogram_short_range( 02764 phistpostprocess, 02765 pstatic, 02766 phistogram, 02767 pgeneral, 02768 ptiming, 02769 pdynamic, 02770 psystem, 02771 ptuning_parms, 02772 pzone_cfg); 02773 02774 02775 02776 if (status == VL53L1_ERROR_NONE) { 02777 02778 02779 02780 02781 02782 VL53L1_init_histogram_config_structure( 02783 7, 7, 0, 0, 1, 1, 02784 0, 0, 0, 1, 1, 1, 02785 phistogram); 02786 02787 02788 VL53L1_init_histogram_multizone_config_structure( 02789 7, 7, 0, 0, 1, 1, 02790 0, 0, 0, 1, 1, 1, 02791 &(pzone_cfg->multizone_hist_cfg)); 02792 02793 02794 02795 VL53L1_copy_hist_cfg_to_static_cfg( 02796 phistogram, 02797 pstatic, 02798 pgeneral, 02799 ptiming, 02800 pdynamic); 02801 02802 02803 02804 ptiming->range_config__vcsel_period_a = 0x02; 02805 ptiming->range_config__vcsel_period_b = 0x03; 02806 02807 02808 02809 pgeneral->cal_config__vcsel_start = 0x00; 02810 02811 02812 02813 pgeneral->phasecal_config__target = 0x31; 02814 02815 02816 02817 pdynamic->sd_config__woi_sd0 = 0x02; 02818 pdynamic->sd_config__woi_sd1 = 0x03; 02819 pdynamic->sd_config__initial_phase_sd0 = 02820 ptuning_parms->tp_init_phase_rtn_hist_short; 02821 pdynamic->sd_config__initial_phase_sd1 = 02822 ptuning_parms->tp_init_phase_ref_hist_short; 02823 02824 02825 02826 phistpostprocess->valid_phase_low = 0x10; 02827 phistpostprocess->valid_phase_high = 0x18; 02828 02829 } 02830 02831 LOG_FUNCTION_END(status); 02832 02833 return status; 02834 } 02835 02836 02837 02838 VL53L1_Error VL53L1_preset_mode_histogram_short_range_mm1( 02839 VL53L1_hist_post_process_config_t *phistpostprocess, 02840 VL53L1_static_config_t *pstatic, 02841 VL53L1_histogram_config_t *phistogram, 02842 VL53L1_general_config_t *pgeneral, 02843 VL53L1_timing_config_t *ptiming, 02844 VL53L1_dynamic_config_t *pdynamic, 02845 VL53L1_system_control_t *psystem, 02846 VL53L1_tuning_parm_storage_t *ptuning_parms, 02847 VL53L1_zone_config_t *pzone_cfg) 02848 { 02849 02850 02851 VL53L1_Error status = VL53L1_ERROR_NONE; 02852 02853 LOG_FUNCTION_START(""); 02854 02855 02856 02857 status = 02858 VL53L1_preset_mode_histogram_short_range( 02859 phistpostprocess, 02860 pstatic, 02861 phistogram, 02862 pgeneral, 02863 ptiming, 02864 pdynamic, 02865 psystem, 02866 ptuning_parms, 02867 pzone_cfg); 02868 02869 02870 02871 if (status == VL53L1_ERROR_NONE) { 02872 02873 02874 02875 02876 02877 VL53L1_init_histogram_config_structure( 02878 7, 7, 0, 1, 1, 1, 02879 8+0, 8+1, 1, 1, 2, 2, 02880 phistogram); 02881 02882 02883 VL53L1_init_histogram_multizone_config_structure( 02884 7, 7, 0, 1, 1, 1, 02885 8+0, 8+1, 1, 1, 2, 2, 02886 &(pzone_cfg->multizone_hist_cfg)); 02887 02888 02889 02890 VL53L1_copy_hist_cfg_to_static_cfg( 02891 phistogram, 02892 pstatic, 02893 pgeneral, 02894 ptiming, 02895 pdynamic); 02896 02897 02898 02899 pdynamic->system__sequence_config = 02900 VL53L1_SEQUENCE_VHV_EN | 02901 VL53L1_SEQUENCE_PHASECAL_EN | 02902 VL53L1_SEQUENCE_DSS1_EN | 02903 VL53L1_SEQUENCE_DSS2_EN | 02904 VL53L1_SEQUENCE_MM1_EN | 02905 VL53L1_SEQUENCE_RANGE_EN; 02906 02907 } 02908 02909 LOG_FUNCTION_END(status); 02910 02911 return status; 02912 } 02913 02914 02915 VL53L1_Error VL53L1_preset_mode_histogram_short_range_mm2( 02916 VL53L1_hist_post_process_config_t *phistpostprocess, 02917 VL53L1_static_config_t *pstatic, 02918 VL53L1_histogram_config_t *phistogram, 02919 VL53L1_general_config_t *pgeneral, 02920 VL53L1_timing_config_t *ptiming, 02921 VL53L1_dynamic_config_t *pdynamic, 02922 VL53L1_system_control_t *psystem, 02923 VL53L1_tuning_parm_storage_t *ptuning_parms, 02924 VL53L1_zone_config_t *pzone_cfg) 02925 { 02926 02927 02928 VL53L1_Error status = VL53L1_ERROR_NONE; 02929 02930 LOG_FUNCTION_START(""); 02931 02932 02933 02934 status = 02935 VL53L1_preset_mode_histogram_short_range_mm1( 02936 phistpostprocess, 02937 pstatic, 02938 phistogram, 02939 pgeneral, 02940 ptiming, 02941 pdynamic, 02942 psystem, 02943 ptuning_parms, 02944 pzone_cfg); 02945 02946 02947 02948 if (status == VL53L1_ERROR_NONE) { 02949 02950 02951 02952 pdynamic->system__sequence_config = 02953 VL53L1_SEQUENCE_VHV_EN | 02954 VL53L1_SEQUENCE_PHASECAL_EN | 02955 VL53L1_SEQUENCE_DSS1_EN | 02956 VL53L1_SEQUENCE_DSS2_EN | 02957 VL53L1_SEQUENCE_MM2_EN | 02958 VL53L1_SEQUENCE_RANGE_EN; 02959 } 02960 02961 LOG_FUNCTION_END(status); 02962 02963 return status; 02964 } 02965 02966 02967 02968 VL53L1_Error VL53L1_preset_mode_histogram_characterisation( 02969 VL53L1_hist_post_process_config_t *phistpostprocess, 02970 VL53L1_static_config_t *pstatic, 02971 VL53L1_histogram_config_t *phistogram, 02972 VL53L1_general_config_t *pgeneral, 02973 VL53L1_timing_config_t *ptiming, 02974 VL53L1_dynamic_config_t *pdynamic, 02975 VL53L1_system_control_t *psystem, 02976 VL53L1_tuning_parm_storage_t *ptuning_parms, 02977 VL53L1_zone_config_t *pzone_cfg) 02978 { 02979 02980 02981 VL53L1_Error status = VL53L1_ERROR_NONE; 02982 02983 LOG_FUNCTION_START(""); 02984 02985 02986 02987 status = 02988 VL53L1_preset_mode_histogram_ranging( 02989 phistpostprocess, 02990 pstatic, 02991 phistogram, 02992 pgeneral, 02993 ptiming, 02994 pdynamic, 02995 psystem, 02996 ptuning_parms, 02997 pzone_cfg); 02998 02999 03000 03001 if (status == VL53L1_ERROR_NONE) { 03002 03003 03004 03005 pstatic->debug__ctrl = 0x01; 03006 psystem->power_management__go1_power_force = 0x01; 03007 03008 pdynamic->system__sequence_config = 03009 VL53L1_SEQUENCE_VHV_EN | 03010 VL53L1_SEQUENCE_PHASECAL_EN | 03011 VL53L1_SEQUENCE_RANGE_EN; 03012 03013 psystem->system__mode_start = 03014 VL53L1_DEVICESCHEDULERMODE_HISTOGRAM | 03015 VL53L1_DEVICEREADOUTMODE_SPLIT_MANUAL | 03016 VL53L1_DEVICEMEASUREMENTMODE_BACKTOBACK; 03017 } 03018 03019 LOG_FUNCTION_END(status); 03020 03021 return status; 03022 } 03023 03024 03025 VL53L1_Error VL53L1_preset_mode_histogram_xtalk_planar( 03026 VL53L1_hist_post_process_config_t *phistpostprocess, 03027 VL53L1_static_config_t *pstatic, 03028 VL53L1_histogram_config_t *phistogram, 03029 VL53L1_general_config_t *pgeneral, 03030 VL53L1_timing_config_t *ptiming, 03031 VL53L1_dynamic_config_t *pdynamic, 03032 VL53L1_system_control_t *psystem, 03033 VL53L1_tuning_parm_storage_t *ptuning_parms, 03034 VL53L1_zone_config_t *pzone_cfg) 03035 { 03036 03037 03038 VL53L1_Error status = VL53L1_ERROR_NONE; 03039 03040 LOG_FUNCTION_START(""); 03041 03042 03043 03044 status = 03045 VL53L1_preset_mode_histogram_multizone_long_range( 03046 phistpostprocess, 03047 pstatic, 03048 phistogram, 03049 pgeneral, 03050 ptiming, 03051 pdynamic, 03052 psystem, 03053 ptuning_parms, 03054 pzone_cfg); 03055 03056 03057 03058 if (status == VL53L1_ERROR_NONE) { 03059 03060 03061 03062 status = 03063 VL53L1_zone_preset_xtalk_planar( 03064 pgeneral, 03065 pzone_cfg); 03066 03067 03068 03069 ptiming->range_config__vcsel_period_a = 0x09; 03070 ptiming->range_config__vcsel_period_b = 0x09; 03071 03072 03073 03074 VL53L1_init_histogram_config_structure( 03075 7, 0, 1, 2, 3, 4, 03076 7, 0, 1, 2, 3, 4, 03077 phistogram); 03078 03079 03080 03081 VL53L1_init_histogram_multizone_config_structure( 03082 7, 0, 1, 2, 3, 4, 03083 7, 0, 1, 2, 3, 4, 03084 &(pzone_cfg->multizone_hist_cfg)); 03085 03086 03087 03088 03089 if (status == VL53L1_ERROR_NONE) { 03090 status = 03091 VL53L1_set_histogram_multizone_initial_bin_config( 03092 pzone_cfg, 03093 phistogram, 03094 &(pzone_cfg->multizone_hist_cfg)); 03095 } 03096 03097 03098 03099 VL53L1_copy_hist_cfg_to_static_cfg( 03100 phistogram, 03101 pstatic, 03102 pgeneral, 03103 ptiming, 03104 pdynamic); 03105 03106 } 03107 03108 LOG_FUNCTION_END(status); 03109 03110 return status; 03111 } 03112 03113 VL53L1_Error VL53L1_preset_mode_histogram_xtalk_mm1( 03114 VL53L1_hist_post_process_config_t *phistpostprocess, 03115 VL53L1_static_config_t *pstatic, 03116 VL53L1_histogram_config_t *phistogram, 03117 VL53L1_general_config_t *pgeneral, 03118 VL53L1_timing_config_t *ptiming, 03119 VL53L1_dynamic_config_t *pdynamic, 03120 VL53L1_system_control_t *psystem, 03121 VL53L1_tuning_parm_storage_t *ptuning_parms, 03122 VL53L1_zone_config_t *pzone_cfg) 03123 { 03124 03125 03126 VL53L1_Error status = VL53L1_ERROR_NONE; 03127 03128 LOG_FUNCTION_START(""); 03129 03130 03131 03132 status = 03133 VL53L1_preset_mode_histogram_ranging( 03134 phistpostprocess, 03135 pstatic, 03136 phistogram, 03137 pgeneral, 03138 ptiming, 03139 pdynamic, 03140 psystem, 03141 ptuning_parms, 03142 pzone_cfg); 03143 03144 03145 03146 03147 if (status == VL53L1_ERROR_NONE) { 03148 03149 03150 03151 03152 03153 VL53L1_init_histogram_config_structure( 03154 8+7, 8+0, 8+1, 8+2, 8+3, 8+4, 03155 8+7, 8+0, 8+1, 8+2, 8+3, 8+4, 03156 phistogram); 03157 03158 03159 VL53L1_init_histogram_multizone_config_structure( 03160 8+7, 8+0, 8+1, 8+2, 8+3, 8+4, 03161 8+7, 8+0, 8+1, 8+2, 8+3, 8+4, 03162 &(pzone_cfg->multizone_hist_cfg)); 03163 03164 03165 03166 VL53L1_copy_hist_cfg_to_static_cfg( 03167 phistogram, 03168 pstatic, 03169 pgeneral, 03170 ptiming, 03171 pdynamic); 03172 03173 03174 03175 ptiming->range_config__vcsel_period_a = 0x09; 03176 ptiming->range_config__vcsel_period_b = 0x09; 03177 03178 03179 03180 ptiming->mm_config__timeout_macrop_a_hi = 0x00; 03181 ptiming->mm_config__timeout_macrop_a_lo = 0x21; 03182 ptiming->mm_config__timeout_macrop_b_hi = 0x00; 03183 ptiming->mm_config__timeout_macrop_b_lo = 0x21; 03184 03185 03186 03187 ptiming->range_config__timeout_macrop_a_hi = 0x00; 03188 ptiming->range_config__timeout_macrop_a_lo = 0x29; 03189 ptiming->range_config__timeout_macrop_b_hi = 0x00; 03190 ptiming->range_config__timeout_macrop_b_lo = 0x29; 03191 03192 03193 03194 pgeneral->cal_config__vcsel_start = 0x09; 03195 03196 03197 03198 pgeneral->phasecal_config__timeout_macrop = 0xF5; 03199 03200 03201 03202 pdynamic->sd_config__woi_sd0 = 0x09; 03203 pdynamic->sd_config__woi_sd1 = 0x09; 03204 pdynamic->sd_config__initial_phase_sd0 = 0x09; 03205 pdynamic->sd_config__initial_phase_sd1 = 0x06; 03206 03207 pdynamic->system__sequence_config = 03208 VL53L1_SEQUENCE_VHV_EN | 03209 VL53L1_SEQUENCE_PHASECAL_EN | 03210 VL53L1_SEQUENCE_DSS1_EN | 03211 VL53L1_SEQUENCE_DSS2_EN | 03212 VL53L1_SEQUENCE_MM1_EN | 03213 VL53L1_SEQUENCE_RANGE_EN; 03214 03215 03216 03217 03218 psystem->system__mode_start = 03219 VL53L1_DEVICESCHEDULERMODE_HISTOGRAM | 03220 VL53L1_DEVICEREADOUTMODE_DUAL_SD | 03221 VL53L1_DEVICEMEASUREMENTMODE_BACKTOBACK; 03222 } 03223 03224 LOG_FUNCTION_END(status); 03225 03226 return status; 03227 } 03228 03229 03230 VL53L1_Error VL53L1_preset_mode_histogram_xtalk_mm2( 03231 VL53L1_hist_post_process_config_t *phistpostprocess, 03232 VL53L1_static_config_t *pstatic, 03233 VL53L1_histogram_config_t *phistogram, 03234 VL53L1_general_config_t *pgeneral, 03235 VL53L1_timing_config_t *ptiming, 03236 VL53L1_dynamic_config_t *pdynamic, 03237 VL53L1_system_control_t *psystem, 03238 VL53L1_tuning_parm_storage_t *ptuning_parms, 03239 VL53L1_zone_config_t *pzone_cfg) 03240 { 03241 03242 03243 VL53L1_Error status = VL53L1_ERROR_NONE; 03244 03245 LOG_FUNCTION_START(""); 03246 03247 03248 03249 status = 03250 VL53L1_preset_mode_histogram_xtalk_mm1( 03251 phistpostprocess, 03252 pstatic, 03253 phistogram, 03254 pgeneral, 03255 ptiming, 03256 pdynamic, 03257 psystem, 03258 ptuning_parms, 03259 pzone_cfg); 03260 03261 03262 pdynamic->system__sequence_config = 03263 VL53L1_SEQUENCE_VHV_EN | 03264 VL53L1_SEQUENCE_PHASECAL_EN | 03265 VL53L1_SEQUENCE_DSS1_EN | 03266 VL53L1_SEQUENCE_DSS2_EN | 03267 VL53L1_SEQUENCE_MM2_EN | 03268 VL53L1_SEQUENCE_RANGE_EN; 03269 03270 03271 03272 LOG_FUNCTION_END(status); 03273 03274 return status; 03275 } 03276 03277 03278 03279 03280 VL53L1_Error VL53L1_preset_mode_histogram_multizone( 03281 VL53L1_hist_post_process_config_t *phistpostprocess, 03282 VL53L1_static_config_t *pstatic, 03283 VL53L1_histogram_config_t *phistogram, 03284 VL53L1_general_config_t *pgeneral, 03285 VL53L1_timing_config_t *ptiming, 03286 VL53L1_dynamic_config_t *pdynamic, 03287 VL53L1_system_control_t *psystem, 03288 VL53L1_tuning_parm_storage_t *ptuning_parms, 03289 VL53L1_zone_config_t *pzone_cfg) 03290 { 03291 03292 03293 VL53L1_Error status = VL53L1_ERROR_NONE; 03294 03295 LOG_FUNCTION_START(""); 03296 03297 03298 03299 status = 03300 VL53L1_preset_mode_histogram_medium_range( 03301 phistpostprocess, 03302 pstatic, 03303 phistogram, 03304 pgeneral, 03305 ptiming, 03306 pdynamic, 03307 psystem, 03308 ptuning_parms, 03309 pzone_cfg); 03310 03311 03312 03313 if (status == VL53L1_ERROR_NONE) { 03314 03315 03316 03317 status = 03318 VL53L1_init_zone_config_structure( 03319 4, 8, 2, 03320 4, 8, 2, 03321 7, 7, 03322 pzone_cfg); 03323 03324 pgeneral->global_config__stream_divider = 03325 pzone_cfg->active_zones + 1; 03326 03327 03328 03329 if (status == VL53L1_ERROR_NONE) { 03330 status = 03331 VL53L1_set_histogram_multizone_initial_bin_config( 03332 pzone_cfg, 03333 phistogram, 03334 &(pzone_cfg->multizone_hist_cfg)); 03335 } 03336 03337 VL53L1_copy_hist_cfg_to_static_cfg( 03338 phistogram, 03339 pstatic, 03340 pgeneral, 03341 ptiming, 03342 pdynamic); 03343 } 03344 03345 LOG_FUNCTION_END(status); 03346 03347 return status; 03348 } 03349 03350 VL53L1_Error VL53L1_preset_mode_histogram_multizone_short_range( 03351 VL53L1_hist_post_process_config_t *phistpostprocess, 03352 VL53L1_static_config_t *pstatic, 03353 VL53L1_histogram_config_t *phistogram, 03354 VL53L1_general_config_t *pgeneral, 03355 VL53L1_timing_config_t *ptiming, 03356 VL53L1_dynamic_config_t *pdynamic, 03357 VL53L1_system_control_t *psystem, 03358 VL53L1_tuning_parm_storage_t *ptuning_parms, 03359 VL53L1_zone_config_t *pzone_cfg) 03360 { 03361 03362 03363 VL53L1_Error status = VL53L1_ERROR_NONE; 03364 03365 LOG_FUNCTION_START(""); 03366 03367 03368 03369 status = 03370 VL53L1_preset_mode_histogram_short_range( 03371 phistpostprocess, 03372 pstatic, 03373 phistogram, 03374 pgeneral, 03375 ptiming, 03376 pdynamic, 03377 psystem, 03378 ptuning_parms, 03379 pzone_cfg); 03380 03381 03382 03383 if (status == VL53L1_ERROR_NONE) { 03384 03385 03386 03387 status = 03388 VL53L1_init_zone_config_structure( 03389 4, 8, 2, 03390 4, 8, 2, 03391 7, 7, 03392 pzone_cfg); 03393 03394 pgeneral->global_config__stream_divider = 03395 pzone_cfg->active_zones + 1; 03396 03397 03398 03399 if (status == VL53L1_ERROR_NONE) { 03400 status = 03401 VL53L1_set_histogram_multizone_initial_bin_config( 03402 pzone_cfg, 03403 phistogram, 03404 &(pzone_cfg->multizone_hist_cfg) 03405 ); 03406 } 03407 03408 03409 03410 VL53L1_copy_hist_cfg_to_static_cfg( 03411 phistogram, 03412 pstatic, 03413 pgeneral, 03414 ptiming, 03415 pdynamic); 03416 } 03417 03418 LOG_FUNCTION_END(status); 03419 03420 return status; 03421 } 03422 03423 03424 VL53L1_Error VL53L1_preset_mode_histogram_multizone_long_range( 03425 VL53L1_hist_post_process_config_t *phistpostprocess, 03426 VL53L1_static_config_t *pstatic, 03427 VL53L1_histogram_config_t *phistogram, 03428 VL53L1_general_config_t *pgeneral, 03429 VL53L1_timing_config_t *ptiming, 03430 VL53L1_dynamic_config_t *pdynamic, 03431 VL53L1_system_control_t *psystem, 03432 VL53L1_tuning_parm_storage_t *ptuning_parms, 03433 VL53L1_zone_config_t *pzone_cfg) 03434 { 03435 03436 03437 VL53L1_Error status = VL53L1_ERROR_NONE; 03438 03439 LOG_FUNCTION_START(""); 03440 03441 03442 03443 status = 03444 VL53L1_preset_mode_histogram_long_range( 03445 phistpostprocess, 03446 pstatic, 03447 phistogram, 03448 pgeneral, 03449 ptiming, 03450 pdynamic, 03451 psystem, 03452 ptuning_parms, 03453 pzone_cfg); 03454 03455 03456 03457 if (status == VL53L1_ERROR_NONE) { 03458 03459 03460 03461 status = 03462 VL53L1_init_zone_config_structure( 03463 4, 8, 2, 03464 4, 8, 2, 03465 7, 7, 03466 pzone_cfg); 03467 03468 pgeneral->global_config__stream_divider = 03469 pzone_cfg->active_zones + 1; 03470 03471 03472 03473 if (status == VL53L1_ERROR_NONE) { 03474 status = 03475 VL53L1_set_histogram_multizone_initial_bin_config( 03476 pzone_cfg, 03477 phistogram, 03478 &(pzone_cfg->multizone_hist_cfg)); 03479 } 03480 03481 03482 03483 VL53L1_copy_hist_cfg_to_static_cfg( 03484 phistogram, 03485 pstatic, 03486 pgeneral, 03487 ptiming, 03488 pdynamic); 03489 } 03490 03491 LOG_FUNCTION_END(status); 03492 03493 return status; 03494 } 03495 03496 03497 03498 03499 VL53L1_Error VL53L1_preset_mode_olt( 03500 VL53L1_static_config_t *pstatic, 03501 VL53L1_histogram_config_t *phistogram, 03502 VL53L1_general_config_t *pgeneral, 03503 VL53L1_timing_config_t *ptiming, 03504 VL53L1_dynamic_config_t *pdynamic, 03505 VL53L1_system_control_t *psystem, 03506 VL53L1_tuning_parm_storage_t *ptuning_parms, 03507 VL53L1_zone_config_t *pzone_cfg) 03508 { 03509 03510 03511 VL53L1_Error status = VL53L1_ERROR_NONE; 03512 03513 LOG_FUNCTION_START(""); 03514 03515 03516 03517 status = VL53L1_preset_mode_standard_ranging( 03518 pstatic, 03519 phistogram, 03520 pgeneral, 03521 ptiming, 03522 pdynamic, 03523 psystem, 03524 ptuning_parms, 03525 pzone_cfg); 03526 03527 03528 03529 if (status == VL53L1_ERROR_NONE) 03530 03531 psystem->system__stream_count_ctrl = 0x01; 03532 03533 LOG_FUNCTION_END(status); 03534 03535 return status; 03536 } 03537 03538 03539 void VL53L1_copy_hist_cfg_to_static_cfg( 03540 VL53L1_histogram_config_t *phistogram, 03541 VL53L1_static_config_t *pstatic, 03542 VL53L1_general_config_t *pgeneral, 03543 VL53L1_timing_config_t *ptiming, 03544 VL53L1_dynamic_config_t *pdynamic) 03545 { 03546 03547 03548 LOG_FUNCTION_START(""); 03549 03550 SUPPRESS_UNUSED_WARNING(pgeneral); 03551 03552 pstatic->sigma_estimator__effective_pulse_width_ns = 03553 phistogram->histogram_config__high_amb_even_bin_0_1; 03554 pstatic->sigma_estimator__effective_ambient_width_ns = 03555 phistogram->histogram_config__high_amb_even_bin_2_3; 03556 pstatic->sigma_estimator__sigma_ref_mm = 03557 phistogram->histogram_config__high_amb_even_bin_4_5; 03558 03559 pstatic->algo__crosstalk_compensation_valid_height_mm = 03560 phistogram->histogram_config__high_amb_odd_bin_0_1; 03561 03562 pstatic->spare_host_config__static_config_spare_0 = 03563 phistogram->histogram_config__high_amb_odd_bin_2_3; 03564 pstatic->spare_host_config__static_config_spare_1 = 03565 phistogram->histogram_config__high_amb_odd_bin_4_5; 03566 03567 pstatic->algo__range_ignore_threshold_mcps = 03568 (((uint16_t)phistogram->histogram_config__mid_amb_even_bin_0_1) 03569 << 8) 03570 + (uint16_t)phistogram->histogram_config__mid_amb_even_bin_2_3; 03571 03572 pstatic->algo__range_ignore_valid_height_mm = 03573 phistogram->histogram_config__mid_amb_even_bin_4_5; 03574 pstatic->algo__range_min_clip = 03575 phistogram->histogram_config__mid_amb_odd_bin_0_1; 03576 pstatic->algo__consistency_check__tolerance = 03577 phistogram->histogram_config__mid_amb_odd_bin_2; 03578 03579 pstatic->spare_host_config__static_config_spare_2 = 03580 phistogram->histogram_config__mid_amb_odd_bin_3_4; 03581 pstatic->sd_config__reset_stages_msb = 03582 phistogram->histogram_config__mid_amb_odd_bin_5; 03583 03584 pstatic->sd_config__reset_stages_lsb = 03585 phistogram->histogram_config__user_bin_offset; 03586 03587 ptiming->range_config__sigma_thresh = 03588 (((uint16_t)phistogram->histogram_config__low_amb_even_bin_0_1) 03589 << 8) 03590 + (uint16_t)phistogram->histogram_config__low_amb_even_bin_2_3; 03591 03592 ptiming->range_config__min_count_rate_rtn_limit_mcps = 03593 (((uint16_t)phistogram->histogram_config__low_amb_even_bin_4_5) 03594 << 8) 03595 + (uint16_t)phistogram->histogram_config__low_amb_odd_bin_0_1; 03596 03597 ptiming->range_config__valid_phase_low = 03598 phistogram->histogram_config__low_amb_odd_bin_2_3; 03599 ptiming->range_config__valid_phase_high = 03600 phistogram->histogram_config__low_amb_odd_bin_4_5; 03601 03602 pdynamic->system__thresh_high = 03603 phistogram->histogram_config__amb_thresh_low; 03604 03605 pdynamic->system__thresh_low = 03606 phistogram->histogram_config__amb_thresh_high; 03607 03608 pdynamic->system__enable_xtalk_per_quadrant = 03609 phistogram->histogram_config__spad_array_selection; 03610 03611 LOG_FUNCTION_END(0); 03612 03613 } 03614 03615 void VL53L1_copy_hist_bins_to_static_cfg( 03616 VL53L1_histogram_config_t *phistogram, 03617 VL53L1_static_config_t *pstatic, 03618 VL53L1_timing_config_t *ptiming) 03619 { 03620 03621 03622 LOG_FUNCTION_START(""); 03623 03624 pstatic->sigma_estimator__effective_pulse_width_ns = 03625 phistogram->histogram_config__high_amb_even_bin_0_1; 03626 pstatic->sigma_estimator__effective_ambient_width_ns = 03627 phistogram->histogram_config__high_amb_even_bin_2_3; 03628 pstatic->sigma_estimator__sigma_ref_mm = 03629 phistogram->histogram_config__high_amb_even_bin_4_5; 03630 03631 pstatic->algo__crosstalk_compensation_valid_height_mm = 03632 phistogram->histogram_config__high_amb_odd_bin_0_1; 03633 03634 pstatic->spare_host_config__static_config_spare_0 = 03635 phistogram->histogram_config__high_amb_odd_bin_2_3; 03636 pstatic->spare_host_config__static_config_spare_1 = 03637 phistogram->histogram_config__high_amb_odd_bin_4_5; 03638 03639 pstatic->algo__range_ignore_threshold_mcps = 03640 (((uint16_t)phistogram->histogram_config__mid_amb_even_bin_0_1) 03641 << 8) 03642 + (uint16_t)phistogram->histogram_config__mid_amb_even_bin_2_3; 03643 03644 pstatic->algo__range_ignore_valid_height_mm = 03645 phistogram->histogram_config__mid_amb_even_bin_4_5; 03646 pstatic->algo__range_min_clip = 03647 phistogram->histogram_config__mid_amb_odd_bin_0_1; 03648 pstatic->algo__consistency_check__tolerance = 03649 phistogram->histogram_config__mid_amb_odd_bin_2; 03650 03651 pstatic->spare_host_config__static_config_spare_2 = 03652 phistogram->histogram_config__mid_amb_odd_bin_3_4; 03653 pstatic->sd_config__reset_stages_msb = 03654 phistogram->histogram_config__mid_amb_odd_bin_5; 03655 03656 ptiming->range_config__sigma_thresh = 03657 (((uint16_t)phistogram->histogram_config__low_amb_even_bin_0_1) 03658 << 8) 03659 + (uint16_t)phistogram->histogram_config__low_amb_even_bin_2_3; 03660 03661 ptiming->range_config__min_count_rate_rtn_limit_mcps = 03662 (((uint16_t)phistogram->histogram_config__low_amb_even_bin_4_5) 03663 << 8) 03664 + (uint16_t)phistogram->histogram_config__low_amb_odd_bin_0_1; 03665 03666 ptiming->range_config__valid_phase_low = 03667 phistogram->histogram_config__low_amb_odd_bin_2_3; 03668 ptiming->range_config__valid_phase_high = 03669 phistogram->histogram_config__low_amb_odd_bin_4_5; 03670 03671 LOG_FUNCTION_END(0); 03672 03673 } 03674 03675 03676 VL53L1_Error VL53L1_preset_mode_histogram_ranging_ref( 03677 VL53L1_hist_post_process_config_t *phistpostprocess, 03678 VL53L1_static_config_t *pstatic, 03679 VL53L1_histogram_config_t *phistogram, 03680 VL53L1_general_config_t *pgeneral, 03681 VL53L1_timing_config_t *ptiming, 03682 VL53L1_dynamic_config_t *pdynamic, 03683 VL53L1_system_control_t *psystem, 03684 VL53L1_tuning_parm_storage_t *ptuning_parms, 03685 VL53L1_zone_config_t *pzone_cfg) 03686 { 03687 03688 03689 VL53L1_Error status = VL53L1_ERROR_NONE; 03690 03691 LOG_FUNCTION_START(""); 03692 03693 03694 03695 status = 03696 VL53L1_preset_mode_histogram_ranging( 03697 phistpostprocess, 03698 pstatic, 03699 phistogram, 03700 pgeneral, 03701 ptiming, 03702 pdynamic, 03703 psystem, 03704 ptuning_parms, 03705 pzone_cfg); 03706 03707 03708 03709 if (status == VL53L1_ERROR_NONE) { 03710 03711 03712 03713 phistogram->histogram_config__spad_array_selection = 0x01; 03714 03715 03716 03717 VL53L1_copy_hist_cfg_to_static_cfg( 03718 phistogram, 03719 pstatic, 03720 pgeneral, 03721 ptiming, 03722 pdynamic); 03723 } 03724 03725 LOG_FUNCTION_END(status); 03726 03727 return status; 03728 } 03729 03730 03731 03732 03733 03734
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