chaithanya rss / Mbed 2 deprecated CDMS_Integrate1_0

June 30

Dependencies:   FreescaleIAP SimpleDMA mbed-rtos mbed

Fork of CDMS_CODE by shubham c

DefinitionsAndGlobals.h@191:d14b1c783736, 2016-07-02 (annotated)

Committer:
chaithanyarss
Date:
Sat Jul 02 13:36:18 2016 +0000
Revision:
191:d14b1c783736
Parent:
190:28a07943dded 
;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
shreeshas95 0:f016e9e8d48b 1 // **************DEFINITIONS*********************
aniruddhv 69:20f09a0c3fd2 2
ee12b079 133:56d37aa8a011 3 #define bypass_adf 1
aniruddhv 69:20f09a0c3fd2 4
shreeshas95 0:f016e9e8d48b 5 // COM_RX
shreeshas95 5:ab276a17ca07 6 #define RX_TIMEOUT_LIMIT 0.5
ee12b079 81:1a39e9e14771 7 //#define COM_RX_UART_TX PTE20 // For bypassing RX1M (SET BAUD RATE 1200) #define COM_RX_UART_TX USBTX
ee12b079 81:1a39e9e14771 8 //#define COM_RX_UART_RX PTE21 // For bypassing RX1M (SET BAUD RATE 1200) #define COM_RX_UART_RX USBRX
ee12b079 81:1a39e9e14771 9
ee12b079 81:1a39e9e14771 10 #define COM_RX_UART_TX USBTX
ee12b079 81:1a39e9e14771 11 #define COM_RX_UART_RX USBRX
aniruddhv 56:a88e16f6c18e 12
shreeshas95 0:f016e9e8d48b 13 // COMMON SPI
chaithanyarss 189:fba4aeebf004 14 #define SPI_MOSI PTE1
chaithanyarss 189:fba4aeebf004 15 #define SPI_MISO PTE3
chaithanyarss 189:fba4aeebf004 16 #define SPI_CLK PTE2
shreeshas95 1:a0055b3280c8 17 #define SPI_CS_ADF PTA15
chaithanyarss 189:fba4aeebf004 18 #define SPI_CS_SDC PIN20
ee12b079 114:9fb55057b13f 19 #define SPI_CS_RTC PIN26
shreeshas95 2:2caf2a9a13aa 20
shreeshas95 4:104dd82c99b8 21 // COM_TX
shreeshas95 4:104dd82c99b8 22 #define COM_TX_CONFIG_LIMIT 3
aniruddhv 52:0bd68655c651 23 #define COM_TX_TICKER_LIMIT 32
shreeshas95 4:104dd82c99b8 24
aniruddhv 137:489a93a04d6b 25 // ADF INTERRUPT
shreeshas95 2:2caf2a9a13aa 26 #define ADF_IRQ PTA14
chaithanyarss 189:fba4aeebf004 27
chaithanyarss 189:fba4aeebf004 28 //I2C - Payload to CDMS (need to change while using CDMS hardware);
chaithanyarss 189:fba4aeebf004 29 I2C master(PIN32,PIN31);
chaithanyarss 189:fba4aeebf004 30 DigitalIn PL_I2C_Intr(PTC13);
chaithanyarss 189:fba4aeebf004 31 DigitalOut PL_I2C_GPIO(PTC1);
chaithanyarss 189:fba4aeebf004 32
chaithanyarss 189:fba4aeebf004 33 //I2C - CDMS to BAE
chaithanyarss 189:fba4aeebf004 34 DigitalIn BAE_I2C_GPIO(PIN39);
chaithanyarss 189:fba4aeebf004 35 DigitalOut CDMS_I2C_GPIO(PIN67);
shreeshas95 0:f016e9e8d48b 36
shreeshas95 0:f016e9e8d48b 37 // TC LIST
shreeshas95 2:2caf2a9a13aa 38 #define TCL_STATE_INCOMPLETE 0x00
shreeshas95 5:ab276a17ca07 39 #define TCL_STATE_ABORTED 0x03
shreeshas95 5:ab276a17ca07 40 #define TCL_STATE_EXECUTING 0x04
shreeshas95 5:ab276a17ca07 41 #define TCL_STATE_COMPLETED 0x05
shreeshas95 5:ab276a17ca07 42 #define TCL_STATE_EXCEEDED_LIMIT 0x06
shreeshas95 0:f016e9e8d48b 43
shreeshas95 0:f016e9e8d48b 44 // LIST OF FLAGS
shreeshas95 2:2caf2a9a13aa 45 #define UART_INT_FLAG 0x0001
shreeshas95 2:2caf2a9a13aa 46 #define NEW_TC_RECEIVED 0x0002
shreeshas95 2:2caf2a9a13aa 47 #define COM_SESSION_FLAG 0x0004
shreeshas95 2:2caf2a9a13aa 48 #define COM_RX_FLAG 0x0008
shreeshas95 2:2caf2a9a13aa 49 #define COM_MNG_TMTC_RUNNING_FLAG 0x0010
shreeshas95 2:2caf2a9a13aa 50 #define COM_SESSION_VALIDITY 0x0020
shreeshas95 2:2caf2a9a13aa 51 #define ALL_CRC_PASS_FLAG 0x0040
shreeshas95 2:2caf2a9a13aa 52 #define COM_PA_HOT_FLAG 0x0080
shreeshas95 2:2caf2a9a13aa 53 #define COM_TX_FLAG 0x0100
shreeshas95 6:79d422d1ed42 54 #define COM_SESSION_TIMEOUT_FLAG 0x0200
aniruddhv 137:489a93a04d6b 55 #define COM_AUTO_POWER_OFF_BAE_FLAG 0x0400
aniruddhv 137:489a93a04d6b 56 #define BAE_SW_EN_FLAG 0x0800
aniruddhv 137:489a93a04d6b 57 #define RF_SW_STATUS_FLAG 0x1000
aniruddhv 137:489a93a04d6b 58 #define COM_INIT_STATUS_FLAG 0x2000
aniruddhv 155:ca7365c03fd7 59 #define COM_TX_STATUS_FLAG 0x4000
aniruddhv 137:489a93a04d6b 60
aniruddhv 137:489a93a04d6b 61 //RF relay STATUS
aniruddhv 137:489a93a04d6b 62 #define RF_COM_TX 0
aniruddhv 137:489a93a04d6b 63 #define RF_BCN 1
shreeshas95 0:f016e9e8d48b 64
shreeshas95 0:f016e9e8d48b 65 // COM_MNG_TMTC THREAD
shreeshas95 6:79d422d1ed42 66 #define SESSION_TIME_LIMIT 1500
shreeshas95 0:f016e9e8d48b 67 #define COM_MNG_TMTC_SIGNAL_UART_INT 0x01
shreeshas95 0:f016e9e8d48b 68 #define COM_MNG_TMTC_SIGNAL_ADF_NSD 0x02
shreeshas95 0:f016e9e8d48b 69 #define COM_MNG_TMTC_SIGNAL_ADF_SD 0x03
ee12b079 93:4d76de54a699 70 #define SCIENCE_SIGNAL 0x04
shreeshas95 0:f016e9e8d48b 71 // COM_MNG_TMTC
shreeshas95 2:2caf2a9a13aa 72 #define COM_PA_COOLING_TIME_LIMIT 20
shreeshas95 4:104dd82c99b8 73 #define COM_MAX_TC_LIMIT 200
shreeshas95 4:104dd82c99b8 74 #define TM_ACK_CODE_INDEX 2
shreeshas95 5:ab276a17ca07 75 #define CRC_FAIL_NACK_CODE 0x01
shreeshas95 2:2caf2a9a13aa 76
shreeshas95 2:2caf2a9a13aa 77 // call sign
shreeshas95 2:2caf2a9a13aa 78 #define PSC_CALLSIGN 0x00
shreeshas95 2:2caf2a9a13aa 79 #define APID_CALLSIGN 0x00
shreeshas95 2:2caf2a9a13aa 80
shreeshas95 2:2caf2a9a13aa 81 // max value of telecommands in a tcl
shreeshas95 2:2caf2a9a13aa 82 #define TCL_OVERFLOW_CONSTANT 256
shreeshas95 4:104dd82c99b8 83 #define TM_OVERFLOW_CONSTANT 256
shreeshas95 2:2caf2a9a13aa 84
shreeshas95 0:f016e9e8d48b 85 // starting value of packet sequence count at each pass
shreeshas95 0:f016e9e8d48b 86 #define PSC_START_VALUE 1
shreeshas95 0:f016e9e8d48b 87
shreeshas95 0:f016e9e8d48b 88 // APID list
aniruddhv 52:0bd68655c651 89 #define APID_COM 0
shreeshas95 0:f016e9e8d48b 90 #define APID_BAE 1
shreeshas95 0:f016e9e8d48b 91 #define APID_CDMS 2
shreeshas95 0:f016e9e8d48b 92 #define APID_SPEED 3
shreeshas95 0:f016e9e8d48b 93
aniruddhv 52:0bd68655c651 94 //SERVICE
aniruddhv 52:0bd68655c651 95 #define SERVICE_OBOSC 0xB
aniruddhv 52:0bd68655c651 96 #define SERVICE_OBSRS 0xF
aniruddhv 52:0bd68655c651 97
shreeshas95 0:f016e9e8d48b 98 // HIGH PRIORITY TC - priority list
shreeshas95 0:f016e9e8d48b 99 // not correct values here
shreeshas95 0:f016e9e8d48b 100 #define HPTC1 5
shreeshas95 0:f016e9e8d48b 101 #define HPTC2 6
shreeshas95 0:f016e9e8d48b 102 // Add more entries above
shreeshas95 0:f016e9e8d48b 103
shreeshas95 0:f016e9e8d48b 104 // SIZE of tc in bytes
shreeshas95 0:f016e9e8d48b 105 #define TC_SHORT_SIZE 11
shreeshas95 0:f016e9e8d48b 106 #define TC_LONG_SIZE 135
shreeshas95 0:f016e9e8d48b 107
shreeshas95 0:f016e9e8d48b 108 // TMID list
shreeshas95 0:f016e9e8d48b 109 #define TMID_ACK_L1 0xA
shreeshas95 4:104dd82c99b8 110 #define TMID_ACK_L234 0xB
shreeshas95 4:104dd82c99b8 111 #define TMID_TCL 0x7
shreeshas95 4:104dd82c99b8 112 #define TMID_CALL_SIGN 0xE
shreeshas95 0:f016e9e8d48b 113
shreeshas95 0:f016e9e8d48b 114 // OBOSC SERVICE SUBTYPE
shreeshas95 4:104dd82c99b8 115 #define OBOSC_TCL_MAX_SHORT_SIZE 11
shreeshas95 4:104dd82c99b8 116 #define OBOSC_LONG_TC_FIRST_HALF_SIZE 67
shreeshas95 4:104dd82c99b8 117 #define OBOSC_LONG_TC_SECOND_HALF_SIZE 68
shreeshas95 4:104dd82c99b8 118 #define OBOSC_TCL_TAG_LONG_FIRST_HALF 0x10
shreeshas95 4:104dd82c99b8 119 #define OBOSC_TCL_TAG_LONG_SECOND_HALF 0x11
shreeshas95 4:104dd82c99b8 120
shreeshas95 0:f016e9e8d48b 121 #define OBOSC_SUB_DISABLE 0x01
shreeshas95 0:f016e9e8d48b 122 #define OBOSC_SUB_RETRY 0x05
shreeshas95 4:104dd82c99b8 123 #define OBOSC_SUB_REP_TCLD 0x06
shreeshas95 0:f016e9e8d48b 124 #define OBOSC_SUB_REP_LE 0x0F
shreeshas95 0:f016e9e8d48b 125 #define OBOSC_SUB_RESET 0x07
shreeshas95 0:f016e9e8d48b 126
shreeshas95 101:bece931236a2 127 // PAYLOAD or SCIENCE
shreeshas95 101:bece931236a2 128 #define PAYLOAD_BUFFER_LENGTH 6723
ee12b079 113:b8991d9e3b6c 129 #define PAY_SPI_MOSI PTE18
ee12b079 113:b8991d9e3b6c 130 #define PAY_SPI_MISO PTE19
ee12b079 113:b8991d9e3b6c 131 #define PAY_SPI_CLK PTE17
ee12b079 113:b8991d9e3b6c 132 #define PAY_SPI_CS PTE16
aniruddhv 144:4c20fcc105ce 133
aniruddhv 144:4c20fcc105ce 134 //BEACON
aniruddhv 144:4c20fcc105ce 135 #define BCN_APID_SOURCE 0x41
aniruddhv 144:4c20fcc105ce 136 #define BCN_SERVICE 0x81
shreeshas95 101:bece931236a2 137
aniruddhv 144:4c20fcc105ce 138 //BAE
aniruddhv 144:4c20fcc105ce 139 #define BAE_APID_SOURCE 0x81
aniruddhv 144:4c20fcc105ce 140 #define BAE_SERVICE 0x81
aniruddhv 144:4c20fcc105ce 141 #define BAE_POWER_ON_PID 0x13
aniruddhv 144:4c20fcc105ce 142 #define BAE_POWER_OFF_PID 0x23
aniruddhv 144:4c20fcc105ce 143 #define BAE_RESET_PID 0x33
aniruddhv 144:4c20fcc105ce 144
aniruddhv 144:4c20fcc105ce 145 //RF RELAY
aniruddhv 144:4c20fcc105ce 146 #define RF_RELAY_CNTRL_TX PTA7
aniruddhv 144:4c20fcc105ce 147 #define RF_RELAY_CNTRL_BCN PTA12
chaithanyarss 190:28a07943dded 148
chaithanyarss 187:2c7263530c57 149
shreeshas95 0:f016e9e8d48b 150 // ****************GLOBAL VARIABLES******************
shreeshas95 0:f016e9e8d48b 151 // DEBUG
shreeshas95 0:f016e9e8d48b 152 Serial gPC( USBTX, USBRX );
shreeshas95 4:104dd82c99b8 153 DigitalOut gLEDR(LED_RED);
shreeshas95 4:104dd82c99b8 154 DigitalOut gLEDG(LED_GREEN);
shreeshas95 0:f016e9e8d48b 155
shreeshas95 0:f016e9e8d48b 156 // COM_RX
shreeshas95 0:f016e9e8d48b 157 RawSerial RX1M( COM_RX_UART_TX, COM_RX_UART_RX );
shreeshas95 0:f016e9e8d48b 158 COM_RX_DATA_NODE *gRX_HEAD_DATA_NODE = NULL;
shreeshas95 0:f016e9e8d48b 159 COM_RX_DATA_NODE *gRX_CURRENT_DATA_NODE = NULL;
shreeshas95 2:2caf2a9a13aa 160 // uint8_t *gRX_CURRENT_PTR = NULL;
shreeshas95 0:f016e9e8d48b 161 uint32_t gRX_COUNT = 0;
shreeshas95 0:f016e9e8d48b 162 uint16_t gTOTAL_INCORRECT_SIZE_TC = 0x00;
shreeshas95 0:f016e9e8d48b 163 uint16_t gTOTAL_CRC_FAIL_TC = 0x00;
shreeshas95 2:2caf2a9a13aa 164 uint16_t gTOTAL_REPEATED_TC = 0x00;
shreeshas95 0:f016e9e8d48b 165
shreeshas95 0:f016e9e8d48b 166 // COMMON SPI
shreeshas95 0:f016e9e8d48b 167 SPI spi( SPI_MOSI, SPI_MISO, SPI_CLK );
shreeshas95 1:a0055b3280c8 168 DigitalOut gCS_ADF(SPI_CS_ADF);
ee12b079 86:a26f5f22631d 169 DigitalOut cs_sd(SPI_CS_SDC);
shreeshas95 2:2caf2a9a13aa 170 DigitalOut gCS_RTC(SPI_CS_RTC);
shreeshas95 0:f016e9e8d48b 171 Mutex SPI_mutex;
shreeshas95 0:f016e9e8d48b 172
chaithanyarss 190:28a07943dded 173 //I2C
chaithanyarss 190:28a07943dded 174 Mutex BAE_I2C_mutex;
chaithanyarss 190:28a07943dded 175
aniruddhv 144:4c20fcc105ce 176 //RF Relay
aniruddhv 144:4c20fcc105ce 177 DigitalOut RF_SW_CNTRL_BCN(RF_RELAY_CNTRL_BCN);
aniruddhv 144:4c20fcc105ce 178 DigitalOut RF_SW_CNTRL_TX(RF_RELAY_CNTRL_TX);
aniruddhv 144:4c20fcc105ce 179
aniruddhv 155:ca7365c03fd7 180 //COM_RX
aniruddhv 155:ca7365c03fd7 181 DigitalOut COM_RX_CNTRL(PIN72);
aniruddhv 155:ca7365c03fd7 182 DigitalOut COM_TX_CNTRL(PIN56);
aniruddhv 144:4c20fcc105ce 183
shreeshas95 0:f016e9e8d48b 184 // TC LIST
shreeshas95 0:f016e9e8d48b 185 Base_tc* gHEAD_NODE_TCL = NULL;
shreeshas95 0:f016e9e8d48b 186 Base_tc* gLAST_NODE_TCL = NULL;
shreeshas95 2:2caf2a9a13aa 187 uint8_t gMASTER_STATE = TCL_STATE_INCOMPLETE;
shreeshas95 2:2caf2a9a13aa 188 uint16_t gFLAGS = 0x0000;
shreeshas95 0:f016e9e8d48b 189
shreeshas95 0:f016e9e8d48b 190 // COM_MNG_TMTC THREAD
shreeshas95 0:f016e9e8d48b 191 Thread* gCOM_MNG_TMTC_THREAD = NULL;
shreeshas95 0:f016e9e8d48b 192 Timeout gRX_TIMEOUT;
shreeshas95 0:f016e9e8d48b 193 Timeout gSESSION_TIMEOUT;
shreeshas95 0:f016e9e8d48b 194
shreeshas95 0:f016e9e8d48b 195 // COM_MNG_TMTC
shreeshas95 2:2caf2a9a13aa 196
aniruddhv 144:4c20fcc105ce 197
aniruddhv 144:4c20fcc105ce 198
shreeshas95 2:2caf2a9a13aa 199 // PA cooling timeout
shreeshas95 4:104dd82c99b8 200 Timeout gCOM_PA_COOLING_TIMEOUT;
shreeshas95 2:2caf2a9a13aa 201
shreeshas95 2:2caf2a9a13aa 202 // GS code for verification
aniruddhv 37:c9a739750806 203 const uint8_t gGSCODE[] = {0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
shreeshas95 2:2caf2a9a13aa 204
shreeshas95 0:f016e9e8d48b 205 uint8_t gTOTAL_VALID_TC = 0x00;
shreeshas95 0:f016e9e8d48b 206 // USE LAST_L1_ACK FOR GENERATING REPORT
shreeshas95 4:104dd82c99b8 207 uint8_t gLAST_TM[TM_LONG_SIZE];
shreeshas95 4:104dd82c99b8 208 uint8_t gLAST_TM_SHORT_OR_LONG = SHORT_TM_CODE;
shreeshas95 3:6c81fc8834e2 209
shreeshas95 101:bece931236a2 210 // PAYLOAD OR SCIENCE_THREAD
shreeshas95 3:6c81fc8834e2 211 Thread* gSCIENCE_THREAD = NULL;
shreeshas95 101:bece931236a2 212 dmaSPISlave gPAY_SPI(PAY_SPI_MOSI, PAY_SPI_MISO, PAY_SPI_CLK, PAY_SPI_CS);
shreeshas95 4:104dd82c99b8 213 uint8_t gPAYLOAD_BUFFER[PAYLOAD_BUFFER_LENGTH];
shreeshas95 4:104dd82c99b8 214
shreeshas95 4:104dd82c99b8 215 // CALL SIGN TM
shreeshas95 103:b55559925dc1 216 const uint8_t gCALL_SIGN_STRING[TM_SHORT_SIZE] = {0xE0, 0x00, 0x00, 0x00, 0x56, 0x55, 0x32, 0x4E, 0x43, 0x46, 0x00, 0xAC, 0x11};
shreeshas95 103:b55559925dc1 217
shreeshas95 103:b55559925dc1 218 // CDMS HK
chaithanyarss 190:28a07943dded 219 uint8_t CDMS_STANDBY;
chaithanyarss 189:fba4aeebf004 220 uint8_t CDMS_HEALTH_DATA[128];
chaithanyarss 187:2c7263530c57 221 uint8_t CDMS_RAM[59];
chaithanyarss 187:2c7263530c57 222 uint16_t GPIO_STATUS;
chaithanyarss 189:fba4aeebf004 223 uint8_t CDMS_HK_MAIN_STATUS;
chaithanyarss 187:2c7263530c57 224 uint8_t COMRX_STATUS;
chaithanyarss 187:2c7263530c57 225 uint8_t RTC_FAULTCOUNT;
chaithanyarss 187:2c7263530c57 226 uint16_t SD_FAULTCOUNT;
chaithanyarss 187:2c7263530c57 227 uint8_t SD_STATUS;
chaithanyarss 187:2c7263530c57 228 uint8_t BAE_FAULTCOUNT;
chaithanyarss 187:2c7263530c57 229 uint8_t BAE_STATUS;
chaithanyarss 187:2c7263530c57 230 uint8_t PL_STATUS;
chaithanyarss 187:2c7263530c57 231 uint16_t PL_FAULTCOUNT;
chaithanyarss 187:2c7263530c57 232 bool BAE_HK_I2C;
chaithanyarss 187:2c7263530c57 233 uint8_t RTC_STATUS;
chaithanyarss 187:2c7263530c57 234 float RSSI_volatge;
chaithanyarss 187:2c7263530c57 235
shreeshas95 103:b55559925dc1 236 CDMS_HK_actual actual_data;
shreeshas95 103:b55559925dc1 237 CDMS_HK_quant quant_data;
shreeshas95 103:b55559925dc1 238 CDMS_HK_min_max min_max_data;
chaithanyarss 187:2c7263530c57 239 bool firstCount=true;
chaithanyarss 187:2c7263530c57 240
chaithanyarss 190:28a07943dded 241 //GPIO PINS
chaithanyarss 190:28a07943dded 242 DigitalIn V_A_PGOOD (PIN88);
chaithanyarss 190:28a07943dded 243 DigitalIn V_B_PGOOD_1 (PIN6);
chaithanyarss 190:28a07943dded 244 DigitalIn V_B_PGOOD_2 (PIN7);
chaithanyarss 190:28a07943dded 245 DigitalIn V_C_PGOOD (PIN54);
chaithanyarss 190:28a07943dded 246 DigitalIn COMRX_OC_FAULT (PIN68);
chaithanyarss 190:28a07943dded 247 DigitalIn COMTX_OC_FAULT (PIN69);
chaithanyarss 190:28a07943dded 248 DigitalIn BAE_OC_FAULT (PIN92);
chaithanyarss 190:28a07943dded 249 DigitalIn PL_GPIO_1_STATUS (PIN71);
chaithanyarss 190:28a07943dded 250 DigitalIn PL_GPIO_2_STATUS (PIN81);
chaithanyarss 190:28a07943dded 251 DigitalIn PL_GPIO_3_STATUS (PIN80);
chaithanyarss 190:28a07943dded 252 DigitalIn PL_BEE_SW_OC_FAULT (PIN4);
chaithanyarss 190:28a07943dded 253 DigitalIn PL_EPS_LATCH_SW_OC_FAULT ();
chaithanyarss 190:28a07943dded 254 DigitalIn V_C_EN_STATUS ();
chaithanyarss 190:28a07943dded 255 DigitalIn V_D_EN_STATUS ();
chaithanyarss 190:28a07943dded 256
chaithanyarss 190:28a07943dded 257
chaithanyarss 190:28a07943dded 258 DigitalIn SD_OC_FAULT (PIN90);
chaithanyarss 190:28a07943dded 259 DigitalOut SD_SW_EN_DS (PIN97);
chaithanyarss 190:28a07943dded 260 DigitalOut BAE_SW_EN_DS (PIN47);
chaithanyarss 190:28a07943dded 261 DigitalOut PL_SW_EN_DS (PIN73);
chaithanyarss 190:28a07943dded 262
chaithanyarss 187:2c7263530c57 263 //SD HK
chaithanyarss 187:2c7263530c57 264 uint32_t FSC_CURRENT[6];
chaithanyarss 189:fba4aeebf004 265 uint32_t FSC_LAST[6];
chaithanyarss 190:28a07943dded 266 uint8_t SD_RD_ERROR;
chaithanyarss 189:fba4aeebf004 267
chaithanyarss 189:fba4aeebf004 268 //Time's
chaithanyarss 189:fba4aeebf004 269 uint32_t TIME_LATEST_RTC;
chaithanyarss 189:fba4aeebf004 270 uint32_t TIME_LATEST_I2C_BAE;
chaithanyarss 189:fba4aeebf004 271 uint32_t TIME_LATEST_I2C_SPEED;
chaithanyarss 189:fba4aeebf004 272 uint32_t TIME_LATEST_SD_WR;
chaithanyarss 189:fba4aeebf004 273 uint32_t TIME_LATEST_SD_RD;
chaithanyarss 189:fba4aeebf004 274 uint32_t TIME_LATEST_SPI_SPEED;
chaithanyarss 189:fba4aeebf004 275
chaithanyarss 189:fba4aeebf004 276 //Counter's
chaithanyarss 189:fba4aeebf004 277 uint16_t CDMS_I2C_ERR_SPEED_COUNTER;
chaithanyarss 189:fba4aeebf004 278 uint16_t CDMS_I2C_ERR_BAE_COUNTER;
chaithanyarss 189:fba4aeebf004 279 uint16_t CDMS_HK_MAIN_COUNTER;
chaithanyarss 189:fba4aeebf004 280 uint16_t COMRX_RESET_COUNTER;
chaithanyarss 189:fba4aeebf004 281 uint16_t PL_MAIN_COUNTER;
chaithanyarss 190:28a07943dded 282 uint16_t PL_RCV_SC_DATA_COUNTER;
chaithanyarss 190:28a07943dded 283
chaithanyarss 190:28a07943dded 284 //CDMS RAM parameters
chaithanyarss 190:28a07943dded 285 uint8_t PL_INIT_STATUS;
chaithanyarss 190:28a07943dded 286 uint8_t PL_MAIN_STATUS;
chaithanyarss 190:28a07943dded 287 uint8_t PL_LOW_POWER;
chaithanyarss 190:28a07943dded 288 uint8_t PL_STATE;
chaithanyarss 190:28a07943dded 289 uint8_t PL_RCV_SC_DATA_STATUS;
chaithanyarss 190:28a07943dded 290 uint8_t COM_SESSION;
chaithanyarss 190:28a07943dded 291 uint8_t COM_RX;
chaithanyarss 190:28a07943dded 292 uint8_t RF_SW_STATUS;
chaithanyarss 190:28a07943dded 293 uint8_t COM_TX;
chaithanyarss 190:28a07943dded 294 uint8_t COM_TX_STATUS;
chaithanyarss 190:28a07943dded 295 uint8_t COM_MNG_TMTC;
chaithanyarss 190:28a07943dded 296 uint8_t CDMS_STANDBY_HK;
chaithanyarss 190:28a07943dded 297 uint8_t CDMS_STANDBY_PL;
chaithanyarss 190:28a07943dded 298 uint8_t CDMS_INIT_STATUS;
chaithanyarss 190:28a07943dded 299 uint8_t CDMS_HK_STATUS;
chaithanyarss 190:28a07943dded 300 uint8_t CDMS_RTC_BL;