Marco Graf

<p>Work at <a href="http://cedes.com">CEDES AG</a> since february 2006. At the moment as SW engengeer of the camera system sensors.</p> <p>Studied at the <a href="http://www.ethz.ch">Swiss Institude of Technology (ETHZ)</a> MSc Electrical Engeneering</p>

Marco’s activity

Program: Check_PLL
Marco Graf - 09 Jun 2010
Program: 20MHz_PWM_on_80MHz_cclk
Marco Graf - 09 Jun 2010
Reply to mbed Physical Dimensions - Hi, I have measured the dimensions: 54mm x 26mm. Sounds more realistic. But a I …
Marco Graf - 08 Jun 2010

Marco’s public repositories

  • Mbed 2 deprecated
    20MHz_PWM_on_80MHz_cclk

    Fast 20MHz PWM, with double edge controlled PWMs (90° Phase shifted). CPU clock had to be adjusted to 80MHz (PLL-controlled). Done by accessing the registers directrly.

    cclk, clock, CPU, pwm
    Last updated: 09 Jun 2010 1 159
  • Mbed 2 deprecated
    Check_PLL

    PLL Check with changed USB-Serial baudrate to 921600

    baudrate, check, PLL, Serial, USB
    Last updated: 09 Jun 2010 1 16
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