cassyarduino cassyarduino
UIPEthernet library for Arduino IDE, Eclipse with arduino plugin and MBED/SMeshStudio (AVR,STM32F,ESP8266,Intel ARC32,Nordic nRF51,Teensy boards,Realtek Ameba(RTL8195A,RTL8710)), ENC28j60 network chip. Compatible with Wiznet W5100 Ethernet library API. Compiled and tested on Nucleo-F302R8. Master repository is: https://github.com/UIPEthernet/UIPEthernet/
utility/enc28j60.h@39:deeb00b81cc9, 2018-01-23 (annotated)
- Committer:
- cassyarduino
- Date:
- Tue Jan 23 15:08:43 2018 +0100
- Revision:
- 39:deeb00b81cc9
- Parent:
- 0:e3fb1267e3c3
Release: 2.0.4
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| cassyarduino | 0:e3fb1267e3c3 | 1 | /***************************************************************************** |
| cassyarduino | 0:e3fb1267e3c3 | 2 | * |
| cassyarduino | 0:e3fb1267e3c3 | 3 | * Title : Microchip ENC28J60 Ethernet Interface Driver |
| cassyarduino | 0:e3fb1267e3c3 | 4 | * Author : Pascal Stang (c)2005 |
| cassyarduino | 0:e3fb1267e3c3 | 5 | * Modified by Norbert Truchsess |
| cassyarduino | 0:e3fb1267e3c3 | 6 | * Copyright: GPL V2 |
| cassyarduino | 0:e3fb1267e3c3 | 7 | * |
| cassyarduino | 0:e3fb1267e3c3 | 8 | *This driver provides initialization and transmit/receive |
| cassyarduino | 0:e3fb1267e3c3 | 9 | *functions for the Microchip ENC28J60 10Mb Ethernet Controller and PHY. |
| cassyarduino | 0:e3fb1267e3c3 | 10 | *This chip is novel in that it is a full MAC+PHY interface all in a 28-pin |
| cassyarduino | 0:e3fb1267e3c3 | 11 | *chip, using an SPI interface to the host processor. |
| cassyarduino | 0:e3fb1267e3c3 | 12 | * |
| cassyarduino | 0:e3fb1267e3c3 | 13 | * |
| cassyarduino | 0:e3fb1267e3c3 | 14 | *****************************************************************************/ |
| cassyarduino | 0:e3fb1267e3c3 | 15 | |
| cassyarduino | 0:e3fb1267e3c3 | 16 | #ifndef ENC28J60_H |
| cassyarduino | 0:e3fb1267e3c3 | 17 | #define ENC28J60_H |
| cassyarduino | 0:e3fb1267e3c3 | 18 | #include <inttypes.h> |
| cassyarduino | 0:e3fb1267e3c3 | 19 | |
| cassyarduino | 0:e3fb1267e3c3 | 20 | // ENC28J60 Control Registers |
| cassyarduino | 0:e3fb1267e3c3 | 21 | // Control register definitions are a combination of address, |
| cassyarduino | 0:e3fb1267e3c3 | 22 | // bank number, and Ethernet/MAC/PHY indicator bits. |
| cassyarduino | 0:e3fb1267e3c3 | 23 | // - Register address (bits 0-4) |
| cassyarduino | 0:e3fb1267e3c3 | 24 | // - Bank number (bits 5-6) |
| cassyarduino | 0:e3fb1267e3c3 | 25 | // - MAC/PHY indicator (bit 7) |
| cassyarduino | 0:e3fb1267e3c3 | 26 | #define ADDR_MASK 0x1F |
| cassyarduino | 0:e3fb1267e3c3 | 27 | #define BANK_MASK 0x60 |
| cassyarduino | 0:e3fb1267e3c3 | 28 | #define SPRD_MASK 0x80 |
| cassyarduino | 0:e3fb1267e3c3 | 29 | // All-bank registers |
| cassyarduino | 0:e3fb1267e3c3 | 30 | #define EIE 0x1B |
| cassyarduino | 0:e3fb1267e3c3 | 31 | #define EIR 0x1C |
| cassyarduino | 0:e3fb1267e3c3 | 32 | #define ESTAT 0x1D |
| cassyarduino | 0:e3fb1267e3c3 | 33 | #define ECON2 0x1E |
| cassyarduino | 0:e3fb1267e3c3 | 34 | #define ECON1 0x1F |
| cassyarduino | 0:e3fb1267e3c3 | 35 | // Bank 0 registers |
| cassyarduino | 0:e3fb1267e3c3 | 36 | #define ERDPTL (0x00|0x00) |
| cassyarduino | 0:e3fb1267e3c3 | 37 | #define ERDPTH (0x01|0x00) |
| cassyarduino | 0:e3fb1267e3c3 | 38 | #define EWRPTL (0x02|0x00) |
| cassyarduino | 0:e3fb1267e3c3 | 39 | #define EWRPTH (0x03|0x00) |
| cassyarduino | 0:e3fb1267e3c3 | 40 | #define ETXSTL (0x04|0x00) |
| cassyarduino | 0:e3fb1267e3c3 | 41 | #define ETXSTH (0x05|0x00) |
| cassyarduino | 0:e3fb1267e3c3 | 42 | #define ETXNDL (0x06|0x00) |
| cassyarduino | 0:e3fb1267e3c3 | 43 | #define ETXNDH (0x07|0x00) |
| cassyarduino | 0:e3fb1267e3c3 | 44 | #define ERXSTL (0x08|0x00) |
| cassyarduino | 0:e3fb1267e3c3 | 45 | #define ERXSTH (0x09|0x00) |
| cassyarduino | 0:e3fb1267e3c3 | 46 | #define ERXNDL (0x0A|0x00) |
| cassyarduino | 0:e3fb1267e3c3 | 47 | #define ERXNDH (0x0B|0x00) |
| cassyarduino | 0:e3fb1267e3c3 | 48 | #define ERXRDPTL (0x0C|0x00) |
| cassyarduino | 0:e3fb1267e3c3 | 49 | #define ERXRDPTH (0x0D|0x00) |
| cassyarduino | 0:e3fb1267e3c3 | 50 | #define ERXWRPTL (0x0E|0x00) |
| cassyarduino | 0:e3fb1267e3c3 | 51 | #define ERXWRPTH (0x0F|0x00) |
| cassyarduino | 0:e3fb1267e3c3 | 52 | #define EDMASTL (0x10|0x00) |
| cassyarduino | 0:e3fb1267e3c3 | 53 | #define EDMASTH (0x11|0x00) |
| cassyarduino | 0:e3fb1267e3c3 | 54 | #define EDMANDL (0x12|0x00) |
| cassyarduino | 0:e3fb1267e3c3 | 55 | #define EDMANDH (0x13|0x00) |
| cassyarduino | 0:e3fb1267e3c3 | 56 | #define EDMADSTL (0x14|0x00) |
| cassyarduino | 0:e3fb1267e3c3 | 57 | #define EDMADSTH (0x15|0x00) |
| cassyarduino | 0:e3fb1267e3c3 | 58 | #define EDMACSL (0x16|0x00) |
| cassyarduino | 0:e3fb1267e3c3 | 59 | #define EDMACSH (0x17|0x00) |
| cassyarduino | 0:e3fb1267e3c3 | 60 | // Bank 1 registers |
| cassyarduino | 0:e3fb1267e3c3 | 61 | #define EHT0 (0x00|0x20) |
| cassyarduino | 0:e3fb1267e3c3 | 62 | #define EHT1 (0x01|0x20) |
| cassyarduino | 0:e3fb1267e3c3 | 63 | #define EHT2 (0x02|0x20) |
| cassyarduino | 0:e3fb1267e3c3 | 64 | #define EHT3 (0x03|0x20) |
| cassyarduino | 0:e3fb1267e3c3 | 65 | #define EHT4 (0x04|0x20) |
| cassyarduino | 0:e3fb1267e3c3 | 66 | #define EHT5 (0x05|0x20) |
| cassyarduino | 0:e3fb1267e3c3 | 67 | #define EHT6 (0x06|0x20) |
| cassyarduino | 0:e3fb1267e3c3 | 68 | #define EHT7 (0x07|0x20) |
| cassyarduino | 0:e3fb1267e3c3 | 69 | #define EPMM0 (0x08|0x20) |
| cassyarduino | 0:e3fb1267e3c3 | 70 | #define EPMM1 (0x09|0x20) |
| cassyarduino | 0:e3fb1267e3c3 | 71 | #define EPMM2 (0x0A|0x20) |
| cassyarduino | 0:e3fb1267e3c3 | 72 | #define EPMM3 (0x0B|0x20) |
| cassyarduino | 0:e3fb1267e3c3 | 73 | #define EPMM4 (0x0C|0x20) |
| cassyarduino | 0:e3fb1267e3c3 | 74 | #define EPMM5 (0x0D|0x20) |
| cassyarduino | 0:e3fb1267e3c3 | 75 | #define EPMM6 (0x0E|0x20) |
| cassyarduino | 0:e3fb1267e3c3 | 76 | #define EPMM7 (0x0F|0x20) |
| cassyarduino | 0:e3fb1267e3c3 | 77 | #define EPMCSL (0x10|0x20) |
| cassyarduino | 0:e3fb1267e3c3 | 78 | #define EPMCSH (0x11|0x20) |
| cassyarduino | 0:e3fb1267e3c3 | 79 | #define EPMOL (0x14|0x20) |
| cassyarduino | 0:e3fb1267e3c3 | 80 | #define EPMOH (0x15|0x20) |
| cassyarduino | 0:e3fb1267e3c3 | 81 | #define EWOLIE (0x16|0x20) |
| cassyarduino | 0:e3fb1267e3c3 | 82 | #define EWOLIR (0x17|0x20) |
| cassyarduino | 0:e3fb1267e3c3 | 83 | #define ERXFCON (0x18|0x20) |
| cassyarduino | 0:e3fb1267e3c3 | 84 | #define EPKTCNT (0x19|0x20) |
| cassyarduino | 0:e3fb1267e3c3 | 85 | // Bank 2 registers |
| cassyarduino | 0:e3fb1267e3c3 | 86 | #define MACON1 (0x00|0x40|0x80) |
| cassyarduino | 0:e3fb1267e3c3 | 87 | #define MACON2 (0x01|0x40|0x80) |
| cassyarduino | 0:e3fb1267e3c3 | 88 | #define MACON3 (0x02|0x40|0x80) |
| cassyarduino | 0:e3fb1267e3c3 | 89 | #define MACON4 (0x03|0x40|0x80) |
| cassyarduino | 0:e3fb1267e3c3 | 90 | #define MABBIPG (0x04|0x40|0x80) |
| cassyarduino | 0:e3fb1267e3c3 | 91 | #define MAIPGL (0x06|0x40|0x80) |
| cassyarduino | 0:e3fb1267e3c3 | 92 | #define MAIPGH (0x07|0x40|0x80) |
| cassyarduino | 0:e3fb1267e3c3 | 93 | #define MACLCON1 (0x08|0x40|0x80) |
| cassyarduino | 0:e3fb1267e3c3 | 94 | #define MACLCON2 (0x09|0x40|0x80) |
| cassyarduino | 0:e3fb1267e3c3 | 95 | #define MAMXFLL (0x0A|0x40|0x80) |
| cassyarduino | 0:e3fb1267e3c3 | 96 | #define MAMXFLH (0x0B|0x40|0x80) |
| cassyarduino | 0:e3fb1267e3c3 | 97 | #define MAPHSUP (0x0D|0x40|0x80) |
| cassyarduino | 0:e3fb1267e3c3 | 98 | #define MICON (0x11|0x40|0x80) |
| cassyarduino | 0:e3fb1267e3c3 | 99 | #define MICMD (0x12|0x40|0x80) |
| cassyarduino | 0:e3fb1267e3c3 | 100 | #define MIREGADR (0x14|0x40|0x80) |
| cassyarduino | 0:e3fb1267e3c3 | 101 | #define MIWRL (0x16|0x40|0x80) |
| cassyarduino | 0:e3fb1267e3c3 | 102 | #define MIWRH (0x17|0x40|0x80) |
| cassyarduino | 0:e3fb1267e3c3 | 103 | #define MIRDL (0x18|0x40|0x80) |
| cassyarduino | 0:e3fb1267e3c3 | 104 | #define MIRDH (0x19|0x40|0x80) |
| cassyarduino | 0:e3fb1267e3c3 | 105 | // Bank 3 registers |
| cassyarduino | 0:e3fb1267e3c3 | 106 | #define MAADR1 (0x00|0x60|0x80) |
| cassyarduino | 0:e3fb1267e3c3 | 107 | #define MAADR0 (0x01|0x60|0x80) |
| cassyarduino | 0:e3fb1267e3c3 | 108 | #define MAADR3 (0x02|0x60|0x80) |
| cassyarduino | 0:e3fb1267e3c3 | 109 | #define MAADR2 (0x03|0x60|0x80) |
| cassyarduino | 0:e3fb1267e3c3 | 110 | #define MAADR5 (0x04|0x60|0x80) |
| cassyarduino | 0:e3fb1267e3c3 | 111 | #define MAADR4 (0x05|0x60|0x80) |
| cassyarduino | 0:e3fb1267e3c3 | 112 | #define EBSTSD (0x06|0x60) |
| cassyarduino | 0:e3fb1267e3c3 | 113 | #define EBSTCON (0x07|0x60) |
| cassyarduino | 0:e3fb1267e3c3 | 114 | #define EBSTCSL (0x08|0x60) |
| cassyarduino | 0:e3fb1267e3c3 | 115 | #define EBSTCSH (0x09|0x60) |
| cassyarduino | 0:e3fb1267e3c3 | 116 | #define MISTAT (0x0A|0x60|0x80) |
| cassyarduino | 0:e3fb1267e3c3 | 117 | #define EREVID (0x12|0x60) |
| cassyarduino | 0:e3fb1267e3c3 | 118 | #define ECOCON (0x15|0x60) |
| cassyarduino | 0:e3fb1267e3c3 | 119 | #define EFLOCON (0x17|0x60) |
| cassyarduino | 0:e3fb1267e3c3 | 120 | #define EPAUSL (0x18|0x60) |
| cassyarduino | 0:e3fb1267e3c3 | 121 | #define EPAUSH (0x19|0x60) |
| cassyarduino | 0:e3fb1267e3c3 | 122 | // PHY registers |
| cassyarduino | 0:e3fb1267e3c3 | 123 | #define PHCON1 0x00 |
| cassyarduino | 0:e3fb1267e3c3 | 124 | #define PHSTAT1 0x01 |
| cassyarduino | 0:e3fb1267e3c3 | 125 | #define PHHID1 0x02 |
| cassyarduino | 0:e3fb1267e3c3 | 126 | #define PHHID2 0x03 |
| cassyarduino | 0:e3fb1267e3c3 | 127 | #define PHCON2 0x10 |
| cassyarduino | 0:e3fb1267e3c3 | 128 | #define PHSTAT2 0x11 |
| cassyarduino | 0:e3fb1267e3c3 | 129 | #define PHIE 0x12 |
| cassyarduino | 0:e3fb1267e3c3 | 130 | #define PHIR 0x13 |
| cassyarduino | 0:e3fb1267e3c3 | 131 | #define PHLCON 0x14 |
| cassyarduino | 0:e3fb1267e3c3 | 132 | |
| cassyarduino | 0:e3fb1267e3c3 | 133 | // ENC28J60 ERXFCON Register Bit Definitions |
| cassyarduino | 0:e3fb1267e3c3 | 134 | #define ERXFCON_UCEN 0x80 |
| cassyarduino | 0:e3fb1267e3c3 | 135 | #define ERXFCON_ANDOR 0x40 |
| cassyarduino | 0:e3fb1267e3c3 | 136 | #define ERXFCON_CRCEN 0x20 |
| cassyarduino | 0:e3fb1267e3c3 | 137 | #define ERXFCON_PMEN 0x10 |
| cassyarduino | 0:e3fb1267e3c3 | 138 | #define ERXFCON_MPEN 0x08 |
| cassyarduino | 0:e3fb1267e3c3 | 139 | #define ERXFCON_HTEN 0x04 |
| cassyarduino | 0:e3fb1267e3c3 | 140 | #define ERXFCON_MCEN 0x02 |
| cassyarduino | 0:e3fb1267e3c3 | 141 | #define ERXFCON_BCEN 0x01 |
| cassyarduino | 0:e3fb1267e3c3 | 142 | // ENC28J60 EIE Register Bit Definitions |
| cassyarduino | 0:e3fb1267e3c3 | 143 | #define EIE_INTIE 0x80 |
| cassyarduino | 0:e3fb1267e3c3 | 144 | #define EIE_PKTIE 0x40 |
| cassyarduino | 0:e3fb1267e3c3 | 145 | #define EIE_DMAIE 0x20 |
| cassyarduino | 0:e3fb1267e3c3 | 146 | #define EIE_LINKIE 0x10 |
| cassyarduino | 0:e3fb1267e3c3 | 147 | #define EIE_TXIE 0x08 |
| cassyarduino | 0:e3fb1267e3c3 | 148 | #define EIE_WOLIE 0x04 |
| cassyarduino | 0:e3fb1267e3c3 | 149 | #define EIE_TXERIE 0x02 |
| cassyarduino | 0:e3fb1267e3c3 | 150 | #define EIE_RXERIE 0x01 |
| cassyarduino | 0:e3fb1267e3c3 | 151 | // ENC28J60 EIR Register Bit Definitions |
| cassyarduino | 0:e3fb1267e3c3 | 152 | #define EIR_PKTIF 0x40 |
| cassyarduino | 0:e3fb1267e3c3 | 153 | #define EIR_DMAIF 0x20 |
| cassyarduino | 0:e3fb1267e3c3 | 154 | #define EIR_LINKIF 0x10 |
| cassyarduino | 0:e3fb1267e3c3 | 155 | #define EIR_TXIF 0x08 |
| cassyarduino | 0:e3fb1267e3c3 | 156 | #define EIR_WOLIF 0x04 |
| cassyarduino | 0:e3fb1267e3c3 | 157 | #define EIR_TXERIF 0x02 |
| cassyarduino | 0:e3fb1267e3c3 | 158 | #define EIR_RXERIF 0x01 |
| cassyarduino | 0:e3fb1267e3c3 | 159 | // ENC28J60 ESTAT Register Bit Definitions |
| cassyarduino | 0:e3fb1267e3c3 | 160 | #define ESTAT_INT 0x80 |
| cassyarduino | 0:e3fb1267e3c3 | 161 | #define ESTAT_LATECOL 0x10 |
| cassyarduino | 0:e3fb1267e3c3 | 162 | #define ESTAT_RXBUSY 0x04 |
| cassyarduino | 0:e3fb1267e3c3 | 163 | #define ESTAT_TXABRT 0x02 |
| cassyarduino | 0:e3fb1267e3c3 | 164 | #define ESTAT_CLKRDY 0x01 |
| cassyarduino | 0:e3fb1267e3c3 | 165 | // ENC28J60 ECON2 Register Bit Definitions |
| cassyarduino | 0:e3fb1267e3c3 | 166 | #define ECON2_AUTOINC 0x80 |
| cassyarduino | 0:e3fb1267e3c3 | 167 | #define ECON2_PKTDEC 0x40 |
| cassyarduino | 0:e3fb1267e3c3 | 168 | #define ECON2_PWRSV 0x20 |
| cassyarduino | 0:e3fb1267e3c3 | 169 | #define ECON2_VRPS 0x08 |
| cassyarduino | 0:e3fb1267e3c3 | 170 | // ENC28J60 ECON1 Register Bit Definitions |
| cassyarduino | 0:e3fb1267e3c3 | 171 | #define ECON1_TXRST 0x80 |
| cassyarduino | 0:e3fb1267e3c3 | 172 | #define ECON1_RXRST 0x40 |
| cassyarduino | 0:e3fb1267e3c3 | 173 | #define ECON1_DMAST 0x20 |
| cassyarduino | 0:e3fb1267e3c3 | 174 | #define ECON1_CSUMEN 0x10 |
| cassyarduino | 0:e3fb1267e3c3 | 175 | #define ECON1_TXRTS 0x08 |
| cassyarduino | 0:e3fb1267e3c3 | 176 | #define ECON1_RXEN 0x04 |
| cassyarduino | 0:e3fb1267e3c3 | 177 | #define ECON1_BSEL1 0x02 |
| cassyarduino | 0:e3fb1267e3c3 | 178 | #define ECON1_BSEL0 0x01 |
| cassyarduino | 0:e3fb1267e3c3 | 179 | // ENC28J60 MACON1 Register Bit Definitions |
| cassyarduino | 0:e3fb1267e3c3 | 180 | #define MACON1_LOOPBK 0x10 |
| cassyarduino | 0:e3fb1267e3c3 | 181 | #define MACON1_TXPAUS 0x08 |
| cassyarduino | 0:e3fb1267e3c3 | 182 | #define MACON1_RXPAUS 0x04 |
| cassyarduino | 0:e3fb1267e3c3 | 183 | #define MACON1_PASSALL 0x02 |
| cassyarduino | 0:e3fb1267e3c3 | 184 | #define MACON1_MARXEN 0x01 |
| cassyarduino | 0:e3fb1267e3c3 | 185 | // ENC28J60 MACON2 Register Bit Definitions |
| cassyarduino | 0:e3fb1267e3c3 | 186 | #define MACON2_MARST 0x80 |
| cassyarduino | 0:e3fb1267e3c3 | 187 | #define MACON2_RNDRST 0x40 |
| cassyarduino | 0:e3fb1267e3c3 | 188 | #define MACON2_MARXRST 0x08 |
| cassyarduino | 0:e3fb1267e3c3 | 189 | #define MACON2_RFUNRST 0x04 |
| cassyarduino | 0:e3fb1267e3c3 | 190 | #define MACON2_MATXRST 0x02 |
| cassyarduino | 0:e3fb1267e3c3 | 191 | #define MACON2_TFUNRST 0x01 |
| cassyarduino | 0:e3fb1267e3c3 | 192 | // ENC28J60 MACON3 Register Bit Definitions |
| cassyarduino | 0:e3fb1267e3c3 | 193 | #define MACON3_PADCFG2 0x80 |
| cassyarduino | 0:e3fb1267e3c3 | 194 | #define MACON3_PADCFG1 0x40 |
| cassyarduino | 0:e3fb1267e3c3 | 195 | #define MACON3_PADCFG0 0x20 |
| cassyarduino | 0:e3fb1267e3c3 | 196 | #define MACON3_TXCRCEN 0x10 |
| cassyarduino | 0:e3fb1267e3c3 | 197 | #define MACON3_PHDRLEN 0x08 |
| cassyarduino | 0:e3fb1267e3c3 | 198 | #define MACON3_HFRMLEN 0x04 |
| cassyarduino | 0:e3fb1267e3c3 | 199 | #define MACON3_FRMLNEN 0x02 |
| cassyarduino | 0:e3fb1267e3c3 | 200 | #define MACON3_FULDPX 0x01 |
| cassyarduino | 0:e3fb1267e3c3 | 201 | // ENC28J60 MICMD Register Bit Definitions |
| cassyarduino | 0:e3fb1267e3c3 | 202 | #define MICMD_MIISCAN 0x02 |
| cassyarduino | 0:e3fb1267e3c3 | 203 | #define MICMD_MIIRD 0x01 |
| cassyarduino | 0:e3fb1267e3c3 | 204 | // ENC28J60 MISTAT Register Bit Definitions |
| cassyarduino | 0:e3fb1267e3c3 | 205 | #define MISTAT_NVALID 0x04 |
| cassyarduino | 0:e3fb1267e3c3 | 206 | #define MISTAT_SCAN 0x02 |
| cassyarduino | 0:e3fb1267e3c3 | 207 | #define MISTAT_BUSY 0x01 |
| cassyarduino | 0:e3fb1267e3c3 | 208 | // ENC28J60 PHY PHCON1 Register Bit Definitions |
| cassyarduino | 0:e3fb1267e3c3 | 209 | #define PHCON1_PRST 0x8000 |
| cassyarduino | 0:e3fb1267e3c3 | 210 | #define PHCON1_PLOOPBK 0x4000 |
| cassyarduino | 0:e3fb1267e3c3 | 211 | #define PHCON1_PPWRSV 0x0800 |
| cassyarduino | 0:e3fb1267e3c3 | 212 | #define PHCON1_PDPXMD 0x0100 |
| cassyarduino | 0:e3fb1267e3c3 | 213 | // ENC28J60 PHY PHSTAT1 Register Bit Definitions |
| cassyarduino | 0:e3fb1267e3c3 | 214 | #define PHSTAT1_PFDPX 0x1000 |
| cassyarduino | 0:e3fb1267e3c3 | 215 | #define PHSTAT1_PHDPX 0x0800 |
| cassyarduino | 0:e3fb1267e3c3 | 216 | #define PHSTAT1_LLSTAT 0x0004 |
| cassyarduino | 0:e3fb1267e3c3 | 217 | #define PHSTAT1_JBSTAT 0x0002 |
| cassyarduino | 0:e3fb1267e3c3 | 218 | // ENC28J60 PHY PHCON2 Register Bit Definitions |
| cassyarduino | 0:e3fb1267e3c3 | 219 | #define PHCON2_FRCLINK 0x4000 |
| cassyarduino | 0:e3fb1267e3c3 | 220 | #define PHCON2_TXDIS 0x2000 |
| cassyarduino | 0:e3fb1267e3c3 | 221 | #define PHCON2_JABBER 0x0400 |
| cassyarduino | 0:e3fb1267e3c3 | 222 | #define PHCON2_HDLDIS 0x0100 |
| cassyarduino | 0:e3fb1267e3c3 | 223 | |
| cassyarduino | 0:e3fb1267e3c3 | 224 | // ENC28J60 Packet Control Byte Bit Definitions |
| cassyarduino | 0:e3fb1267e3c3 | 225 | #define PKTCTRL_PHUGEEN 0x08 |
| cassyarduino | 0:e3fb1267e3c3 | 226 | #define PKTCTRL_PPADEN 0x04 |
| cassyarduino | 0:e3fb1267e3c3 | 227 | #define PKTCTRL_PCRCEN 0x02 |
| cassyarduino | 0:e3fb1267e3c3 | 228 | #define PKTCTRL_POVERRIDE 0x01 |
| cassyarduino | 0:e3fb1267e3c3 | 229 | |
| cassyarduino | 0:e3fb1267e3c3 | 230 | // SPI operation codes |
| cassyarduino | 0:e3fb1267e3c3 | 231 | #define ENC28J60_READ_CTRL_REG 0x00 |
| cassyarduino | 0:e3fb1267e3c3 | 232 | #define ENC28J60_READ_BUF_MEM 0x3A |
| cassyarduino | 0:e3fb1267e3c3 | 233 | #define ENC28J60_WRITE_CTRL_REG 0x40 |
| cassyarduino | 0:e3fb1267e3c3 | 234 | #define ENC28J60_WRITE_BUF_MEM 0x7A |
| cassyarduino | 0:e3fb1267e3c3 | 235 | #define ENC28J60_BIT_FIELD_SET 0x80 |
| cassyarduino | 0:e3fb1267e3c3 | 236 | #define ENC28J60_BIT_FIELD_CLR 0xA0 |
| cassyarduino | 0:e3fb1267e3c3 | 237 | #define ENC28J60_SOFT_RESET 0xFF |
| cassyarduino | 0:e3fb1267e3c3 | 238 | |
| cassyarduino | 0:e3fb1267e3c3 | 239 | |
| cassyarduino | 0:e3fb1267e3c3 | 240 | // The RXSTART_INIT should be zero. See Rev. B4 Silicon Errata |
| cassyarduino | 0:e3fb1267e3c3 | 241 | // buffer boundaries applied to internal 8K ram |
| cassyarduino | 0:e3fb1267e3c3 | 242 | // the entire available packet buffer space is allocated |
| cassyarduino | 0:e3fb1267e3c3 | 243 | // |
| cassyarduino | 0:e3fb1267e3c3 | 244 | // start with recbuf at 0/ |
| cassyarduino | 0:e3fb1267e3c3 | 245 | #define RXSTART_INIT 0x0 |
| cassyarduino | 0:e3fb1267e3c3 | 246 | // receive buffer end. make sure this is an odd value ( See Rev. B1,B4,B5,B7 Silicon Errata 'Memory (Ethernet Buffer)') |
| cassyarduino | 0:e3fb1267e3c3 | 247 | #define RXSTOP_INIT (0x1FFF-0x1800) |
| cassyarduino | 0:e3fb1267e3c3 | 248 | // start TX buffer RXSTOP_INIT+1 |
| cassyarduino | 0:e3fb1267e3c3 | 249 | #define TXSTART_INIT (RXSTOP_INIT+1) |
| cassyarduino | 0:e3fb1267e3c3 | 250 | // stp TX buffer at end of mem |
| cassyarduino | 0:e3fb1267e3c3 | 251 | #define TXSTOP_INIT 0x1FFF |
| cassyarduino | 0:e3fb1267e3c3 | 252 | // |
| cassyarduino | 0:e3fb1267e3c3 | 253 | // max frame length which the conroller will accept: |
| cassyarduino | 0:e3fb1267e3c3 | 254 | #define MAX_FRAMELEN 1500 // (note: maximum ethernet frame length would be 1518) |
| cassyarduino | 0:e3fb1267e3c3 | 255 | //#define MAX_FRAMELEN 600 |
| cassyarduino | 0:e3fb1267e3c3 | 256 | |
| cassyarduino | 0:e3fb1267e3c3 | 257 | #endif |