UIPEthernet library for Arduino IDE, Eclipse with arduino plugin and MBED/SMeshStudio (AVR,STM32F,ESP8266,Intel ARC32,Nordic nRF51,Teensy boards,Realtek Ameba(RTL8195A,RTL8710)), ENC28j60 network chip. Compatible with Wiznet W5100 Ethernet library API. Compiled and tested on Nucleo-F302R8. Master repository is: https://github.com/UIPEthernet/UIPEthernet/

Committer:
cassyarduino
Date:
Sun Jan 01 20:33:12 2017 +0100
Revision:
16:66225c1d660c
Parent:
0:e3fb1267e3c3
Child:
17:be34a75aa9a7
Changes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
cassyarduino 0:e3fb1267e3c3 1 /*
cassyarduino 0:e3fb1267e3c3 2 Enc28J60NetworkClass.h
cassyarduino 0:e3fb1267e3c3 3 UIPEthernet network driver for Microchip ENC28J60 Ethernet Interface.
cassyarduino 0:e3fb1267e3c3 4
cassyarduino 0:e3fb1267e3c3 5 Copyright (c) 2013 Norbert Truchsess <norbert.truchsess@t-online.de>
cassyarduino 0:e3fb1267e3c3 6 All rights reserved.
cassyarduino 0:e3fb1267e3c3 7
cassyarduino 0:e3fb1267e3c3 8 based on enc28j60.c file from the AVRlib library by Pascal Stang.
cassyarduino 0:e3fb1267e3c3 9 For AVRlib See http://www.procyonengineering.com/
cassyarduino 0:e3fb1267e3c3 10
cassyarduino 0:e3fb1267e3c3 11 This program is free software: you can redistribute it and/or modify
cassyarduino 0:e3fb1267e3c3 12 it under the terms of the GNU General Public License as published by
cassyarduino 0:e3fb1267e3c3 13 the Free Software Foundation, either version 3 of the License, or
cassyarduino 0:e3fb1267e3c3 14 (at your option) any later version.
cassyarduino 0:e3fb1267e3c3 15
cassyarduino 0:e3fb1267e3c3 16 This program is distributed in the hope that it will be useful,
cassyarduino 0:e3fb1267e3c3 17 but WITHOUT ANY WARRANTY; without even the implied warranty of
cassyarduino 0:e3fb1267e3c3 18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cassyarduino 0:e3fb1267e3c3 19 GNU General Public License for more details.
cassyarduino 0:e3fb1267e3c3 20
cassyarduino 0:e3fb1267e3c3 21 You should have received a copy of the GNU General Public License
cassyarduino 0:e3fb1267e3c3 22 along with this program. If not, see <http://www.gnu.org/licenses/>.
cassyarduino 0:e3fb1267e3c3 23 */
cassyarduino 0:e3fb1267e3c3 24
cassyarduino 0:e3fb1267e3c3 25 #include "Enc28J60Network.h"
cassyarduino 0:e3fb1267e3c3 26 #if defined(ARDUINO)
cassyarduino 0:e3fb1267e3c3 27 #include "Arduino.h"
cassyarduino 0:e3fb1267e3c3 28 #endif
cassyarduino 0:e3fb1267e3c3 29 #if defined(__MBED__)
cassyarduino 0:e3fb1267e3c3 30 #include <mbed.h>
cassyarduino 0:e3fb1267e3c3 31 #define delay(x) wait_ms(x)
cassyarduino 0:e3fb1267e3c3 32 #endif
cassyarduino 0:e3fb1267e3c3 33 #include "logging.h"
cassyarduino 0:e3fb1267e3c3 34
cassyarduino 0:e3fb1267e3c3 35 #if ENC28J60_USE_SPILIB
cassyarduino 0:e3fb1267e3c3 36 #include <SPI.h>
cassyarduino 0:e3fb1267e3c3 37 #if defined(ARDUINO)
cassyarduino 0:e3fb1267e3c3 38 extern SPIClass SPI;
cassyarduino 0:e3fb1267e3c3 39 #endif
cassyarduino 0:e3fb1267e3c3 40 #if defined(__MBED__)
cassyarduino 0:e3fb1267e3c3 41 SPI _spi(SPI_MOSI,SPI_MISO,SPI_SCK);
cassyarduino 0:e3fb1267e3c3 42 DigitalOut _cs(ENC28J60_CONTROL_CS);
cassyarduino 0:e3fb1267e3c3 43 Serial LogObject(SERIAL_TX,SERIAL_RX);
cassyarduino 0:e3fb1267e3c3 44 #endif
cassyarduino 0:e3fb1267e3c3 45 #endif
cassyarduino 0:e3fb1267e3c3 46
cassyarduino 0:e3fb1267e3c3 47 extern "C" {
cassyarduino 0:e3fb1267e3c3 48 #if defined(ARDUINO_ARCH_AVR)
cassyarduino 0:e3fb1267e3c3 49 // AVR-specific code
cassyarduino 0:e3fb1267e3c3 50 #include <avr/io.h>
cassyarduino 0:e3fb1267e3c3 51 #elif defined(ARDUINO_ARCH_SAM)
cassyarduino 0:e3fb1267e3c3 52 // SAM-specific code
cassyarduino 0:e3fb1267e3c3 53 #else
cassyarduino 0:e3fb1267e3c3 54 // generic, non-platform specific code
cassyarduino 0:e3fb1267e3c3 55 #endif
cassyarduino 0:e3fb1267e3c3 56 #include "enc28j60.h"
cassyarduino 0:e3fb1267e3c3 57 #include "uip.h"
cassyarduino 0:e3fb1267e3c3 58 }
cassyarduino 0:e3fb1267e3c3 59
cassyarduino 0:e3fb1267e3c3 60 #if defined(ARDUINO)
cassyarduino 0:e3fb1267e3c3 61 // set CS to 0 = active
cassyarduino 0:e3fb1267e3c3 62 #define CSACTIVE digitalWrite(ENC28J60_CONTROL_CS, LOW)
cassyarduino 0:e3fb1267e3c3 63 // set CS to 1 = passive
cassyarduino 0:e3fb1267e3c3 64 #define CSPASSIVE digitalWrite(ENC28J60_CONTROL_CS, HIGH)
cassyarduino 0:e3fb1267e3c3 65 #endif
cassyarduino 0:e3fb1267e3c3 66 #if defined(__MBED__)
cassyarduino 0:e3fb1267e3c3 67 // set CS to 0 = active
cassyarduino 0:e3fb1267e3c3 68 #define CSACTIVE _cs=0
cassyarduino 0:e3fb1267e3c3 69 // set CS to 1 = passive
cassyarduino 0:e3fb1267e3c3 70 #define CSPASSIVE _cs=1
cassyarduino 0:e3fb1267e3c3 71 #endif
cassyarduino 0:e3fb1267e3c3 72
cassyarduino 0:e3fb1267e3c3 73 //
cassyarduino 0:e3fb1267e3c3 74 #if defined(ARDUINO_ARCH_AVR)
cassyarduino 0:e3fb1267e3c3 75 #define waitspi() while(!(SPSR&(1<<SPIF)))
cassyarduino 0:e3fb1267e3c3 76 #elif defined(ARDUINO_ARCH_SAM)
cassyarduino 0:e3fb1267e3c3 77 #if ENC28J60_CONTROL_CS==BOARD_SPI_SS0 or ENC28J60_CONTROL_CS==BOARD_SPI_SS1 or ENC28J60_CONTROL_CS==BOARD_SPI_SS2 or ENC28J60_CONTROL_CS==BOARD_SPI_SS3
cassyarduino 0:e3fb1267e3c3 78 #define ENC28J60_USE_SPILIB_EXT 1
cassyarduino 0:e3fb1267e3c3 79 #endif
cassyarduino 0:e3fb1267e3c3 80 #endif
cassyarduino 0:e3fb1267e3c3 81
cassyarduino 0:e3fb1267e3c3 82 uint16_t Enc28J60Network::nextPacketPtr;
cassyarduino 0:e3fb1267e3c3 83 uint8_t Enc28J60Network::bank=0xff;
cassyarduino 0:e3fb1267e3c3 84 uint8_t Enc28J60Network::erevid=0;
cassyarduino 0:e3fb1267e3c3 85
cassyarduino 0:e3fb1267e3c3 86 struct memblock Enc28J60Network::receivePkt;
cassyarduino 0:e3fb1267e3c3 87
cassyarduino 0:e3fb1267e3c3 88 bool Enc28J60Network::broadcast_enabled = false;
cassyarduino 0:e3fb1267e3c3 89
cassyarduino 0:e3fb1267e3c3 90
cassyarduino 0:e3fb1267e3c3 91 void Enc28J60Network::init(uint8_t* macaddr)
cassyarduino 0:e3fb1267e3c3 92 {
cassyarduino 0:e3fb1267e3c3 93 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 94 LogObject.uart_send_strln(F("Enc28J60Network::init(uint8_t* macaddr) DEBUG_V3:Function started"));
cassyarduino 0:e3fb1267e3c3 95 #endif
cassyarduino 0:e3fb1267e3c3 96 receivePkt.begin = 0;
cassyarduino 0:e3fb1267e3c3 97 receivePkt.size = 0;
cassyarduino 0:e3fb1267e3c3 98
cassyarduino 0:e3fb1267e3c3 99 unsigned int timeout = 15;
cassyarduino 0:e3fb1267e3c3 100 MemoryPool::init(); // 1 byte in between RX_STOP_INIT and pool to allow prepending of controlbyte
cassyarduino 0:e3fb1267e3c3 101 // initialize I/O
cassyarduino 0:e3fb1267e3c3 102 // ss as output:
cassyarduino 0:e3fb1267e3c3 103 #if defined(ARDUINO)
cassyarduino 0:e3fb1267e3c3 104 pinMode(ENC28J60_CONTROL_CS, OUTPUT);
cassyarduino 0:e3fb1267e3c3 105 #endif
cassyarduino 0:e3fb1267e3c3 106 CSPASSIVE; // ss=0
cassyarduino 0:e3fb1267e3c3 107 //
cassyarduino 0:e3fb1267e3c3 108
cassyarduino 0:e3fb1267e3c3 109 #if ACTLOGLEVEL>=LOG_DEBUG
cassyarduino 0:e3fb1267e3c3 110 LogObject.uart_send_str(F("ENC28J60::init DEBUG:csPin = "));
cassyarduino 0:e3fb1267e3c3 111 LogObject.uart_send_decln(ENC28J60_CONTROL_CS);
cassyarduino 0:e3fb1267e3c3 112 LogObject.uart_send_str(F("ENC28J60::init DEBUG:miso = "));
cassyarduino 0:e3fb1267e3c3 113 LogObject.uart_send_decln(SPI_MISO);
cassyarduino 0:e3fb1267e3c3 114 LogObject.uart_send_str(F("ENC28J60::init DEBUG:mosi = "));
cassyarduino 0:e3fb1267e3c3 115 LogObject.uart_send_decln(SPI_MOSI);
cassyarduino 0:e3fb1267e3c3 116 LogObject.uart_send_str(F("ENC28J60::init DEBUG:sck = "));
cassyarduino 0:e3fb1267e3c3 117 LogObject.uart_send_decln(SPI_SCK);
cassyarduino 0:e3fb1267e3c3 118 #endif
cassyarduino 0:e3fb1267e3c3 119 #if ENC28J60_USE_SPILIB
cassyarduino 0:e3fb1267e3c3 120 #if ACTLOGLEVEL>=LOG_DEBUG
cassyarduino 0:e3fb1267e3c3 121 LogObject.uart_send_strln(F("ENC28J60::init DEBUG:Use SPI lib SPI.begin()"));
cassyarduino 0:e3fb1267e3c3 122 #endif
cassyarduino 0:e3fb1267e3c3 123 #if defined(ARDUINO)
cassyarduino 0:e3fb1267e3c3 124 SPI.begin();
cassyarduino 0:e3fb1267e3c3 125 #endif
cassyarduino 0:e3fb1267e3c3 126 #if defined(ARDUINO_ARCH_AVR)
cassyarduino 0:e3fb1267e3c3 127 // AVR-specific code
cassyarduino 0:e3fb1267e3c3 128 SPI.setClockDivider(SPI_CLOCK_DIV2); //results in 8MHZ at 16MHZ system clock.
cassyarduino 0:e3fb1267e3c3 129 #elif defined(ARDUINO_ARCH_SAM)
cassyarduino 0:e3fb1267e3c3 130 // SAM-specific code
cassyarduino 0:e3fb1267e3c3 131 SPI.setClockDivider(10); //defaults to 21 which results in aprox. 4MHZ. A 10 should result in a little more than 8MHZ.
cassyarduino 0:e3fb1267e3c3 132 #elif defined(__STM32F1__) || defined(__STM32F3__) || defined(__STM32F4__)
cassyarduino 0:e3fb1267e3c3 133 // generic, non-platform specific code
cassyarduino 0:e3fb1267e3c3 134 #define USE_STM32F1_DMAC 1 //on STM32
cassyarduino 0:e3fb1267e3c3 135 // BOARD_NR_SPI >= 1 BOARD_SPI1_NSS_PIN, BOARD_SPI1_SCK_PIN, BOARD_SPI1_MISO_PIN, BOARD_SPI1_MOSI_PIN
cassyarduino 0:e3fb1267e3c3 136 SPI.setBitOrder(MSBFIRST);
cassyarduino 0:e3fb1267e3c3 137 SPI.setDataMode(SPI_MODE0);
cassyarduino 0:e3fb1267e3c3 138 SPI.setClockDivider(SPI_CLOCK_DIV8); //value 8 the result is 9MHz at 72MHz clock.
cassyarduino 0:e3fb1267e3c3 139 #else
cassyarduino 0:e3fb1267e3c3 140 #if defined(ARDUINO)
cassyarduino 0:e3fb1267e3c3 141 SPI.setBitOrder(MSBFIRST);
cassyarduino 0:e3fb1267e3c3 142 //SPI.setDataMode(SPI_MODE0);
cassyarduino 0:e3fb1267e3c3 143 //SPI.setClockDivider(SPI_CLOCK_DIV16);
cassyarduino 0:e3fb1267e3c3 144 #endif
cassyarduino 0:e3fb1267e3c3 145 #if defined(__MBED__)
cassyarduino 0:e3fb1267e3c3 146 _spi.format(8, 0); // 8bit, mode 0
cassyarduino 0:e3fb1267e3c3 147 _spi.frequency(7000000); // 7MHz
cassyarduino 0:e3fb1267e3c3 148 #endif
cassyarduino 0:e3fb1267e3c3 149 #endif
cassyarduino 0:e3fb1267e3c3 150 #else
cassyarduino 0:e3fb1267e3c3 151 #if ACTLOGLEVEL>=LOG_DEBUG
cassyarduino 0:e3fb1267e3c3 152 LogObject.uart_send_strln(F("ENC28J60::init DEBUG:Use Native hardware SPI"));
cassyarduino 0:e3fb1267e3c3 153 #endif
cassyarduino 0:e3fb1267e3c3 154 pinMode(SPI_MOSI, OUTPUT);
cassyarduino 0:e3fb1267e3c3 155 pinMode(SPI_SCK, OUTPUT);
cassyarduino 0:e3fb1267e3c3 156 pinMode(SPI_MISO, INPUT);
cassyarduino 0:e3fb1267e3c3 157 //Hardware SS must be configured as OUTPUT to enable SPI-master (regardless of which pin is configured as ENC28J60_CONTROL_CS)
cassyarduino 0:e3fb1267e3c3 158 //pinMode(ENC28J60_CONTROL_CS, OUTPUT);
cassyarduino 0:e3fb1267e3c3 159
cassyarduino 0:e3fb1267e3c3 160 digitalWrite(SPI_MOSI, LOW);
cassyarduino 0:e3fb1267e3c3 161 digitalWrite(SPI_SCK, LOW);
cassyarduino 0:e3fb1267e3c3 162
cassyarduino 0:e3fb1267e3c3 163 // initialize SPI interface
cassyarduino 0:e3fb1267e3c3 164 // master mode and Fosc/2 clock:
cassyarduino 0:e3fb1267e3c3 165 SPCR = (1<<SPE)|(1<<MSTR);
cassyarduino 0:e3fb1267e3c3 166 SPSR |= (1<<SPI2X);
cassyarduino 0:e3fb1267e3c3 167 #endif
cassyarduino 0:e3fb1267e3c3 168
cassyarduino 0:e3fb1267e3c3 169 // perform system reset
cassyarduino 0:e3fb1267e3c3 170 writeOp(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
cassyarduino 0:e3fb1267e3c3 171 delay(2); // errata B7/2
cassyarduino 0:e3fb1267e3c3 172 delay(50);
cassyarduino 0:e3fb1267e3c3 173 // check CLKRDY bit to see if reset is complete
cassyarduino 0:e3fb1267e3c3 174 // The CLKRDY does not work. See Rev. B4 Silicon Errata point. Just wait.
cassyarduino 0:e3fb1267e3c3 175 //while(!(readReg(ESTAT) & ESTAT_CLKRDY));
cassyarduino 0:e3fb1267e3c3 176 // do bank 0 stuff
cassyarduino 0:e3fb1267e3c3 177 // initialize receive buffer
cassyarduino 0:e3fb1267e3c3 178 // 16-bit transfers, must write low byte first
cassyarduino 0:e3fb1267e3c3 179 // set receive buffer start address
cassyarduino 0:e3fb1267e3c3 180 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 181 LogObject.uart_send_strln(F("ENC28J60::init DEBUG_V3:Before readOp(ENC28J60_READ_CTRL_REG, ESTAT)"));
cassyarduino 0:e3fb1267e3c3 182 #endif
cassyarduino 0:e3fb1267e3c3 183 nextPacketPtr = RXSTART_INIT;
cassyarduino 0:e3fb1267e3c3 184 while ((!readOp(ENC28J60_READ_CTRL_REG, ESTAT) & ESTAT_CLKRDY) && (timeout>0))
cassyarduino 0:e3fb1267e3c3 185 {
cassyarduino 0:e3fb1267e3c3 186 timeout=timeout-1;
cassyarduino 0:e3fb1267e3c3 187 delay(10);
cassyarduino 0:e3fb1267e3c3 188 #if defined(ESP8266)
cassyarduino 0:e3fb1267e3c3 189 wdt_reset();
cassyarduino 0:e3fb1267e3c3 190 #endif
cassyarduino 0:e3fb1267e3c3 191 }
cassyarduino 0:e3fb1267e3c3 192 #if ACTLOGLEVEL>=LOG_ERR
cassyarduino 0:e3fb1267e3c3 193 if (timeout==0) {LogObject.uart_send_strln(F("ENC28J60::init ERROR:TIMEOUT !!!"));}
cassyarduino 0:e3fb1267e3c3 194 #endif
cassyarduino 0:e3fb1267e3c3 195 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 196 LogObject.uart_send_strln(F("ENC28J60::init DEBUG_V3:After readOp(ENC28J60_READ_CTRL_REG, ESTAT)"));
cassyarduino 0:e3fb1267e3c3 197 #endif
cassyarduino 0:e3fb1267e3c3 198 // Rx start
cassyarduino 0:e3fb1267e3c3 199 writeRegPair(ERXSTL, RXSTART_INIT);
cassyarduino 0:e3fb1267e3c3 200 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 201 LogObject.uart_send_strln(F("ENC28J60::init DEBUG_V3:After writeRegPair(ERXSTL, RXSTART_INIT)"));
cassyarduino 0:e3fb1267e3c3 202 #endif
cassyarduino 0:e3fb1267e3c3 203 // set receive pointer address
cassyarduino 0:e3fb1267e3c3 204 writeRegPair(ERXRDPTL, RXSTART_INIT);
cassyarduino 0:e3fb1267e3c3 205 // RX end
cassyarduino 0:e3fb1267e3c3 206 writeRegPair(ERXNDL, RXSTOP_INIT);
cassyarduino 0:e3fb1267e3c3 207 // TX start
cassyarduino 0:e3fb1267e3c3 208 //writeRegPair(ETXSTL, TXSTART_INIT);
cassyarduino 0:e3fb1267e3c3 209 // TX end
cassyarduino 0:e3fb1267e3c3 210 //writeRegPair(ETXNDL, TXSTOP_INIT);
cassyarduino 0:e3fb1267e3c3 211 // do bank 1 stuff, packet filter:
cassyarduino 0:e3fb1267e3c3 212 // For broadcast packets we allow only ARP packtets
cassyarduino 0:e3fb1267e3c3 213 // All other packets should be unicast only for our mac (MAADR)
cassyarduino 0:e3fb1267e3c3 214 //
cassyarduino 0:e3fb1267e3c3 215 // The pattern to match on is therefore
cassyarduino 0:e3fb1267e3c3 216 // Type ETH.DST
cassyarduino 0:e3fb1267e3c3 217 // ARP BROADCAST
cassyarduino 0:e3fb1267e3c3 218 // 06 08 -- ff ff ff ff ff ff -> ip checksum for theses bytes=f7f9
cassyarduino 0:e3fb1267e3c3 219 // in binary these poitions are:11 0000 0011 1111
cassyarduino 0:e3fb1267e3c3 220 // This is hex 303F->EPMM0=0x3f,EPMM1=0x30
cassyarduino 0:e3fb1267e3c3 221 //TODO define specific pattern to receive dhcp-broadcast packages instead of setting ERFCON_BCEN!
cassyarduino 0:e3fb1267e3c3 222 // enableBroadcast(); // change to add ERXFCON_BCEN recommended by epam
cassyarduino 0:e3fb1267e3c3 223 writeReg(ERXFCON, ERXFCON_UCEN|ERXFCON_CRCEN|ERXFCON_PMEN|ERXFCON_BCEN);
cassyarduino 0:e3fb1267e3c3 224 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 225 LogObject.uart_send_strln(F("ENC28J60::init DEBUG_V3:After writeReg(ERXFCON, ERXFCON_UCEN|ERXFCON_CRCEN|ERXFCON_PMEN|ERXFCON_BCEN)"));
cassyarduino 0:e3fb1267e3c3 226 #endif
cassyarduino 0:e3fb1267e3c3 227 writeRegPair(EPMM0, 0x303f);
cassyarduino 0:e3fb1267e3c3 228 writeRegPair(EPMCSL, 0xf7f9);
cassyarduino 0:e3fb1267e3c3 229 //
cassyarduino 0:e3fb1267e3c3 230 //
cassyarduino 0:e3fb1267e3c3 231 // do bank 2 stuff
cassyarduino 0:e3fb1267e3c3 232 // enable MAC receive
cassyarduino 0:e3fb1267e3c3 233 // and bring MAC out of reset (writes 0x00 to MACON2)
cassyarduino 0:e3fb1267e3c3 234 writeRegPair(MACON1, MACON1_MARXEN|MACON1_TXPAUS|MACON1_RXPAUS);
cassyarduino 0:e3fb1267e3c3 235 // enable automatic padding to 60bytes and CRC operations
cassyarduino 0:e3fb1267e3c3 236 writeOp(ENC28J60_BIT_FIELD_SET, MACON3, MACON3_PADCFG0|MACON3_TXCRCEN|MACON3_FRMLNEN);
cassyarduino 0:e3fb1267e3c3 237 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 238 LogObject.uart_send_strln(F("ENC28J60::init DEBUG_V3:After writeOp(ENC28J60_BIT_FIELD_SET, MACON3, MACON3_PADCFG0|MACON3_TXCRCEN|MACON3_FRMLNEN)"));
cassyarduino 0:e3fb1267e3c3 239 #endif
cassyarduino 0:e3fb1267e3c3 240 // set inter-frame gap (non-back-to-back)
cassyarduino 0:e3fb1267e3c3 241 writeRegPair(MAIPGL, 0x0C12);
cassyarduino 0:e3fb1267e3c3 242 // set inter-frame gap (back-to-back)
cassyarduino 0:e3fb1267e3c3 243 writeReg(MABBIPG, 0x12);
cassyarduino 0:e3fb1267e3c3 244 // Set the maximum packet size which the controller will accept
cassyarduino 0:e3fb1267e3c3 245 // Do not send packets longer than MAX_FRAMELEN:
cassyarduino 0:e3fb1267e3c3 246 writeRegPair(MAMXFLL, MAX_FRAMELEN);
cassyarduino 0:e3fb1267e3c3 247 // do bank 3 stuff
cassyarduino 0:e3fb1267e3c3 248 // write MAC address
cassyarduino 0:e3fb1267e3c3 249 // NOTE: MAC address in ENC28J60 is byte-backward
cassyarduino 0:e3fb1267e3c3 250 writeReg(MAADR5, macaddr[0]);
cassyarduino 0:e3fb1267e3c3 251 writeReg(MAADR4, macaddr[1]);
cassyarduino 0:e3fb1267e3c3 252 writeReg(MAADR3, macaddr[2]);
cassyarduino 0:e3fb1267e3c3 253 writeReg(MAADR2, macaddr[3]);
cassyarduino 0:e3fb1267e3c3 254 writeReg(MAADR1, macaddr[4]);
cassyarduino 0:e3fb1267e3c3 255 writeReg(MAADR0, macaddr[5]);
cassyarduino 0:e3fb1267e3c3 256 // no loopback of transmitted frames
cassyarduino 0:e3fb1267e3c3 257 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 258 LogObject.uart_send_strln(F("ENC28J60::init DEBUG_V3:Before phyWrite(PHCON2, PHCON2_HDLDIS)"));
cassyarduino 0:e3fb1267e3c3 259 #endif
cassyarduino 0:e3fb1267e3c3 260 phyWrite(PHCON2, PHCON2_HDLDIS);
cassyarduino 0:e3fb1267e3c3 261 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 262 LogObject.uart_send_strln(F("ENC28J60::init DEBUG_V3:After phyWrite(PHCON2, PHCON2_HDLDIS)"));
cassyarduino 0:e3fb1267e3c3 263 #endif
cassyarduino 0:e3fb1267e3c3 264 // switch to bank 0
cassyarduino 0:e3fb1267e3c3 265 setBank(ECON1);
cassyarduino 0:e3fb1267e3c3 266 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 267 LogObject.uart_send_strln(F("ENC28J60::init DEBUG_V3:After setBank(ECON1)"));
cassyarduino 0:e3fb1267e3c3 268 #endif
cassyarduino 0:e3fb1267e3c3 269 // enable interrutps
cassyarduino 0:e3fb1267e3c3 270 writeOp(ENC28J60_BIT_FIELD_SET, EIE, EIE_INTIE|EIE_PKTIE);
cassyarduino 0:e3fb1267e3c3 271 // enable packet reception
cassyarduino 0:e3fb1267e3c3 272 writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
cassyarduino 0:e3fb1267e3c3 273 //Configure leds
cassyarduino 0:e3fb1267e3c3 274 phyWrite(PHLCON,0x476);
cassyarduino 0:e3fb1267e3c3 275
cassyarduino 0:e3fb1267e3c3 276 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 277 LogObject.uart_send_strln(F("ENC28J60::init DEBUG_V3:Before readReg(EREVID);"));
cassyarduino 0:e3fb1267e3c3 278 #endif
cassyarduino 0:e3fb1267e3c3 279 erevid=readReg(EREVID);
cassyarduino 0:e3fb1267e3c3 280 if (erevid==0xFF) {erevid=0;}
cassyarduino 0:e3fb1267e3c3 281 // microchip forgot to step the number on the silcon when they
cassyarduino 0:e3fb1267e3c3 282 // released the revision B7. 6 is now rev B7. We still have
cassyarduino 0:e3fb1267e3c3 283 // to see what they do when they release B8. At the moment
cassyarduino 0:e3fb1267e3c3 284 // there is no B8 out yet
cassyarduino 0:e3fb1267e3c3 285 //if (erevid > 5) ++erevid;
cassyarduino 0:e3fb1267e3c3 286 #if ACTLOGLEVEL>=LOG_INFO
cassyarduino 0:e3fb1267e3c3 287 LogObject.uart_send_str(F("ENC28J60::init INFO: Chip erevid="));
cassyarduino 0:e3fb1267e3c3 288 LogObject.uart_send_dec(erevid);
cassyarduino 0:e3fb1267e3c3 289 LogObject.uart_send_strln(F(" initialization completed."));
cassyarduino 0:e3fb1267e3c3 290 #endif
cassyarduino 0:e3fb1267e3c3 291
cassyarduino 0:e3fb1267e3c3 292 // return Enc28J60Network::erevid;
cassyarduino 0:e3fb1267e3c3 293 }
cassyarduino 0:e3fb1267e3c3 294
cassyarduino 0:e3fb1267e3c3 295 memhandle
cassyarduino 0:e3fb1267e3c3 296 Enc28J60Network::receivePacket(void)
cassyarduino 0:e3fb1267e3c3 297 {
cassyarduino 0:e3fb1267e3c3 298 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 299 LogObject.uart_send_strln(F("Enc28J60Network::receivePacket(void) DEBUG_V3:Function started"));
cassyarduino 0:e3fb1267e3c3 300 #endif
cassyarduino 0:e3fb1267e3c3 301 #if defined(ESP8266)
cassyarduino 0:e3fb1267e3c3 302 wdt_reset();
cassyarduino 0:e3fb1267e3c3 303 #endif
cassyarduino 0:e3fb1267e3c3 304 uint8_t rxstat;
cassyarduino 0:e3fb1267e3c3 305 uint16_t len;
cassyarduino 0:e3fb1267e3c3 306 // check if a packet has been received and buffered
cassyarduino 0:e3fb1267e3c3 307 //if( !(readReg(EIR) & EIR_PKTIF) ){
cassyarduino 0:e3fb1267e3c3 308 // The above does not work. See Rev. B4 Silicon Errata point 6.
cassyarduino 0:e3fb1267e3c3 309 #if ACTLOGLEVEL>=LOG_ERR
cassyarduino 0:e3fb1267e3c3 310 if (erevid==0)
cassyarduino 0:e3fb1267e3c3 311 {
cassyarduino 0:e3fb1267e3c3 312 LogObject.uart_send_strln(F("Enc28J60Network::receivePacket(void) ERROR:ENC28j50 Device not found !!! Bypass receivePacket function !!!"));
cassyarduino 0:e3fb1267e3c3 313 }
cassyarduino 0:e3fb1267e3c3 314 #endif
cassyarduino 0:e3fb1267e3c3 315 uint8_t epktcnt=readReg(EPKTCNT);
cassyarduino 16:66225c1d660c 316 if ((erevid!=0) && (epktcnt!=0))
cassyarduino 0:e3fb1267e3c3 317 {
cassyarduino 0:e3fb1267e3c3 318 uint16_t readPtr = nextPacketPtr+6 > RXSTOP_INIT ? nextPacketPtr+6-RXSTOP_INIT+RXSTART_INIT : nextPacketPtr+6;
cassyarduino 0:e3fb1267e3c3 319 // Set the read pointer to the start of the received packet
cassyarduino 0:e3fb1267e3c3 320 writeRegPair(ERDPTL, nextPacketPtr);
cassyarduino 0:e3fb1267e3c3 321 // read the next packet pointer
cassyarduino 0:e3fb1267e3c3 322 nextPacketPtr = readOp(ENC28J60_READ_BUF_MEM, 0);
cassyarduino 0:e3fb1267e3c3 323 nextPacketPtr |= readOp(ENC28J60_READ_BUF_MEM, 0) << 8;
cassyarduino 0:e3fb1267e3c3 324 // read the packet length (see datasheet page 43)
cassyarduino 0:e3fb1267e3c3 325 len = readOp(ENC28J60_READ_BUF_MEM, 0);
cassyarduino 0:e3fb1267e3c3 326 len |= readOp(ENC28J60_READ_BUF_MEM, 0) << 8;
cassyarduino 0:e3fb1267e3c3 327 len -= 4; //remove the CRC count
cassyarduino 0:e3fb1267e3c3 328 // read the receive status (see datasheet page 43)
cassyarduino 0:e3fb1267e3c3 329 rxstat = readOp(ENC28J60_READ_BUF_MEM, 0);
cassyarduino 0:e3fb1267e3c3 330 //rxstat |= readOp(ENC28J60_READ_BUF_MEM, 0) << 8;
cassyarduino 0:e3fb1267e3c3 331 #if ACTLOGLEVEL>=LOG_DEBUG
cassyarduino 0:e3fb1267e3c3 332 LogObject.uart_send_str(F("Enc28J60Network::receivePacket(void) DEBUG:receivePacket ["));
cassyarduino 0:e3fb1267e3c3 333 LogObject.uart_send_hex(readPtr);
cassyarduino 0:e3fb1267e3c3 334 LogObject.uart_send_str(F("-"));
cassyarduino 0:e3fb1267e3c3 335 LogObject.uart_send_hex((readPtr+len) % (RXSTOP_INIT+1));
cassyarduino 0:e3fb1267e3c3 336 LogObject.uart_send_str(F("], next: "));
cassyarduino 0:e3fb1267e3c3 337 LogObject.uart_send_hex(nextPacketPtr);
cassyarduino 0:e3fb1267e3c3 338 LogObject.uart_send_str(F(", stat: "));
cassyarduino 0:e3fb1267e3c3 339 LogObject.uart_send_hex(rxstat);
cassyarduino 0:e3fb1267e3c3 340 LogObject.uart_send_str(F(", Packet count: "));
cassyarduino 0:e3fb1267e3c3 341 LogObject.uart_send_dec(epktcnt);
cassyarduino 0:e3fb1267e3c3 342 LogObject.uart_send_str(F(" -> "));
cassyarduino 0:e3fb1267e3c3 343 LogObject.uart_send_strln((rxstat & 0x80)!=0 ? "OK" : "failed");
cassyarduino 0:e3fb1267e3c3 344 #endif
cassyarduino 0:e3fb1267e3c3 345 // decrement the packet counter indicate we are done with this packet
cassyarduino 0:e3fb1267e3c3 346 writeOp(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_PKTDEC);
cassyarduino 0:e3fb1267e3c3 347 // check CRC and symbol errors (see datasheet page 44, table 7-3):
cassyarduino 0:e3fb1267e3c3 348 // The ERXFCON.CRCEN is set by default. Normally we should not
cassyarduino 0:e3fb1267e3c3 349 // need to check this.
cassyarduino 0:e3fb1267e3c3 350 if (((rxstat & 0x80) != 0) && (nextPacketPtr<=RXSTOP_INIT))
cassyarduino 0:e3fb1267e3c3 351 {
cassyarduino 0:e3fb1267e3c3 352 receivePkt.begin = readPtr;
cassyarduino 0:e3fb1267e3c3 353 receivePkt.size = len;
cassyarduino 0:e3fb1267e3c3 354 #if ACTLOGLEVEL>=LOG_DEBUG
cassyarduino 0:e3fb1267e3c3 355 LogObject.uart_send_str(F("Enc28J60Network::receivePacket(void) DEBUG: rxstat OK. receivePkt.size="));
cassyarduino 0:e3fb1267e3c3 356 LogObject.uart_send_decln(len);
cassyarduino 0:e3fb1267e3c3 357 #endif
cassyarduino 0:e3fb1267e3c3 358 return UIP_RECEIVEBUFFERHANDLE;
cassyarduino 0:e3fb1267e3c3 359 }
cassyarduino 0:e3fb1267e3c3 360 // Move the RX read pointer to the start of the next received packet
cassyarduino 0:e3fb1267e3c3 361 // This frees the memory we just read out
cassyarduino 0:e3fb1267e3c3 362 setERXRDPT();
cassyarduino 0:e3fb1267e3c3 363 }
cassyarduino 0:e3fb1267e3c3 364 return (NOBLOCK);
cassyarduino 0:e3fb1267e3c3 365 }
cassyarduino 0:e3fb1267e3c3 366
cassyarduino 0:e3fb1267e3c3 367 void
cassyarduino 0:e3fb1267e3c3 368 Enc28J60Network::setERXRDPT(void)
cassyarduino 0:e3fb1267e3c3 369 {
cassyarduino 0:e3fb1267e3c3 370 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 371 LogObject.uart_send_strln(F("Enc28J60Network::setERXRDPT(void) DEBUG_V3:Function started"));
cassyarduino 0:e3fb1267e3c3 372 #endif
cassyarduino 0:e3fb1267e3c3 373 nextPacketPtr == RXSTART_INIT ? RXSTOP_INIT : nextPacketPtr-1;
cassyarduino 0:e3fb1267e3c3 374 if (nextPacketPtr>RXSTOP_INIT) {nextPacketPtr=RXSTART_INIT;}
cassyarduino 0:e3fb1267e3c3 375 if ((nextPacketPtr&1)!=0) {nextPacketPtr--;}
cassyarduino 16:66225c1d660c 376 #if ACTLOGLEVEL>=LOG_DEBUG
cassyarduino 0:e3fb1267e3c3 377 LogObject.uart_send_str(F("Enc28J60Network::setERXRDPT(void) DEBUG:Set nextPacketPtr:"));
cassyarduino 0:e3fb1267e3c3 378 LogObject.uart_send_hexln(nextPacketPtr);
cassyarduino 0:e3fb1267e3c3 379 #endif
cassyarduino 0:e3fb1267e3c3 380 writeRegPair(ERXRDPTL, nextPacketPtr);
cassyarduino 0:e3fb1267e3c3 381 }
cassyarduino 0:e3fb1267e3c3 382
cassyarduino 0:e3fb1267e3c3 383 memaddress
cassyarduino 0:e3fb1267e3c3 384 Enc28J60Network::blockSize(memhandle handle)
cassyarduino 0:e3fb1267e3c3 385 {
cassyarduino 0:e3fb1267e3c3 386 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 387 LogObject.uart_send_strln(F("Enc28J60Network::blockSize(memhandle handle) DEBUG_V3:Function started"));
cassyarduino 0:e3fb1267e3c3 388 #endif
cassyarduino 0:e3fb1267e3c3 389 return ((handle == NOBLOCK) || (erevid==0)) ? 0 : handle == UIP_RECEIVEBUFFERHANDLE ? receivePkt.size : blocks[handle].size;
cassyarduino 0:e3fb1267e3c3 390 }
cassyarduino 0:e3fb1267e3c3 391
cassyarduino 0:e3fb1267e3c3 392 void
cassyarduino 0:e3fb1267e3c3 393 Enc28J60Network::sendPacket(memhandle handle)
cassyarduino 0:e3fb1267e3c3 394 {
cassyarduino 0:e3fb1267e3c3 395 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 396 LogObject.uart_send_strln(F("Enc28J60Network::sendPacket(memhandle handle) INFO:Function started"));
cassyarduino 0:e3fb1267e3c3 397 #endif
cassyarduino 0:e3fb1267e3c3 398 #if defined(ESP8266)
cassyarduino 0:e3fb1267e3c3 399 wdt_reset();
cassyarduino 0:e3fb1267e3c3 400 #endif
cassyarduino 0:e3fb1267e3c3 401 memblock *packet = &blocks[handle];
cassyarduino 0:e3fb1267e3c3 402 uint16_t start = packet->begin-1;
cassyarduino 0:e3fb1267e3c3 403 uint16_t end = start + packet->size;
cassyarduino 0:e3fb1267e3c3 404
cassyarduino 0:e3fb1267e3c3 405 // backup data at control-byte position
cassyarduino 0:e3fb1267e3c3 406 uint8_t data = readByte(start);
cassyarduino 0:e3fb1267e3c3 407 // write control-byte (if not 0 anyway)
cassyarduino 0:e3fb1267e3c3 408 if (data)
cassyarduino 0:e3fb1267e3c3 409 writeByte(start, 0);
cassyarduino 0:e3fb1267e3c3 410
cassyarduino 0:e3fb1267e3c3 411 #if ACTLOGLEVEL>=LOG_DEBUG
cassyarduino 0:e3fb1267e3c3 412 LogObject.uart_send_str(F("Enc28J60Network::sendPacket(memhandle handle) DEBUG:sendPacket("));
cassyarduino 0:e3fb1267e3c3 413 LogObject.uart_send_dec(handle);
cassyarduino 0:e3fb1267e3c3 414 LogObject.uart_send_str(F(") ["));
cassyarduino 0:e3fb1267e3c3 415 LogObject.uart_send_hex(start);
cassyarduino 0:e3fb1267e3c3 416 LogObject.uart_send_str(F("-"));
cassyarduino 0:e3fb1267e3c3 417 LogObject.uart_send_hex(end);
cassyarduino 0:e3fb1267e3c3 418 LogObject.uart_send_str(F("]: "));
cassyarduino 0:e3fb1267e3c3 419 for (uint16_t i=start; i<=end; i++)
cassyarduino 0:e3fb1267e3c3 420 {
cassyarduino 0:e3fb1267e3c3 421 LogObject.uart_send_hex(readByte(i));
cassyarduino 0:e3fb1267e3c3 422 LogObject.uart_send_str(F(" "));
cassyarduino 0:e3fb1267e3c3 423 }
cassyarduino 0:e3fb1267e3c3 424 LogObject.uart_send_strln(F(""));
cassyarduino 0:e3fb1267e3c3 425 #endif
cassyarduino 0:e3fb1267e3c3 426
cassyarduino 0:e3fb1267e3c3 427 // TX start
cassyarduino 0:e3fb1267e3c3 428 writeRegPair(ETXSTL, start);
cassyarduino 0:e3fb1267e3c3 429 // Set the TXND pointer to correspond to the packet size given
cassyarduino 0:e3fb1267e3c3 430 writeRegPair(ETXNDL, end);
cassyarduino 0:e3fb1267e3c3 431 // send the contents of the transmit buffer onto the network
cassyarduino 0:e3fb1267e3c3 432 writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRTS);
cassyarduino 0:e3fb1267e3c3 433 // Reset the transmit logic problem. See Rev. B4 Silicon Errata point 12.
cassyarduino 0:e3fb1267e3c3 434 if( (readReg(EIR) & EIR_TXERIF) )
cassyarduino 0:e3fb1267e3c3 435 {
cassyarduino 0:e3fb1267e3c3 436 writeOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRTS);
cassyarduino 0:e3fb1267e3c3 437 }
cassyarduino 0:e3fb1267e3c3 438
cassyarduino 0:e3fb1267e3c3 439 //restore data on control-byte position
cassyarduino 0:e3fb1267e3c3 440 if (data)
cassyarduino 0:e3fb1267e3c3 441 writeByte(start, data);
cassyarduino 0:e3fb1267e3c3 442 }
cassyarduino 0:e3fb1267e3c3 443
cassyarduino 0:e3fb1267e3c3 444 uint16_t
cassyarduino 0:e3fb1267e3c3 445 Enc28J60Network::setReadPtr(memhandle handle, memaddress position, uint16_t len)
cassyarduino 0:e3fb1267e3c3 446 {
cassyarduino 0:e3fb1267e3c3 447 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 448 LogObject.uart_send_strln(F("Enc28J60Network::setReadPtr(memhandle handle, memaddress position, uint16_t len) DEBUG_V3:Function started"));
cassyarduino 0:e3fb1267e3c3 449 #endif
cassyarduino 0:e3fb1267e3c3 450 memblock *packet = handle == UIP_RECEIVEBUFFERHANDLE ? &receivePkt : &blocks[handle];
cassyarduino 0:e3fb1267e3c3 451 memaddress start = handle == UIP_RECEIVEBUFFERHANDLE && packet->begin + position > RXSTOP_INIT ? packet->begin + position-RXSTOP_INIT+RXSTART_INIT : packet->begin + position;
cassyarduino 0:e3fb1267e3c3 452
cassyarduino 0:e3fb1267e3c3 453 writeRegPair(ERDPTL, start);
cassyarduino 0:e3fb1267e3c3 454
cassyarduino 0:e3fb1267e3c3 455 if (len > packet->size - position)
cassyarduino 0:e3fb1267e3c3 456 len = packet->size - position;
cassyarduino 0:e3fb1267e3c3 457 return len;
cassyarduino 0:e3fb1267e3c3 458 }
cassyarduino 0:e3fb1267e3c3 459
cassyarduino 0:e3fb1267e3c3 460 uint16_t
cassyarduino 0:e3fb1267e3c3 461 Enc28J60Network::readPacket(memhandle handle, memaddress position, uint8_t* buffer, uint16_t len)
cassyarduino 0:e3fb1267e3c3 462 {
cassyarduino 0:e3fb1267e3c3 463 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 464 LogObject.uart_send_strln(F("Enc28J60Network::readPacket(memhandle handle, memaddress position, uint8_t* buffer, uint16_t len) DEBUG_V3:Function started"));
cassyarduino 0:e3fb1267e3c3 465 #endif
cassyarduino 0:e3fb1267e3c3 466 #if defined(ESP8266)
cassyarduino 0:e3fb1267e3c3 467 wdt_reset();
cassyarduino 0:e3fb1267e3c3 468 #endif
cassyarduino 0:e3fb1267e3c3 469 len = setReadPtr(handle, position, len);
cassyarduino 0:e3fb1267e3c3 470 readBuffer(len, buffer);
cassyarduino 0:e3fb1267e3c3 471 return len;
cassyarduino 0:e3fb1267e3c3 472 }
cassyarduino 0:e3fb1267e3c3 473
cassyarduino 0:e3fb1267e3c3 474 uint16_t
cassyarduino 0:e3fb1267e3c3 475 Enc28J60Network::writePacket(memhandle handle, memaddress position, uint8_t* buffer, uint16_t len)
cassyarduino 0:e3fb1267e3c3 476 {
cassyarduino 0:e3fb1267e3c3 477 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 478 LogObject.uart_send_str(F("Enc28J60Network::writePacket(memhandle handle, memaddress position, uint8_t* buffer, uint16_t len) DEBUG_V3:Function started with len:"));
cassyarduino 0:e3fb1267e3c3 479 LogObject.uart_send_decln(len);
cassyarduino 0:e3fb1267e3c3 480 #endif
cassyarduino 0:e3fb1267e3c3 481 #if defined(ESP8266)
cassyarduino 0:e3fb1267e3c3 482 wdt_reset();
cassyarduino 0:e3fb1267e3c3 483 #endif
cassyarduino 0:e3fb1267e3c3 484 memblock *packet = &blocks[handle];
cassyarduino 0:e3fb1267e3c3 485 uint16_t start = packet->begin + position;
cassyarduino 0:e3fb1267e3c3 486
cassyarduino 0:e3fb1267e3c3 487 writeRegPair(EWRPTL, start);
cassyarduino 0:e3fb1267e3c3 488
cassyarduino 0:e3fb1267e3c3 489 if (len > packet->size - position)
cassyarduino 0:e3fb1267e3c3 490 len = packet->size - position;
cassyarduino 0:e3fb1267e3c3 491 writeBuffer(len, buffer);
cassyarduino 0:e3fb1267e3c3 492 return len;
cassyarduino 0:e3fb1267e3c3 493 }
cassyarduino 0:e3fb1267e3c3 494
cassyarduino 0:e3fb1267e3c3 495
cassyarduino 0:e3fb1267e3c3 496 void Enc28J60Network::enableBroadcast (bool temporary) {
cassyarduino 0:e3fb1267e3c3 497 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 498 LogObject.uart_send_strln(F("Enc28J60Network::enableBroadcast (bool temporary) DEBUG_V3:Function started"));
cassyarduino 0:e3fb1267e3c3 499 #endif
cassyarduino 0:e3fb1267e3c3 500 writeRegByte(ERXFCON, readRegByte(ERXFCON) | ERXFCON_BCEN);
cassyarduino 0:e3fb1267e3c3 501 if(!temporary)
cassyarduino 0:e3fb1267e3c3 502 broadcast_enabled = true;
cassyarduino 0:e3fb1267e3c3 503 }
cassyarduino 0:e3fb1267e3c3 504
cassyarduino 0:e3fb1267e3c3 505 void Enc28J60Network::disableBroadcast (bool temporary) {
cassyarduino 0:e3fb1267e3c3 506 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 507 LogObject.uart_send_strln(F("Enc28J60Network::disableBroadcast (bool temporary) DEBUG_V3:Function started"));
cassyarduino 0:e3fb1267e3c3 508 #endif
cassyarduino 0:e3fb1267e3c3 509 if(!temporary)
cassyarduino 0:e3fb1267e3c3 510 broadcast_enabled = false;
cassyarduino 0:e3fb1267e3c3 511 if(!broadcast_enabled)
cassyarduino 0:e3fb1267e3c3 512 writeRegByte(ERXFCON, readRegByte(ERXFCON) & ~ERXFCON_BCEN);
cassyarduino 0:e3fb1267e3c3 513 }
cassyarduino 0:e3fb1267e3c3 514
cassyarduino 0:e3fb1267e3c3 515 void Enc28J60Network::enableMulticast (void) {
cassyarduino 0:e3fb1267e3c3 516 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 517 LogObject.uart_send_strln(F("Enc28J60Network::enableMulticast (void) DEBUG_V3:Function started"));
cassyarduino 0:e3fb1267e3c3 518 #endif
cassyarduino 0:e3fb1267e3c3 519 writeRegByte(ERXFCON, readRegByte(ERXFCON) | ERXFCON_MCEN);
cassyarduino 0:e3fb1267e3c3 520 }
cassyarduino 0:e3fb1267e3c3 521
cassyarduino 0:e3fb1267e3c3 522 void Enc28J60Network::disableMulticast (void) {
cassyarduino 0:e3fb1267e3c3 523 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 524 LogObject.uart_send_strln(F("Enc28J60Network::disableMulticast (void) DEBUG_V3:Function started"));
cassyarduino 0:e3fb1267e3c3 525 #endif
cassyarduino 0:e3fb1267e3c3 526 writeRegByte(ERXFCON, readRegByte(ERXFCON) & ~ERXFCON_MCEN);
cassyarduino 0:e3fb1267e3c3 527 }
cassyarduino 0:e3fb1267e3c3 528
cassyarduino 0:e3fb1267e3c3 529 uint8_t Enc28J60Network::readRegByte (uint8_t address) {
cassyarduino 0:e3fb1267e3c3 530 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 531 LogObject.uart_send_strln(F("Enc28J60Network::readRegByte (uint8_t address) DEBUG_V3:Function started"));
cassyarduino 0:e3fb1267e3c3 532 #endif
cassyarduino 0:e3fb1267e3c3 533 setBank(address);
cassyarduino 0:e3fb1267e3c3 534 return readOp(ENC28J60_READ_CTRL_REG, address);
cassyarduino 0:e3fb1267e3c3 535 }
cassyarduino 0:e3fb1267e3c3 536
cassyarduino 0:e3fb1267e3c3 537 void Enc28J60Network::writeRegByte (uint8_t address, uint8_t data) {
cassyarduino 0:e3fb1267e3c3 538 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 539 LogObject.uart_send_strln(F("Enc28J60Network::writeRegByte (uint8_t address, uint8_t data) DEBUG_V3:Function started"));
cassyarduino 0:e3fb1267e3c3 540 #endif
cassyarduino 0:e3fb1267e3c3 541 setBank(address);
cassyarduino 0:e3fb1267e3c3 542 writeOp(ENC28J60_WRITE_CTRL_REG, address, data);
cassyarduino 0:e3fb1267e3c3 543 }
cassyarduino 0:e3fb1267e3c3 544
cassyarduino 0:e3fb1267e3c3 545
cassyarduino 0:e3fb1267e3c3 546 uint8_t Enc28J60Network::readByte(uint16_t addr)
cassyarduino 0:e3fb1267e3c3 547 {
cassyarduino 0:e3fb1267e3c3 548 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 549 LogObject.uart_send_strln(F("Enc28J60Network::readByte(uint16_t addr) DEBUG_V3:Function started"));
cassyarduino 0:e3fb1267e3c3 550 #endif
cassyarduino 0:e3fb1267e3c3 551 #if defined(ESP8266)
cassyarduino 0:e3fb1267e3c3 552 wdt_reset();
cassyarduino 0:e3fb1267e3c3 553 #endif
cassyarduino 0:e3fb1267e3c3 554 writeRegPair(ERDPTL, addr);
cassyarduino 0:e3fb1267e3c3 555
cassyarduino 0:e3fb1267e3c3 556 CSACTIVE;
cassyarduino 0:e3fb1267e3c3 557 #if ENC28J60_USE_SPILIB
cassyarduino 0:e3fb1267e3c3 558 // issue read command
cassyarduino 0:e3fb1267e3c3 559 #if defined(ARDUINO)
cassyarduino 0:e3fb1267e3c3 560 SPI.transfer(ENC28J60_READ_BUF_MEM);
cassyarduino 0:e3fb1267e3c3 561 // read data
cassyarduino 0:e3fb1267e3c3 562 uint8_t c = SPI.transfer(0x00);
cassyarduino 0:e3fb1267e3c3 563 #endif
cassyarduino 0:e3fb1267e3c3 564 #if defined(__MBED__)
cassyarduino 0:e3fb1267e3c3 565 _spi.write(ENC28J60_READ_BUF_MEM);
cassyarduino 0:e3fb1267e3c3 566 // read data
cassyarduino 0:e3fb1267e3c3 567 uint8_t c = _spi.write(0x00);
cassyarduino 0:e3fb1267e3c3 568 #endif
cassyarduino 0:e3fb1267e3c3 569 CSPASSIVE;
cassyarduino 0:e3fb1267e3c3 570 return (c);
cassyarduino 0:e3fb1267e3c3 571 #else
cassyarduino 0:e3fb1267e3c3 572 // issue read command
cassyarduino 0:e3fb1267e3c3 573 SPDR = ENC28J60_READ_BUF_MEM;
cassyarduino 0:e3fb1267e3c3 574 waitspi();
cassyarduino 0:e3fb1267e3c3 575 // read data
cassyarduino 0:e3fb1267e3c3 576 SPDR = 0x00;
cassyarduino 0:e3fb1267e3c3 577 waitspi();
cassyarduino 0:e3fb1267e3c3 578 CSPASSIVE;
cassyarduino 0:e3fb1267e3c3 579 return (SPDR);
cassyarduino 0:e3fb1267e3c3 580 #endif
cassyarduino 0:e3fb1267e3c3 581 }
cassyarduino 0:e3fb1267e3c3 582
cassyarduino 0:e3fb1267e3c3 583 void Enc28J60Network::writeByte(uint16_t addr, uint8_t data)
cassyarduino 0:e3fb1267e3c3 584 {
cassyarduino 0:e3fb1267e3c3 585 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 586 LogObject.uart_send_strln(F("Enc28J60Network::writeByte(uint16_t addr, uint8_t data) DEBUG_V3:Function started"));
cassyarduino 0:e3fb1267e3c3 587 #endif
cassyarduino 0:e3fb1267e3c3 588 #if defined(ESP8266)
cassyarduino 0:e3fb1267e3c3 589 wdt_reset();
cassyarduino 0:e3fb1267e3c3 590 #endif
cassyarduino 0:e3fb1267e3c3 591 writeRegPair(EWRPTL, addr);
cassyarduino 0:e3fb1267e3c3 592
cassyarduino 0:e3fb1267e3c3 593 CSACTIVE;
cassyarduino 0:e3fb1267e3c3 594 #if ENC28J60_USE_SPILIB
cassyarduino 0:e3fb1267e3c3 595 // issue write command
cassyarduino 0:e3fb1267e3c3 596 #if defined(ARDUINO)
cassyarduino 0:e3fb1267e3c3 597 SPI.transfer(ENC28J60_WRITE_BUF_MEM);
cassyarduino 0:e3fb1267e3c3 598 // write data
cassyarduino 0:e3fb1267e3c3 599 SPI.transfer(data);
cassyarduino 0:e3fb1267e3c3 600 #endif
cassyarduino 0:e3fb1267e3c3 601 #if defined(__MBED__)
cassyarduino 0:e3fb1267e3c3 602 _spi.write(ENC28J60_WRITE_BUF_MEM);
cassyarduino 0:e3fb1267e3c3 603 // write data
cassyarduino 0:e3fb1267e3c3 604 _spi.write(data);
cassyarduino 0:e3fb1267e3c3 605 #endif
cassyarduino 0:e3fb1267e3c3 606 #else
cassyarduino 0:e3fb1267e3c3 607 // issue write command
cassyarduino 0:e3fb1267e3c3 608 SPDR = ENC28J60_WRITE_BUF_MEM;
cassyarduino 0:e3fb1267e3c3 609 waitspi();
cassyarduino 0:e3fb1267e3c3 610 // write data
cassyarduino 0:e3fb1267e3c3 611 SPDR = data;
cassyarduino 0:e3fb1267e3c3 612 waitspi();
cassyarduino 0:e3fb1267e3c3 613 #endif
cassyarduino 0:e3fb1267e3c3 614 CSPASSIVE;
cassyarduino 0:e3fb1267e3c3 615 }
cassyarduino 0:e3fb1267e3c3 616
cassyarduino 0:e3fb1267e3c3 617 void
cassyarduino 0:e3fb1267e3c3 618 Enc28J60Network::copyPacket(memhandle dest_pkt, memaddress dest_pos, memhandle src_pkt, memaddress src_pos, uint16_t len)
cassyarduino 0:e3fb1267e3c3 619 {
cassyarduino 0:e3fb1267e3c3 620 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 621 LogObject.uart_send_strln(F("Enc28J60Network::copyPacket(memhandle dest_pkt, memaddress dest_pos, memhandle src_pkt, memaddress src_pos, uint16_t len) DEBUG_V3:Function started"));
cassyarduino 0:e3fb1267e3c3 622 #endif
cassyarduino 0:e3fb1267e3c3 623 memblock *dest = &blocks[dest_pkt];
cassyarduino 0:e3fb1267e3c3 624 memblock *src = src_pkt == UIP_RECEIVEBUFFERHANDLE ? &receivePkt : &blocks[src_pkt];
cassyarduino 0:e3fb1267e3c3 625 memaddress start = src_pkt == UIP_RECEIVEBUFFERHANDLE && src->begin + src_pos > RXSTOP_INIT ? src->begin + src_pos-RXSTOP_INIT+RXSTART_INIT : src->begin + src_pos;
cassyarduino 0:e3fb1267e3c3 626 enc28J60_mempool_block_move_callback(dest->begin+dest_pos,start,len);
cassyarduino 0:e3fb1267e3c3 627 // Move the RX read pointer to the start of the next received packet
cassyarduino 0:e3fb1267e3c3 628 // This frees the memory we just read out
cassyarduino 0:e3fb1267e3c3 629 setERXRDPT();
cassyarduino 0:e3fb1267e3c3 630 }
cassyarduino 0:e3fb1267e3c3 631
cassyarduino 0:e3fb1267e3c3 632 void
cassyarduino 0:e3fb1267e3c3 633 enc28J60_mempool_block_move_callback(memaddress dest, memaddress src, memaddress len)
cassyarduino 0:e3fb1267e3c3 634 {
cassyarduino 0:e3fb1267e3c3 635 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 636 LogObject.uart_send_strln(F("enc28J60_mempool_block_move_callback(memaddress dest, memaddress src, memaddress len) DEBUG_V3:Function started"));
cassyarduino 0:e3fb1267e3c3 637 #endif
cassyarduino 0:e3fb1267e3c3 638 //void
cassyarduino 0:e3fb1267e3c3 639 //Enc28J60Network::memblock_mv_cb(uint16_t dest, uint16_t src, uint16_t len)
cassyarduino 0:e3fb1267e3c3 640 //{
cassyarduino 0:e3fb1267e3c3 641 //as ENC28J60 DMA is unable to copy single bytes:
cassyarduino 0:e3fb1267e3c3 642 if (len == 1)
cassyarduino 0:e3fb1267e3c3 643 {
cassyarduino 0:e3fb1267e3c3 644 Enc28J60Network::writeByte(dest,Enc28J60Network::readByte(src));
cassyarduino 0:e3fb1267e3c3 645 }
cassyarduino 0:e3fb1267e3c3 646 else
cassyarduino 0:e3fb1267e3c3 647 {
cassyarduino 0:e3fb1267e3c3 648 // calculate address of last byte
cassyarduino 0:e3fb1267e3c3 649 len += src - 1;
cassyarduino 0:e3fb1267e3c3 650
cassyarduino 0:e3fb1267e3c3 651 /* 1. Appropriately program the EDMAST, EDMAND
cassyarduino 0:e3fb1267e3c3 652 and EDMADST register pairs. The EDMAST
cassyarduino 0:e3fb1267e3c3 653 registers should point to the first byte to copy
cassyarduino 0:e3fb1267e3c3 654 from, the EDMAND registers should point to the
cassyarduino 0:e3fb1267e3c3 655 last byte to copy and the EDMADST registers
cassyarduino 0:e3fb1267e3c3 656 should point to the first byte in the destination
cassyarduino 0:e3fb1267e3c3 657 range. The destination range will always be
cassyarduino 0:e3fb1267e3c3 658 linear, never wrapping at any values except from
cassyarduino 0:e3fb1267e3c3 659 8191 to 0 (the 8-Kbyte memory boundary).
cassyarduino 0:e3fb1267e3c3 660 Extreme care should be taken when
cassyarduino 0:e3fb1267e3c3 661 programming the start and end pointers to
cassyarduino 0:e3fb1267e3c3 662 prevent a never ending DMA operation which
cassyarduino 0:e3fb1267e3c3 663 would overwrite the entire 8-Kbyte buffer.
cassyarduino 0:e3fb1267e3c3 664 */
cassyarduino 0:e3fb1267e3c3 665 Enc28J60Network::writeRegPair(EDMASTL, src);
cassyarduino 0:e3fb1267e3c3 666 Enc28J60Network::writeRegPair(EDMADSTL, dest);
cassyarduino 0:e3fb1267e3c3 667
cassyarduino 0:e3fb1267e3c3 668 if ((src <= RXSTOP_INIT)&& (len > RXSTOP_INIT))len -= (RXSTOP_INIT-RXSTART_INIT);
cassyarduino 0:e3fb1267e3c3 669 Enc28J60Network::writeRegPair(EDMANDL, len);
cassyarduino 0:e3fb1267e3c3 670
cassyarduino 0:e3fb1267e3c3 671 /*
cassyarduino 0:e3fb1267e3c3 672 2. If an interrupt at the end of the copy process is
cassyarduino 0:e3fb1267e3c3 673 desired, set EIE.DMAIE and EIE.INTIE and
cassyarduino 0:e3fb1267e3c3 674 clear EIR.DMAIF.
cassyarduino 0:e3fb1267e3c3 675
cassyarduino 0:e3fb1267e3c3 676 3. Verify that ECON1.CSUMEN is clear. */
cassyarduino 0:e3fb1267e3c3 677 Enc28J60Network::writeOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_CSUMEN);
cassyarduino 0:e3fb1267e3c3 678
cassyarduino 0:e3fb1267e3c3 679 /* 4. Start the DMA copy by setting ECON1.DMAST. */
cassyarduino 0:e3fb1267e3c3 680 Enc28J60Network::writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_DMAST);
cassyarduino 0:e3fb1267e3c3 681
cassyarduino 0:e3fb1267e3c3 682 // wait until runnig DMA is completed
cassyarduino 0:e3fb1267e3c3 683 while (Enc28J60Network::readOp(ENC28J60_READ_CTRL_REG, ECON1) & ECON1_DMAST)
cassyarduino 0:e3fb1267e3c3 684 {
cassyarduino 0:e3fb1267e3c3 685 delay(1);
cassyarduino 0:e3fb1267e3c3 686 }
cassyarduino 0:e3fb1267e3c3 687 }
cassyarduino 0:e3fb1267e3c3 688 }
cassyarduino 0:e3fb1267e3c3 689
cassyarduino 0:e3fb1267e3c3 690 void
cassyarduino 0:e3fb1267e3c3 691 Enc28J60Network::freePacket(void)
cassyarduino 0:e3fb1267e3c3 692 {
cassyarduino 0:e3fb1267e3c3 693 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 694 LogObject.uart_send_strln(F("Enc28J60Network::freePacket(void) DEBUG_V3:Function started"));
cassyarduino 0:e3fb1267e3c3 695 #endif
cassyarduino 0:e3fb1267e3c3 696 setERXRDPT();
cassyarduino 0:e3fb1267e3c3 697 }
cassyarduino 0:e3fb1267e3c3 698
cassyarduino 0:e3fb1267e3c3 699 uint8_t
cassyarduino 0:e3fb1267e3c3 700 Enc28J60Network::readOp(uint8_t op, uint8_t address)
cassyarduino 0:e3fb1267e3c3 701 {
cassyarduino 0:e3fb1267e3c3 702 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 703 LogObject.uart_send_strln(F("Enc28J60Network::readOp(uint8_t op, uint8_t address) DEBUG_V3:Function started"));
cassyarduino 0:e3fb1267e3c3 704 #endif
cassyarduino 0:e3fb1267e3c3 705 CSACTIVE;
cassyarduino 0:e3fb1267e3c3 706 // issue read command
cassyarduino 0:e3fb1267e3c3 707 #if ENC28J60_USE_SPILIB
cassyarduino 0:e3fb1267e3c3 708 #if defined(ARDUINO)
cassyarduino 0:e3fb1267e3c3 709 SPI.transfer(op | (address & ADDR_MASK));
cassyarduino 0:e3fb1267e3c3 710 // read data
cassyarduino 0:e3fb1267e3c3 711 if(address & 0x80)
cassyarduino 0:e3fb1267e3c3 712 {
cassyarduino 0:e3fb1267e3c3 713 // do dummy read if needed (for mac and mii, see datasheet page 29)
cassyarduino 0:e3fb1267e3c3 714 SPI.transfer(0x00);
cassyarduino 0:e3fb1267e3c3 715 }
cassyarduino 0:e3fb1267e3c3 716 uint8_t c = SPI.transfer(0x00);
cassyarduino 0:e3fb1267e3c3 717 #endif
cassyarduino 0:e3fb1267e3c3 718 #if defined(__MBED__)
cassyarduino 0:e3fb1267e3c3 719 _spi.write(op | (address & ADDR_MASK));
cassyarduino 0:e3fb1267e3c3 720 // read data
cassyarduino 0:e3fb1267e3c3 721 if(address & 0x80)
cassyarduino 0:e3fb1267e3c3 722 {
cassyarduino 0:e3fb1267e3c3 723 // do dummy read if needed (for mac and mii, see datasheet page 29)
cassyarduino 0:e3fb1267e3c3 724 _spi.write(0x00);
cassyarduino 0:e3fb1267e3c3 725 }
cassyarduino 0:e3fb1267e3c3 726 uint8_t c = _spi.write(0x00);
cassyarduino 0:e3fb1267e3c3 727 #endif
cassyarduino 0:e3fb1267e3c3 728 // release CS
cassyarduino 0:e3fb1267e3c3 729 CSPASSIVE;
cassyarduino 0:e3fb1267e3c3 730 return(c);
cassyarduino 0:e3fb1267e3c3 731 #else
cassyarduino 0:e3fb1267e3c3 732 // issue read command
cassyarduino 0:e3fb1267e3c3 733 SPDR = op | (address & ADDR_MASK);
cassyarduino 0:e3fb1267e3c3 734 waitspi();
cassyarduino 0:e3fb1267e3c3 735 // read data
cassyarduino 0:e3fb1267e3c3 736 SPDR = 0x00;
cassyarduino 0:e3fb1267e3c3 737 waitspi();
cassyarduino 0:e3fb1267e3c3 738 // do dummy read if needed (for mac and mii, see datasheet page 29)
cassyarduino 0:e3fb1267e3c3 739 if(address & 0x80)
cassyarduino 0:e3fb1267e3c3 740 {
cassyarduino 0:e3fb1267e3c3 741 SPDR = 0x00;
cassyarduino 0:e3fb1267e3c3 742 waitspi();
cassyarduino 0:e3fb1267e3c3 743 }
cassyarduino 0:e3fb1267e3c3 744 // release CS
cassyarduino 0:e3fb1267e3c3 745 CSPASSIVE;
cassyarduino 0:e3fb1267e3c3 746 return(SPDR);
cassyarduino 0:e3fb1267e3c3 747 #endif
cassyarduino 0:e3fb1267e3c3 748 }
cassyarduino 0:e3fb1267e3c3 749
cassyarduino 0:e3fb1267e3c3 750 void
cassyarduino 0:e3fb1267e3c3 751 Enc28J60Network::writeOp(uint8_t op, uint8_t address, uint8_t data)
cassyarduino 0:e3fb1267e3c3 752 {
cassyarduino 0:e3fb1267e3c3 753 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 754 LogObject.uart_send_strln(F("Enc28J60Network::writeOp(uint8_t op, uint8_t address, uint8_t data) DEBUG_V3:Function started"));
cassyarduino 0:e3fb1267e3c3 755 #endif
cassyarduino 0:e3fb1267e3c3 756 CSACTIVE;
cassyarduino 0:e3fb1267e3c3 757 // issue write command
cassyarduino 0:e3fb1267e3c3 758 #if ENC28J60_USE_SPILIB
cassyarduino 0:e3fb1267e3c3 759 #if defined(ARDUINO)
cassyarduino 0:e3fb1267e3c3 760 SPI.transfer(op | (address & ADDR_MASK));
cassyarduino 0:e3fb1267e3c3 761 // write data
cassyarduino 0:e3fb1267e3c3 762 SPI.transfer(data);
cassyarduino 0:e3fb1267e3c3 763 #endif
cassyarduino 0:e3fb1267e3c3 764 #if defined(__MBED__)
cassyarduino 0:e3fb1267e3c3 765 _spi.write(op | (address & ADDR_MASK));
cassyarduino 0:e3fb1267e3c3 766 // write data
cassyarduino 0:e3fb1267e3c3 767 _spi.write(data);
cassyarduino 0:e3fb1267e3c3 768 #endif
cassyarduino 0:e3fb1267e3c3 769 #else
cassyarduino 0:e3fb1267e3c3 770 // issue write command
cassyarduino 0:e3fb1267e3c3 771 SPDR = op | (address & ADDR_MASK);
cassyarduino 0:e3fb1267e3c3 772 waitspi();
cassyarduino 0:e3fb1267e3c3 773 // write data
cassyarduino 0:e3fb1267e3c3 774 SPDR = data;
cassyarduino 0:e3fb1267e3c3 775 waitspi();
cassyarduino 0:e3fb1267e3c3 776 #endif
cassyarduino 0:e3fb1267e3c3 777 CSPASSIVE;
cassyarduino 0:e3fb1267e3c3 778 }
cassyarduino 0:e3fb1267e3c3 779
cassyarduino 0:e3fb1267e3c3 780 void
cassyarduino 0:e3fb1267e3c3 781 Enc28J60Network::readBuffer(uint16_t len, uint8_t* data)
cassyarduino 0:e3fb1267e3c3 782 {
cassyarduino 0:e3fb1267e3c3 783 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 784 LogObject.uart_send_strln(F("Enc28J60Network::readBuffer(uint16_t len, uint8_t* data) DEBUG_V3:Function started"));
cassyarduino 0:e3fb1267e3c3 785 #endif
cassyarduino 0:e3fb1267e3c3 786 CSACTIVE;
cassyarduino 0:e3fb1267e3c3 787 // issue read command
cassyarduino 0:e3fb1267e3c3 788 #if ENC28J60_USE_SPILIB
cassyarduino 0:e3fb1267e3c3 789 #if defined(ARDUINO)
cassyarduino 0:e3fb1267e3c3 790 SPI.transfer(ENC28J60_READ_BUF_MEM);
cassyarduino 0:e3fb1267e3c3 791 #endif
cassyarduino 0:e3fb1267e3c3 792 #if defined(__MBED__)
cassyarduino 0:e3fb1267e3c3 793 _spi.write(ENC28J60_READ_BUF_MEM);
cassyarduino 0:e3fb1267e3c3 794 #endif
cassyarduino 0:e3fb1267e3c3 795 #else
cassyarduino 0:e3fb1267e3c3 796 SPDR = ENC28J60_READ_BUF_MEM;
cassyarduino 0:e3fb1267e3c3 797 waitspi();
cassyarduino 0:e3fb1267e3c3 798 #endif
cassyarduino 0:e3fb1267e3c3 799 while(len)
cassyarduino 0:e3fb1267e3c3 800 {
cassyarduino 0:e3fb1267e3c3 801 len--;
cassyarduino 0:e3fb1267e3c3 802 // read data
cassyarduino 0:e3fb1267e3c3 803 #if ENC28J60_USE_SPILIB
cassyarduino 0:e3fb1267e3c3 804 #if defined(ARDUINO)
cassyarduino 0:e3fb1267e3c3 805 *data = SPI.transfer(0x00);
cassyarduino 0:e3fb1267e3c3 806 #endif
cassyarduino 0:e3fb1267e3c3 807 #if defined(__MBED__)
cassyarduino 0:e3fb1267e3c3 808 *data = _spi.write(0x00);
cassyarduino 0:e3fb1267e3c3 809 #endif
cassyarduino 0:e3fb1267e3c3 810 #else
cassyarduino 0:e3fb1267e3c3 811 SPDR = 0x00;
cassyarduino 0:e3fb1267e3c3 812 waitspi();
cassyarduino 0:e3fb1267e3c3 813 *data = SPDR;
cassyarduino 0:e3fb1267e3c3 814 #endif
cassyarduino 0:e3fb1267e3c3 815 data++;
cassyarduino 0:e3fb1267e3c3 816 }
cassyarduino 0:e3fb1267e3c3 817 //*data='\0';
cassyarduino 0:e3fb1267e3c3 818 CSPASSIVE;
cassyarduino 0:e3fb1267e3c3 819 }
cassyarduino 0:e3fb1267e3c3 820
cassyarduino 0:e3fb1267e3c3 821 void
cassyarduino 0:e3fb1267e3c3 822 Enc28J60Network::writeBuffer(uint16_t len, uint8_t* data)
cassyarduino 0:e3fb1267e3c3 823 {
cassyarduino 0:e3fb1267e3c3 824 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 825 LogObject.uart_send_strln(F("Enc28J60Network::writeBuffer(uint16_t len, uint8_t* data) DEBUG_V3:Function started"));
cassyarduino 0:e3fb1267e3c3 826 #endif
cassyarduino 0:e3fb1267e3c3 827 CSACTIVE;
cassyarduino 0:e3fb1267e3c3 828 // issue write command
cassyarduino 0:e3fb1267e3c3 829 #if ENC28J60_USE_SPILIB
cassyarduino 0:e3fb1267e3c3 830 #if defined(ARDUINO)
cassyarduino 0:e3fb1267e3c3 831 SPI.transfer(ENC28J60_WRITE_BUF_MEM);
cassyarduino 0:e3fb1267e3c3 832 #endif
cassyarduino 0:e3fb1267e3c3 833 #if defined(__MBED__)
cassyarduino 0:e3fb1267e3c3 834 _spi.write(ENC28J60_WRITE_BUF_MEM);
cassyarduino 0:e3fb1267e3c3 835 #endif
cassyarduino 0:e3fb1267e3c3 836 #else
cassyarduino 0:e3fb1267e3c3 837 SPDR = ENC28J60_WRITE_BUF_MEM;
cassyarduino 0:e3fb1267e3c3 838 waitspi();
cassyarduino 0:e3fb1267e3c3 839 #endif
cassyarduino 0:e3fb1267e3c3 840 while(len)
cassyarduino 0:e3fb1267e3c3 841 {
cassyarduino 0:e3fb1267e3c3 842 len--;
cassyarduino 0:e3fb1267e3c3 843 // write data
cassyarduino 0:e3fb1267e3c3 844 #if ENC28J60_USE_SPILIB
cassyarduino 0:e3fb1267e3c3 845 #if defined(ARDUINO)
cassyarduino 0:e3fb1267e3c3 846 SPI.transfer(*data);
cassyarduino 0:e3fb1267e3c3 847 #endif
cassyarduino 0:e3fb1267e3c3 848 #if defined(__MBED__)
cassyarduino 0:e3fb1267e3c3 849 _spi.write(*data);
cassyarduino 0:e3fb1267e3c3 850 #endif
cassyarduino 0:e3fb1267e3c3 851 data++;
cassyarduino 0:e3fb1267e3c3 852 #else
cassyarduino 0:e3fb1267e3c3 853 SPDR = *data;
cassyarduino 0:e3fb1267e3c3 854 data++;
cassyarduino 0:e3fb1267e3c3 855 waitspi();
cassyarduino 0:e3fb1267e3c3 856 #endif
cassyarduino 0:e3fb1267e3c3 857 }
cassyarduino 0:e3fb1267e3c3 858 CSPASSIVE;
cassyarduino 0:e3fb1267e3c3 859 }
cassyarduino 0:e3fb1267e3c3 860
cassyarduino 0:e3fb1267e3c3 861 void
cassyarduino 0:e3fb1267e3c3 862 Enc28J60Network::setBank(uint8_t address)
cassyarduino 0:e3fb1267e3c3 863 {
cassyarduino 0:e3fb1267e3c3 864 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 865 LogObject.uart_send_strln(F("Enc28J60Network::setBank(uint8_t address) DEBUG_V3:Function started"));
cassyarduino 0:e3fb1267e3c3 866 #endif
cassyarduino 0:e3fb1267e3c3 867 // set the bank (if needed)
cassyarduino 0:e3fb1267e3c3 868 if((address & BANK_MASK) != bank)
cassyarduino 0:e3fb1267e3c3 869 {
cassyarduino 0:e3fb1267e3c3 870 // set the bank
cassyarduino 0:e3fb1267e3c3 871 writeOp(ENC28J60_BIT_FIELD_CLR, ECON1, (ECON1_BSEL1|ECON1_BSEL0));
cassyarduino 0:e3fb1267e3c3 872 writeOp(ENC28J60_BIT_FIELD_SET, ECON1, (address & BANK_MASK)>>5);
cassyarduino 0:e3fb1267e3c3 873 bank = (address & BANK_MASK);
cassyarduino 0:e3fb1267e3c3 874 }
cassyarduino 0:e3fb1267e3c3 875 }
cassyarduino 0:e3fb1267e3c3 876
cassyarduino 0:e3fb1267e3c3 877 uint8_t
cassyarduino 0:e3fb1267e3c3 878 Enc28J60Network::readReg(uint8_t address)
cassyarduino 0:e3fb1267e3c3 879 {
cassyarduino 0:e3fb1267e3c3 880 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 881 LogObject.uart_send_strln(F("Enc28J60Network::readReg(uint8_t address) DEBUG_V3:Function started"));
cassyarduino 0:e3fb1267e3c3 882 #endif
cassyarduino 0:e3fb1267e3c3 883 // set the bank
cassyarduino 0:e3fb1267e3c3 884 setBank(address);
cassyarduino 0:e3fb1267e3c3 885 // do the read
cassyarduino 0:e3fb1267e3c3 886 return readOp(ENC28J60_READ_CTRL_REG, address);
cassyarduino 0:e3fb1267e3c3 887 }
cassyarduino 0:e3fb1267e3c3 888
cassyarduino 0:e3fb1267e3c3 889 void
cassyarduino 0:e3fb1267e3c3 890 Enc28J60Network::writeReg(uint8_t address, uint8_t data)
cassyarduino 0:e3fb1267e3c3 891 {
cassyarduino 0:e3fb1267e3c3 892 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 893 LogObject.uart_send_strln(F("Enc28J60Network::writeReg(uint8_t address, uint8_t data) DEBUG_V3:Function started"));
cassyarduino 0:e3fb1267e3c3 894 #endif
cassyarduino 0:e3fb1267e3c3 895 // set the bank
cassyarduino 0:e3fb1267e3c3 896 setBank(address);
cassyarduino 0:e3fb1267e3c3 897 // do the write
cassyarduino 0:e3fb1267e3c3 898 writeOp(ENC28J60_WRITE_CTRL_REG, address, data);
cassyarduino 0:e3fb1267e3c3 899 }
cassyarduino 0:e3fb1267e3c3 900
cassyarduino 0:e3fb1267e3c3 901 void
cassyarduino 0:e3fb1267e3c3 902 Enc28J60Network::writeRegPair(uint8_t address, uint16_t data)
cassyarduino 0:e3fb1267e3c3 903 {
cassyarduino 0:e3fb1267e3c3 904 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 905 LogObject.uart_send_strln(F("Enc28J60Network::writeRegPair(uint8_t address, uint16_t data) DEBUG_V3:Function started"));
cassyarduino 0:e3fb1267e3c3 906 #endif
cassyarduino 0:e3fb1267e3c3 907 // set the bank
cassyarduino 0:e3fb1267e3c3 908 setBank(address);
cassyarduino 0:e3fb1267e3c3 909 // do the write
cassyarduino 0:e3fb1267e3c3 910 writeOp(ENC28J60_WRITE_CTRL_REG, address, (data&0xFF));
cassyarduino 0:e3fb1267e3c3 911 writeOp(ENC28J60_WRITE_CTRL_REG, address+1, (data) >> 8);
cassyarduino 0:e3fb1267e3c3 912 }
cassyarduino 0:e3fb1267e3c3 913
cassyarduino 0:e3fb1267e3c3 914 void
cassyarduino 0:e3fb1267e3c3 915 Enc28J60Network::phyWrite(uint8_t address, uint16_t data)
cassyarduino 0:e3fb1267e3c3 916 {
cassyarduino 0:e3fb1267e3c3 917 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 918 LogObject.uart_send_strln(F("Enc28J60Network::phyWrite(uint8_t address, uint16_t data) DEBUG_V3:Function started"));
cassyarduino 0:e3fb1267e3c3 919 #endif
cassyarduino 0:e3fb1267e3c3 920 unsigned int timeout = 15;
cassyarduino 0:e3fb1267e3c3 921 // set the PHY register address
cassyarduino 0:e3fb1267e3c3 922 writeReg(MIREGADR, address);
cassyarduino 0:e3fb1267e3c3 923 // write the PHY data
cassyarduino 0:e3fb1267e3c3 924 writeRegPair(MIWRL, data);
cassyarduino 0:e3fb1267e3c3 925 // wait until the PHY write completes
cassyarduino 0:e3fb1267e3c3 926 while (readReg(MISTAT) & MISTAT_BUSY)
cassyarduino 0:e3fb1267e3c3 927 {
cassyarduino 0:e3fb1267e3c3 928 delay(10);
cassyarduino 0:e3fb1267e3c3 929 #if defined(ESP8266)
cassyarduino 0:e3fb1267e3c3 930 wdt_reset();
cassyarduino 0:e3fb1267e3c3 931 #endif
cassyarduino 0:e3fb1267e3c3 932 if (--timeout == 0)
cassyarduino 0:e3fb1267e3c3 933 {
cassyarduino 0:e3fb1267e3c3 934 #if ACTLOGLEVEL>=LOG_ERR
cassyarduino 0:e3fb1267e3c3 935 LogObject.uart_send_strln(F("Enc28J60Network::phyWrite ERROR:TIMEOUT !!!"));
cassyarduino 0:e3fb1267e3c3 936 #endif
cassyarduino 0:e3fb1267e3c3 937 return;
cassyarduino 0:e3fb1267e3c3 938 }
cassyarduino 0:e3fb1267e3c3 939 }
cassyarduino 0:e3fb1267e3c3 940 }
cassyarduino 0:e3fb1267e3c3 941
cassyarduino 0:e3fb1267e3c3 942 uint16_t
cassyarduino 0:e3fb1267e3c3 943 Enc28J60Network::phyRead(uint8_t address)
cassyarduino 0:e3fb1267e3c3 944 {
cassyarduino 0:e3fb1267e3c3 945 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 946 LogObject.uart_send_strln(F("Enc28J60Network::phyRead(uint8_t address) DEBUG_V3:Function started"));
cassyarduino 0:e3fb1267e3c3 947 #endif
cassyarduino 0:e3fb1267e3c3 948 unsigned int timeout = 15;
cassyarduino 0:e3fb1267e3c3 949 writeReg(MIREGADR,address);
cassyarduino 0:e3fb1267e3c3 950 writeReg(MICMD, MICMD_MIIRD);
cassyarduino 0:e3fb1267e3c3 951 // wait until the PHY read completes
cassyarduino 0:e3fb1267e3c3 952 while(readReg(MISTAT) & MISTAT_BUSY)
cassyarduino 0:e3fb1267e3c3 953 {
cassyarduino 0:e3fb1267e3c3 954 delay(10);
cassyarduino 0:e3fb1267e3c3 955 #if defined(ESP8266)
cassyarduino 0:e3fb1267e3c3 956 wdt_reset();
cassyarduino 0:e3fb1267e3c3 957 #endif
cassyarduino 0:e3fb1267e3c3 958 if (--timeout == 0)
cassyarduino 0:e3fb1267e3c3 959 {
cassyarduino 0:e3fb1267e3c3 960 #if ACTLOGLEVEL>=LOG_ERR
cassyarduino 0:e3fb1267e3c3 961 LogObject.uart_send_strln(F("Enc28J60Network::phyRead ERROR:TIMEOUT !!!"));
cassyarduino 0:e3fb1267e3c3 962 #endif
cassyarduino 0:e3fb1267e3c3 963 return 0;
cassyarduino 0:e3fb1267e3c3 964 }
cassyarduino 0:e3fb1267e3c3 965 }
cassyarduino 0:e3fb1267e3c3 966 writeReg(MICMD, 0);
cassyarduino 0:e3fb1267e3c3 967 return (readReg(MIRDL) | readReg(MIRDH) << 8);
cassyarduino 0:e3fb1267e3c3 968 }
cassyarduino 0:e3fb1267e3c3 969
cassyarduino 0:e3fb1267e3c3 970 void
cassyarduino 0:e3fb1267e3c3 971 Enc28J60Network::clkout(uint8_t clk)
cassyarduino 0:e3fb1267e3c3 972 {
cassyarduino 0:e3fb1267e3c3 973 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 974 LogObject.uart_send_strln(F("Enc28J60Network::clkout(uint8_t clk) DEBUG_V3:Function started"));
cassyarduino 0:e3fb1267e3c3 975 #endif
cassyarduino 0:e3fb1267e3c3 976 //setup clkout: 2 is 12.5MHz:
cassyarduino 0:e3fb1267e3c3 977 writeReg(ECOCON, clk & 0x7);
cassyarduino 0:e3fb1267e3c3 978 }
cassyarduino 0:e3fb1267e3c3 979
cassyarduino 0:e3fb1267e3c3 980 uint16_t
cassyarduino 0:e3fb1267e3c3 981 Enc28J60Network::chksum(uint16_t sum, memhandle handle, memaddress pos, uint16_t len)
cassyarduino 0:e3fb1267e3c3 982 {
cassyarduino 0:e3fb1267e3c3 983 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 984 LogObject.uart_send_strln(F("Enc28J60Network::chksum(uint16_t sum, memhandle handle, memaddress pos, uint16_t len) DEBUG_V3:Function started"));
cassyarduino 0:e3fb1267e3c3 985 #endif
cassyarduino 0:e3fb1267e3c3 986 uint16_t t;
cassyarduino 0:e3fb1267e3c3 987 len = setReadPtr(handle, pos, len)-1;
cassyarduino 0:e3fb1267e3c3 988 CSACTIVE;
cassyarduino 0:e3fb1267e3c3 989 // issue read command
cassyarduino 0:e3fb1267e3c3 990 #if ENC28J60_USE_SPILIB
cassyarduino 0:e3fb1267e3c3 991 #if defined(ARDUINO)
cassyarduino 0:e3fb1267e3c3 992 SPI.transfer(ENC28J60_READ_BUF_MEM);
cassyarduino 0:e3fb1267e3c3 993 #endif
cassyarduino 0:e3fb1267e3c3 994 #if defined(__MBED__)
cassyarduino 0:e3fb1267e3c3 995 _spi.write(ENC28J60_READ_BUF_MEM);
cassyarduino 0:e3fb1267e3c3 996 #endif
cassyarduino 0:e3fb1267e3c3 997 #else
cassyarduino 0:e3fb1267e3c3 998 SPDR = ENC28J60_READ_BUF_MEM;
cassyarduino 0:e3fb1267e3c3 999 waitspi();
cassyarduino 0:e3fb1267e3c3 1000 #endif
cassyarduino 0:e3fb1267e3c3 1001 uint16_t i;
cassyarduino 0:e3fb1267e3c3 1002 for (i = 0; i < len; i+=2)
cassyarduino 0:e3fb1267e3c3 1003 {
cassyarduino 0:e3fb1267e3c3 1004 // read data
cassyarduino 0:e3fb1267e3c3 1005 #if ENC28J60_USE_SPILIB
cassyarduino 0:e3fb1267e3c3 1006 #if defined(ARDUINO)
cassyarduino 0:e3fb1267e3c3 1007 t = SPI.transfer(0x00) << 8;
cassyarduino 0:e3fb1267e3c3 1008 t += SPI.transfer(0x00);
cassyarduino 0:e3fb1267e3c3 1009 #endif
cassyarduino 0:e3fb1267e3c3 1010 #if defined(__MBED__)
cassyarduino 0:e3fb1267e3c3 1011 t = _spi.write(0x00) << 8;
cassyarduino 0:e3fb1267e3c3 1012 t += _spi.write(0x00);
cassyarduino 0:e3fb1267e3c3 1013 #endif
cassyarduino 0:e3fb1267e3c3 1014 #else
cassyarduino 0:e3fb1267e3c3 1015 SPDR = 0x00;
cassyarduino 0:e3fb1267e3c3 1016 waitspi();
cassyarduino 0:e3fb1267e3c3 1017 t = SPDR << 8;
cassyarduino 0:e3fb1267e3c3 1018 SPDR = 0x00;
cassyarduino 0:e3fb1267e3c3 1019 waitspi();
cassyarduino 0:e3fb1267e3c3 1020 t += SPDR;
cassyarduino 0:e3fb1267e3c3 1021 #endif
cassyarduino 0:e3fb1267e3c3 1022 sum += t;
cassyarduino 0:e3fb1267e3c3 1023 if(sum < t)
cassyarduino 0:e3fb1267e3c3 1024 {
cassyarduino 0:e3fb1267e3c3 1025 sum++; /* carry */
cassyarduino 0:e3fb1267e3c3 1026 }
cassyarduino 0:e3fb1267e3c3 1027 }
cassyarduino 0:e3fb1267e3c3 1028 if(i == len)
cassyarduino 0:e3fb1267e3c3 1029 {
cassyarduino 0:e3fb1267e3c3 1030 #if ENC28J60_USE_SPILIB
cassyarduino 0:e3fb1267e3c3 1031 #if defined(ARDUINO)
cassyarduino 0:e3fb1267e3c3 1032 t = (SPI.transfer(0x00) << 8) + 0;
cassyarduino 0:e3fb1267e3c3 1033 #endif
cassyarduino 0:e3fb1267e3c3 1034 #if defined(__MBED__)
cassyarduino 0:e3fb1267e3c3 1035 t = (_spi.write(0x00) << 8) + 0;
cassyarduino 0:e3fb1267e3c3 1036 #endif
cassyarduino 0:e3fb1267e3c3 1037 #else
cassyarduino 0:e3fb1267e3c3 1038 SPDR = 0x00;
cassyarduino 0:e3fb1267e3c3 1039 waitspi();
cassyarduino 0:e3fb1267e3c3 1040 t = (SPDR << 8) + 0;
cassyarduino 0:e3fb1267e3c3 1041 #endif
cassyarduino 0:e3fb1267e3c3 1042 sum += t;
cassyarduino 0:e3fb1267e3c3 1043 if(sum < t)
cassyarduino 0:e3fb1267e3c3 1044 {
cassyarduino 0:e3fb1267e3c3 1045 sum++; /* carry */
cassyarduino 0:e3fb1267e3c3 1046 }
cassyarduino 0:e3fb1267e3c3 1047 }
cassyarduino 0:e3fb1267e3c3 1048 CSPASSIVE;
cassyarduino 0:e3fb1267e3c3 1049
cassyarduino 0:e3fb1267e3c3 1050 /* Return sum in host byte order. */
cassyarduino 0:e3fb1267e3c3 1051 return sum;
cassyarduino 0:e3fb1267e3c3 1052 }
cassyarduino 0:e3fb1267e3c3 1053
cassyarduino 0:e3fb1267e3c3 1054 void
cassyarduino 0:e3fb1267e3c3 1055 Enc28J60Network::powerOff(void)
cassyarduino 0:e3fb1267e3c3 1056 {
cassyarduino 0:e3fb1267e3c3 1057 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 1058 LogObject.uart_send_strln(F("Enc28J60Network::powerOff(void) DEBUG_V3:Function started"));
cassyarduino 0:e3fb1267e3c3 1059 #endif
cassyarduino 0:e3fb1267e3c3 1060 writeOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_RXEN);
cassyarduino 0:e3fb1267e3c3 1061 delay(50);
cassyarduino 0:e3fb1267e3c3 1062 writeOp(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_VRPS);
cassyarduino 0:e3fb1267e3c3 1063 delay(50);
cassyarduino 0:e3fb1267e3c3 1064 writeOp(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_PWRSV);
cassyarduino 0:e3fb1267e3c3 1065 }
cassyarduino 0:e3fb1267e3c3 1066
cassyarduino 0:e3fb1267e3c3 1067 void
cassyarduino 0:e3fb1267e3c3 1068 Enc28J60Network::powerOn(void)
cassyarduino 0:e3fb1267e3c3 1069 {
cassyarduino 0:e3fb1267e3c3 1070 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 1071 LogObject.uart_send_strln(F("Enc28J60Network::powerOn(void) DEBUG_V3:Function started"));
cassyarduino 0:e3fb1267e3c3 1072 #endif
cassyarduino 0:e3fb1267e3c3 1073 writeOp(ENC28J60_BIT_FIELD_CLR, ECON2, ECON2_PWRSV);
cassyarduino 0:e3fb1267e3c3 1074 delay(50);
cassyarduino 0:e3fb1267e3c3 1075 writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
cassyarduino 0:e3fb1267e3c3 1076 delay(50);
cassyarduino 0:e3fb1267e3c3 1077 }
cassyarduino 0:e3fb1267e3c3 1078
cassyarduino 0:e3fb1267e3c3 1079 // read erevid from object:
cassyarduino 0:e3fb1267e3c3 1080 uint8_t
cassyarduino 0:e3fb1267e3c3 1081 Enc28J60Network::geterevid(void)
cassyarduino 0:e3fb1267e3c3 1082 {
cassyarduino 0:e3fb1267e3c3 1083 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 1084 LogObject.uart_send_str(F("Enc28J60Network::geterevid(void) DEBUG_V3:Function started and return:"));
cassyarduino 0:e3fb1267e3c3 1085 LogObject.uart_send_decln(erevid);
cassyarduino 0:e3fb1267e3c3 1086 #endif
cassyarduino 0:e3fb1267e3c3 1087 return(erevid);
cassyarduino 0:e3fb1267e3c3 1088 }
cassyarduino 0:e3fb1267e3c3 1089
cassyarduino 0:e3fb1267e3c3 1090 // read the phstat2 of the chip:
cassyarduino 0:e3fb1267e3c3 1091 uint16_t
cassyarduino 0:e3fb1267e3c3 1092 Enc28J60Network::PhyStatus(void)
cassyarduino 0:e3fb1267e3c3 1093 {
cassyarduino 0:e3fb1267e3c3 1094 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 1095 LogObject.uart_send_str(F("Enc28J60Network::PhyStatus(void) DEBUG_V3:Function started"));
cassyarduino 0:e3fb1267e3c3 1096 LogObject.uart_send_decln(erevid);
cassyarduino 0:e3fb1267e3c3 1097 #endif
cassyarduino 0:e3fb1267e3c3 1098 uint16_t phstat2;
cassyarduino 0:e3fb1267e3c3 1099 phstat2=phyRead(PHSTAT2);
cassyarduino 0:e3fb1267e3c3 1100 if ((phstat2 & 0x20) > 0) {phstat2=phstat2 &0x100;}
cassyarduino 0:e3fb1267e3c3 1101 phstat2=(phstat2 & 0xFF00) | erevid;
cassyarduino 0:e3fb1267e3c3 1102 if ((phstat2 & 0x8000) > 0) {phstat2=0;}
cassyarduino 0:e3fb1267e3c3 1103 return phstat2;
cassyarduino 0:e3fb1267e3c3 1104 }
cassyarduino 0:e3fb1267e3c3 1105
cassyarduino 0:e3fb1267e3c3 1106 bool
cassyarduino 0:e3fb1267e3c3 1107 Enc28J60Network::linkStatus(void)
cassyarduino 0:e3fb1267e3c3 1108 {
cassyarduino 0:e3fb1267e3c3 1109 #if ACTLOGLEVEL>=LOG_DEBUG_V3
cassyarduino 0:e3fb1267e3c3 1110 LogObject.uart_send_strln(F("Enc28J60Network::linkStatus(void) DEBUG_V3:Function started"));
cassyarduino 0:e3fb1267e3c3 1111 #endif
cassyarduino 0:e3fb1267e3c3 1112 return (phyRead(PHSTAT2) & 0x0400) > 0;
cassyarduino 0:e3fb1267e3c3 1113 }
cassyarduino 0:e3fb1267e3c3 1114
cassyarduino 0:e3fb1267e3c3 1115 Enc28J60Network Enc28J60;