paolo della vedova / Mbed 2 deprecated stm32_pulse_counter

pulse counter stm32

Dependencies:   mbed

counter.cpp@0:6adab3889554, 2015-09-29 (annotated)

Committer:
c128
Date:
Tue Sep 29 14:05:36 2015 +0000
Revision:
0:6adab3889554
Child:
1:3d22d4e6de38
pulse counter stm32

Who changed what in which revision?

UserRevisionLine numberNew contents of line
c128 0:6adab3889554 1 // reference this code http://www.fmf.uni-lj.si/~ponikvar/STM32F407%20project/Timer2_Counting.pdf
c128 0:6adab3889554 2 #include "mbed.h"
c128 0:6adab3889554 3 #include "stm32f4xx.h"
c128 0:6adab3889554 4
c128 0:6adab3889554 5 int main(){
c128 0:6adab3889554 6 RCC->AHB1ENR |= 0x01 + 0x10; // Clock for PortA, E
c128 0:6adab3889554 7 RCC->APB1ENR |= 0x01; // Clock for Timer2
c128 0:6adab3889554 8 GPIOA->MODER |= 0x00000008; // all inputs but: PA1 => AF mode
c128 0:6adab3889554 9 GPIOA->AFR[0] |= 0x00000010; // select AF1 (TIM2) for PA01 -> TIM2_CH2
c128 0:6adab3889554 10
c128 0:6adab3889554 11 TIM2->CCMR1 |= 0x0100; // Ch. 2 as TI2
c128 0:6adab3889554 12 TIM2->SMCR |= 0x0007; // Ext. clk mode 1
c128 0:6adab3889554 13 TIM2->SMCR |= 0x0060; // TI2FP2 as ext. clock
c128 0:6adab3889554 14 TIM2->CR1 |= 0x0001; // enable counting
c128 0:6adab3889554 15
c128 0:6adab3889554 16 while (1) {
c128 0:6adab3889554 17 int16_t count1;
c128 0:6adab3889554 18 count1=TIM2->CNT; //OK 401 411 TICKER 030
c128 0:6adab3889554 19
c128 0:6adab3889554 20 printf("%d\r\n", count1);
c128 0:6adab3889554 21 wait(1.0);
c128 0:6adab3889554 22 if (GPIOE->IDR & 0x01) TIM2->CNT = 0; // reset counter
c128 0:6adab3889554 23 if (GPIOE->IDR & 0x02) TIM2->CR1 |= 0x01; // enable counter
c128 0:6adab3889554 24 if (GPIOE->IDR & 0x04) TIM2->CR1 &= ~0x01; // disable counter
c128 0:6adab3889554 25 };
c128 0:6adab3889554 26 }