Mark Bundgus / LPC1114_Deep_Power_Down

During Deep power-down mode, the contents of the SRAM and registers are not retained except for a small amount of data which can be stored in five 32-bit general purpose registers of the power management unit block. All functional pins are tri-stated in Deep power-down mode except for the WAKEUP pin.

Dependents:   LPC1114_5110_PIR

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Last updated: 03 Jan 2015