During Deep power-down mode, the contents of the SRAM and registers are not retained except for a small amount of data which can be stored in five 32-bit general purpose registers of the power management unit block. All functional pins are tri-stated in Deep power-down mode except for the WAKEUP pin.
DeepPowerDown.cpp@0:959f4e23f133, 2015-01-03 (annotated)
- Committer:
- bundgus
- Date:
- Sat Jan 03 17:22:30 2015 +0000
- Revision:
- 0:959f4e23f133
During Deep power-down mode, the contents of the SRAM and registers are not retained except for a small amount of data which can be stored in five 32-bit general purpose registers of the power management unit block. All functional pins are tri-stated
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
bundgus | 0:959f4e23f133 | 1 | /* |
bundgus | 0:959f4e23f133 | 2 | * DeepPowerDown.cpp |
bundgus | 0:959f4e23f133 | 3 | * |
bundgus | 0:959f4e23f133 | 4 | * Created on: Dec 26, 2014 |
bundgus | 0:959f4e23f133 | 5 | * Author: bundgus |
bundgus | 0:959f4e23f133 | 6 | */ |
bundgus | 0:959f4e23f133 | 7 | |
bundgus | 0:959f4e23f133 | 8 | #include "DeepPowerDown.h" |
bundgus | 0:959f4e23f133 | 9 | #include "LPC11xx.h" |
bundgus | 0:959f4e23f133 | 10 | |
bundgus | 0:959f4e23f133 | 11 | DeepPowerDown::DeepPowerDown() { |
bundgus | 0:959f4e23f133 | 12 | // TODO Auto-generated constructor stub |
bundgus | 0:959f4e23f133 | 13 | |
bundgus | 0:959f4e23f133 | 14 | } |
bundgus | 0:959f4e23f133 | 15 | |
bundgus | 0:959f4e23f133 | 16 | DeepPowerDown::~DeepPowerDown() { |
bundgus | 0:959f4e23f133 | 17 | // TODO Auto-generated destructor stub |
bundgus | 0:959f4e23f133 | 18 | } |
bundgus | 0:959f4e23f133 | 19 | |
bundgus | 0:959f4e23f133 | 20 | |
bundgus | 0:959f4e23f133 | 21 | void DeepPowerDown::powerDown(){ |
bundgus | 0:959f4e23f133 | 22 | |
bundgus | 0:959f4e23f133 | 23 | /* |
bundgus | 0:959f4e23f133 | 24 | * Table 49. |
bundgus | 0:959f4e23f133 | 25 | Register overview: PMU (base address 0x4003 8000) |
bundgus | 0:959f4e23f133 | 26 | |
bundgus | 0:959f4e23f133 | 27 | Name Access Address offset Description Reset value |
bundgus | 0:959f4e23f133 | 28 | PCON R/W 0x000 Power control register 0x0 |
bundgus | 0:959f4e23f133 | 29 | GPREG0 R/W 0x004 General purpose register 0 0x0 |
bundgus | 0:959f4e23f133 | 30 | GPREG1 R/W 0x008 General purpose register 1 0x0 |
bundgus | 0:959f4e23f133 | 31 | GPREG2 R/W 0x00C General purpose register 2 0x0 |
bundgus | 0:959f4e23f133 | 32 | GPREG3 R/W 0x010 General purpose register 3 0x0 |
bundgus | 0:959f4e23f133 | 33 | GPREG4 R/W 0x014 General purpose register 4 0x0 |
bundgus | 0:959f4e23f133 | 34 | */ |
bundgus | 0:959f4e23f133 | 35 | |
bundgus | 0:959f4e23f133 | 36 | |
bundgus | 0:959f4e23f133 | 37 | // Write one to the DPDEN bit in the PCON register. |
bundgus | 0:959f4e23f133 | 38 | LPC_PMU->PCON = (1 << 1) | (1 << 11); |
bundgus | 0:959f4e23f133 | 39 | |
bundgus | 0:959f4e23f133 | 40 | // Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register. |
bundgus | 0:959f4e23f133 | 41 | |
bundgus | 0:959f4e23f133 | 42 | SCB->SCR |= (1 << 2); //Set SLEEPDEEP bit |
bundgus | 0:959f4e23f133 | 43 | |
bundgus | 0:959f4e23f133 | 44 | // Ensure that the IRC is powered by setting bits IRCOUT_PD and IRC_PD to zero in the PDRUNCFG register before entering Deep power-down mode. |
bundgus | 0:959f4e23f133 | 45 | LPC_SYSCON->PDRUNCFG &= ~((1 << 0) | (1 << 1)); |
bundgus | 0:959f4e23f133 | 46 | |
bundgus | 0:959f4e23f133 | 47 | // Deep Power Down |
bundgus | 0:959f4e23f133 | 48 | __WFI(); |
bundgus | 0:959f4e23f133 | 49 | |
bundgus | 0:959f4e23f133 | 50 | } |
bundgus | 0:959f4e23f133 | 51 | |
bundgus | 0:959f4e23f133 | 52 | void DeepPowerDown::setGPREG0(unsigned int newregval){ |
bundgus | 0:959f4e23f133 | 53 | LPC_PMU->GPREG0 = newregval; |
bundgus | 0:959f4e23f133 | 54 | } |
bundgus | 0:959f4e23f133 | 55 | |
bundgus | 0:959f4e23f133 | 56 | unsigned int DeepPowerDown::getGPREG0(){ |
bundgus | 0:959f4e23f133 | 57 | return LPC_PMU->GPREG0; |
bundgus | 0:959f4e23f133 | 58 | } |
bundgus | 0:959f4e23f133 | 59 | |
bundgus | 0:959f4e23f133 | 60 | void DeepPowerDown::setGPREG1(unsigned int newregval){ |
bundgus | 0:959f4e23f133 | 61 | LPC_PMU->GPREG1 = newregval; |
bundgus | 0:959f4e23f133 | 62 | } |
bundgus | 0:959f4e23f133 | 63 | |
bundgus | 0:959f4e23f133 | 64 | unsigned int DeepPowerDown::getGPREG1(){ |
bundgus | 0:959f4e23f133 | 65 | return LPC_PMU->GPREG1; |
bundgus | 0:959f4e23f133 | 66 | } |
bundgus | 0:959f4e23f133 | 67 | |
bundgus | 0:959f4e23f133 | 68 | void DeepPowerDown::setGPREG2(unsigned int newregval){ |
bundgus | 0:959f4e23f133 | 69 | LPC_PMU->GPREG2 = newregval; |
bundgus | 0:959f4e23f133 | 70 | } |
bundgus | 0:959f4e23f133 | 71 | |
bundgus | 0:959f4e23f133 | 72 | unsigned int DeepPowerDown::getGPREG2(){ |
bundgus | 0:959f4e23f133 | 73 | return LPC_PMU->GPREG2; |
bundgus | 0:959f4e23f133 | 74 | } |
bundgus | 0:959f4e23f133 | 75 | |
bundgus | 0:959f4e23f133 | 76 | void DeepPowerDown::setGPREG3(unsigned int newregval){ |
bundgus | 0:959f4e23f133 | 77 | LPC_PMU->GPREG3 = newregval; |
bundgus | 0:959f4e23f133 | 78 | } |
bundgus | 0:959f4e23f133 | 79 | |
bundgus | 0:959f4e23f133 | 80 | unsigned int DeepPowerDown::getGPREG3(){ |
bundgus | 0:959f4e23f133 | 81 | return LPC_PMU->GPREG3; |
bundgus | 0:959f4e23f133 | 82 | } |
bundgus | 0:959f4e23f133 | 83 | |
bundgus | 0:959f4e23f133 | 84 | void DeepPowerDown::setGPREG4(unsigned int newregval){ |
bundgus | 0:959f4e23f133 | 85 | LPC_PMU->GPREG4 = newregval; |
bundgus | 0:959f4e23f133 | 86 | } |
bundgus | 0:959f4e23f133 | 87 | |
bundgus | 0:959f4e23f133 | 88 | unsigned int DeepPowerDown::getGPREG4(){ |
bundgus | 0:959f4e23f133 | 89 | return LPC_PMU->GPREG4; |
bundgus | 0:959f4e23f133 | 90 | } |