Bruno Cavalcanti
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Dependencies: DS1820 HighSpeedAnalogIn devices mbed
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modbusMaster1.cpp
00001 #include "modbusMaster1.h" 00002 #define maxRetentativas 5 00003 #define maxDelayEntreTentativas 100 00004 //RAD 00005 enum { 00006 READ_COIL_STATUS = 1, 00007 READ_INPUT_STATUS, 00008 READ_HOLDING_REGISTERS, 00009 READ_INPUT_REGISTERS, 00010 WRITE_SINGLE_COIL, 00011 WRITE_SINGLE_REGISTER, 00012 WRITE_MULTIPLE_COILS, 00013 WRITE_MULTIPLE_REGISTERS 00014 }modBusFunctions; 00015 00016 uint16_t modBusMaster1::T3_5; 00017 uint16_t modBusMaster1::T1_5; 00018 bool modBusMaster1::pacoteEmEspera; 00019 bool modBusMaster1::pacoteEmEsperaValido; 00020 uint16_t modBusMaster1::MODBUS_TIMEOUT; 00021 bool modBusMaster1::startThreadModBusMaster; 00022 Serial *modBusMaster1::serModBus; 00023 DigitalOut *modBusMaster1::de; 00024 uint16_t modBusMaster1::MODBUS_SERIAL_BAUD; 00025 00026 uint8_t modBusMaster1::buffer[maxLenBufModBus]; //Buffer in e out; 00027 uint16_t modBusMaster1::index; 00028 00029 //Timer 00030 osTimerId modBusMaster1::timer_pacote; 00031 osTimerDef(timerProcessaPacoteModBusMaster1,modBusMaster1::processaPacote); 00032 //Timer 00033 00034 void modBusMaster1::processaPacote(void const *){ 00035 //Validando CRC 00036 uint16_t crc_calculado; 00037 uint16_t crc_lido; 00038 00039 if(debug){ 00040 //Lido resposta DEBUG 00041 pc.printf("Lido de resposta modbus <"); 00042 for(crc_lido = 0; crc_lido < modBusMaster1::index; crc_lido++){ 00043 pc.printf("%02X ",modBusMaster1::buffer[crc_lido]); 00044 } 00045 pc.printf(">.\n"); 00046 } 00047 if(modBusMaster1::index<3){ 00048 modBusMaster1::pacoteEmEspera=false; 00049 return; 00050 } 00051 00052 crc_calculado = modBusMaster1::CRC16(modBusMaster1::buffer,modBusMaster1::index-2); 00053 crc_lido = (modBusMaster1::buffer[modBusMaster1::index-2]<<8)+(modBusMaster1::buffer[modBusMaster1::index-1]); 00054 00055 modBusMaster1::pacoteEmEspera=true; 00056 if(crc_calculado == crc_lido){ 00057 modBusMaster1::pacoteEmEsperaValido=true; 00058 } 00059 //pc.printf("crc_calculado = 0x%02x, crc_lido = 0x%02x.\n",crc_calculado,crc_lido); 00060 } 00061 00062 uint16_t modBusMaster1::CRC16(uint8_t *buf,uint16_t len){ 00063 uint16_t crc = 0xFFFF; 00064 uint16_t pos; 00065 uint16_t i; 00066 for (pos = 0; pos < len; pos++) { 00067 crc ^= buf[pos]; // XOR byte into least sig. byte of crc 00068 00069 for (i = 8; i != 0; i--) { // Loop over each bit 00070 if ((crc & 0x0001) != 0) { // If the LSB is set 00071 crc >>= 1; // Shift right and XOR 0xA001 00072 crc ^= 0xA001; 00073 } 00074 else // Else LSB is not set 00075 crc >>= 1; // Just shift right 00076 } 00077 } 00078 // Note, this number has low and high bytes swapped, so use it accordingly (or swap bytes) 00079 return ((crc<<8)+(crc>>8)); 00080 } 00081 00082 void modBusMaster1::modBusMaster(Serial *serial,uint32_t baud,DigitalOut *pinDe){ 00083 modBusMaster1::serModBus = serial; 00084 modBusMaster1::de = pinDe; 00085 modBusMaster1::index = 0; 00086 *modBusMaster1::de = 0; 00087 modBusMaster1::serModBus->attach(&modBusMaster1::processaCaractere); 00088 modBusMaster1::serModBus->baud(baud); 00089 modBusMaster1::pacoteEmEspera = false; 00090 //Criando timer_pacote 00091 modBusMaster1::timer_pacote = osTimerCreate(osTimer(timerProcessaPacoteModBusMaster1),osTimerOnce,NULL); 00092 } 00093 00094 void modBusMaster1::setBaud(uint32_t baud){ 00095 modBusMaster1::serModBus->baud(baud); 00096 if (baud > 19200){ 00097 modBusMaster1::T1_5 = 750; 00098 modBusMaster1::T3_5 = 1750; 00099 }else { 00100 modBusMaster1::T1_5 = 15000000/baud; 00101 modBusMaster1::T3_5 = 35000000/baud; 00102 } 00103 } 00104 00105 00106 00107 void modBusMaster1::processaCaractere(){ 00108 uint32_t RBR = LPC_UART1->RBR; //Reset RBR interrupt flag e captura o caractere entrante 00109 modBusMaster1::buffer[modBusMaster1::index]=RBR; 00110 modBusMaster1::index++; 00111 if(modBusMaster1::index>=maxLenBufModBus){ 00112 modBusMaster1::index=modBusMaster1::index-1; 00113 } 00114 modBusMaster1::startThreadModBusMaster=true; 00115 osSignalSet(idThreadTimers, 0x1); //Envia sinal para a thread de manipulação dos timers para ativar os timers agendados 00116 //comLedIn=!comLedIn; 00117 //pc.printf("%c",RBR); 00118 } 00119 00120 uint16_t modBusMaster1::sendFrame(uint16_t tamBytes){ 00121 uint16_t timeout = modBusMaster1::MODBUS_TIMEOUT; 00122 timeout /=10; 00123 uint16_t i; 00124 00125 if(debug){ 00126 //DEBUG Mostrando o que é enviado via modbus 00127 pc.printf("Frame enviado (hexa) <"); 00128 for(i=0;i<tamBytes;i++){ 00129 pc.printf("%02x ",modBusMaster1::buffer[i]); 00130 } 00131 pc.printf(">.\n"); 00132 } 00133 00134 //osDelay(5); 00135 00136 modBusMaster1::pacoteEmEspera = false; 00137 modBusMaster1::index=0; 00138 *modBusMaster1::de=1; 00139 //wait_us(1750); 00140 osDelay(1); 00141 for(i=0;i<tamBytes;i++){ 00142 modBusMaster1::serModBus->putc(modBusMaster1::buffer[i]); 00143 //wait_us(750); 00144 while( 00145 ((LPC_UART1->LSR >> 6) &0x1) 00146 == 0 ); 00147 //wait_us(modBusMaster1::T1_5); 00148 } 00149 //wait_us(1750); 00150 //osDelay(1); 00151 *modBusMaster1::de=0; 00152 00153 while((timeout>0)&&(modBusMaster1::pacoteEmEspera!=true)){ 00154 osDelay(10); 00155 //wait_us(1000); 00156 timeout--; 00157 } 00158 wait_us(modBusMaster1::T3_5*2); 00159 return timeout; 00160 } 00161 00162 uint8_t modBusMaster1::readRegister16BIT(uint8_t enderecoSlave,uint8_t funcao,uint16_t registrador,uint16_t qtdRegistros,uint16_t *var){ 00163 union{ 00164 char c[2]; 00165 uint16_t v; 00166 }u; 00167 uint16_t crc; 00168 uint16_t qtd_dados_recebidos; 00169 uint16_t i; 00170 uint8_t result; 00171 00172 for(i=0;i<qtdRegistros;i++){ 00173 var[i]=NULL; 00174 } 00175 00176 //-----------------Bloco de tentativas--------------------- 00177 uint16_t retentativas = maxRetentativas+1; 00178 uint16_t delayEntreTentativas = maxDelayEntreTentativas; 00179 while(retentativas){ 00180 modBusMaster1::buffer[0]=enderecoSlave; 00181 modBusMaster1::buffer[1]=funcao; 00182 modBusMaster1::buffer[2]=registrador>>8; 00183 modBusMaster1::buffer[3]=(registrador & 0xFF); 00184 modBusMaster1::buffer[4]=qtdRegistros>>8; 00185 modBusMaster1::buffer[5]=(qtdRegistros & 0xFF); 00186 00187 crc=modBusMaster1::CRC16(modBusMaster1::buffer,6); 00188 00189 modBusMaster1::buffer[6]=crc>>8; 00190 modBusMaster1::buffer[7]=(crc & 0xFF); 00191 00192 if(!modBusMaster1::sendFrame(8)){ 00193 osDelay(delayEntreTentativas); 00194 retentativas--; 00195 if(debug){ 00196 //DEBUG Mostrando o que é enviado via modbus 00197 pc.printf("Retentativa de comando modbus.\r\n"); 00198 } 00199 if(retentativas==0){ 00200 //erro de timeout certamente 00201 pc.printf("Erro de timeout.\n"); 00202 modBusMaster1::pacoteEmEspera = false; //Sinalizo que li o pacote 00203 modBusMaster1::index = 0; 00204 return 254; 00205 } 00206 }else{ 00207 //Chegou pacote, vamos ver se é valido 00208 retentativas = 0; 00209 } 00210 } 00211 if(!modBusMaster1::pacoteEmEsperaValido){ 00212 pc.printf("Erro de CRC.\n"); 00213 modBusMaster1::pacoteEmEspera = false; //Sinalizo que li o pacote 00214 modBusMaster1::index = 0; 00215 return 255; 00216 } 00217 //-----------------Bloco de tentativas--------------------- 00218 00219 if(modBusMaster1::buffer[1]&(0x1<<7)){ 00220 result = modBusMaster1::buffer[2]; 00221 }else{ 00222 qtd_dados_recebidos = modBusMaster1::buffer[2]/2; 00223 for(i=0;i<qtd_dados_recebidos;i++){ 00224 u.c[1]=modBusMaster1::buffer[(i*2)+3]; 00225 u.c[0]=modBusMaster1::buffer[(i*2)+4]; 00226 var[i]=u.v; 00227 } 00228 result = 0; 00229 } 00230 00231 00232 00233 modBusMaster1::pacoteEmEspera = false; //Sinalizo que li o pacote 00234 modBusMaster1::index = 0; 00235 return result; 00236 } 00237 00238 uint8_t modBusMaster1::writeSingleCoil(uint8_t enderecoSlave,uint16_t registrador,bool var){ 00239 uint16_t crc; 00240 uint16_t estadoSetado; 00241 uint8_t result = 0; 00242 //-----------------Bloco de tentativas--------------------- 00243 uint16_t retentativas = maxRetentativas+1; 00244 uint16_t delayEntreTentativas = maxDelayEntreTentativas; 00245 while(retentativas){ 00246 //------------Bloco de construcao de frame request---------- 00247 modBusMaster1::buffer[0]=enderecoSlave; 00248 modBusMaster1::buffer[1]=5; 00249 modBusMaster1::buffer[2]=registrador>>8; 00250 modBusMaster1::buffer[3]=(registrador & 0xFF); 00251 00252 if(var){ 00253 modBusMaster1::buffer[4]=0xFF; 00254 modBusMaster1::buffer[5]=0x00; 00255 estadoSetado = 0xFF00; 00256 00257 }else{ 00258 modBusMaster1::buffer[4]=0x00; 00259 modBusMaster1::buffer[5]=0x00; 00260 estadoSetado = 0x0000; 00261 } 00262 00263 00264 crc=modBusMaster1::CRC16(modBusMaster1::buffer,6); 00265 00266 modBusMaster1::buffer[6]=crc>>8; 00267 modBusMaster1::buffer[7]=(crc & 0xFF); 00268 //------------Bloco de construcao de frame request---------- 00269 if(!modBusMaster1::sendFrame(8)){ 00270 osDelay(delayEntreTentativas); 00271 retentativas--; 00272 if(debug){ 00273 //DEBUG Mostrando o que é enviado via modbus 00274 pc.printf("Retentativa de comando modbus.\r\n"); 00275 } 00276 if(retentativas==0){ 00277 //erro de timeout certamente 00278 pc.printf("Erro de timeout.\n"); 00279 modBusMaster1::pacoteEmEspera = false; //Sinalizo que li o pacote 00280 modBusMaster1::index = 0; 00281 return 254; 00282 } 00283 }else{ 00284 //Chegou pacote, vamos ver se é valido 00285 retentativas = 0; 00286 } 00287 } 00288 if(!modBusMaster1::pacoteEmEsperaValido){ 00289 pc.printf("Erro de CRC.\n"); 00290 modBusMaster1::pacoteEmEspera = false; //Sinalizo que li o pacote 00291 modBusMaster1::index = 0; 00292 return 255; 00293 } 00294 //-----------------Bloco de tentativas--------------------- 00295 00296 00297 if(modBusMaster1::buffer[1]&(0x1<<7)){ 00298 result = modBusMaster1::buffer[2]; 00299 }else{ 00300 if( 00301 (((modBusMaster1::buffer[2]<<8)+(modBusMaster1::buffer[3]))==registrador) 00302 && 00303 (((modBusMaster1::buffer[4]<<8)+(modBusMaster1::buffer[5]))==estadoSetado) 00304 ){ 00305 result=0; 00306 }else{ 00307 result=253; 00308 } 00309 } 00310 modBusMaster1::pacoteEmEspera = false; //Sinalizo que li o pacote 00311 modBusMaster1::index = 0; 00312 return result; 00313 } 00314 00315 uint8_t modBusMaster1::readCoils(uint8_t enderecoSlave,uint16_t registrador,uint16_t qtdRegistros,bool *var){ 00316 uint16_t crc; 00317 uint8_t result; 00318 uint16_t i; 00319 //-----------------Bloco de tentativas--------------------- 00320 uint16_t retentativas = maxRetentativas+1; 00321 uint16_t delayEntreTentativas = maxDelayEntreTentativas; 00322 while(retentativas){ 00323 //------------Bloco de construcao de frame request---------- 00324 00325 modBusMaster1::buffer[0]=enderecoSlave; 00326 modBusMaster1::buffer[1]=1; 00327 modBusMaster1::buffer[2]=registrador>>8; 00328 modBusMaster1::buffer[3]=(registrador & 0xFF); 00329 modBusMaster1::buffer[4]=qtdRegistros>>8; 00330 modBusMaster1::buffer[5]=(qtdRegistros & 0xFF); 00331 00332 crc=modBusMaster1::CRC16(modBusMaster1::buffer,6); 00333 00334 modBusMaster1::buffer[6]=crc>>8; 00335 modBusMaster1::buffer[7]=(crc & 0xFF); 00336 00337 //------------Bloco de construcao de frame request---------- 00338 if(!modBusMaster1::sendFrame(8)){ 00339 osDelay(delayEntreTentativas); 00340 retentativas--; 00341 if(debug){ 00342 //DEBUG Mostrando o que é enviado via modbus 00343 pc.printf("Retentativa de comando modbus.\r\n"); 00344 } 00345 if(retentativas==0){ 00346 //erro de timeout certamente 00347 pc.printf("Erro de timeout.\n"); 00348 modBusMaster1::pacoteEmEspera = false; //Sinalizo que li o pacote 00349 modBusMaster1::index = 0; 00350 return 254; 00351 } 00352 }else{ 00353 //Chegou pacote, vamos ver se é valido 00354 retentativas = 0; 00355 } 00356 } 00357 if(!modBusMaster1::pacoteEmEsperaValido){ 00358 pc.printf("Erro de CRC.\n"); 00359 modBusMaster1::pacoteEmEspera = false; //Sinalizo que li o pacote 00360 modBusMaster1::index = 0; 00361 return 255; 00362 } 00363 //-----------------Bloco de tentativas--------------------- 00364 00365 if(modBusMaster1::buffer[1]&(0x1<<7)){ 00366 result = modBusMaster1::buffer[2]; 00367 }else{ 00368 if( 00369 modBusMaster1::buffer[2] == (1+((uint16_t)(qtdRegistros/8))) 00370 ){ 00371 //Bloco de leitura das coils 00372 for(i=0;i<qtdRegistros;i++){ 00373 var[i] = ( 00374 (modBusMaster1::buffer[(i/8)+3] & ( 0x1 << (i%8) )) >0 00375 ); 00376 } 00377 result = 0; 00378 }else{ 00379 result = 253; 00380 } 00381 } 00382 00383 00384 modBusMaster1::pacoteEmEspera = false; //Sinalizo que li o pacote 00385 modBusMaster1::index = 0; 00386 return result; 00387 } 00388 uint8_t modBusMaster1::readRegister32BIT(uint8_t enderecoSlave,uint8_t funcao,uint16_t registrador,uint16_t qtdRegistros,uint32_t *var){ 00389 union{ 00390 char c[4]; 00391 uint32_t v; 00392 }u; 00393 uint16_t crc; 00394 uint16_t qtd_dados_recebidos; 00395 uint16_t i; 00396 uint8_t result; 00397 00398 for(i=0;i<qtdRegistros;i++){ 00399 var[i]=NULL; 00400 } 00401 00402 //-----------------Bloco de tentativas--------------------- 00403 uint16_t retentativas = maxRetentativas+1; 00404 uint16_t delayEntreTentativas = maxDelayEntreTentativas; 00405 while(retentativas){ 00406 //------------Bloco de construcao de frame request---------- 00407 00408 modBusMaster1::buffer[0]=enderecoSlave; 00409 modBusMaster1::buffer[1]=funcao; 00410 modBusMaster1::buffer[2]=registrador>>8; 00411 modBusMaster1::buffer[3]=(registrador & 0xFF); 00412 modBusMaster1::buffer[4]=qtdRegistros>>8; 00413 modBusMaster1::buffer[5]=(qtdRegistros & 0xFF); 00414 00415 crc=modBusMaster1::CRC16(modBusMaster1::buffer,6); 00416 00417 modBusMaster1::buffer[6]=crc>>8; 00418 modBusMaster1::buffer[7]=(crc & 0xFF); 00419 00420 //------------Bloco de construcao de frame request---------- 00421 if(!modBusMaster1::sendFrame(8)){ 00422 osDelay(delayEntreTentativas); 00423 retentativas--; 00424 if(debug){ 00425 //DEBUG Mostrando o que é enviado via modbus 00426 pc.printf("Retentativa de comando modbus.\r\n"); 00427 } 00428 if(retentativas==0){ 00429 //erro de timeout certamente 00430 pc.printf("Erro de timeout.\n"); 00431 modBusMaster1::pacoteEmEspera = false; //Sinalizo que li o pacote 00432 modBusMaster1::index = 0; 00433 return 254; 00434 } 00435 }else{ 00436 //Chegou pacote, vamos ver se é valido 00437 retentativas = 0; 00438 } 00439 } 00440 if(!modBusMaster1::pacoteEmEsperaValido){ 00441 pc.printf("Erro de CRC.\n"); 00442 modBusMaster1::pacoteEmEspera = false; //Sinalizo que li o pacote 00443 modBusMaster1::index = 0; 00444 return 255; 00445 } 00446 //-----------------Bloco de tentativas--------------------- 00447 00448 if(modBusMaster1::buffer[1]&(0x1<<7)){ 00449 result = modBusMaster1::buffer[2]; 00450 }else{ 00451 00452 qtd_dados_recebidos = modBusMaster1::buffer[2]/4; 00453 for(i=0;i<qtd_dados_recebidos;i++){ 00454 u.c[3]=modBusMaster1::buffer[(i*4)+3]; 00455 u.c[2]=modBusMaster1::buffer[(i*4)+4]; 00456 u.c[1]=modBusMaster1::buffer[(i*4)+5]; 00457 u.c[0]=modBusMaster1::buffer[(i*4)+6]; 00458 var[i]=u.v; 00459 } 00460 result =0; 00461 } 00462 00463 modBusMaster1::pacoteEmEspera = false; //Sinalizo que li o pacote 00464 modBusMaster1::index = 0; 00465 return result; 00466 } 00467 00468 uint8_t modBusMaster1::writeRegister16BIT(uint8_t enderecoSlave,uint16_t registrador,uint16_t qtdRegistros,uint16_t *var){ 00469 uint16_t i; 00470 uint16_t crc; 00471 uint8_t result; 00472 00473 //-----------------Bloco de tentativas--------------------- 00474 uint16_t retentativas = maxRetentativas+1; 00475 uint16_t delayEntreTentativas = maxDelayEntreTentativas; 00476 while(retentativas){ 00477 //------------Bloco de construcao de frame request---------- 00478 00479 modBusMaster1::buffer[0]=enderecoSlave; 00480 modBusMaster1::buffer[1]=16; 00481 modBusMaster1::buffer[2]=registrador>>8; 00482 modBusMaster1::buffer[3]=(registrador & 0xFF); 00483 modBusMaster1::buffer[4]=qtdRegistros>>8; 00484 modBusMaster1::buffer[5]=(qtdRegistros & 0xFF); 00485 modBusMaster1::buffer[6]=qtdRegistros*2; 00486 00487 for(i=0;i<qtdRegistros;i++){ 00488 modBusMaster1::buffer[(i*2)+7]=var[i]>>8; 00489 modBusMaster1::buffer[(i*2)+8]=var[i]&0xFF; 00490 } 00491 00492 crc=modBusMaster1::CRC16(modBusMaster1::buffer,((qtdRegistros)*2)+7); 00493 00494 modBusMaster1::buffer[(qtdRegistros*2)+7]=crc>>8;; 00495 modBusMaster1::buffer[(qtdRegistros*2)+8]=(crc & 0xFF); 00496 00497 //------------Bloco de construcao de frame request---------- 00498 if(!modBusMaster1::sendFrame((qtdRegistros*2)+9)){ 00499 osDelay(delayEntreTentativas); 00500 retentativas--; 00501 if(debug){ 00502 //DEBUG Mostrando o que é enviado via modbus 00503 pc.printf("Retentativa de comando modbus.\r\n"); 00504 } 00505 if(retentativas==0){ 00506 //erro de timeout certamente 00507 pc.printf("Erro de timeout.\n"); 00508 modBusMaster1::pacoteEmEspera = false; //Sinalizo que li o pacote 00509 modBusMaster1::index = 0; 00510 return 254; 00511 } 00512 }else{ 00513 //Chegou pacote, vamos ver se é valido 00514 retentativas = 0; 00515 } 00516 } 00517 if(!modBusMaster1::pacoteEmEsperaValido){ 00518 pc.printf("Erro de CRC.\n"); 00519 modBusMaster1::pacoteEmEspera = false; //Sinalizo que li o pacote 00520 modBusMaster1::index = 0; 00521 return 255; 00522 } 00523 //-----------------Bloco de tentativas--------------------- 00524 00525 modBusMaster1::pacoteEmEspera = false; //Sinalizo que li o pacote 00526 modBusMaster1::index = 0; 00527 00528 if(modBusMaster1::buffer[1]&(0x1<<7)){ 00529 result = modBusMaster1::buffer[2]; 00530 }else{ 00531 00532 //Interpratando resposta 00533 if(((modBusMaster1::buffer[4]<<8)+(modBusMaster1::buffer[5]))!=qtdRegistros){ 00534 return 253; 00535 }else{ 00536 result = 0; 00537 } 00538 } 00539 return result; 00540 } 00541 00542 uint8_t modBusMaster1::writeRegister32BIT(uint8_t enderecoSlave,uint16_t registrador,uint16_t qtdRegistros,uint32_t *var){ 00543 uint16_t i; 00544 uint16_t crc; 00545 uint8_t result; 00546 00547 //-----------------Bloco de tentativas--------------------- 00548 uint16_t retentativas = maxRetentativas+1; 00549 uint16_t delayEntreTentativas = maxDelayEntreTentativas; 00550 while(retentativas){ 00551 //------------Bloco de construcao de frame request---------- 00552 00553 modBusMaster1::buffer[0]=enderecoSlave; 00554 modBusMaster1::buffer[1]=16; 00555 modBusMaster1::buffer[2]=registrador>>8; 00556 modBusMaster1::buffer[3]=(registrador & 0xFF); 00557 modBusMaster1::buffer[4]=qtdRegistros>>8; 00558 modBusMaster1::buffer[5]=(qtdRegistros & 0xFF); 00559 modBusMaster1::buffer[6]=qtdRegistros*4; 00560 00561 for(i=0;i<qtdRegistros;i++){ 00562 modBusMaster1::buffer[(i*4)+7]=(var[i]>>24)&0xFF; 00563 modBusMaster1::buffer[(i*4)+8]=(var[i]>>16)&0xFF; 00564 modBusMaster1::buffer[(i*4)+9]=(var[i]>>8)&0xFF; 00565 modBusMaster1::buffer[(i*4)+10]=var[i]&0xFF; 00566 } 00567 00568 crc=modBusMaster1::CRC16(modBusMaster1::buffer,((qtdRegistros)*4)+7); 00569 00570 modBusMaster1::buffer[(qtdRegistros*4)+7]=crc>>8;; 00571 modBusMaster1::buffer[(qtdRegistros*4)+8]=(crc & 0xFF); 00572 00573 //------------Bloco de construcao de frame request---------- 00574 if(!modBusMaster1::sendFrame((qtdRegistros*4)+9)){ 00575 osDelay(delayEntreTentativas); 00576 retentativas--; 00577 if(debug){ 00578 //DEBUG Mostrando o que é enviado via modbus 00579 pc.printf("Retentativa de comando modbus.\r\n"); 00580 } 00581 if(retentativas==0){ 00582 //erro de timeout certamente 00583 pc.printf("Erro de timeout.\n"); 00584 modBusMaster1::pacoteEmEspera = false; //Sinalizo que li o pacote 00585 modBusMaster1::index = 0; 00586 return 254; 00587 } 00588 }else{ 00589 //Chegou pacote, vamos ver se é valido 00590 retentativas = 0; 00591 } 00592 } 00593 if(!modBusMaster1::pacoteEmEsperaValido){ 00594 pc.printf("Erro de CRC.\n"); 00595 modBusMaster1::pacoteEmEspera = false; //Sinalizo que li o pacote 00596 modBusMaster1::index = 0; 00597 return 255; 00598 } 00599 //-----------------Bloco de tentativas--------------------- 00600 00601 00602 modBusMaster1::pacoteEmEspera = false; //Sinalizo que li o pacote 00603 modBusMaster1::index = 0; 00604 00605 if(modBusMaster1::buffer[1]&(0x1<<7)){ 00606 result = modBusMaster1::buffer[2]; 00607 }else{ 00608 00609 //Interpratando resposta 00610 if(((modBusMaster1::buffer[4]<<8)+(modBusMaster1::buffer[5]))!=qtdRegistros){ 00611 return 253; 00612 }else{ 00613 result = 0; 00614 } 00615 } 00616 return result; 00617 } 00618 00619 uint8_t modBusMaster1::writeFloat(uint8_t enderecoSlave,uint16_t registrador,uint8_t qtdRegistros,float *var){ 00620 union{ 00621 char c[4]; 00622 float v; 00623 }u; 00624 uint16_t i; 00625 uint16_t crc; 00626 uint8_t result; 00627 //-----------------Bloco de tentativas--------------------- 00628 uint16_t retentativas = maxRetentativas+1; 00629 uint16_t delayEntreTentativas = maxDelayEntreTentativas; 00630 while(retentativas){ 00631 //------------Bloco de construcao de frame request---------- 00632 00633 modBusMaster1::buffer[0]=enderecoSlave; 00634 modBusMaster1::buffer[1]=16; 00635 modBusMaster1::buffer[2]=registrador>>8; 00636 modBusMaster1::buffer[3]=(registrador & 0xFF); 00637 modBusMaster1::buffer[4]=qtdRegistros>>8; 00638 modBusMaster1::buffer[5]=(qtdRegistros & 0xFF); 00639 modBusMaster1::buffer[6]=qtdRegistros*4; 00640 00641 for(i=0;i<qtdRegistros;i++){ 00642 u.v = var[i]; 00643 modBusMaster1::buffer[(i*4)+7]=u.c[3]; 00644 modBusMaster1::buffer[(i*4)+8]=u.c[2]; 00645 modBusMaster1::buffer[(i*4)+9]=u.c[1]; 00646 modBusMaster1::buffer[(i*4)+10]=u.c[0]; 00647 } 00648 00649 crc=modBusMaster1::CRC16(modBusMaster1::buffer,((qtdRegistros)*4)+7); 00650 00651 modBusMaster1::buffer[(qtdRegistros*4)+7]=crc>>8;; 00652 modBusMaster1::buffer[(qtdRegistros*4)+8]=(crc & 0xFF); 00653 00654 //------------Bloco de construcao de frame request---------- 00655 if(!modBusMaster1::sendFrame((qtdRegistros*4)+9)){ 00656 osDelay(delayEntreTentativas); 00657 retentativas--; 00658 if(debug){ 00659 //DEBUG Mostrando o que é enviado via modbus 00660 pc.printf("Retentativa de comando modbus.\r\n"); 00661 } 00662 if(retentativas==0){ 00663 //erro de timeout certamente 00664 pc.printf("Erro de timeout.\n"); 00665 modBusMaster1::pacoteEmEspera = false; //Sinalizo que li o pacote 00666 modBusMaster1::index = 0; 00667 return 254; 00668 } 00669 }else{ 00670 //Chegou pacote, vamos ver se é valido 00671 retentativas = 0; 00672 } 00673 } 00674 if(!modBusMaster1::pacoteEmEsperaValido){ 00675 pc.printf("Erro de CRC.\n"); 00676 modBusMaster1::pacoteEmEspera = false; //Sinalizo que li o pacote 00677 modBusMaster1::index = 0; 00678 return 255; 00679 } 00680 //-----------------Bloco de tentativas--------------------- 00681 00682 00683 modBusMaster1::pacoteEmEspera = false; //Sinalizo que li o pacote 00684 modBusMaster1::index = 0; 00685 00686 if(modBusMaster1::buffer[1]&(0x1<<7)){ 00687 result = modBusMaster1::buffer[2]; 00688 }else{ 00689 //Interpratando resposta 00690 if(((modBusMaster1::buffer[4]<<8)+(modBusMaster1::buffer[5]))!=qtdRegistros){ 00691 return 253; 00692 }else{ 00693 result = 0; 00694 } 00695 } 00696 return result; 00697 } 00698 00699 uint8_t modBusMaster1::readFloat(uint8_t enderecoSlave,uint8_t funcao,uint16_t registrador,uint16_t qtdRegistros,float *var){ 00700 union { 00701 char c[4]; 00702 float v; 00703 }u; 00704 uint16_t crc; 00705 uint16_t qtd_dados_recebidos; 00706 //void *p; 00707 uint16_t i; 00708 uint8_t result; 00709 00710 for(i=0;i<qtdRegistros;i++){ 00711 var[i]=0.0; 00712 } 00713 00714 //-----------------Bloco de tentativas--------------------- 00715 uint16_t retentativas = maxRetentativas+1; 00716 uint16_t delayEntreTentativas = maxDelayEntreTentativas; 00717 while(retentativas){ 00718 //------------Bloco de construcao de frame request---------- 00719 00720 modBusMaster1::buffer[0]=enderecoSlave; 00721 modBusMaster1::buffer[1]=funcao; 00722 modBusMaster1::buffer[2]=registrador>>8; 00723 modBusMaster1::buffer[3]=(registrador & 0xFF); 00724 modBusMaster1::buffer[4]=qtdRegistros>>8; 00725 modBusMaster1::buffer[5]=(qtdRegistros & 0xFF); 00726 00727 crc=modBusMaster1::CRC16(modBusMaster1::buffer,6); 00728 00729 modBusMaster1::buffer[6]=crc>>8; 00730 modBusMaster1::buffer[7]=(crc & 0xFF); 00731 00732 //------------Bloco de construcao de frame request---------- 00733 if(!modBusMaster1::sendFrame(8)){ 00734 osDelay(delayEntreTentativas); 00735 retentativas--; 00736 if(debug){ 00737 //DEBUG Mostrando o que é enviado via modbus 00738 pc.printf("Retentativa de comando modbus.\r\n"); 00739 } 00740 if(retentativas==0){ 00741 //erro de timeout certamente 00742 pc.printf("Erro de timeout.\n"); 00743 modBusMaster1::pacoteEmEspera = false; //Sinalizo que li o pacote 00744 modBusMaster1::index = 0; 00745 return 254; 00746 } 00747 }else{ 00748 //Chegou pacote, vamos ver se é valido 00749 retentativas = 0; 00750 } 00751 } 00752 if(!modBusMaster1::pacoteEmEsperaValido){ 00753 pc.printf("Erro de CRC.\n"); 00754 modBusMaster1::pacoteEmEspera = false; //Sinalizo que li o pacote 00755 modBusMaster1::index = 0; 00756 return 255; 00757 } 00758 //-----------------Bloco de tentativas--------------------- 00759 00760 if(modBusMaster1::buffer[1]&(0x1<<7)){ 00761 result = modBusMaster1::buffer[2]; 00762 }else{ 00763 qtd_dados_recebidos = modBusMaster1::buffer[2]/4; 00764 for(i=0;i<qtd_dados_recebidos;i++){ 00765 u.c[3]=modBusMaster1::buffer[(i*4)+3]; 00766 u.c[2]=modBusMaster1::buffer[(i*4)+4]; 00767 u.c[1]=modBusMaster1::buffer[(i*4)+5]; 00768 u.c[0]=modBusMaster1::buffer[(i*4)+6]; 00769 var[i]=u.v; 00770 } 00771 result = 0; 00772 } 00773 modBusMaster1::pacoteEmEspera = false; //Sinalizo que li o pacote 00774 modBusMaster1::index = 0; 00775 return result; 00776 }
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