Bruno Cavalcanti / Mbed 2 deprecated brunoDrome

teste de publish

Dependencies:   DS1820 HighSpeedAnalogIn devices mbed

mbed-rtos/rtx/TARGET_CORTEX_A/rt_HAL_CA.h@38:07d3907b74e5, 2018-06-08 (annotated)

Committer:
brunofgc
Date:
Fri Jun 08 22:14:21 2018 +0000
Revision:
38:07d3907b74e5
Parent:
0:1c0a769988ee 
teste de publish para compilar no mbed-cli

Who changed what in which revision?

UserRevisionLine numberNew contents of line
brunofgc 0:1c0a769988ee 1 /*----------------------------------------------------------------------------
brunofgc 0:1c0a769988ee 2 * RL-ARM - RTX
brunofgc 0:1c0a769988ee 3 *----------------------------------------------------------------------------
brunofgc 0:1c0a769988ee 4 * Name: RT_HAL_CM.H
brunofgc 0:1c0a769988ee 5 * Purpose: Hardware Abstraction Layer for Cortex-A definitions
brunofgc 0:1c0a769988ee 6 * Rev.: 21 Aug 2013
brunofgc 0:1c0a769988ee 7 *----------------------------------------------------------------------------
brunofgc 0:1c0a769988ee 8 *
brunofgc 0:1c0a769988ee 9 * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
brunofgc 0:1c0a769988ee 10 * All rights reserved.
brunofgc 0:1c0a769988ee 11 * Redistribution and use in source and binary forms, with or without
brunofgc 0:1c0a769988ee 12 * modification, are permitted provided that the following conditions are met:
brunofgc 0:1c0a769988ee 13 * - Redistributions of source code must retain the above copyright
brunofgc 0:1c0a769988ee 14 * notice, this list of conditions and the following disclaimer.
brunofgc 0:1c0a769988ee 15 * - Redistributions in binary form must reproduce the above copyright
brunofgc 0:1c0a769988ee 16 * notice, this list of conditions and the following disclaimer in the
brunofgc 0:1c0a769988ee 17 * documentation and/or other materials provided with the distribution.
brunofgc 0:1c0a769988ee 18 * - Neither the name of ARM nor the names of its contributors may be used
brunofgc 0:1c0a769988ee 19 * to endorse or promote products derived from this software without
brunofgc 0:1c0a769988ee 20 * specific prior written permission.
brunofgc 0:1c0a769988ee 21 *
brunofgc 0:1c0a769988ee 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
brunofgc 0:1c0a769988ee 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
brunofgc 0:1c0a769988ee 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
brunofgc 0:1c0a769988ee 25 * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
brunofgc 0:1c0a769988ee 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
brunofgc 0:1c0a769988ee 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
brunofgc 0:1c0a769988ee 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
brunofgc 0:1c0a769988ee 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
brunofgc 0:1c0a769988ee 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
brunofgc 0:1c0a769988ee 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
brunofgc 0:1c0a769988ee 32 * POSSIBILITY OF SUCH DAMAGE.
brunofgc 0:1c0a769988ee 33 *---------------------------------------------------------------------------*/
brunofgc 0:1c0a769988ee 34
brunofgc 0:1c0a769988ee 35 /* Definitions */
brunofgc 0:1c0a769988ee 36 #define INIT_CPSR_SYS 0x4000001F
brunofgc 0:1c0a769988ee 37 #define INIT_CPSR_USER 0x40000010
brunofgc 0:1c0a769988ee 38
brunofgc 0:1c0a769988ee 39 #define CPSR_T_BIT 0x20
brunofgc 0:1c0a769988ee 40 #define CPSR_I_BIT 0x80
brunofgc 0:1c0a769988ee 41 #define CPSR_F_BIT 0x40
brunofgc 0:1c0a769988ee 42
brunofgc 0:1c0a769988ee 43 #define MODE_USR 0x10
brunofgc 0:1c0a769988ee 44 #define MODE_FIQ 0x11
brunofgc 0:1c0a769988ee 45 #define MODE_IRQ 0x12
brunofgc 0:1c0a769988ee 46 #define MODE_SVC 0x13
brunofgc 0:1c0a769988ee 47 #define MODE_ABT 0x17
brunofgc 0:1c0a769988ee 48 #define MODE_UND 0x1B
brunofgc 0:1c0a769988ee 49 #define MODE_SYS 0x1F
brunofgc 0:1c0a769988ee 50
brunofgc 0:1c0a769988ee 51 #define MAGIC_WORD 0xE25A2EA5
brunofgc 0:1c0a769988ee 52
brunofgc 0:1c0a769988ee 53 #include "core_ca9.h"
brunofgc 0:1c0a769988ee 54
brunofgc 0:1c0a769988ee 55 #if defined (__CC_ARM) /* ARM Compiler */
brunofgc 0:1c0a769988ee 56
brunofgc 0:1c0a769988ee 57 #if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M || __TARGET_ARCH_7_A) && !NO_EXCLUSIVE_ACCESS)
brunofgc 0:1c0a769988ee 58 #define __USE_EXCLUSIVE_ACCESS
brunofgc 0:1c0a769988ee 59 #else
brunofgc 0:1c0a769988ee 60 #undef __USE_EXCLUSIVE_ACCESS
brunofgc 0:1c0a769988ee 61 #endif
brunofgc 0:1c0a769988ee 62
brunofgc 0:1c0a769988ee 63 #elif defined (__GNUC__) /* GNU Compiler */
brunofgc 0:1c0a769988ee 64
brunofgc 0:1c0a769988ee 65 #error GNU Compiler support not implemented for Cortex-A
brunofgc 0:1c0a769988ee 66
brunofgc 0:1c0a769988ee 67 #elif defined (__ICCARM__) /* IAR Compiler */
brunofgc 0:1c0a769988ee 68
brunofgc 0:1c0a769988ee 69 #error IAR Compiler support not implemented for Cortex-A
brunofgc 0:1c0a769988ee 70
brunofgc 0:1c0a769988ee 71 #endif
brunofgc 0:1c0a769988ee 72
brunofgc 0:1c0a769988ee 73 static U8 priority = 0xff;
brunofgc 0:1c0a769988ee 74
brunofgc 0:1c0a769988ee 75 extern const U32 GICDistributor_BASE;
brunofgc 0:1c0a769988ee 76 extern const U32 GICInterface_BASE;
brunofgc 0:1c0a769988ee 77
brunofgc 0:1c0a769988ee 78 /* GIC registers - Distributor */
brunofgc 0:1c0a769988ee 79 #define GICD_ICDICER0 (*((volatile U32 *)(GICDistributor_BASE + 0x180))) /* - RW - Interrupt Clear-Enable Registers */
brunofgc 0:1c0a769988ee 80 #define GICD_ICDISER0 (*((volatile U32 *)(GICDistributor_BASE + 0x100))) /* - RW - Interrupt Set-Enable Registers */
brunofgc 0:1c0a769988ee 81 #define GICD_ICDIPR0 (*((volatile U32 *)(GICDistributor_BASE + 0x400))) /* - RW - Interrupt Priority Registers */
brunofgc 0:1c0a769988ee 82 #define GICD_ICDSGIR (*((volatile U32 *)(GICDistributor_BASE + 0xf00))) /* - RW - Interrupt Software Interrupt Register */
brunofgc 0:1c0a769988ee 83 #define GICD_ICDICERx(irq) *(volatile U32 *)(&GICD_ICDICER0 + irq/32)
brunofgc 0:1c0a769988ee 84 #define GICD_ICDISERx(irq) *(volatile U32 *)(&GICD_ICDISER0 + irq/32)
brunofgc 0:1c0a769988ee 85
brunofgc 0:1c0a769988ee 86 /* GIC register - CPU Interface */
brunofgc 0:1c0a769988ee 87 #define GICI_ICCPMR (*((volatile U32 *)(GICInterface_BASE + 0x004))) /* - RW - Interrupt Priority Mask Register */
brunofgc 0:1c0a769988ee 88
brunofgc 0:1c0a769988ee 89 #define SGI_PENDSV 0 /* SGI0 */
brunofgc 0:1c0a769988ee 90 #define SGI_PENDSV_BIT ((U32)(1 << (SGI_PENDSV & 0xf)))
brunofgc 0:1c0a769988ee 91
brunofgc 0:1c0a769988ee 92 //Increase priority filter to prevent timer and PendSV interrupts signaling. Guarantees that interrupts will not be forwarded.
brunofgc 0:1c0a769988ee 93 #define OS_LOCK() int irq_dis = __disable_irq();\
brunofgc 0:1c0a769988ee 94 priority = GICI_ICCPMR; \
brunofgc 0:1c0a769988ee 95 GICI_ICCPMR = 0xff; \
brunofgc 0:1c0a769988ee 96 GICI_ICCPMR = GICI_ICCPMR - 1; \
brunofgc 0:1c0a769988ee 97 while(GICI_ICCPMR > priority);\
brunofgc 0:1c0a769988ee 98 __DSB();\
brunofgc 0:1c0a769988ee 99 if(!irq_dis) __enable_irq(); \
brunofgc 0:1c0a769988ee 100
brunofgc 0:1c0a769988ee 101 //Restore priority filter. Re-enable timer and PendSV signaling
brunofgc 0:1c0a769988ee 102 #define OS_UNLOCK() __DSB(); \
brunofgc 0:1c0a769988ee 103 GICI_ICCPMR = priority; \
brunofgc 0:1c0a769988ee 104
brunofgc 0:1c0a769988ee 105 #define OS_PEND_IRQ() GICD_ICDSGIR = 0x0010000 | SGI_PENDSV
brunofgc 0:1c0a769988ee 106 #define OS_PEND(fl,p) if(p) OS_PEND_IRQ();
brunofgc 0:1c0a769988ee 107 #define OS_UNPEND(fl)
brunofgc 0:1c0a769988ee 108
brunofgc 0:1c0a769988ee 109 /* HW initialization needs to be done in os_tick_init (void) -RTX_Conf_CM.c-
brunofgc 0:1c0a769988ee 110 * OS_X_INIT enables the IRQ n in the GIC */
brunofgc 0:1c0a769988ee 111 #define OS_X_INIT(n) volatile char *reg; \
brunofgc 0:1c0a769988ee 112 reg = (char *)(&GICD_ICDIPR0 + n / 4); \
brunofgc 0:1c0a769988ee 113 reg += n % 4; \
brunofgc 0:1c0a769988ee 114 *reg = (char)0xff; \
brunofgc 0:1c0a769988ee 115 *reg = *reg - 1; \
brunofgc 0:1c0a769988ee 116 GICD_ICDISERx(n) = (U32)(1 << n % 32);
brunofgc 0:1c0a769988ee 117 #define OS_X_LOCK(n) OS_LOCK()
brunofgc 0:1c0a769988ee 118 #define OS_X_UNLOCK(n) OS_UNLOCK()
brunofgc 0:1c0a769988ee 119 #define OS_X_PEND_IRQ() OS_PEND_IRQ()
brunofgc 0:1c0a769988ee 120 #define OS_X_PEND(fl,p) if(p) OS_X_PEND_IRQ();
brunofgc 0:1c0a769988ee 121 #define OS_X_UNPEND(fl)
brunofgc 0:1c0a769988ee 122
brunofgc 0:1c0a769988ee 123
brunofgc 0:1c0a769988ee 124 /* Functions */
brunofgc 0:1c0a769988ee 125 #ifdef __USE_EXCLUSIVE_ACCESS
brunofgc 0:1c0a769988ee 126 #define rt_inc(p) while(__strex((__ldrex(p)+1),p))
brunofgc 0:1c0a769988ee 127 #define rt_dec(p) while(__strex((__ldrex(p)-1),p))
brunofgc 0:1c0a769988ee 128 #else
brunofgc 0:1c0a769988ee 129 #define rt_inc(p) { int irq_dis = __disable_irq();(*p)++;if(!irq_dis) __enable_irq(); }
brunofgc 0:1c0a769988ee 130 #define rt_dec(p) { int irq_dis = __disable_irq();(*p)--;if(!irq_dis) __enable_irq(); }
brunofgc 0:1c0a769988ee 131 #endif
brunofgc 0:1c0a769988ee 132
brunofgc 0:1c0a769988ee 133 __inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
brunofgc 0:1c0a769988ee 134 U32 cnt,c2;
brunofgc 0:1c0a769988ee 135 #ifdef __USE_EXCLUSIVE_ACCESS
brunofgc 0:1c0a769988ee 136 do {
brunofgc 0:1c0a769988ee 137 if ((cnt = __ldrex(count)) == size) {
brunofgc 0:1c0a769988ee 138 __clrex();
brunofgc 0:1c0a769988ee 139 return (cnt); }
brunofgc 0:1c0a769988ee 140 } while (__strex(cnt+1, count));
brunofgc 0:1c0a769988ee 141 do {
brunofgc 0:1c0a769988ee 142 c2 = (cnt = __ldrex(first)) + 1;
brunofgc 0:1c0a769988ee 143 if (c2 == size) c2 = 0;
brunofgc 0:1c0a769988ee 144 } while (__strex(c2, first));
brunofgc 0:1c0a769988ee 145 #else
brunofgc 0:1c0a769988ee 146 int irq_dis;
brunofgc 0:1c0a769988ee 147 irq_dis = __disable_irq();
brunofgc 0:1c0a769988ee 148 if ((cnt = *count) < size) {
brunofgc 0:1c0a769988ee 149 *count = cnt+1;
brunofgc 0:1c0a769988ee 150 c2 = (cnt = *first) + 1;
brunofgc 0:1c0a769988ee 151 if (c2 == size) c2 = 0;
brunofgc 0:1c0a769988ee 152 *first = c2;
brunofgc 0:1c0a769988ee 153 }
brunofgc 0:1c0a769988ee 154 if(!irq_dis) __enable_irq ();
brunofgc 0:1c0a769988ee 155 #endif
brunofgc 0:1c0a769988ee 156 return (cnt);
brunofgc 0:1c0a769988ee 157 }
brunofgc 0:1c0a769988ee 158
brunofgc 0:1c0a769988ee 159 __inline static void rt_systick_init (void) {
brunofgc 0:1c0a769988ee 160 /* Cortex-A doesn't have a Systick. User needs to provide an alternative timer using RTX_Conf_CM configuration */
brunofgc 0:1c0a769988ee 161 /* HW initialization needs to be done in os_tick_init (void) -RTX_Conf_CM.c- */
brunofgc 0:1c0a769988ee 162 }
brunofgc 0:1c0a769988ee 163
brunofgc 0:1c0a769988ee 164 __inline static void rt_svc_init (void) {
brunofgc 0:1c0a769988ee 165 /* Register pendSV - through SGI */
brunofgc 0:1c0a769988ee 166 volatile char *reg;
brunofgc 0:1c0a769988ee 167
brunofgc 0:1c0a769988ee 168 reg = (char *)(&GICD_ICDIPR0 + SGI_PENDSV/4);
brunofgc 0:1c0a769988ee 169 reg += SGI_PENDSV % 4;
brunofgc 0:1c0a769988ee 170 /* Write 0xff to read priority level */
brunofgc 0:1c0a769988ee 171 *reg = (char)0xff;
brunofgc 0:1c0a769988ee 172 /* Read priority level and set the lowest possible*/
brunofgc 0:1c0a769988ee 173 *reg = *reg - 1;
brunofgc 0:1c0a769988ee 174
brunofgc 0:1c0a769988ee 175 GICD_ICDISERx(SGI_PENDSV) = (U32)SGI_PENDSV_BIT;
brunofgc 0:1c0a769988ee 176 }
brunofgc 0:1c0a769988ee 177
brunofgc 0:1c0a769988ee 178 extern void rt_set_PSP (U32 stack);
brunofgc 0:1c0a769988ee 179 extern U32 rt_get_PSP (void);
brunofgc 0:1c0a769988ee 180 extern void os_set_env (P_TCB p_TCB);
brunofgc 0:1c0a769988ee 181 extern void *_alloc_box (void *box_mem);
brunofgc 0:1c0a769988ee 182 extern int _free_box (void *box_mem, void *box);
brunofgc 0:1c0a769988ee 183
brunofgc 0:1c0a769988ee 184 extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
brunofgc 0:1c0a769988ee 185 extern void rt_ret_val (P_TCB p_TCB, U32 v0);
brunofgc 0:1c0a769988ee 186 extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1);
brunofgc 0:1c0a769988ee 187
brunofgc 0:1c0a769988ee 188 extern void dbg_init (void);
brunofgc 0:1c0a769988ee 189 extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
brunofgc 0:1c0a769988ee 190 extern void dbg_task_switch (U32 task_id);
brunofgc 0:1c0a769988ee 191
brunofgc 0:1c0a769988ee 192 #define DBG_INIT()
brunofgc 0:1c0a769988ee 193 #define DBG_TASK_NOTIFY(p_tcb,create)
brunofgc 0:1c0a769988ee 194 #define DBG_TASK_SWITCH(task_id)
brunofgc 0:1c0a769988ee 195
brunofgc 0:1c0a769988ee 196 /*----------------------------------------------------------------------------
brunofgc 0:1c0a769988ee 197 * end of file
brunofgc 0:1c0a769988ee 198 *---------------------------------------------------------------------------*/
brunofgc 0:1c0a769988ee 199