Nicolas Borla
/
BBR_1Ebene
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mbed-os/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_system.h@0:fbdae7e6d805, 2018-05-14 (annotated)
- Committer:
- borlanic
- Date:
- Mon May 14 11:29:06 2018 +0000
- Revision:
- 0:fbdae7e6d805
BBR
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| borlanic | 0:fbdae7e6d805 | 1 | /** |
| borlanic | 0:fbdae7e6d805 | 2 | ****************************************************************************** |
| borlanic | 0:fbdae7e6d805 | 3 | * @file stm32l1xx_ll_system.h |
| borlanic | 0:fbdae7e6d805 | 4 | * @author MCD Application Team |
| borlanic | 0:fbdae7e6d805 | 5 | * @brief Header file of SYSTEM LL module. |
| borlanic | 0:fbdae7e6d805 | 6 | @verbatim |
| borlanic | 0:fbdae7e6d805 | 7 | ============================================================================== |
| borlanic | 0:fbdae7e6d805 | 8 | ##### How to use this driver ##### |
| borlanic | 0:fbdae7e6d805 | 9 | ============================================================================== |
| borlanic | 0:fbdae7e6d805 | 10 | [..] |
| borlanic | 0:fbdae7e6d805 | 11 | The LL SYSTEM driver contains a set of generic APIs that can be |
| borlanic | 0:fbdae7e6d805 | 12 | used by user: |
| borlanic | 0:fbdae7e6d805 | 13 | (+) Some of the FLASH features need to be handled in the SYSTEM file. |
| borlanic | 0:fbdae7e6d805 | 14 | (+) Access to DBGCMU registers |
| borlanic | 0:fbdae7e6d805 | 15 | (+) Access to SYSCFG registers |
| borlanic | 0:fbdae7e6d805 | 16 | (+) Access to Routing Interfaces registers |
| borlanic | 0:fbdae7e6d805 | 17 | |
| borlanic | 0:fbdae7e6d805 | 18 | @endverbatim |
| borlanic | 0:fbdae7e6d805 | 19 | ****************************************************************************** |
| borlanic | 0:fbdae7e6d805 | 20 | * @attention |
| borlanic | 0:fbdae7e6d805 | 21 | * |
| borlanic | 0:fbdae7e6d805 | 22 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| borlanic | 0:fbdae7e6d805 | 23 | * |
| borlanic | 0:fbdae7e6d805 | 24 | * Redistribution and use in source and binary forms, with or without modification, |
| borlanic | 0:fbdae7e6d805 | 25 | * are permitted provided that the following conditions are met: |
| borlanic | 0:fbdae7e6d805 | 26 | * 1. Redistributions of source code must retain the above copyright notice, |
| borlanic | 0:fbdae7e6d805 | 27 | * this list of conditions and the following disclaimer. |
| borlanic | 0:fbdae7e6d805 | 28 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| borlanic | 0:fbdae7e6d805 | 29 | * this list of conditions and the following disclaimer in the documentation |
| borlanic | 0:fbdae7e6d805 | 30 | * and/or other materials provided with the distribution. |
| borlanic | 0:fbdae7e6d805 | 31 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| borlanic | 0:fbdae7e6d805 | 32 | * may be used to endorse or promote products derived from this software |
| borlanic | 0:fbdae7e6d805 | 33 | * without specific prior written permission. |
| borlanic | 0:fbdae7e6d805 | 34 | * |
| borlanic | 0:fbdae7e6d805 | 35 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| borlanic | 0:fbdae7e6d805 | 36 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| borlanic | 0:fbdae7e6d805 | 37 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| borlanic | 0:fbdae7e6d805 | 38 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| borlanic | 0:fbdae7e6d805 | 39 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| borlanic | 0:fbdae7e6d805 | 40 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| borlanic | 0:fbdae7e6d805 | 41 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| borlanic | 0:fbdae7e6d805 | 42 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| borlanic | 0:fbdae7e6d805 | 43 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| borlanic | 0:fbdae7e6d805 | 44 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| borlanic | 0:fbdae7e6d805 | 45 | * |
| borlanic | 0:fbdae7e6d805 | 46 | ****************************************************************************** |
| borlanic | 0:fbdae7e6d805 | 47 | */ |
| borlanic | 0:fbdae7e6d805 | 48 | |
| borlanic | 0:fbdae7e6d805 | 49 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| borlanic | 0:fbdae7e6d805 | 50 | #ifndef __STM32L1xx_LL_SYSTEM_H |
| borlanic | 0:fbdae7e6d805 | 51 | #define __STM32L1xx_LL_SYSTEM_H |
| borlanic | 0:fbdae7e6d805 | 52 | |
| borlanic | 0:fbdae7e6d805 | 53 | #ifdef __cplusplus |
| borlanic | 0:fbdae7e6d805 | 54 | extern "C" { |
| borlanic | 0:fbdae7e6d805 | 55 | #endif |
| borlanic | 0:fbdae7e6d805 | 56 | |
| borlanic | 0:fbdae7e6d805 | 57 | /* Includes ------------------------------------------------------------------*/ |
| borlanic | 0:fbdae7e6d805 | 58 | #include "stm32l1xx.h" |
| borlanic | 0:fbdae7e6d805 | 59 | |
| borlanic | 0:fbdae7e6d805 | 60 | /** @addtogroup STM32L1xx_LL_Driver |
| borlanic | 0:fbdae7e6d805 | 61 | * @{ |
| borlanic | 0:fbdae7e6d805 | 62 | */ |
| borlanic | 0:fbdae7e6d805 | 63 | |
| borlanic | 0:fbdae7e6d805 | 64 | #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined(RI) |
| borlanic | 0:fbdae7e6d805 | 65 | |
| borlanic | 0:fbdae7e6d805 | 66 | /** @defgroup SYSTEM_LL SYSTEM |
| borlanic | 0:fbdae7e6d805 | 67 | * @{ |
| borlanic | 0:fbdae7e6d805 | 68 | */ |
| borlanic | 0:fbdae7e6d805 | 69 | |
| borlanic | 0:fbdae7e6d805 | 70 | /* Private types -------------------------------------------------------------*/ |
| borlanic | 0:fbdae7e6d805 | 71 | /* Private variables ---------------------------------------------------------*/ |
| borlanic | 0:fbdae7e6d805 | 72 | |
| borlanic | 0:fbdae7e6d805 | 73 | /* Private constants ---------------------------------------------------------*/ |
| borlanic | 0:fbdae7e6d805 | 74 | /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants |
| borlanic | 0:fbdae7e6d805 | 75 | * @{ |
| borlanic | 0:fbdae7e6d805 | 76 | */ |
| borlanic | 0:fbdae7e6d805 | 77 | |
| borlanic | 0:fbdae7e6d805 | 78 | /** |
| borlanic | 0:fbdae7e6d805 | 79 | * @brief Power-down in Run mode Flash key |
| borlanic | 0:fbdae7e6d805 | 80 | */ |
| borlanic | 0:fbdae7e6d805 | 81 | #define FLASH_PDKEY1 (0x04152637U) /*!< Flash power down key1 */ |
| borlanic | 0:fbdae7e6d805 | 82 | #define FLASH_PDKEY2 (0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1 |
| borlanic | 0:fbdae7e6d805 | 83 | to unlock the RUN_PD bit in FLASH_ACR */ |
| borlanic | 0:fbdae7e6d805 | 84 | |
| borlanic | 0:fbdae7e6d805 | 85 | /** |
| borlanic | 0:fbdae7e6d805 | 86 | * @} |
| borlanic | 0:fbdae7e6d805 | 87 | */ |
| borlanic | 0:fbdae7e6d805 | 88 | |
| borlanic | 0:fbdae7e6d805 | 89 | /* Private macros ------------------------------------------------------------*/ |
| borlanic | 0:fbdae7e6d805 | 90 | |
| borlanic | 0:fbdae7e6d805 | 91 | /* Exported types ------------------------------------------------------------*/ |
| borlanic | 0:fbdae7e6d805 | 92 | /* Exported constants --------------------------------------------------------*/ |
| borlanic | 0:fbdae7e6d805 | 93 | /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants |
| borlanic | 0:fbdae7e6d805 | 94 | * @{ |
| borlanic | 0:fbdae7e6d805 | 95 | */ |
| borlanic | 0:fbdae7e6d805 | 96 | |
| borlanic | 0:fbdae7e6d805 | 97 | /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP |
| borlanic | 0:fbdae7e6d805 | 98 | * @{ |
| borlanic | 0:fbdae7e6d805 | 99 | */ |
| borlanic | 0:fbdae7e6d805 | 100 | #define LL_SYSCFG_REMAP_FLASH (0x00000000U) /*<! Main Flash memory mapped at 0x00000000 */ |
| borlanic | 0:fbdae7e6d805 | 101 | #define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /*<! System Flash memory mapped at 0x00000000 */ |
| borlanic | 0:fbdae7e6d805 | 102 | #define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*<! Embedded SRAM mapped at 0x00000000 */ |
| borlanic | 0:fbdae7e6d805 | 103 | #if defined(FSMC_R_BASE) |
| borlanic | 0:fbdae7e6d805 | 104 | #define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1 /*<! FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 */ |
| borlanic | 0:fbdae7e6d805 | 105 | #endif /* FSMC_R_BASE */ |
| borlanic | 0:fbdae7e6d805 | 106 | /** |
| borlanic | 0:fbdae7e6d805 | 107 | * @} |
| borlanic | 0:fbdae7e6d805 | 108 | */ |
| borlanic | 0:fbdae7e6d805 | 109 | |
| borlanic | 0:fbdae7e6d805 | 110 | /** @defgroup SYSTEM_LL_EC_BOOT SYSCFG BOOT MODE |
| borlanic | 0:fbdae7e6d805 | 111 | * @{ |
| borlanic | 0:fbdae7e6d805 | 112 | */ |
| borlanic | 0:fbdae7e6d805 | 113 | #define LL_SYSCFG_BOOTMODE_FLASH (0x00000000U) /*<! Main Flash memory boot mode */ |
| borlanic | 0:fbdae7e6d805 | 114 | #define LL_SYSCFG_BOOTMODE_SYSTEMFLASH SYSCFG_MEMRMP_BOOT_MODE_0 /*<! System Flash memory boot mode */ |
| borlanic | 0:fbdae7e6d805 | 115 | #if defined(FSMC_BANK1) |
| borlanic | 0:fbdae7e6d805 | 116 | #define LL_SYSCFG_BOOTMODE_FSMC SYSCFG_MEMRMP_BOOT_MODE_1 /*<! FSMC boot mode */ |
| borlanic | 0:fbdae7e6d805 | 117 | #endif /* FSMC_BANK1 */ |
| borlanic | 0:fbdae7e6d805 | 118 | #define LL_SYSCFG_BOOTMODE_SRAM SYSCFG_MEMRMP_BOOT_MODE /*<! Embedded SRAM boot mode */ |
| borlanic | 0:fbdae7e6d805 | 119 | /** |
| borlanic | 0:fbdae7e6d805 | 120 | * @} |
| borlanic | 0:fbdae7e6d805 | 121 | */ |
| borlanic | 0:fbdae7e6d805 | 122 | |
| borlanic | 0:fbdae7e6d805 | 123 | #if defined(LCD) |
| borlanic | 0:fbdae7e6d805 | 124 | /** @defgroup SYSTEM_LL_EC_LCDCAPA SYSCFG LCD capacitance connection |
| borlanic | 0:fbdae7e6d805 | 125 | * @{ |
| borlanic | 0:fbdae7e6d805 | 126 | */ |
| borlanic | 0:fbdae7e6d805 | 127 | #define LL_SYSCFG_LCDCAPA_PB2 SYSCFG_PMC_LCD_CAPA_0 /*<! controls the connection of VLCDrail2 on PB2/LCD_VCAP2 */ |
| borlanic | 0:fbdae7e6d805 | 128 | #define LL_SYSCFG_LCDCAPA_PB12 SYSCFG_PMC_LCD_CAPA_1 /*<! controls the connection of VLCDrail1 on PB12/LCD_VCAP1 */ |
| borlanic | 0:fbdae7e6d805 | 129 | #define LL_SYSCFG_LCDCAPA_PB0 SYSCFG_PMC_LCD_CAPA_2 /*<! controls the connection of VLCDrail3 on PB0/LCD_VCAP3 */ |
| borlanic | 0:fbdae7e6d805 | 130 | #define LL_SYSCFG_LCDCAPA_PE11 SYSCFG_PMC_LCD_CAPA_3 /*<! controls the connection of VLCDrail1 on PE11/LCD_VCAP1 */ |
| borlanic | 0:fbdae7e6d805 | 131 | #define LL_SYSCFG_LCDCAPA_PE12 SYSCFG_PMC_LCD_CAPA_4 /*<! controls the connection of VLCDrail3 on PE12/LCD_VCAP3 */ |
| borlanic | 0:fbdae7e6d805 | 132 | /** |
| borlanic | 0:fbdae7e6d805 | 133 | * @} |
| borlanic | 0:fbdae7e6d805 | 134 | */ |
| borlanic | 0:fbdae7e6d805 | 135 | |
| borlanic | 0:fbdae7e6d805 | 136 | #endif /* LCD */ |
| borlanic | 0:fbdae7e6d805 | 137 | |
| borlanic | 0:fbdae7e6d805 | 138 | /** @defgroup SYSTEM_LL_EC_EXTI SYSCFG EXTI PORT |
| borlanic | 0:fbdae7e6d805 | 139 | * @{ |
| borlanic | 0:fbdae7e6d805 | 140 | */ |
| borlanic | 0:fbdae7e6d805 | 141 | #define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */ |
| borlanic | 0:fbdae7e6d805 | 142 | #define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */ |
| borlanic | 0:fbdae7e6d805 | 143 | #define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */ |
| borlanic | 0:fbdae7e6d805 | 144 | #define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */ |
| borlanic | 0:fbdae7e6d805 | 145 | #if defined(GPIOE) |
| borlanic | 0:fbdae7e6d805 | 146 | #define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */ |
| borlanic | 0:fbdae7e6d805 | 147 | #endif /* GPIOE */ |
| borlanic | 0:fbdae7e6d805 | 148 | #if defined(GPIOF) |
| borlanic | 0:fbdae7e6d805 | 149 | #define LL_SYSCFG_EXTI_PORTF 6U /*!< EXTI PORT F */ |
| borlanic | 0:fbdae7e6d805 | 150 | #endif /* GPIOF */ |
| borlanic | 0:fbdae7e6d805 | 151 | #if defined(GPIOG) |
| borlanic | 0:fbdae7e6d805 | 152 | #define LL_SYSCFG_EXTI_PORTG 7U /*!< EXTI PORT G */ |
| borlanic | 0:fbdae7e6d805 | 153 | #endif /* GPIOG */ |
| borlanic | 0:fbdae7e6d805 | 154 | #define LL_SYSCFG_EXTI_PORTH 5U /*!< EXTI PORT H */ |
| borlanic | 0:fbdae7e6d805 | 155 | /** |
| borlanic | 0:fbdae7e6d805 | 156 | * @} |
| borlanic | 0:fbdae7e6d805 | 157 | */ |
| borlanic | 0:fbdae7e6d805 | 158 | |
| borlanic | 0:fbdae7e6d805 | 159 | /** @addtogroup SYSTEM_LL_EC_SYSCFG EXTI LINE |
| borlanic | 0:fbdae7e6d805 | 160 | * @{ |
| borlanic | 0:fbdae7e6d805 | 161 | */ |
| borlanic | 0:fbdae7e6d805 | 162 | #define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16U | 0U) /* EXTI_POSITION_0 | EXTICR[0] */ |
| borlanic | 0:fbdae7e6d805 | 163 | #define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16U | 0U) /* EXTI_POSITION_4 | EXTICR[0] */ |
| borlanic | 0:fbdae7e6d805 | 164 | #define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16U | 0U) /* EXTI_POSITION_8 | EXTICR[0] */ |
| borlanic | 0:fbdae7e6d805 | 165 | #define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16U | 0U) /* EXTI_POSITION_12 | EXTICR[0] */ |
| borlanic | 0:fbdae7e6d805 | 166 | #define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16U | 1U) /* EXTI_POSITION_0 | EXTICR[1] */ |
| borlanic | 0:fbdae7e6d805 | 167 | #define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16U | 1U) /* EXTI_POSITION_4 | EXTICR[1] */ |
| borlanic | 0:fbdae7e6d805 | 168 | #define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16U | 1U) /* EXTI_POSITION_8 | EXTICR[1] */ |
| borlanic | 0:fbdae7e6d805 | 169 | #define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16U | 1U) /* EXTI_POSITION_12 | EXTICR[1] */ |
| borlanic | 0:fbdae7e6d805 | 170 | #define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16U | 2U) /* EXTI_POSITION_0 | EXTICR[2] */ |
| borlanic | 0:fbdae7e6d805 | 171 | #define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16U | 2U) /* EXTI_POSITION_4 | EXTICR[2] */ |
| borlanic | 0:fbdae7e6d805 | 172 | #define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16U | 2U) /* EXTI_POSITION_8 | EXTICR[2] */ |
| borlanic | 0:fbdae7e6d805 | 173 | #define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16U | 2U) /* EXTI_POSITION_12 | EXTICR[2] */ |
| borlanic | 0:fbdae7e6d805 | 174 | #define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16U | 3U) /* EXTI_POSITION_0 | EXTICR[3] */ |
| borlanic | 0:fbdae7e6d805 | 175 | #define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16U | 3U) /* EXTI_POSITION_4 | EXTICR[3] */ |
| borlanic | 0:fbdae7e6d805 | 176 | #define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16U | 3U) /* EXTI_POSITION_8 | EXTICR[3] */ |
| borlanic | 0:fbdae7e6d805 | 177 | #define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16U | 3U) /* EXTI_POSITION_12 | EXTICR[3] */ |
| borlanic | 0:fbdae7e6d805 | 178 | /** |
| borlanic | 0:fbdae7e6d805 | 179 | * @} |
| borlanic | 0:fbdae7e6d805 | 180 | */ |
| borlanic | 0:fbdae7e6d805 | 181 | |
| borlanic | 0:fbdae7e6d805 | 182 | /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment |
| borlanic | 0:fbdae7e6d805 | 183 | * @{ |
| borlanic | 0:fbdae7e6d805 | 184 | */ |
| borlanic | 0:fbdae7e6d805 | 185 | #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */ |
| borlanic | 0:fbdae7e6d805 | 186 | #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */ |
| borlanic | 0:fbdae7e6d805 | 187 | #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */ |
| borlanic | 0:fbdae7e6d805 | 188 | #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */ |
| borlanic | 0:fbdae7e6d805 | 189 | #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */ |
| borlanic | 0:fbdae7e6d805 | 190 | /** |
| borlanic | 0:fbdae7e6d805 | 191 | * @} |
| borlanic | 0:fbdae7e6d805 | 192 | */ |
| borlanic | 0:fbdae7e6d805 | 193 | |
| borlanic | 0:fbdae7e6d805 | 194 | /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP |
| borlanic | 0:fbdae7e6d805 | 195 | * @{ |
| borlanic | 0:fbdae7e6d805 | 196 | */ |
| borlanic | 0:fbdae7e6d805 | 197 | #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */ |
| borlanic | 0:fbdae7e6d805 | 198 | #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */ |
| borlanic | 0:fbdae7e6d805 | 199 | #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */ |
| borlanic | 0:fbdae7e6d805 | 200 | #if defined (DBGMCU_APB1_FZ_DBG_TIM5_STOP) |
| borlanic | 0:fbdae7e6d805 | 201 | #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */ |
| borlanic | 0:fbdae7e6d805 | 202 | #endif /* DBGMCU_APB1_FZ_DBG_TIM5_STOP */ |
| borlanic | 0:fbdae7e6d805 | 203 | #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */ |
| borlanic | 0:fbdae7e6d805 | 204 | #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */ |
| borlanic | 0:fbdae7e6d805 | 205 | #if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP) |
| borlanic | 0:fbdae7e6d805 | 206 | #define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC Counter stopped when Core is halted */ |
| borlanic | 0:fbdae7e6d805 | 207 | #endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */ |
| borlanic | 0:fbdae7e6d805 | 208 | #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */ |
| borlanic | 0:fbdae7e6d805 | 209 | #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */ |
| borlanic | 0:fbdae7e6d805 | 210 | #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ |
| borlanic | 0:fbdae7e6d805 | 211 | #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */ |
| borlanic | 0:fbdae7e6d805 | 212 | /** |
| borlanic | 0:fbdae7e6d805 | 213 | * @} |
| borlanic | 0:fbdae7e6d805 | 214 | */ |
| borlanic | 0:fbdae7e6d805 | 215 | |
| borlanic | 0:fbdae7e6d805 | 216 | /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP |
| borlanic | 0:fbdae7e6d805 | 217 | * @{ |
| borlanic | 0:fbdae7e6d805 | 218 | */ |
| borlanic | 0:fbdae7e6d805 | 219 | #define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */ |
| borlanic | 0:fbdae7e6d805 | 220 | #define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */ |
| borlanic | 0:fbdae7e6d805 | 221 | #define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */ |
| borlanic | 0:fbdae7e6d805 | 222 | /** |
| borlanic | 0:fbdae7e6d805 | 223 | * @} |
| borlanic | 0:fbdae7e6d805 | 224 | */ |
| borlanic | 0:fbdae7e6d805 | 225 | |
| borlanic | 0:fbdae7e6d805 | 226 | /** @defgroup SYSTEM_LL_EC_TIM_SELECT RI TIM selection |
| borlanic | 0:fbdae7e6d805 | 227 | * @{ |
| borlanic | 0:fbdae7e6d805 | 228 | */ |
| borlanic | 0:fbdae7e6d805 | 229 | #define LL_RI_TIM_SELECT_NONE (0x00000000U) /*!< No timer selected */ |
| borlanic | 0:fbdae7e6d805 | 230 | #define LL_RI_TIM_SELECT_TIM2 RI_ICR_TIM_0 /*!< Timer 2 selected */ |
| borlanic | 0:fbdae7e6d805 | 231 | #define LL_RI_TIM_SELECT_TIM3 RI_ICR_TIM_1 /*!< Timer 3 selected */ |
| borlanic | 0:fbdae7e6d805 | 232 | #define LL_RI_TIM_SELECT_TIM4 RI_ICR_TIM /*!< Timer 4 selected */ |
| borlanic | 0:fbdae7e6d805 | 233 | /** |
| borlanic | 0:fbdae7e6d805 | 234 | * @} |
| borlanic | 0:fbdae7e6d805 | 235 | */ |
| borlanic | 0:fbdae7e6d805 | 236 | |
| borlanic | 0:fbdae7e6d805 | 237 | /** @defgroup SYSTEM_LL_EC_INPUTCAPTURE RI Input Capture number |
| borlanic | 0:fbdae7e6d805 | 238 | * @{ |
| borlanic | 0:fbdae7e6d805 | 239 | */ |
| borlanic | 0:fbdae7e6d805 | 240 | #define LL_RI_INPUTCAPTURE_1 (RI_ICR_IC1 | RI_ICR_IC1OS) /*!< Input Capture 1 select output */ |
| borlanic | 0:fbdae7e6d805 | 241 | #define LL_RI_INPUTCAPTURE_2 (RI_ICR_IC2 | RI_ICR_IC2OS) /*!< Input Capture 2 select output */ |
| borlanic | 0:fbdae7e6d805 | 242 | #define LL_RI_INPUTCAPTURE_3 (RI_ICR_IC3 | RI_ICR_IC3OS) /*!< Input Capture 3 select output */ |
| borlanic | 0:fbdae7e6d805 | 243 | #define LL_RI_INPUTCAPTURE_4 (RI_ICR_IC4 | RI_ICR_IC4OS) /*!< Input Capture 4 select output */ |
| borlanic | 0:fbdae7e6d805 | 244 | /** |
| borlanic | 0:fbdae7e6d805 | 245 | * @} |
| borlanic | 0:fbdae7e6d805 | 246 | */ |
| borlanic | 0:fbdae7e6d805 | 247 | |
| borlanic | 0:fbdae7e6d805 | 248 | /** @defgroup SYSTEM_LL_EC_INPUTCAPTUREROUTING RI Input Capture Routing |
| borlanic | 0:fbdae7e6d805 | 249 | * @{ |
| borlanic | 0:fbdae7e6d805 | 250 | */ |
| borlanic | 0:fbdae7e6d805 | 251 | /* TIMx_IC1 TIMx_IC2 TIMx_IC3 TIMx_IC4 */ |
| borlanic | 0:fbdae7e6d805 | 252 | #define LL_RI_INPUTCAPTUREROUTING_0 (0x00000000U) /*!< PA0 PA1 PA2 PA3 */ |
| borlanic | 0:fbdae7e6d805 | 253 | #define LL_RI_INPUTCAPTUREROUTING_1 (0x00000001U) /*!< PA4 PA5 PA6 PA7 */ |
| borlanic | 0:fbdae7e6d805 | 254 | #define LL_RI_INPUTCAPTUREROUTING_2 (0x00000002U) /*!< PA8 PA9 PA10 PA11 */ |
| borlanic | 0:fbdae7e6d805 | 255 | #define LL_RI_INPUTCAPTUREROUTING_3 (0x00000003U) /*!< PA12 PA13 PA14 PA15 */ |
| borlanic | 0:fbdae7e6d805 | 256 | #define LL_RI_INPUTCAPTUREROUTING_4 (0x00000004U) /*!< PC0 PC1 PC2 PC3 */ |
| borlanic | 0:fbdae7e6d805 | 257 | #define LL_RI_INPUTCAPTUREROUTING_5 (0x00000005U) /*!< PC4 PC5 PC6 PC7 */ |
| borlanic | 0:fbdae7e6d805 | 258 | #define LL_RI_INPUTCAPTUREROUTING_6 (0x00000006U) /*!< PC8 PC9 PC10 PC11 */ |
| borlanic | 0:fbdae7e6d805 | 259 | #define LL_RI_INPUTCAPTUREROUTING_7 (0x00000007U) /*!< PC12 PC13 PC14 PC15 */ |
| borlanic | 0:fbdae7e6d805 | 260 | #define LL_RI_INPUTCAPTUREROUTING_8 (0x00000008U) /*!< PD0 PD1 PD2 PD3 */ |
| borlanic | 0:fbdae7e6d805 | 261 | #define LL_RI_INPUTCAPTUREROUTING_9 (0x00000009U) /*!< PD4 PD5 PD6 PD7 */ |
| borlanic | 0:fbdae7e6d805 | 262 | #define LL_RI_INPUTCAPTUREROUTING_10 (0x0000000AU) /*!< PD8 PD9 PD10 PD11 */ |
| borlanic | 0:fbdae7e6d805 | 263 | #define LL_RI_INPUTCAPTUREROUTING_11 (0x0000000BU) /*!< PD12 PD13 PD14 PD15 */ |
| borlanic | 0:fbdae7e6d805 | 264 | #if defined(GPIOE) |
| borlanic | 0:fbdae7e6d805 | 265 | #define LL_RI_INPUTCAPTUREROUTING_12 (0x0000000CU) /*!< PE0 PE1 PE2 PE3 */ |
| borlanic | 0:fbdae7e6d805 | 266 | #define LL_RI_INPUTCAPTUREROUTING_13 (0x0000000DU) /*!< PE4 PE5 PE6 PE7 */ |
| borlanic | 0:fbdae7e6d805 | 267 | #define LL_RI_INPUTCAPTUREROUTING_14 (0x0000000EU) /*!< PE8 PE9 PE10 PE11 */ |
| borlanic | 0:fbdae7e6d805 | 268 | #define LL_RI_INPUTCAPTUREROUTING_15 (0x0000000FU) /*!< PE12 PE13 PE14 PE15 */ |
| borlanic | 0:fbdae7e6d805 | 269 | #endif /* GPIOE */ |
| borlanic | 0:fbdae7e6d805 | 270 | /** |
| borlanic | 0:fbdae7e6d805 | 271 | * @} |
| borlanic | 0:fbdae7e6d805 | 272 | */ |
| borlanic | 0:fbdae7e6d805 | 273 | |
| borlanic | 0:fbdae7e6d805 | 274 | /** @defgroup SYSTEM_LL_EC_IOSWITCH_LINKED_ADC RI IO Switch linked to ADC |
| borlanic | 0:fbdae7e6d805 | 275 | * @{ |
| borlanic | 0:fbdae7e6d805 | 276 | */ |
| borlanic | 0:fbdae7e6d805 | 277 | #define LL_RI_IOSWITCH_CH0 RI_ASCR1_CH_0 /*!< CH[3:0] GR1[4:1]: I/O Analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 278 | #define LL_RI_IOSWITCH_CH1 RI_ASCR1_CH_1 /*!< CH[3:0] GR1[4:1]: I/O Analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 279 | #define LL_RI_IOSWITCH_CH2 RI_ASCR1_CH_2 /*!< CH[3:0] GR1[4:1]: I/O Analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 280 | #define LL_RI_IOSWITCH_CH3 RI_ASCR1_CH_3 /*!< CH[3:0] GR1[4:1]: I/O Analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 281 | #define LL_RI_IOSWITCH_CH4 RI_ASCR1_CH_4 /*!< CH4: Analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 282 | #define LL_RI_IOSWITCH_CH5 RI_ASCR1_CH_5 /*!< CH5: Comparator 1 analog switch*/ |
| borlanic | 0:fbdae7e6d805 | 283 | #define LL_RI_IOSWITCH_CH6 RI_ASCR1_CH_6 /*!< CH[7:6] GR2[2:1]: I/O Analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 284 | #define LL_RI_IOSWITCH_CH7 RI_ASCR1_CH_7 /*!< CH[7:6] GR2[2:1]: I/O Analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 285 | #define LL_RI_IOSWITCH_CH8 RI_ASCR1_CH_8 /*!< CH[9:8] GR3[2:1]: I/O Analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 286 | #define LL_RI_IOSWITCH_CH9 RI_ASCR1_CH_9 /*!< CH[9:8] GR3[2:1]: I/O Analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 287 | #define LL_RI_IOSWITCH_CH10 RI_ASCR1_CH_10 /*!< CH[13:10] GR8[4:1]: I/O Analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 288 | #define LL_RI_IOSWITCH_CH11 RI_ASCR1_CH_11 /*!< CH[13:10] GR8[4:1]: I/O Analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 289 | #define LL_RI_IOSWITCH_CH12 RI_ASCR1_CH_12 /*!< CH[13:10] GR8[4:1]: I/O Analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 290 | #define LL_RI_IOSWITCH_CH13 RI_ASCR1_CH_13 /*!< CH[13:10] GR8[4:1]: I/O Analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 291 | #define LL_RI_IOSWITCH_CH14 RI_ASCR1_CH_14 /*!< CH[15:14] GR9[2:1]: I/O Analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 292 | #define LL_RI_IOSWITCH_CH15 RI_ASCR1_CH_15 /*!< CH[15:14] GR9[2:1]: I/O Analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 293 | #define LL_RI_IOSWITCH_CH18 RI_ASCR1_CH_18 /*!< CH[21:18]/GR7[4:1]: I/O Analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 294 | #define LL_RI_IOSWITCH_CH19 RI_ASCR1_CH_19 /*!< CH[21:18]/GR7[4:1]: I/O Analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 295 | #define LL_RI_IOSWITCH_CH20 RI_ASCR1_CH_20 /*!< CH[21:18]/GR7[4:1]: I/O Analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 296 | #define LL_RI_IOSWITCH_CH21 RI_ASCR1_CH_21 /*!< CH[21:18]/GR7[4:1]: I/O Analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 297 | #define LL_RI_IOSWITCH_CH22 RI_ASCR1_CH_22 /*!< Analog I/O switch control of channels CH22 */ |
| borlanic | 0:fbdae7e6d805 | 298 | #define LL_RI_IOSWITCH_CH23 RI_ASCR1_CH_23 /*!< Analog I/O switch control of channels CH23 */ |
| borlanic | 0:fbdae7e6d805 | 299 | #define LL_RI_IOSWITCH_CH24 RI_ASCR1_CH_24 /*!< Analog I/O switch control of channels CH24 */ |
| borlanic | 0:fbdae7e6d805 | 300 | #define LL_RI_IOSWITCH_CH25 RI_ASCR1_CH_25 /*!< Analog I/O switch control of channels CH25 */ |
| borlanic | 0:fbdae7e6d805 | 301 | #define LL_RI_IOSWITCH_VCOMP RI_ASCR1_VCOMP /*!< VCOMP (ADC channel 26) is an internal switch |
| borlanic | 0:fbdae7e6d805 | 302 | used to connect selected channel to COMP1 non inverting input */ |
| borlanic | 0:fbdae7e6d805 | 303 | #if defined(RI_ASCR1_CH_27) |
| borlanic | 0:fbdae7e6d805 | 304 | #define LL_RI_IOSWITCH_CH27 RI_ASCR1_CH_27 /*!< CH[30:27]/GR11[4:1]: I/O Analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 305 | #define LL_RI_IOSWITCH_CH28 RI_ASCR1_CH_28 /*!< CH[30:27]/GR11[4:1]: I/O Analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 306 | #define LL_RI_IOSWITCH_CH29 RI_ASCR1_CH_29 /*!< CH[30:27]/GR11[4:1]: I/O Analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 307 | #define LL_RI_IOSWITCH_CH30 RI_ASCR1_CH_30 /*!< CH[30:27]/GR11[4:1]: I/O Analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 308 | #define LL_RI_IOSWITCH_CH31 RI_ASCR1_CH_31 /*!< CH31/GR11-5 I/O Analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 309 | #endif /* RI_ASCR1_CH_27 */ |
| borlanic | 0:fbdae7e6d805 | 310 | /** |
| borlanic | 0:fbdae7e6d805 | 311 | * @} |
| borlanic | 0:fbdae7e6d805 | 312 | */ |
| borlanic | 0:fbdae7e6d805 | 313 | |
| borlanic | 0:fbdae7e6d805 | 314 | /** @defgroup SYSTEM_LL_EC_IOSWITCH_NOT_LINKED_ADC RI IO Switch not linked to ADC |
| borlanic | 0:fbdae7e6d805 | 315 | * @{ |
| borlanic | 0:fbdae7e6d805 | 316 | */ |
| borlanic | 0:fbdae7e6d805 | 317 | #define LL_RI_IOSWITCH_GR10_1 RI_ASCR2_GR10_1 /*!< GR10-1 I/O analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 318 | #define LL_RI_IOSWITCH_GR10_2 RI_ASCR2_GR10_2 /*!< GR10-2 I/O analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 319 | #define LL_RI_IOSWITCH_GR10_3 RI_ASCR2_GR10_3 /*!< GR10-3 I/O analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 320 | #define LL_RI_IOSWITCH_GR10_4 RI_ASCR2_GR10_4 /*!< GR10-4 I/O analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 321 | #define LL_RI_IOSWITCH_GR6_1 RI_ASCR2_GR6_1 /*!< GR6-1 I/O analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 322 | #define LL_RI_IOSWITCH_GR6_2 RI_ASCR2_GR6_2 /*!< GR6-2 I/O analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 323 | #define LL_RI_IOSWITCH_GR5_1 RI_ASCR2_GR5_1 /*!< GR5-1 I/O analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 324 | #define LL_RI_IOSWITCH_GR5_2 RI_ASCR2_GR5_2 /*!< GR5-2 I/O analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 325 | #define LL_RI_IOSWITCH_GR5_3 RI_ASCR2_GR5_3 /*!< GR5-3 I/O analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 326 | #define LL_RI_IOSWITCH_GR4_1 RI_ASCR2_GR4_1 /*!< GR4-1 I/O analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 327 | #define LL_RI_IOSWITCH_GR4_2 RI_ASCR2_GR4_2 /*!< GR4-2 I/O analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 328 | #define LL_RI_IOSWITCH_GR4_3 RI_ASCR2_GR4_3 /*!< GR4-3 I/O analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 329 | #if defined(RI_ASCR2_CH0b) |
| borlanic | 0:fbdae7e6d805 | 330 | #define LL_RI_IOSWITCH_CH0b RI_ASCR2_CH0b /*!< CH0b-GR03-3 I/O analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 331 | #if defined(RI_ASCR2_CH1b) |
| borlanic | 0:fbdae7e6d805 | 332 | #define LL_RI_IOSWITCH_CH1b RI_ASCR2_CH1b /*!< CH1b-GR03-4 I/O analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 333 | #define LL_RI_IOSWITCH_CH2b RI_ASCR2_CH2b /*!< CH2b-GR03-5 I/O analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 334 | #define LL_RI_IOSWITCH_CH3b RI_ASCR2_CH3b /*!< CH3b-GR09-3 I/O analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 335 | #define LL_RI_IOSWITCH_CH6b RI_ASCR2_CH6b /*!< CH6b-GR09-4 I/O analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 336 | #define LL_RI_IOSWITCH_CH7b RI_ASCR2_CH7b /*!< CH7b-GR02-3 I/O analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 337 | #define LL_RI_IOSWITCH_CH8b RI_ASCR2_CH8b /*!< CH8b-GR02-4 I/O analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 338 | #define LL_RI_IOSWITCH_CH9b RI_ASCR2_CH9b /*!< CH9b-GR02-5 I/O analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 339 | #define LL_RI_IOSWITCH_CH10b RI_ASCR2_CH10b /*!< CH10b-GR07-5 I/O analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 340 | #define LL_RI_IOSWITCH_CH11b RI_ASCR2_CH11b /*!< CH11b-GR07-6 I/O analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 341 | #define LL_RI_IOSWITCH_CH12b RI_ASCR2_CH12b /*!< CH12b-GR07-7 I/O analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 342 | #endif /* RI_ASCR2_CH1b */ |
| borlanic | 0:fbdae7e6d805 | 343 | #define LL_RI_IOSWITCH_GR6_3 RI_ASCR2_GR6_3 /*!< GR6-3 I/O analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 344 | #define LL_RI_IOSWITCH_GR6_4 RI_ASCR2_GR6_4 /*!< GR6-4 I/O analog switch control */ |
| borlanic | 0:fbdae7e6d805 | 345 | #endif /* RI_ASCR2_CH0b */ |
| borlanic | 0:fbdae7e6d805 | 346 | /** |
| borlanic | 0:fbdae7e6d805 | 347 | * @} |
| borlanic | 0:fbdae7e6d805 | 348 | */ |
| borlanic | 0:fbdae7e6d805 | 349 | |
| borlanic | 0:fbdae7e6d805 | 350 | /** @defgroup SYSTEM_LL_EC_HSYTERESIS_PORT RI HSYTERESIS PORT |
| borlanic | 0:fbdae7e6d805 | 351 | * @{ |
| borlanic | 0:fbdae7e6d805 | 352 | */ |
| borlanic | 0:fbdae7e6d805 | 353 | #define LL_RI_HSYTERESIS_PORT_A 0U /*!< HYSTERESIS PORT A */ |
| borlanic | 0:fbdae7e6d805 | 354 | #define LL_RI_HSYTERESIS_PORT_B 1U /*!< HYSTERESIS PORT B */ |
| borlanic | 0:fbdae7e6d805 | 355 | #define LL_RI_HSYTERESIS_PORT_C 2U /*!< HYSTERESIS PORT C */ |
| borlanic | 0:fbdae7e6d805 | 356 | #define LL_RI_HSYTERESIS_PORT_D 3U /*!< HYSTERESIS PORT D */ |
| borlanic | 0:fbdae7e6d805 | 357 | #if defined(GPIOE) |
| borlanic | 0:fbdae7e6d805 | 358 | #define LL_RI_HSYTERESIS_PORT_E 4U /*!< HYSTERESIS PORT E */ |
| borlanic | 0:fbdae7e6d805 | 359 | #endif /* GPIOE */ |
| borlanic | 0:fbdae7e6d805 | 360 | #if defined(GPIOF) |
| borlanic | 0:fbdae7e6d805 | 361 | #define LL_RI_HSYTERESIS_PORT_F 5U /*!< HYSTERESIS PORT F */ |
| borlanic | 0:fbdae7e6d805 | 362 | #endif /* GPIOF */ |
| borlanic | 0:fbdae7e6d805 | 363 | #if defined(GPIOG) |
| borlanic | 0:fbdae7e6d805 | 364 | #define LL_RI_HSYTERESIS_PORT_G 6U /*!< HYSTERESIS PORT G */ |
| borlanic | 0:fbdae7e6d805 | 365 | #endif /* GPIOG */ |
| borlanic | 0:fbdae7e6d805 | 366 | /** |
| borlanic | 0:fbdae7e6d805 | 367 | * @} |
| borlanic | 0:fbdae7e6d805 | 368 | */ |
| borlanic | 0:fbdae7e6d805 | 369 | |
| borlanic | 0:fbdae7e6d805 | 370 | /** @defgroup SYSTEM_LL_EC_PIN RI PIN |
| borlanic | 0:fbdae7e6d805 | 371 | * @{ |
| borlanic | 0:fbdae7e6d805 | 372 | */ |
| borlanic | 0:fbdae7e6d805 | 373 | #define LL_RI_PIN_0 ((uint16_t)0x0001U) /*!< Pin 0 selected */ |
| borlanic | 0:fbdae7e6d805 | 374 | #define LL_RI_PIN_1 ((uint16_t)0x0002U) /*!< Pin 1 selected */ |
| borlanic | 0:fbdae7e6d805 | 375 | #define LL_RI_PIN_2 ((uint16_t)0x0004U) /*!< Pin 2 selected */ |
| borlanic | 0:fbdae7e6d805 | 376 | #define LL_RI_PIN_3 ((uint16_t)0x0008U) /*!< Pin 3 selected */ |
| borlanic | 0:fbdae7e6d805 | 377 | #define LL_RI_PIN_4 ((uint16_t)0x0010U) /*!< Pin 4 selected */ |
| borlanic | 0:fbdae7e6d805 | 378 | #define LL_RI_PIN_5 ((uint16_t)0x0020U) /*!< Pin 5 selected */ |
| borlanic | 0:fbdae7e6d805 | 379 | #define LL_RI_PIN_6 ((uint16_t)0x0040U) /*!< Pin 6 selected */ |
| borlanic | 0:fbdae7e6d805 | 380 | #define LL_RI_PIN_7 ((uint16_t)0x0080U) /*!< Pin 7 selected */ |
| borlanic | 0:fbdae7e6d805 | 381 | #define LL_RI_PIN_8 ((uint16_t)0x0100U) /*!< Pin 8 selected */ |
| borlanic | 0:fbdae7e6d805 | 382 | #define LL_RI_PIN_9 ((uint16_t)0x0200U) /*!< Pin 9 selected */ |
| borlanic | 0:fbdae7e6d805 | 383 | #define LL_RI_PIN_10 ((uint16_t)0x0400U) /*!< Pin 10 selected */ |
| borlanic | 0:fbdae7e6d805 | 384 | #define LL_RI_PIN_11 ((uint16_t)0x0800U) /*!< Pin 11 selected */ |
| borlanic | 0:fbdae7e6d805 | 385 | #define LL_RI_PIN_12 ((uint16_t)0x1000U) /*!< Pin 12 selected */ |
| borlanic | 0:fbdae7e6d805 | 386 | #define LL_RI_PIN_13 ((uint16_t)0x2000U) /*!< Pin 13 selected */ |
| borlanic | 0:fbdae7e6d805 | 387 | #define LL_RI_PIN_14 ((uint16_t)0x4000U) /*!< Pin 14 selected */ |
| borlanic | 0:fbdae7e6d805 | 388 | #define LL_RI_PIN_15 ((uint16_t)0x8000U) /*!< Pin 15 selected */ |
| borlanic | 0:fbdae7e6d805 | 389 | #define LL_RI_PIN_ALL ((uint16_t)0xFFFFU) /*!< All pins selected */ |
| borlanic | 0:fbdae7e6d805 | 390 | /** |
| borlanic | 0:fbdae7e6d805 | 391 | * @} |
| borlanic | 0:fbdae7e6d805 | 392 | */ |
| borlanic | 0:fbdae7e6d805 | 393 | |
| borlanic | 0:fbdae7e6d805 | 394 | #if defined(RI_ASMR1_PA) |
| borlanic | 0:fbdae7e6d805 | 395 | /** @defgroup SYSTEM_LL_EC_PORT RI PORT |
| borlanic | 0:fbdae7e6d805 | 396 | * @{ |
| borlanic | 0:fbdae7e6d805 | 397 | */ |
| borlanic | 0:fbdae7e6d805 | 398 | #define LL_RI_PORT_A 0U /*!< PORT A */ |
| borlanic | 0:fbdae7e6d805 | 399 | #define LL_RI_PORT_B 1U /*!< PORT B */ |
| borlanic | 0:fbdae7e6d805 | 400 | #define LL_RI_PORT_C 2U /*!< PORT C */ |
| borlanic | 0:fbdae7e6d805 | 401 | #if defined(GPIOF) |
| borlanic | 0:fbdae7e6d805 | 402 | #define LL_RI_PORT_F 3U /*!< PORT F */ |
| borlanic | 0:fbdae7e6d805 | 403 | #endif /* GPIOF */ |
| borlanic | 0:fbdae7e6d805 | 404 | #if defined(GPIOG) |
| borlanic | 0:fbdae7e6d805 | 405 | #define LL_RI_PORT_G 4U /*!< PORT G */ |
| borlanic | 0:fbdae7e6d805 | 406 | #endif /* GPIOG */ |
| borlanic | 0:fbdae7e6d805 | 407 | /** |
| borlanic | 0:fbdae7e6d805 | 408 | * @} |
| borlanic | 0:fbdae7e6d805 | 409 | */ |
| borlanic | 0:fbdae7e6d805 | 410 | |
| borlanic | 0:fbdae7e6d805 | 411 | #endif /* RI_ASMR1_PA */ |
| borlanic | 0:fbdae7e6d805 | 412 | |
| borlanic | 0:fbdae7e6d805 | 413 | |
| borlanic | 0:fbdae7e6d805 | 414 | /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY |
| borlanic | 0:fbdae7e6d805 | 415 | * @{ |
| borlanic | 0:fbdae7e6d805 | 416 | */ |
| borlanic | 0:fbdae7e6d805 | 417 | #define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */ |
| borlanic | 0:fbdae7e6d805 | 418 | #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */ |
| borlanic | 0:fbdae7e6d805 | 419 | /** |
| borlanic | 0:fbdae7e6d805 | 420 | * @} |
| borlanic | 0:fbdae7e6d805 | 421 | */ |
| borlanic | 0:fbdae7e6d805 | 422 | |
| borlanic | 0:fbdae7e6d805 | 423 | /** |
| borlanic | 0:fbdae7e6d805 | 424 | * @} |
| borlanic | 0:fbdae7e6d805 | 425 | */ |
| borlanic | 0:fbdae7e6d805 | 426 | |
| borlanic | 0:fbdae7e6d805 | 427 | /* Exported macro ------------------------------------------------------------*/ |
| borlanic | 0:fbdae7e6d805 | 428 | |
| borlanic | 0:fbdae7e6d805 | 429 | /* Exported functions --------------------------------------------------------*/ |
| borlanic | 0:fbdae7e6d805 | 430 | /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions |
| borlanic | 0:fbdae7e6d805 | 431 | * @{ |
| borlanic | 0:fbdae7e6d805 | 432 | */ |
| borlanic | 0:fbdae7e6d805 | 433 | |
| borlanic | 0:fbdae7e6d805 | 434 | /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG |
| borlanic | 0:fbdae7e6d805 | 435 | * @{ |
| borlanic | 0:fbdae7e6d805 | 436 | */ |
| borlanic | 0:fbdae7e6d805 | 437 | |
| borlanic | 0:fbdae7e6d805 | 438 | /** |
| borlanic | 0:fbdae7e6d805 | 439 | * @brief Set memory mapping at address 0x00000000 |
| borlanic | 0:fbdae7e6d805 | 440 | * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory |
| borlanic | 0:fbdae7e6d805 | 441 | * @param Memory This parameter can be one of the following values: |
| borlanic | 0:fbdae7e6d805 | 442 | * @arg @ref LL_SYSCFG_REMAP_FLASH |
| borlanic | 0:fbdae7e6d805 | 443 | * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH |
| borlanic | 0:fbdae7e6d805 | 444 | * @arg @ref LL_SYSCFG_REMAP_SRAM |
| borlanic | 0:fbdae7e6d805 | 445 | * @arg @ref LL_SYSCFG_REMAP_FMC (*) |
| borlanic | 0:fbdae7e6d805 | 446 | * |
| borlanic | 0:fbdae7e6d805 | 447 | * (*) value not defined in all devices |
| borlanic | 0:fbdae7e6d805 | 448 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 449 | */ |
| borlanic | 0:fbdae7e6d805 | 450 | __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory) |
| borlanic | 0:fbdae7e6d805 | 451 | { |
| borlanic | 0:fbdae7e6d805 | 452 | MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory); |
| borlanic | 0:fbdae7e6d805 | 453 | } |
| borlanic | 0:fbdae7e6d805 | 454 | |
| borlanic | 0:fbdae7e6d805 | 455 | /** |
| borlanic | 0:fbdae7e6d805 | 456 | * @brief Get memory mapping at address 0x00000000 |
| borlanic | 0:fbdae7e6d805 | 457 | * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory |
| borlanic | 0:fbdae7e6d805 | 458 | * @retval Returned value can be one of the following values: |
| borlanic | 0:fbdae7e6d805 | 459 | * @arg @ref LL_SYSCFG_REMAP_FLASH |
| borlanic | 0:fbdae7e6d805 | 460 | * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH |
| borlanic | 0:fbdae7e6d805 | 461 | * @arg @ref LL_SYSCFG_REMAP_SRAM |
| borlanic | 0:fbdae7e6d805 | 462 | * @arg @ref LL_SYSCFG_REMAP_FMC (*) |
| borlanic | 0:fbdae7e6d805 | 463 | * |
| borlanic | 0:fbdae7e6d805 | 464 | * (*) value not defined in all devices. |
| borlanic | 0:fbdae7e6d805 | 465 | */ |
| borlanic | 0:fbdae7e6d805 | 466 | __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void) |
| borlanic | 0:fbdae7e6d805 | 467 | { |
| borlanic | 0:fbdae7e6d805 | 468 | return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)); |
| borlanic | 0:fbdae7e6d805 | 469 | } |
| borlanic | 0:fbdae7e6d805 | 470 | |
| borlanic | 0:fbdae7e6d805 | 471 | /** |
| borlanic | 0:fbdae7e6d805 | 472 | * @brief Return the boot mode as configured by user. |
| borlanic | 0:fbdae7e6d805 | 473 | * @rmtoll SYSCFG_MEMRMP BOOT_MODE LL_SYSCFG_GetBootMode |
| borlanic | 0:fbdae7e6d805 | 474 | * @retval Returned value can be one of the following values: |
| borlanic | 0:fbdae7e6d805 | 475 | * @arg @ref LL_SYSCFG_BOOTMODE_FLASH |
| borlanic | 0:fbdae7e6d805 | 476 | * @arg @ref LL_SYSCFG_BOOTMODE_SYSTEMFLASH |
| borlanic | 0:fbdae7e6d805 | 477 | * @arg @ref LL_SYSCFG_BOOTMODE_FSMC (*) |
| borlanic | 0:fbdae7e6d805 | 478 | * @arg @ref LL_SYSCFG_BOOTMODE_SRAM |
| borlanic | 0:fbdae7e6d805 | 479 | * |
| borlanic | 0:fbdae7e6d805 | 480 | * (*) value not defined in all devices. |
| borlanic | 0:fbdae7e6d805 | 481 | */ |
| borlanic | 0:fbdae7e6d805 | 482 | __STATIC_INLINE uint32_t LL_SYSCFG_GetBootMode(void) |
| borlanic | 0:fbdae7e6d805 | 483 | { |
| borlanic | 0:fbdae7e6d805 | 484 | return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BOOT_MODE)); |
| borlanic | 0:fbdae7e6d805 | 485 | } |
| borlanic | 0:fbdae7e6d805 | 486 | |
| borlanic | 0:fbdae7e6d805 | 487 | /** |
| borlanic | 0:fbdae7e6d805 | 488 | * @brief Enable internal pull-up on USB DP line. |
| borlanic | 0:fbdae7e6d805 | 489 | * @rmtoll SYSCFG_PMC USB_PU LL_SYSCFG_EnableUSBPullUp |
| borlanic | 0:fbdae7e6d805 | 490 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 491 | */ |
| borlanic | 0:fbdae7e6d805 | 492 | __STATIC_INLINE void LL_SYSCFG_EnableUSBPullUp(void) |
| borlanic | 0:fbdae7e6d805 | 493 | { |
| borlanic | 0:fbdae7e6d805 | 494 | SET_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU); |
| borlanic | 0:fbdae7e6d805 | 495 | } |
| borlanic | 0:fbdae7e6d805 | 496 | |
| borlanic | 0:fbdae7e6d805 | 497 | /** |
| borlanic | 0:fbdae7e6d805 | 498 | * @brief Disable internal pull-up on USB DP line. |
| borlanic | 0:fbdae7e6d805 | 499 | * @rmtoll SYSCFG_PMC USB_PU LL_SYSCFG_DisableUSBPullUp |
| borlanic | 0:fbdae7e6d805 | 500 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 501 | */ |
| borlanic | 0:fbdae7e6d805 | 502 | __STATIC_INLINE void LL_SYSCFG_DisableUSBPullUp(void) |
| borlanic | 0:fbdae7e6d805 | 503 | { |
| borlanic | 0:fbdae7e6d805 | 504 | CLEAR_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU); |
| borlanic | 0:fbdae7e6d805 | 505 | } |
| borlanic | 0:fbdae7e6d805 | 506 | |
| borlanic | 0:fbdae7e6d805 | 507 | #if defined(LCD) |
| borlanic | 0:fbdae7e6d805 | 508 | /** |
| borlanic | 0:fbdae7e6d805 | 509 | * @brief Enable decoupling capacitance connection. |
| borlanic | 0:fbdae7e6d805 | 510 | * @rmtoll SYSCFG_PMC LCD_CAPA LL_SYSCFG_EnableLCDCapacitanceConnection |
| borlanic | 0:fbdae7e6d805 | 511 | * @param Pin This parameter can be a combination of the following values: |
| borlanic | 0:fbdae7e6d805 | 512 | * @arg @ref LL_SYSCFG_LCDCAPA_PB2 |
| borlanic | 0:fbdae7e6d805 | 513 | * @arg @ref LL_SYSCFG_LCDCAPA_PB12 |
| borlanic | 0:fbdae7e6d805 | 514 | * @arg @ref LL_SYSCFG_LCDCAPA_PB0 |
| borlanic | 0:fbdae7e6d805 | 515 | * @arg @ref LL_SYSCFG_LCDCAPA_PE11 |
| borlanic | 0:fbdae7e6d805 | 516 | * @arg @ref LL_SYSCFG_LCDCAPA_PE12 |
| borlanic | 0:fbdae7e6d805 | 517 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 518 | */ |
| borlanic | 0:fbdae7e6d805 | 519 | __STATIC_INLINE void LL_SYSCFG_EnableLCDCapacitanceConnection(uint32_t Pin) |
| borlanic | 0:fbdae7e6d805 | 520 | { |
| borlanic | 0:fbdae7e6d805 | 521 | SET_BIT(SYSCFG->PMC, Pin); |
| borlanic | 0:fbdae7e6d805 | 522 | } |
| borlanic | 0:fbdae7e6d805 | 523 | |
| borlanic | 0:fbdae7e6d805 | 524 | /** |
| borlanic | 0:fbdae7e6d805 | 525 | * @brief DIsable decoupling capacitance connection. |
| borlanic | 0:fbdae7e6d805 | 526 | * @rmtoll SYSCFG_PMC LCD_CAPA LL_SYSCFG_DisableLCDCapacitanceConnection |
| borlanic | 0:fbdae7e6d805 | 527 | * @param Pin This parameter can be a combination of the following values: |
| borlanic | 0:fbdae7e6d805 | 528 | * @arg @ref LL_SYSCFG_LCDCAPA_PB2 |
| borlanic | 0:fbdae7e6d805 | 529 | * @arg @ref LL_SYSCFG_LCDCAPA_PB12 |
| borlanic | 0:fbdae7e6d805 | 530 | * @arg @ref LL_SYSCFG_LCDCAPA_PB0 |
| borlanic | 0:fbdae7e6d805 | 531 | * @arg @ref LL_SYSCFG_LCDCAPA_PE11 |
| borlanic | 0:fbdae7e6d805 | 532 | * @arg @ref LL_SYSCFG_LCDCAPA_PE12 |
| borlanic | 0:fbdae7e6d805 | 533 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 534 | */ |
| borlanic | 0:fbdae7e6d805 | 535 | __STATIC_INLINE void LL_SYSCFG_DisableLCDCapacitanceConnection(uint32_t Pin) |
| borlanic | 0:fbdae7e6d805 | 536 | { |
| borlanic | 0:fbdae7e6d805 | 537 | CLEAR_BIT(SYSCFG->PMC, Pin); |
| borlanic | 0:fbdae7e6d805 | 538 | } |
| borlanic | 0:fbdae7e6d805 | 539 | #endif /* LCD */ |
| borlanic | 0:fbdae7e6d805 | 540 | |
| borlanic | 0:fbdae7e6d805 | 541 | /** |
| borlanic | 0:fbdae7e6d805 | 542 | * @brief Configure source input for the EXTI external interrupt. |
| borlanic | 0:fbdae7e6d805 | 543 | * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 544 | * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 545 | * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 546 | * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 547 | * SYSCFG_EXTICR1 EXTI4 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 548 | * SYSCFG_EXTICR1 EXTI5 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 549 | * SYSCFG_EXTICR1 EXTI6 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 550 | * SYSCFG_EXTICR1 EXTI7 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 551 | * SYSCFG_EXTICR1 EXTI8 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 552 | * SYSCFG_EXTICR1 EXTI9 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 553 | * SYSCFG_EXTICR1 EXTI10 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 554 | * SYSCFG_EXTICR1 EXTI11 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 555 | * SYSCFG_EXTICR1 EXTI12 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 556 | * SYSCFG_EXTICR1 EXTI13 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 557 | * SYSCFG_EXTICR1 EXTI14 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 558 | * SYSCFG_EXTICR1 EXTI15 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 559 | * SYSCFG_EXTICR2 EXTI0 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 560 | * SYSCFG_EXTICR2 EXTI1 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 561 | * SYSCFG_EXTICR2 EXTI2 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 562 | * SYSCFG_EXTICR2 EXTI3 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 563 | * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 564 | * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 565 | * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 566 | * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 567 | * SYSCFG_EXTICR2 EXTI8 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 568 | * SYSCFG_EXTICR2 EXTI9 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 569 | * SYSCFG_EXTICR2 EXTI10 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 570 | * SYSCFG_EXTICR2 EXTI11 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 571 | * SYSCFG_EXTICR2 EXTI12 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 572 | * SYSCFG_EXTICR2 EXTI13 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 573 | * SYSCFG_EXTICR2 EXTI14 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 574 | * SYSCFG_EXTICR2 EXTI15 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 575 | * SYSCFG_EXTICR3 EXTI0 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 576 | * SYSCFG_EXTICR3 EXTI1 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 577 | * SYSCFG_EXTICR3 EXTI2 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 578 | * SYSCFG_EXTICR3 EXTI3 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 579 | * SYSCFG_EXTICR3 EXTI4 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 580 | * SYSCFG_EXTICR3 EXTI5 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 581 | * SYSCFG_EXTICR3 EXTI6 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 582 | * SYSCFG_EXTICR3 EXTI7 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 583 | * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 584 | * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 585 | * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 586 | * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 587 | * SYSCFG_EXTICR3 EXTI12 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 588 | * SYSCFG_EXTICR3 EXTI13 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 589 | * SYSCFG_EXTICR3 EXTI14 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 590 | * SYSCFG_EXTICR3 EXTI15 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 591 | * SYSCFG_EXTICR4 EXTI0 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 592 | * SYSCFG_EXTICR4 EXTI1 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 593 | * SYSCFG_EXTICR4 EXTI2 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 594 | * SYSCFG_EXTICR4 EXTI3 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 595 | * SYSCFG_EXTICR4 EXTI4 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 596 | * SYSCFG_EXTICR4 EXTI5 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 597 | * SYSCFG_EXTICR4 EXTI6 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 598 | * SYSCFG_EXTICR4 EXTI7 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 599 | * SYSCFG_EXTICR4 EXTI8 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 600 | * SYSCFG_EXTICR4 EXTI9 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 601 | * SYSCFG_EXTICR4 EXTI10 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 602 | * SYSCFG_EXTICR4 EXTI11 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 603 | * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 604 | * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 605 | * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 606 | * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource |
| borlanic | 0:fbdae7e6d805 | 607 | * @param Port This parameter can be one of the following values: |
| borlanic | 0:fbdae7e6d805 | 608 | * @arg @ref LL_SYSCFG_EXTI_PORTA |
| borlanic | 0:fbdae7e6d805 | 609 | * @arg @ref LL_SYSCFG_EXTI_PORTB |
| borlanic | 0:fbdae7e6d805 | 610 | * @arg @ref LL_SYSCFG_EXTI_PORTC |
| borlanic | 0:fbdae7e6d805 | 611 | * @arg @ref LL_SYSCFG_EXTI_PORTD |
| borlanic | 0:fbdae7e6d805 | 612 | * @arg @ref LL_SYSCFG_EXTI_PORTE (*) |
| borlanic | 0:fbdae7e6d805 | 613 | * @arg @ref LL_SYSCFG_EXTI_PORTF (*) |
| borlanic | 0:fbdae7e6d805 | 614 | * @arg @ref LL_SYSCFG_EXTI_PORTG (*) |
| borlanic | 0:fbdae7e6d805 | 615 | * @arg @ref LL_SYSCFG_EXTI_PORTH |
| borlanic | 0:fbdae7e6d805 | 616 | * |
| borlanic | 0:fbdae7e6d805 | 617 | * (*) value not defined in all devices. |
| borlanic | 0:fbdae7e6d805 | 618 | * @param Line This parameter can be one of the following values: |
| borlanic | 0:fbdae7e6d805 | 619 | * @arg @ref LL_SYSCFG_EXTI_LINE0 |
| borlanic | 0:fbdae7e6d805 | 620 | * @arg @ref LL_SYSCFG_EXTI_LINE1 |
| borlanic | 0:fbdae7e6d805 | 621 | * @arg @ref LL_SYSCFG_EXTI_LINE2 |
| borlanic | 0:fbdae7e6d805 | 622 | * @arg @ref LL_SYSCFG_EXTI_LINE3 |
| borlanic | 0:fbdae7e6d805 | 623 | * @arg @ref LL_SYSCFG_EXTI_LINE4 |
| borlanic | 0:fbdae7e6d805 | 624 | * @arg @ref LL_SYSCFG_EXTI_LINE5 |
| borlanic | 0:fbdae7e6d805 | 625 | * @arg @ref LL_SYSCFG_EXTI_LINE6 |
| borlanic | 0:fbdae7e6d805 | 626 | * @arg @ref LL_SYSCFG_EXTI_LINE7 |
| borlanic | 0:fbdae7e6d805 | 627 | * @arg @ref LL_SYSCFG_EXTI_LINE8 |
| borlanic | 0:fbdae7e6d805 | 628 | * @arg @ref LL_SYSCFG_EXTI_LINE9 |
| borlanic | 0:fbdae7e6d805 | 629 | * @arg @ref LL_SYSCFG_EXTI_LINE10 |
| borlanic | 0:fbdae7e6d805 | 630 | * @arg @ref LL_SYSCFG_EXTI_LINE11 |
| borlanic | 0:fbdae7e6d805 | 631 | * @arg @ref LL_SYSCFG_EXTI_LINE12 |
| borlanic | 0:fbdae7e6d805 | 632 | * @arg @ref LL_SYSCFG_EXTI_LINE13 |
| borlanic | 0:fbdae7e6d805 | 633 | * @arg @ref LL_SYSCFG_EXTI_LINE14 |
| borlanic | 0:fbdae7e6d805 | 634 | * @arg @ref LL_SYSCFG_EXTI_LINE15 |
| borlanic | 0:fbdae7e6d805 | 635 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 636 | */ |
| borlanic | 0:fbdae7e6d805 | 637 | __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) |
| borlanic | 0:fbdae7e6d805 | 638 | { |
| borlanic | 0:fbdae7e6d805 | 639 | MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16))); |
| borlanic | 0:fbdae7e6d805 | 640 | } |
| borlanic | 0:fbdae7e6d805 | 641 | |
| borlanic | 0:fbdae7e6d805 | 642 | /** |
| borlanic | 0:fbdae7e6d805 | 643 | * @brief Get the configured defined for specific EXTI Line |
| borlanic | 0:fbdae7e6d805 | 644 | * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 645 | * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 646 | * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 647 | * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 648 | * SYSCFG_EXTICR1 EXTI4 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 649 | * SYSCFG_EXTICR1 EXTI5 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 650 | * SYSCFG_EXTICR1 EXTI6 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 651 | * SYSCFG_EXTICR1 EXTI7 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 652 | * SYSCFG_EXTICR1 EXTI8 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 653 | * SYSCFG_EXTICR1 EXTI9 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 654 | * SYSCFG_EXTICR1 EXTI10 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 655 | * SYSCFG_EXTICR1 EXTI11 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 656 | * SYSCFG_EXTICR1 EXTI12 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 657 | * SYSCFG_EXTICR1 EXTI13 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 658 | * SYSCFG_EXTICR1 EXTI14 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 659 | * SYSCFG_EXTICR1 EXTI15 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 660 | * SYSCFG_EXTICR2 EXTI0 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 661 | * SYSCFG_EXTICR2 EXTI1 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 662 | * SYSCFG_EXTICR2 EXTI2 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 663 | * SYSCFG_EXTICR2 EXTI3 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 664 | * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 665 | * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 666 | * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 667 | * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 668 | * SYSCFG_EXTICR2 EXTI8 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 669 | * SYSCFG_EXTICR2 EXTI9 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 670 | * SYSCFG_EXTICR2 EXTI10 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 671 | * SYSCFG_EXTICR2 EXTI11 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 672 | * SYSCFG_EXTICR2 EXTI12 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 673 | * SYSCFG_EXTICR2 EXTI13 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 674 | * SYSCFG_EXTICR2 EXTI14 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 675 | * SYSCFG_EXTICR2 EXTI15 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 676 | * SYSCFG_EXTICR3 EXTI0 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 677 | * SYSCFG_EXTICR3 EXTI1 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 678 | * SYSCFG_EXTICR3 EXTI2 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 679 | * SYSCFG_EXTICR3 EXTI3 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 680 | * SYSCFG_EXTICR3 EXTI4 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 681 | * SYSCFG_EXTICR3 EXTI5 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 682 | * SYSCFG_EXTICR3 EXTI6 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 683 | * SYSCFG_EXTICR3 EXTI7 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 684 | * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 685 | * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 686 | * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 687 | * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 688 | * SYSCFG_EXTICR3 EXTI12 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 689 | * SYSCFG_EXTICR3 EXTI13 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 690 | * SYSCFG_EXTICR3 EXTI14 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 691 | * SYSCFG_EXTICR3 EXTI15 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 692 | * SYSCFG_EXTICR4 EXTI0 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 693 | * SYSCFG_EXTICR4 EXTI1 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 694 | * SYSCFG_EXTICR4 EXTI2 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 695 | * SYSCFG_EXTICR4 EXTI3 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 696 | * SYSCFG_EXTICR4 EXTI4 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 697 | * SYSCFG_EXTICR4 EXTI5 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 698 | * SYSCFG_EXTICR4 EXTI6 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 699 | * SYSCFG_EXTICR4 EXTI7 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 700 | * SYSCFG_EXTICR4 EXTI8 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 701 | * SYSCFG_EXTICR4 EXTI9 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 702 | * SYSCFG_EXTICR4 EXTI10 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 703 | * SYSCFG_EXTICR4 EXTI11 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 704 | * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 705 | * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 706 | * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_GetEXTISource\n |
| borlanic | 0:fbdae7e6d805 | 707 | * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_GetEXTISource |
| borlanic | 0:fbdae7e6d805 | 708 | * @param Line This parameter can be one of the following values: |
| borlanic | 0:fbdae7e6d805 | 709 | * @arg @ref LL_SYSCFG_EXTI_LINE0 |
| borlanic | 0:fbdae7e6d805 | 710 | * @arg @ref LL_SYSCFG_EXTI_LINE1 |
| borlanic | 0:fbdae7e6d805 | 711 | * @arg @ref LL_SYSCFG_EXTI_LINE2 |
| borlanic | 0:fbdae7e6d805 | 712 | * @arg @ref LL_SYSCFG_EXTI_LINE3 |
| borlanic | 0:fbdae7e6d805 | 713 | * @arg @ref LL_SYSCFG_EXTI_LINE4 |
| borlanic | 0:fbdae7e6d805 | 714 | * @arg @ref LL_SYSCFG_EXTI_LINE5 |
| borlanic | 0:fbdae7e6d805 | 715 | * @arg @ref LL_SYSCFG_EXTI_LINE6 |
| borlanic | 0:fbdae7e6d805 | 716 | * @arg @ref LL_SYSCFG_EXTI_LINE7 |
| borlanic | 0:fbdae7e6d805 | 717 | * @arg @ref LL_SYSCFG_EXTI_LINE8 |
| borlanic | 0:fbdae7e6d805 | 718 | * @arg @ref LL_SYSCFG_EXTI_LINE9 |
| borlanic | 0:fbdae7e6d805 | 719 | * @arg @ref LL_SYSCFG_EXTI_LINE10 |
| borlanic | 0:fbdae7e6d805 | 720 | * @arg @ref LL_SYSCFG_EXTI_LINE11 |
| borlanic | 0:fbdae7e6d805 | 721 | * @arg @ref LL_SYSCFG_EXTI_LINE12 |
| borlanic | 0:fbdae7e6d805 | 722 | * @arg @ref LL_SYSCFG_EXTI_LINE13 |
| borlanic | 0:fbdae7e6d805 | 723 | * @arg @ref LL_SYSCFG_EXTI_LINE14 |
| borlanic | 0:fbdae7e6d805 | 724 | * @arg @ref LL_SYSCFG_EXTI_LINE15 |
| borlanic | 0:fbdae7e6d805 | 725 | * @retval Returned value can be one of the following values: |
| borlanic | 0:fbdae7e6d805 | 726 | * @arg @ref LL_SYSCFG_EXTI_PORTA |
| borlanic | 0:fbdae7e6d805 | 727 | * @arg @ref LL_SYSCFG_EXTI_PORTB |
| borlanic | 0:fbdae7e6d805 | 728 | * @arg @ref LL_SYSCFG_EXTI_PORTC |
| borlanic | 0:fbdae7e6d805 | 729 | * @arg @ref LL_SYSCFG_EXTI_PORTD |
| borlanic | 0:fbdae7e6d805 | 730 | * @arg @ref LL_SYSCFG_EXTI_PORTE (*) |
| borlanic | 0:fbdae7e6d805 | 731 | * @arg @ref LL_SYSCFG_EXTI_PORTF (*) |
| borlanic | 0:fbdae7e6d805 | 732 | * @arg @ref LL_SYSCFG_EXTI_PORTG (*) |
| borlanic | 0:fbdae7e6d805 | 733 | * @arg @ref LL_SYSCFG_EXTI_PORTH |
| borlanic | 0:fbdae7e6d805 | 734 | * |
| borlanic | 0:fbdae7e6d805 | 735 | * (*) value not defined in all devices. |
| borlanic | 0:fbdae7e6d805 | 736 | */ |
| borlanic | 0:fbdae7e6d805 | 737 | __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) |
| borlanic | 0:fbdae7e6d805 | 738 | { |
| borlanic | 0:fbdae7e6d805 | 739 | return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16)); |
| borlanic | 0:fbdae7e6d805 | 740 | } |
| borlanic | 0:fbdae7e6d805 | 741 | |
| borlanic | 0:fbdae7e6d805 | 742 | /** |
| borlanic | 0:fbdae7e6d805 | 743 | * @} |
| borlanic | 0:fbdae7e6d805 | 744 | */ |
| borlanic | 0:fbdae7e6d805 | 745 | |
| borlanic | 0:fbdae7e6d805 | 746 | /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU |
| borlanic | 0:fbdae7e6d805 | 747 | * @{ |
| borlanic | 0:fbdae7e6d805 | 748 | */ |
| borlanic | 0:fbdae7e6d805 | 749 | |
| borlanic | 0:fbdae7e6d805 | 750 | /** |
| borlanic | 0:fbdae7e6d805 | 751 | * @brief Return the device identifier |
| borlanic | 0:fbdae7e6d805 | 752 | * @note 0x416: Cat.1 device\n |
| borlanic | 0:fbdae7e6d805 | 753 | * 0x429: Cat.2 device\n |
| borlanic | 0:fbdae7e6d805 | 754 | * 0x427: Cat.3 device\n |
| borlanic | 0:fbdae7e6d805 | 755 | * 0x436: Cat.4 device or Cat.3 device(1)\n |
| borlanic | 0:fbdae7e6d805 | 756 | * 0x437: Cat.5 device\n |
| borlanic | 0:fbdae7e6d805 | 757 | * |
| borlanic | 0:fbdae7e6d805 | 758 | * (1) Cat.3 devices: STM32L15xxC or STM3216xxC devices with |
| borlanic | 0:fbdae7e6d805 | 759 | * RPN ending with letter 'A', in WLCSP64 packages or with more then 100 pin. |
| borlanic | 0:fbdae7e6d805 | 760 | * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID |
| borlanic | 0:fbdae7e6d805 | 761 | * @retval Values between Min_Data=0x00 and Max_Data=0xFFF |
| borlanic | 0:fbdae7e6d805 | 762 | */ |
| borlanic | 0:fbdae7e6d805 | 763 | __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) |
| borlanic | 0:fbdae7e6d805 | 764 | { |
| borlanic | 0:fbdae7e6d805 | 765 | return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); |
| borlanic | 0:fbdae7e6d805 | 766 | } |
| borlanic | 0:fbdae7e6d805 | 767 | |
| borlanic | 0:fbdae7e6d805 | 768 | /** |
| borlanic | 0:fbdae7e6d805 | 769 | * @brief Return the device revision identifier |
| borlanic | 0:fbdae7e6d805 | 770 | * @note This field indicates the revision of the device. |
| borlanic | 0:fbdae7e6d805 | 771 | For example, it is read as Cat.1 RevA -> 0x1000, Cat.2 Rev Z -> 0x1018... |
| borlanic | 0:fbdae7e6d805 | 772 | * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID |
| borlanic | 0:fbdae7e6d805 | 773 | * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF |
| borlanic | 0:fbdae7e6d805 | 774 | */ |
| borlanic | 0:fbdae7e6d805 | 775 | __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) |
| borlanic | 0:fbdae7e6d805 | 776 | { |
| borlanic | 0:fbdae7e6d805 | 777 | return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); |
| borlanic | 0:fbdae7e6d805 | 778 | } |
| borlanic | 0:fbdae7e6d805 | 779 | |
| borlanic | 0:fbdae7e6d805 | 780 | /** |
| borlanic | 0:fbdae7e6d805 | 781 | * @brief Enable the Debug Module during SLEEP mode |
| borlanic | 0:fbdae7e6d805 | 782 | * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode |
| borlanic | 0:fbdae7e6d805 | 783 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 784 | */ |
| borlanic | 0:fbdae7e6d805 | 785 | __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) |
| borlanic | 0:fbdae7e6d805 | 786 | { |
| borlanic | 0:fbdae7e6d805 | 787 | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); |
| borlanic | 0:fbdae7e6d805 | 788 | } |
| borlanic | 0:fbdae7e6d805 | 789 | |
| borlanic | 0:fbdae7e6d805 | 790 | /** |
| borlanic | 0:fbdae7e6d805 | 791 | * @brief Disable the Debug Module during SLEEP mode |
| borlanic | 0:fbdae7e6d805 | 792 | * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode |
| borlanic | 0:fbdae7e6d805 | 793 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 794 | */ |
| borlanic | 0:fbdae7e6d805 | 795 | __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) |
| borlanic | 0:fbdae7e6d805 | 796 | { |
| borlanic | 0:fbdae7e6d805 | 797 | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); |
| borlanic | 0:fbdae7e6d805 | 798 | } |
| borlanic | 0:fbdae7e6d805 | 799 | |
| borlanic | 0:fbdae7e6d805 | 800 | /** |
| borlanic | 0:fbdae7e6d805 | 801 | * @brief Enable the Debug Module during STOP mode |
| borlanic | 0:fbdae7e6d805 | 802 | * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode |
| borlanic | 0:fbdae7e6d805 | 803 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 804 | */ |
| borlanic | 0:fbdae7e6d805 | 805 | __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) |
| borlanic | 0:fbdae7e6d805 | 806 | { |
| borlanic | 0:fbdae7e6d805 | 807 | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); |
| borlanic | 0:fbdae7e6d805 | 808 | } |
| borlanic | 0:fbdae7e6d805 | 809 | |
| borlanic | 0:fbdae7e6d805 | 810 | /** |
| borlanic | 0:fbdae7e6d805 | 811 | * @brief Disable the Debug Module during STOP mode |
| borlanic | 0:fbdae7e6d805 | 812 | * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode |
| borlanic | 0:fbdae7e6d805 | 813 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 814 | */ |
| borlanic | 0:fbdae7e6d805 | 815 | __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) |
| borlanic | 0:fbdae7e6d805 | 816 | { |
| borlanic | 0:fbdae7e6d805 | 817 | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); |
| borlanic | 0:fbdae7e6d805 | 818 | } |
| borlanic | 0:fbdae7e6d805 | 819 | |
| borlanic | 0:fbdae7e6d805 | 820 | /** |
| borlanic | 0:fbdae7e6d805 | 821 | * @brief Enable the Debug Module during STANDBY mode |
| borlanic | 0:fbdae7e6d805 | 822 | * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode |
| borlanic | 0:fbdae7e6d805 | 823 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 824 | */ |
| borlanic | 0:fbdae7e6d805 | 825 | __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) |
| borlanic | 0:fbdae7e6d805 | 826 | { |
| borlanic | 0:fbdae7e6d805 | 827 | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); |
| borlanic | 0:fbdae7e6d805 | 828 | } |
| borlanic | 0:fbdae7e6d805 | 829 | |
| borlanic | 0:fbdae7e6d805 | 830 | /** |
| borlanic | 0:fbdae7e6d805 | 831 | * @brief Disable the Debug Module during STANDBY mode |
| borlanic | 0:fbdae7e6d805 | 832 | * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode |
| borlanic | 0:fbdae7e6d805 | 833 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 834 | */ |
| borlanic | 0:fbdae7e6d805 | 835 | __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) |
| borlanic | 0:fbdae7e6d805 | 836 | { |
| borlanic | 0:fbdae7e6d805 | 837 | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); |
| borlanic | 0:fbdae7e6d805 | 838 | } |
| borlanic | 0:fbdae7e6d805 | 839 | |
| borlanic | 0:fbdae7e6d805 | 840 | /** |
| borlanic | 0:fbdae7e6d805 | 841 | * @brief Set Trace pin assignment control |
| borlanic | 0:fbdae7e6d805 | 842 | * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n |
| borlanic | 0:fbdae7e6d805 | 843 | * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment |
| borlanic | 0:fbdae7e6d805 | 844 | * @param PinAssignment This parameter can be one of the following values: |
| borlanic | 0:fbdae7e6d805 | 845 | * @arg @ref LL_DBGMCU_TRACE_NONE |
| borlanic | 0:fbdae7e6d805 | 846 | * @arg @ref LL_DBGMCU_TRACE_ASYNCH |
| borlanic | 0:fbdae7e6d805 | 847 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 |
| borlanic | 0:fbdae7e6d805 | 848 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 |
| borlanic | 0:fbdae7e6d805 | 849 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 |
| borlanic | 0:fbdae7e6d805 | 850 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 851 | */ |
| borlanic | 0:fbdae7e6d805 | 852 | __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment) |
| borlanic | 0:fbdae7e6d805 | 853 | { |
| borlanic | 0:fbdae7e6d805 | 854 | MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment); |
| borlanic | 0:fbdae7e6d805 | 855 | } |
| borlanic | 0:fbdae7e6d805 | 856 | |
| borlanic | 0:fbdae7e6d805 | 857 | /** |
| borlanic | 0:fbdae7e6d805 | 858 | * @brief Get Trace pin assignment control |
| borlanic | 0:fbdae7e6d805 | 859 | * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n |
| borlanic | 0:fbdae7e6d805 | 860 | * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment |
| borlanic | 0:fbdae7e6d805 | 861 | * @retval Returned value can be one of the following values: |
| borlanic | 0:fbdae7e6d805 | 862 | * @arg @ref LL_DBGMCU_TRACE_NONE |
| borlanic | 0:fbdae7e6d805 | 863 | * @arg @ref LL_DBGMCU_TRACE_ASYNCH |
| borlanic | 0:fbdae7e6d805 | 864 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 |
| borlanic | 0:fbdae7e6d805 | 865 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 |
| borlanic | 0:fbdae7e6d805 | 866 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 |
| borlanic | 0:fbdae7e6d805 | 867 | */ |
| borlanic | 0:fbdae7e6d805 | 868 | __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) |
| borlanic | 0:fbdae7e6d805 | 869 | { |
| borlanic | 0:fbdae7e6d805 | 870 | return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)); |
| borlanic | 0:fbdae7e6d805 | 871 | } |
| borlanic | 0:fbdae7e6d805 | 872 | |
| borlanic | 0:fbdae7e6d805 | 873 | /** |
| borlanic | 0:fbdae7e6d805 | 874 | * @brief Freeze APB1 peripherals (group1 peripherals) |
| borlanic | 0:fbdae7e6d805 | 875 | * @rmtoll APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| borlanic | 0:fbdae7e6d805 | 876 | * APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| borlanic | 0:fbdae7e6d805 | 877 | * APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| borlanic | 0:fbdae7e6d805 | 878 | * APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| borlanic | 0:fbdae7e6d805 | 879 | * APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| borlanic | 0:fbdae7e6d805 | 880 | * APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| borlanic | 0:fbdae7e6d805 | 881 | * APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| borlanic | 0:fbdae7e6d805 | 882 | * APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| borlanic | 0:fbdae7e6d805 | 883 | * APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| borlanic | 0:fbdae7e6d805 | 884 | * APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| borlanic | 0:fbdae7e6d805 | 885 | * APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph |
| borlanic | 0:fbdae7e6d805 | 886 | * @param Periphs This parameter can be a combination of the following values: |
| borlanic | 0:fbdae7e6d805 | 887 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP |
| borlanic | 0:fbdae7e6d805 | 888 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP |
| borlanic | 0:fbdae7e6d805 | 889 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP |
| borlanic | 0:fbdae7e6d805 | 890 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*) |
| borlanic | 0:fbdae7e6d805 | 891 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP |
| borlanic | 0:fbdae7e6d805 | 892 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP |
| borlanic | 0:fbdae7e6d805 | 893 | * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP (*) |
| borlanic | 0:fbdae7e6d805 | 894 | * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP |
| borlanic | 0:fbdae7e6d805 | 895 | * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP |
| borlanic | 0:fbdae7e6d805 | 896 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP |
| borlanic | 0:fbdae7e6d805 | 897 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP |
| borlanic | 0:fbdae7e6d805 | 898 | * (*) value not defined in all devices. |
| borlanic | 0:fbdae7e6d805 | 899 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 900 | */ |
| borlanic | 0:fbdae7e6d805 | 901 | __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) |
| borlanic | 0:fbdae7e6d805 | 902 | { |
| borlanic | 0:fbdae7e6d805 | 903 | SET_BIT(DBGMCU->APB1FZ, Periphs); |
| borlanic | 0:fbdae7e6d805 | 904 | } |
| borlanic | 0:fbdae7e6d805 | 905 | |
| borlanic | 0:fbdae7e6d805 | 906 | /** |
| borlanic | 0:fbdae7e6d805 | 907 | * @brief Unfreeze APB1 peripherals (group1 peripherals) |
| borlanic | 0:fbdae7e6d805 | 908 | * @rmtoll APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| borlanic | 0:fbdae7e6d805 | 909 | * APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| borlanic | 0:fbdae7e6d805 | 910 | * APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| borlanic | 0:fbdae7e6d805 | 911 | * APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| borlanic | 0:fbdae7e6d805 | 912 | * APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| borlanic | 0:fbdae7e6d805 | 913 | * APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| borlanic | 0:fbdae7e6d805 | 914 | * APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| borlanic | 0:fbdae7e6d805 | 915 | * APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| borlanic | 0:fbdae7e6d805 | 916 | * APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| borlanic | 0:fbdae7e6d805 | 917 | * APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| borlanic | 0:fbdae7e6d805 | 918 | * APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph |
| borlanic | 0:fbdae7e6d805 | 919 | * @param Periphs This parameter can be a combination of the following values: |
| borlanic | 0:fbdae7e6d805 | 920 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP |
| borlanic | 0:fbdae7e6d805 | 921 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP |
| borlanic | 0:fbdae7e6d805 | 922 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP |
| borlanic | 0:fbdae7e6d805 | 923 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*) |
| borlanic | 0:fbdae7e6d805 | 924 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP |
| borlanic | 0:fbdae7e6d805 | 925 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP |
| borlanic | 0:fbdae7e6d805 | 926 | * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP (*) |
| borlanic | 0:fbdae7e6d805 | 927 | * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP |
| borlanic | 0:fbdae7e6d805 | 928 | * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP |
| borlanic | 0:fbdae7e6d805 | 929 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP |
| borlanic | 0:fbdae7e6d805 | 930 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP |
| borlanic | 0:fbdae7e6d805 | 931 | * (*) value not defined in all devices. |
| borlanic | 0:fbdae7e6d805 | 932 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 933 | */ |
| borlanic | 0:fbdae7e6d805 | 934 | __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) |
| borlanic | 0:fbdae7e6d805 | 935 | { |
| borlanic | 0:fbdae7e6d805 | 936 | CLEAR_BIT(DBGMCU->APB1FZ, Periphs); |
| borlanic | 0:fbdae7e6d805 | 937 | } |
| borlanic | 0:fbdae7e6d805 | 938 | |
| borlanic | 0:fbdae7e6d805 | 939 | /** |
| borlanic | 0:fbdae7e6d805 | 940 | * @brief Freeze APB2 peripherals |
| borlanic | 0:fbdae7e6d805 | 941 | * @rmtoll APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| borlanic | 0:fbdae7e6d805 | 942 | * APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| borlanic | 0:fbdae7e6d805 | 943 | * APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph |
| borlanic | 0:fbdae7e6d805 | 944 | * @param Periphs This parameter can be a combination of the following values: |
| borlanic | 0:fbdae7e6d805 | 945 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP |
| borlanic | 0:fbdae7e6d805 | 946 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP |
| borlanic | 0:fbdae7e6d805 | 947 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP |
| borlanic | 0:fbdae7e6d805 | 948 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 949 | */ |
| borlanic | 0:fbdae7e6d805 | 950 | __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) |
| borlanic | 0:fbdae7e6d805 | 951 | { |
| borlanic | 0:fbdae7e6d805 | 952 | SET_BIT(DBGMCU->APB2FZ, Periphs); |
| borlanic | 0:fbdae7e6d805 | 953 | } |
| borlanic | 0:fbdae7e6d805 | 954 | |
| borlanic | 0:fbdae7e6d805 | 955 | /** |
| borlanic | 0:fbdae7e6d805 | 956 | * @brief Unfreeze APB2 peripherals |
| borlanic | 0:fbdae7e6d805 | 957 | * @rmtoll APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n |
| borlanic | 0:fbdae7e6d805 | 958 | * APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n |
| borlanic | 0:fbdae7e6d805 | 959 | * APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph |
| borlanic | 0:fbdae7e6d805 | 960 | * @param Periphs This parameter can be a combination of the following values: |
| borlanic | 0:fbdae7e6d805 | 961 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP |
| borlanic | 0:fbdae7e6d805 | 962 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP |
| borlanic | 0:fbdae7e6d805 | 963 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP |
| borlanic | 0:fbdae7e6d805 | 964 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 965 | */ |
| borlanic | 0:fbdae7e6d805 | 966 | __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) |
| borlanic | 0:fbdae7e6d805 | 967 | { |
| borlanic | 0:fbdae7e6d805 | 968 | CLEAR_BIT(DBGMCU->APB2FZ, Periphs); |
| borlanic | 0:fbdae7e6d805 | 969 | } |
| borlanic | 0:fbdae7e6d805 | 970 | |
| borlanic | 0:fbdae7e6d805 | 971 | /** |
| borlanic | 0:fbdae7e6d805 | 972 | * @} |
| borlanic | 0:fbdae7e6d805 | 973 | */ |
| borlanic | 0:fbdae7e6d805 | 974 | |
| borlanic | 0:fbdae7e6d805 | 975 | /** @defgroup SYSTEM_LL_EF_RI RI |
| borlanic | 0:fbdae7e6d805 | 976 | * @{ |
| borlanic | 0:fbdae7e6d805 | 977 | */ |
| borlanic | 0:fbdae7e6d805 | 978 | |
| borlanic | 0:fbdae7e6d805 | 979 | /** |
| borlanic | 0:fbdae7e6d805 | 980 | * @brief Configures the routing interface to map Input Capture x of TIMx to a selected I/O pin. |
| borlanic | 0:fbdae7e6d805 | 981 | * @rmtoll RI_ICR IC1OS LL_RI_SetRemapInputCapture_TIM\n |
| borlanic | 0:fbdae7e6d805 | 982 | * RI_ICR IC2OS LL_RI_SetRemapInputCapture_TIM\n |
| borlanic | 0:fbdae7e6d805 | 983 | * RI_ICR IC3OS LL_RI_SetRemapInputCapture_TIM\n |
| borlanic | 0:fbdae7e6d805 | 984 | * RI_ICR IC4OS LL_RI_SetRemapInputCapture_TIM\n |
| borlanic | 0:fbdae7e6d805 | 985 | * RI_ICR TIM LL_RI_SetRemapInputCapture_TIM\n |
| borlanic | 0:fbdae7e6d805 | 986 | * RI_ICR IC1 LL_RI_SetRemapInputCapture_TIM\n |
| borlanic | 0:fbdae7e6d805 | 987 | * RI_ICR IC2 LL_RI_SetRemapInputCapture_TIM\n |
| borlanic | 0:fbdae7e6d805 | 988 | * RI_ICR IC3 LL_RI_SetRemapInputCapture_TIM\n |
| borlanic | 0:fbdae7e6d805 | 989 | * RI_ICR IC4 LL_RI_SetRemapInputCapture_TIM |
| borlanic | 0:fbdae7e6d805 | 990 | * @param TIM_Select This parameter can be one of the following values: |
| borlanic | 0:fbdae7e6d805 | 991 | * @arg @ref LL_RI_TIM_SELECT_NONE |
| borlanic | 0:fbdae7e6d805 | 992 | * @arg @ref LL_RI_TIM_SELECT_TIM2 |
| borlanic | 0:fbdae7e6d805 | 993 | * @arg @ref LL_RI_TIM_SELECT_TIM3 |
| borlanic | 0:fbdae7e6d805 | 994 | * @arg @ref LL_RI_TIM_SELECT_TIM4 |
| borlanic | 0:fbdae7e6d805 | 995 | * @param InputCaptureChannel This parameter can be one of the following values: |
| borlanic | 0:fbdae7e6d805 | 996 | * @arg @ref LL_RI_INPUTCAPTURE_1 |
| borlanic | 0:fbdae7e6d805 | 997 | * @arg @ref LL_RI_INPUTCAPTURE_2 |
| borlanic | 0:fbdae7e6d805 | 998 | * @arg @ref LL_RI_INPUTCAPTURE_3 |
| borlanic | 0:fbdae7e6d805 | 999 | * @arg @ref LL_RI_INPUTCAPTURE_4 |
| borlanic | 0:fbdae7e6d805 | 1000 | * @param Input This parameter can be one of the following values: |
| borlanic | 0:fbdae7e6d805 | 1001 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_0 |
| borlanic | 0:fbdae7e6d805 | 1002 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_1 |
| borlanic | 0:fbdae7e6d805 | 1003 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_2 |
| borlanic | 0:fbdae7e6d805 | 1004 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_3 |
| borlanic | 0:fbdae7e6d805 | 1005 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_4 |
| borlanic | 0:fbdae7e6d805 | 1006 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_5 |
| borlanic | 0:fbdae7e6d805 | 1007 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_6 |
| borlanic | 0:fbdae7e6d805 | 1008 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_7 |
| borlanic | 0:fbdae7e6d805 | 1009 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_8 |
| borlanic | 0:fbdae7e6d805 | 1010 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_9 |
| borlanic | 0:fbdae7e6d805 | 1011 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_10 |
| borlanic | 0:fbdae7e6d805 | 1012 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_11 |
| borlanic | 0:fbdae7e6d805 | 1013 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_12 (*) |
| borlanic | 0:fbdae7e6d805 | 1014 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_13 (*) |
| borlanic | 0:fbdae7e6d805 | 1015 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_14 (*) |
| borlanic | 0:fbdae7e6d805 | 1016 | * @arg @ref LL_RI_INPUTCAPTUREROUTING_15 (*) |
| borlanic | 0:fbdae7e6d805 | 1017 | * |
| borlanic | 0:fbdae7e6d805 | 1018 | * (*) value not defined in all devices. |
| borlanic | 0:fbdae7e6d805 | 1019 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 1020 | */ |
| borlanic | 0:fbdae7e6d805 | 1021 | __STATIC_INLINE void LL_RI_SetRemapInputCapture_TIM(uint32_t TIM_Select, uint32_t InputCaptureChannel, uint32_t Input) |
| borlanic | 0:fbdae7e6d805 | 1022 | { |
| borlanic | 0:fbdae7e6d805 | 1023 | MODIFY_REG(RI->ICR, |
| borlanic | 0:fbdae7e6d805 | 1024 | RI_ICR_TIM | (InputCaptureChannel & (RI_ICR_IC4 | RI_ICR_IC3 | RI_ICR_IC2 | RI_ICR_IC1)) | (InputCaptureChannel & (RI_ICR_IC4OS | RI_ICR_IC3OS | RI_ICR_IC2OS | RI_ICR_IC1OS)), |
| borlanic | 0:fbdae7e6d805 | 1025 | TIM_Select | (InputCaptureChannel & (RI_ICR_IC4 | RI_ICR_IC3 | RI_ICR_IC2 | RI_ICR_IC1)) | (Input << POSITION_VAL(InputCaptureChannel))); |
| borlanic | 0:fbdae7e6d805 | 1026 | } |
| borlanic | 0:fbdae7e6d805 | 1027 | |
| borlanic | 0:fbdae7e6d805 | 1028 | /** |
| borlanic | 0:fbdae7e6d805 | 1029 | * @brief Disable the TIM Input capture remap (select the standard AF) |
| borlanic | 0:fbdae7e6d805 | 1030 | * @rmtoll RI_ICR IC1 LL_RI_DisableRemapInputCapture_TIM\n |
| borlanic | 0:fbdae7e6d805 | 1031 | * RI_ICR IC2 LL_RI_DisableRemapInputCapture_TIM\n |
| borlanic | 0:fbdae7e6d805 | 1032 | * RI_ICR IC3 LL_RI_DisableRemapInputCapture_TIM\n |
| borlanic | 0:fbdae7e6d805 | 1033 | * RI_ICR IC4 LL_RI_DisableRemapInputCapture_TIM |
| borlanic | 0:fbdae7e6d805 | 1034 | * @param InputCaptureChannel This parameter can be a combination of the following values: |
| borlanic | 0:fbdae7e6d805 | 1035 | * @arg @ref LL_RI_INPUTCAPTURE_1 |
| borlanic | 0:fbdae7e6d805 | 1036 | * @arg @ref LL_RI_INPUTCAPTURE_2 |
| borlanic | 0:fbdae7e6d805 | 1037 | * @arg @ref LL_RI_INPUTCAPTURE_3 |
| borlanic | 0:fbdae7e6d805 | 1038 | * @arg @ref LL_RI_INPUTCAPTURE_4 |
| borlanic | 0:fbdae7e6d805 | 1039 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 1040 | */ |
| borlanic | 0:fbdae7e6d805 | 1041 | __STATIC_INLINE void LL_RI_DisableRemapInputCapture_TIM(uint32_t InputCaptureChannel) |
| borlanic | 0:fbdae7e6d805 | 1042 | { |
| borlanic | 0:fbdae7e6d805 | 1043 | CLEAR_BIT(RI->ICR, (InputCaptureChannel & (RI_ICR_IC4 | RI_ICR_IC3 | RI_ICR_IC2 | RI_ICR_IC1))); |
| borlanic | 0:fbdae7e6d805 | 1044 | } |
| borlanic | 0:fbdae7e6d805 | 1045 | |
| borlanic | 0:fbdae7e6d805 | 1046 | /** |
| borlanic | 0:fbdae7e6d805 | 1047 | * @brief Close the routing interface Input Output switches linked to ADC. |
| borlanic | 0:fbdae7e6d805 | 1048 | * @rmtoll RI_ASCR1 CH LL_RI_CloseIOSwitchLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1049 | * RI_ASCR1 VCOMP LL_RI_CloseIOSwitchLinkedToADC |
| borlanic | 0:fbdae7e6d805 | 1050 | * @param IOSwitch This parameter can be a combination of the following values: |
| borlanic | 0:fbdae7e6d805 | 1051 | * @arg @ref LL_RI_IOSWITCH_CH0 |
| borlanic | 0:fbdae7e6d805 | 1052 | * @arg @ref LL_RI_IOSWITCH_CH1 |
| borlanic | 0:fbdae7e6d805 | 1053 | * @arg @ref LL_RI_IOSWITCH_CH2 |
| borlanic | 0:fbdae7e6d805 | 1054 | * @arg @ref LL_RI_IOSWITCH_CH3 |
| borlanic | 0:fbdae7e6d805 | 1055 | * @arg @ref LL_RI_IOSWITCH_CH4 |
| borlanic | 0:fbdae7e6d805 | 1056 | * @arg @ref LL_RI_IOSWITCH_CH5 |
| borlanic | 0:fbdae7e6d805 | 1057 | * @arg @ref LL_RI_IOSWITCH_CH6 |
| borlanic | 0:fbdae7e6d805 | 1058 | * @arg @ref LL_RI_IOSWITCH_CH7 |
| borlanic | 0:fbdae7e6d805 | 1059 | * @arg @ref LL_RI_IOSWITCH_CH8 |
| borlanic | 0:fbdae7e6d805 | 1060 | * @arg @ref LL_RI_IOSWITCH_CH9 |
| borlanic | 0:fbdae7e6d805 | 1061 | * @arg @ref LL_RI_IOSWITCH_CH10 |
| borlanic | 0:fbdae7e6d805 | 1062 | * @arg @ref LL_RI_IOSWITCH_CH11 |
| borlanic | 0:fbdae7e6d805 | 1063 | * @arg @ref LL_RI_IOSWITCH_CH12 |
| borlanic | 0:fbdae7e6d805 | 1064 | * @arg @ref LL_RI_IOSWITCH_CH13 |
| borlanic | 0:fbdae7e6d805 | 1065 | * @arg @ref LL_RI_IOSWITCH_CH14 |
| borlanic | 0:fbdae7e6d805 | 1066 | * @arg @ref LL_RI_IOSWITCH_CH15 |
| borlanic | 0:fbdae7e6d805 | 1067 | * @arg @ref LL_RI_IOSWITCH_CH18 |
| borlanic | 0:fbdae7e6d805 | 1068 | * @arg @ref LL_RI_IOSWITCH_CH19 |
| borlanic | 0:fbdae7e6d805 | 1069 | * @arg @ref LL_RI_IOSWITCH_CH20 |
| borlanic | 0:fbdae7e6d805 | 1070 | * @arg @ref LL_RI_IOSWITCH_CH21 |
| borlanic | 0:fbdae7e6d805 | 1071 | * @arg @ref LL_RI_IOSWITCH_CH22 |
| borlanic | 0:fbdae7e6d805 | 1072 | * @arg @ref LL_RI_IOSWITCH_CH23 |
| borlanic | 0:fbdae7e6d805 | 1073 | * @arg @ref LL_RI_IOSWITCH_CH24 |
| borlanic | 0:fbdae7e6d805 | 1074 | * @arg @ref LL_RI_IOSWITCH_CH25 |
| borlanic | 0:fbdae7e6d805 | 1075 | * @arg @ref LL_RI_IOSWITCH_VCOMP |
| borlanic | 0:fbdae7e6d805 | 1076 | * @arg @ref LL_RI_IOSWITCH_CH27 (*) |
| borlanic | 0:fbdae7e6d805 | 1077 | * @arg @ref LL_RI_IOSWITCH_CH28 (*) |
| borlanic | 0:fbdae7e6d805 | 1078 | * @arg @ref LL_RI_IOSWITCH_CH29 (*) |
| borlanic | 0:fbdae7e6d805 | 1079 | * @arg @ref LL_RI_IOSWITCH_CH30 (*) |
| borlanic | 0:fbdae7e6d805 | 1080 | * @arg @ref LL_RI_IOSWITCH_CH31 (*) |
| borlanic | 0:fbdae7e6d805 | 1081 | * |
| borlanic | 0:fbdae7e6d805 | 1082 | * (*) value not defined in all devices. |
| borlanic | 0:fbdae7e6d805 | 1083 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 1084 | */ |
| borlanic | 0:fbdae7e6d805 | 1085 | __STATIC_INLINE void LL_RI_CloseIOSwitchLinkedToADC(uint32_t IOSwitch) |
| borlanic | 0:fbdae7e6d805 | 1086 | { |
| borlanic | 0:fbdae7e6d805 | 1087 | SET_BIT(RI->ASCR1, IOSwitch); |
| borlanic | 0:fbdae7e6d805 | 1088 | } |
| borlanic | 0:fbdae7e6d805 | 1089 | |
| borlanic | 0:fbdae7e6d805 | 1090 | /** |
| borlanic | 0:fbdae7e6d805 | 1091 | * @brief Open the routing interface Input Output switches linked to ADC. |
| borlanic | 0:fbdae7e6d805 | 1092 | * @rmtoll RI_ASCR1 CH LL_RI_OpenIOSwitchLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1093 | * RI_ASCR1 VCOMP LL_RI_OpenIOSwitchLinkedToADC |
| borlanic | 0:fbdae7e6d805 | 1094 | * @param IOSwitch This parameter can be a combination of the following values: |
| borlanic | 0:fbdae7e6d805 | 1095 | * @arg @ref LL_RI_IOSWITCH_CH0 |
| borlanic | 0:fbdae7e6d805 | 1096 | * @arg @ref LL_RI_IOSWITCH_CH1 |
| borlanic | 0:fbdae7e6d805 | 1097 | * @arg @ref LL_RI_IOSWITCH_CH2 |
| borlanic | 0:fbdae7e6d805 | 1098 | * @arg @ref LL_RI_IOSWITCH_CH3 |
| borlanic | 0:fbdae7e6d805 | 1099 | * @arg @ref LL_RI_IOSWITCH_CH4 |
| borlanic | 0:fbdae7e6d805 | 1100 | * @arg @ref LL_RI_IOSWITCH_CH5 |
| borlanic | 0:fbdae7e6d805 | 1101 | * @arg @ref LL_RI_IOSWITCH_CH6 |
| borlanic | 0:fbdae7e6d805 | 1102 | * @arg @ref LL_RI_IOSWITCH_CH7 |
| borlanic | 0:fbdae7e6d805 | 1103 | * @arg @ref LL_RI_IOSWITCH_CH8 |
| borlanic | 0:fbdae7e6d805 | 1104 | * @arg @ref LL_RI_IOSWITCH_CH9 |
| borlanic | 0:fbdae7e6d805 | 1105 | * @arg @ref LL_RI_IOSWITCH_CH10 |
| borlanic | 0:fbdae7e6d805 | 1106 | * @arg @ref LL_RI_IOSWITCH_CH11 |
| borlanic | 0:fbdae7e6d805 | 1107 | * @arg @ref LL_RI_IOSWITCH_CH12 |
| borlanic | 0:fbdae7e6d805 | 1108 | * @arg @ref LL_RI_IOSWITCH_CH13 |
| borlanic | 0:fbdae7e6d805 | 1109 | * @arg @ref LL_RI_IOSWITCH_CH14 |
| borlanic | 0:fbdae7e6d805 | 1110 | * @arg @ref LL_RI_IOSWITCH_CH15 |
| borlanic | 0:fbdae7e6d805 | 1111 | * @arg @ref LL_RI_IOSWITCH_CH18 |
| borlanic | 0:fbdae7e6d805 | 1112 | * @arg @ref LL_RI_IOSWITCH_CH19 |
| borlanic | 0:fbdae7e6d805 | 1113 | * @arg @ref LL_RI_IOSWITCH_CH20 |
| borlanic | 0:fbdae7e6d805 | 1114 | * @arg @ref LL_RI_IOSWITCH_CH21 |
| borlanic | 0:fbdae7e6d805 | 1115 | * @arg @ref LL_RI_IOSWITCH_CH22 |
| borlanic | 0:fbdae7e6d805 | 1116 | * @arg @ref LL_RI_IOSWITCH_CH23 |
| borlanic | 0:fbdae7e6d805 | 1117 | * @arg @ref LL_RI_IOSWITCH_CH24 |
| borlanic | 0:fbdae7e6d805 | 1118 | * @arg @ref LL_RI_IOSWITCH_CH25 |
| borlanic | 0:fbdae7e6d805 | 1119 | * @arg @ref LL_RI_IOSWITCH_VCOMP |
| borlanic | 0:fbdae7e6d805 | 1120 | * @arg @ref LL_RI_IOSWITCH_CH27 (*) |
| borlanic | 0:fbdae7e6d805 | 1121 | * @arg @ref LL_RI_IOSWITCH_CH28 (*) |
| borlanic | 0:fbdae7e6d805 | 1122 | * @arg @ref LL_RI_IOSWITCH_CH29 (*) |
| borlanic | 0:fbdae7e6d805 | 1123 | * @arg @ref LL_RI_IOSWITCH_CH30 (*) |
| borlanic | 0:fbdae7e6d805 | 1124 | * @arg @ref LL_RI_IOSWITCH_CH31 (*) |
| borlanic | 0:fbdae7e6d805 | 1125 | * |
| borlanic | 0:fbdae7e6d805 | 1126 | * (*) value not defined in all devices. |
| borlanic | 0:fbdae7e6d805 | 1127 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 1128 | */ |
| borlanic | 0:fbdae7e6d805 | 1129 | __STATIC_INLINE void LL_RI_OpenIOSwitchLinkedToADC(uint32_t IOSwitch) |
| borlanic | 0:fbdae7e6d805 | 1130 | { |
| borlanic | 0:fbdae7e6d805 | 1131 | CLEAR_BIT(RI->ASCR1, IOSwitch); |
| borlanic | 0:fbdae7e6d805 | 1132 | } |
| borlanic | 0:fbdae7e6d805 | 1133 | |
| borlanic | 0:fbdae7e6d805 | 1134 | /** |
| borlanic | 0:fbdae7e6d805 | 1135 | * @brief Enable the switch control mode. |
| borlanic | 0:fbdae7e6d805 | 1136 | * @rmtoll RI_ASCR1 SCM LL_RI_EnableSwitchControlMode |
| borlanic | 0:fbdae7e6d805 | 1137 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 1138 | */ |
| borlanic | 0:fbdae7e6d805 | 1139 | __STATIC_INLINE void LL_RI_EnableSwitchControlMode(void) |
| borlanic | 0:fbdae7e6d805 | 1140 | { |
| borlanic | 0:fbdae7e6d805 | 1141 | SET_BIT(RI->ASCR1, RI_ASCR1_SCM); |
| borlanic | 0:fbdae7e6d805 | 1142 | } |
| borlanic | 0:fbdae7e6d805 | 1143 | |
| borlanic | 0:fbdae7e6d805 | 1144 | /** |
| borlanic | 0:fbdae7e6d805 | 1145 | * @brief Disable the switch control mode. |
| borlanic | 0:fbdae7e6d805 | 1146 | * @rmtoll RI_ASCR1 SCM LL_RI_DisableSwitchControlMode |
| borlanic | 0:fbdae7e6d805 | 1147 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 1148 | */ |
| borlanic | 0:fbdae7e6d805 | 1149 | __STATIC_INLINE void LL_RI_DisableSwitchControlMode(void) |
| borlanic | 0:fbdae7e6d805 | 1150 | { |
| borlanic | 0:fbdae7e6d805 | 1151 | CLEAR_BIT(RI->ASCR1, RI_ASCR1_SCM); |
| borlanic | 0:fbdae7e6d805 | 1152 | } |
| borlanic | 0:fbdae7e6d805 | 1153 | |
| borlanic | 0:fbdae7e6d805 | 1154 | /** |
| borlanic | 0:fbdae7e6d805 | 1155 | * @brief Close the routing interface Input Output switches not linked to ADC. |
| borlanic | 0:fbdae7e6d805 | 1156 | * @rmtoll RI_ASCR2 GR10_1 LL_RI_CloseIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1157 | * RI_ASCR2 GR10_2 LL_RI_CloseIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1158 | * RI_ASCR2 GR10_3 LL_RI_CloseIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1159 | * RI_ASCR2 GR10_4 LL_RI_CloseIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1160 | * RI_ASCR2 GR6_1 LL_RI_CloseIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1161 | * RI_ASCR2 GR6_2 LL_RI_CloseIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1162 | * RI_ASCR2 GR5_1 LL_RI_CloseIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1163 | * RI_ASCR2 GR5_2 LL_RI_CloseIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1164 | * RI_ASCR2 GR5_3 LL_RI_CloseIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1165 | * RI_ASCR2 GR4_1 LL_RI_CloseIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1166 | * RI_ASCR2 GR4_2 LL_RI_CloseIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1167 | * RI_ASCR2 GR4_3 LL_RI_CloseIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1168 | * RI_ASCR2 GR4_4 LL_RI_CloseIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1169 | * RI_ASCR2 CH0b LL_RI_CloseIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1170 | * RI_ASCR2 CH1b LL_RI_CloseIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1171 | * RI_ASCR2 CH2b LL_RI_CloseIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1172 | * RI_ASCR2 CH3b LL_RI_CloseIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1173 | * RI_ASCR2 CH6b LL_RI_CloseIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1174 | * RI_ASCR2 CH7b LL_RI_CloseIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1175 | * RI_ASCR2 CH8b LL_RI_CloseIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1176 | * RI_ASCR2 CH9b LL_RI_CloseIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1177 | * RI_ASCR2 CH10b LL_RI_CloseIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1178 | * RI_ASCR2 CH11b LL_RI_CloseIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1179 | * RI_ASCR2 CH12b LL_RI_CloseIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1180 | * RI_ASCR2 GR6_3 LL_RI_CloseIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1181 | * RI_ASCR2 GR6_4 LL_RI_CloseIOSwitchNotLinkedToADC |
| borlanic | 0:fbdae7e6d805 | 1182 | * @param IOSwitch This parameter can be a combination of the following values: |
| borlanic | 0:fbdae7e6d805 | 1183 | * @arg @ref LL_RI_IOSWITCH_GR10_1 |
| borlanic | 0:fbdae7e6d805 | 1184 | * @arg @ref LL_RI_IOSWITCH_GR10_2 |
| borlanic | 0:fbdae7e6d805 | 1185 | * @arg @ref LL_RI_IOSWITCH_GR10_3 |
| borlanic | 0:fbdae7e6d805 | 1186 | * @arg @ref LL_RI_IOSWITCH_GR10_4 |
| borlanic | 0:fbdae7e6d805 | 1187 | * @arg @ref LL_RI_IOSWITCH_GR6_1 |
| borlanic | 0:fbdae7e6d805 | 1188 | * @arg @ref LL_RI_IOSWITCH_GR6_2 |
| borlanic | 0:fbdae7e6d805 | 1189 | * @arg @ref LL_RI_IOSWITCH_GR5_1 |
| borlanic | 0:fbdae7e6d805 | 1190 | * @arg @ref LL_RI_IOSWITCH_GR5_2 |
| borlanic | 0:fbdae7e6d805 | 1191 | * @arg @ref LL_RI_IOSWITCH_GR5_3 |
| borlanic | 0:fbdae7e6d805 | 1192 | * @arg @ref LL_RI_IOSWITCH_GR4_1 |
| borlanic | 0:fbdae7e6d805 | 1193 | * @arg @ref LL_RI_IOSWITCH_GR4_2 |
| borlanic | 0:fbdae7e6d805 | 1194 | * @arg @ref LL_RI_IOSWITCH_GR4_3 |
| borlanic | 0:fbdae7e6d805 | 1195 | * @arg @ref LL_RI_IOSWITCH_CH0b (*) |
| borlanic | 0:fbdae7e6d805 | 1196 | * @arg @ref LL_RI_IOSWITCH_CH1b (*) |
| borlanic | 0:fbdae7e6d805 | 1197 | * @arg @ref LL_RI_IOSWITCH_CH2b (*) |
| borlanic | 0:fbdae7e6d805 | 1198 | * @arg @ref LL_RI_IOSWITCH_CH3b (*) |
| borlanic | 0:fbdae7e6d805 | 1199 | * @arg @ref LL_RI_IOSWITCH_CH6b (*) |
| borlanic | 0:fbdae7e6d805 | 1200 | * @arg @ref LL_RI_IOSWITCH_CH7b (*) |
| borlanic | 0:fbdae7e6d805 | 1201 | * @arg @ref LL_RI_IOSWITCH_CH8b (*) |
| borlanic | 0:fbdae7e6d805 | 1202 | * @arg @ref LL_RI_IOSWITCH_CH9b (*) |
| borlanic | 0:fbdae7e6d805 | 1203 | * @arg @ref LL_RI_IOSWITCH_CH10b (*) |
| borlanic | 0:fbdae7e6d805 | 1204 | * @arg @ref LL_RI_IOSWITCH_CH11b (*) |
| borlanic | 0:fbdae7e6d805 | 1205 | * @arg @ref LL_RI_IOSWITCH_CH12b (*) |
| borlanic | 0:fbdae7e6d805 | 1206 | * @arg @ref LL_RI_IOSWITCH_GR6_3 |
| borlanic | 0:fbdae7e6d805 | 1207 | * @arg @ref LL_RI_IOSWITCH_GR6_4 |
| borlanic | 0:fbdae7e6d805 | 1208 | * |
| borlanic | 0:fbdae7e6d805 | 1209 | * (*) value not defined in all devices. |
| borlanic | 0:fbdae7e6d805 | 1210 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 1211 | */ |
| borlanic | 0:fbdae7e6d805 | 1212 | __STATIC_INLINE void LL_RI_CloseIOSwitchNotLinkedToADC(uint32_t IOSwitch) |
| borlanic | 0:fbdae7e6d805 | 1213 | { |
| borlanic | 0:fbdae7e6d805 | 1214 | SET_BIT(RI->ASCR2, IOSwitch); |
| borlanic | 0:fbdae7e6d805 | 1215 | } |
| borlanic | 0:fbdae7e6d805 | 1216 | |
| borlanic | 0:fbdae7e6d805 | 1217 | /** |
| borlanic | 0:fbdae7e6d805 | 1218 | * @brief Open the routing interface Input Output switches not linked to ADC. |
| borlanic | 0:fbdae7e6d805 | 1219 | * @rmtoll RI_ASCR2 GR10_1 LL_RI_OpenIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1220 | * RI_ASCR2 GR10_2 LL_RI_OpenIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1221 | * RI_ASCR2 GR10_3 LL_RI_OpenIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1222 | * RI_ASCR2 GR10_4 LL_RI_OpenIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1223 | * RI_ASCR2 GR6_1 LL_RI_OpenIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1224 | * RI_ASCR2 GR6_2 LL_RI_OpenIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1225 | * RI_ASCR2 GR5_1 LL_RI_OpenIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1226 | * RI_ASCR2 GR5_2 LL_RI_OpenIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1227 | * RI_ASCR2 GR5_3 LL_RI_OpenIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1228 | * RI_ASCR2 GR4_1 LL_RI_OpenIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1229 | * RI_ASCR2 GR4_2 LL_RI_OpenIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1230 | * RI_ASCR2 GR4_3 LL_RI_OpenIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1231 | * RI_ASCR2 GR4_4 LL_RI_OpenIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1232 | * RI_ASCR2 CH0b LL_RI_OpenIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1233 | * RI_ASCR2 CH1b LL_RI_OpenIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1234 | * RI_ASCR2 CH2b LL_RI_OpenIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1235 | * RI_ASCR2 CH3b LL_RI_OpenIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1236 | * RI_ASCR2 CH6b LL_RI_OpenIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1237 | * RI_ASCR2 CH7b LL_RI_OpenIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1238 | * RI_ASCR2 CH8b LL_RI_OpenIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1239 | * RI_ASCR2 CH9b LL_RI_OpenIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1240 | * RI_ASCR2 CH10b LL_RI_OpenIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1241 | * RI_ASCR2 CH11b LL_RI_OpenIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1242 | * RI_ASCR2 CH12b LL_RI_OpenIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1243 | * RI_ASCR2 GR6_3 LL_RI_OpenIOSwitchNotLinkedToADC\n |
| borlanic | 0:fbdae7e6d805 | 1244 | * RI_ASCR2 GR6_4 LL_RI_OpenIOSwitchNotLinkedToADC |
| borlanic | 0:fbdae7e6d805 | 1245 | * @param IOSwitch This parameter can be a combination of the following values: |
| borlanic | 0:fbdae7e6d805 | 1246 | * @arg @ref LL_RI_IOSWITCH_GR10_1 |
| borlanic | 0:fbdae7e6d805 | 1247 | * @arg @ref LL_RI_IOSWITCH_GR10_2 |
| borlanic | 0:fbdae7e6d805 | 1248 | * @arg @ref LL_RI_IOSWITCH_GR10_3 |
| borlanic | 0:fbdae7e6d805 | 1249 | * @arg @ref LL_RI_IOSWITCH_GR10_4 |
| borlanic | 0:fbdae7e6d805 | 1250 | * @arg @ref LL_RI_IOSWITCH_GR6_1 |
| borlanic | 0:fbdae7e6d805 | 1251 | * @arg @ref LL_RI_IOSWITCH_GR6_2 |
| borlanic | 0:fbdae7e6d805 | 1252 | * @arg @ref LL_RI_IOSWITCH_GR5_1 |
| borlanic | 0:fbdae7e6d805 | 1253 | * @arg @ref LL_RI_IOSWITCH_GR5_2 |
| borlanic | 0:fbdae7e6d805 | 1254 | * @arg @ref LL_RI_IOSWITCH_GR5_3 |
| borlanic | 0:fbdae7e6d805 | 1255 | * @arg @ref LL_RI_IOSWITCH_GR4_1 |
| borlanic | 0:fbdae7e6d805 | 1256 | * @arg @ref LL_RI_IOSWITCH_GR4_2 |
| borlanic | 0:fbdae7e6d805 | 1257 | * @arg @ref LL_RI_IOSWITCH_GR4_3 |
| borlanic | 0:fbdae7e6d805 | 1258 | * @arg @ref LL_RI_IOSWITCH_CH0b (*) |
| borlanic | 0:fbdae7e6d805 | 1259 | * @arg @ref LL_RI_IOSWITCH_CH1b (*) |
| borlanic | 0:fbdae7e6d805 | 1260 | * @arg @ref LL_RI_IOSWITCH_CH2b (*) |
| borlanic | 0:fbdae7e6d805 | 1261 | * @arg @ref LL_RI_IOSWITCH_CH3b (*) |
| borlanic | 0:fbdae7e6d805 | 1262 | * @arg @ref LL_RI_IOSWITCH_CH6b (*) |
| borlanic | 0:fbdae7e6d805 | 1263 | * @arg @ref LL_RI_IOSWITCH_CH7b (*) |
| borlanic | 0:fbdae7e6d805 | 1264 | * @arg @ref LL_RI_IOSWITCH_CH8b (*) |
| borlanic | 0:fbdae7e6d805 | 1265 | * @arg @ref LL_RI_IOSWITCH_CH9b (*) |
| borlanic | 0:fbdae7e6d805 | 1266 | * @arg @ref LL_RI_IOSWITCH_CH10b (*) |
| borlanic | 0:fbdae7e6d805 | 1267 | * @arg @ref LL_RI_IOSWITCH_CH11b (*) |
| borlanic | 0:fbdae7e6d805 | 1268 | * @arg @ref LL_RI_IOSWITCH_CH12b (*) |
| borlanic | 0:fbdae7e6d805 | 1269 | * @arg @ref LL_RI_IOSWITCH_GR6_3 |
| borlanic | 0:fbdae7e6d805 | 1270 | * @arg @ref LL_RI_IOSWITCH_GR6_4 |
| borlanic | 0:fbdae7e6d805 | 1271 | * |
| borlanic | 0:fbdae7e6d805 | 1272 | * (*) value not defined in all devices. |
| borlanic | 0:fbdae7e6d805 | 1273 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 1274 | */ |
| borlanic | 0:fbdae7e6d805 | 1275 | __STATIC_INLINE void LL_RI_OpenIOSwitchNotLinkedToADC(uint32_t IOSwitch) |
| borlanic | 0:fbdae7e6d805 | 1276 | { |
| borlanic | 0:fbdae7e6d805 | 1277 | CLEAR_BIT(RI->ASCR2, IOSwitch); |
| borlanic | 0:fbdae7e6d805 | 1278 | } |
| borlanic | 0:fbdae7e6d805 | 1279 | |
| borlanic | 0:fbdae7e6d805 | 1280 | /** |
| borlanic | 0:fbdae7e6d805 | 1281 | * @brief Enable Hysteresis of the input schmitt triger of the port X |
| borlanic | 0:fbdae7e6d805 | 1282 | * @rmtoll RI_HYSCR1 PA LL_RI_EnableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1283 | * RI_HYSCR1 PB LL_RI_EnableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1284 | * RI_HYSCR1 PC LL_RI_EnableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1285 | * RI_HYSCR1 PD LL_RI_EnableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1286 | * RI_HYSCR1 PE LL_RI_EnableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1287 | * RI_HYSCR1 PF LL_RI_EnableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1288 | * RI_HYSCR1 PG LL_RI_EnableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1289 | * RI_HYSCR2 PA LL_RI_EnableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1290 | * RI_HYSCR2 PB LL_RI_EnableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1291 | * RI_HYSCR2 PC LL_RI_EnableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1292 | * RI_HYSCR2 PD LL_RI_EnableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1293 | * RI_HYSCR2 PE LL_RI_EnableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1294 | * RI_HYSCR2 PF LL_RI_EnableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1295 | * RI_HYSCR2 PG LL_RI_EnableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1296 | * RI_HYSCR3 PA LL_RI_EnableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1297 | * RI_HYSCR3 PB LL_RI_EnableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1298 | * RI_HYSCR3 PC LL_RI_EnableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1299 | * RI_HYSCR3 PD LL_RI_EnableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1300 | * RI_HYSCR3 PE LL_RI_EnableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1301 | * RI_HYSCR3 PF LL_RI_EnableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1302 | * RI_HYSCR3 PG LL_RI_EnableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1303 | * RI_HYSCR4 PA LL_RI_EnableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1304 | * RI_HYSCR4 PB LL_RI_EnableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1305 | * RI_HYSCR4 PC LL_RI_EnableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1306 | * RI_HYSCR4 PD LL_RI_EnableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1307 | * RI_HYSCR4 PE LL_RI_EnableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1308 | * RI_HYSCR4 PF LL_RI_EnableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1309 | * RI_HYSCR4 PG LL_RI_EnableHysteresis |
| borlanic | 0:fbdae7e6d805 | 1310 | * @param Port This parameter can be one of the following values: |
| borlanic | 0:fbdae7e6d805 | 1311 | * @arg @ref LL_RI_HSYTERESIS_PORT_A |
| borlanic | 0:fbdae7e6d805 | 1312 | * @arg @ref LL_RI_HSYTERESIS_PORT_B |
| borlanic | 0:fbdae7e6d805 | 1313 | * @arg @ref LL_RI_HSYTERESIS_PORT_C |
| borlanic | 0:fbdae7e6d805 | 1314 | * @arg @ref LL_RI_HSYTERESIS_PORT_D |
| borlanic | 0:fbdae7e6d805 | 1315 | * @arg @ref LL_RI_HSYTERESIS_PORT_E (*) |
| borlanic | 0:fbdae7e6d805 | 1316 | * @arg @ref LL_RI_HSYTERESIS_PORT_F (*) |
| borlanic | 0:fbdae7e6d805 | 1317 | * @arg @ref LL_RI_HSYTERESIS_PORT_G (*) |
| borlanic | 0:fbdae7e6d805 | 1318 | * |
| borlanic | 0:fbdae7e6d805 | 1319 | * (*) value not defined in all devices. |
| borlanic | 0:fbdae7e6d805 | 1320 | * @param Pin This parameter can be a combination of the following values: |
| borlanic | 0:fbdae7e6d805 | 1321 | * @arg @ref LL_RI_PIN_0 |
| borlanic | 0:fbdae7e6d805 | 1322 | * @arg @ref LL_RI_PIN_1 |
| borlanic | 0:fbdae7e6d805 | 1323 | * @arg @ref LL_RI_PIN_2 |
| borlanic | 0:fbdae7e6d805 | 1324 | * @arg @ref LL_RI_PIN_3 |
| borlanic | 0:fbdae7e6d805 | 1325 | * @arg @ref LL_RI_PIN_4 |
| borlanic | 0:fbdae7e6d805 | 1326 | * @arg @ref LL_RI_PIN_5 |
| borlanic | 0:fbdae7e6d805 | 1327 | * @arg @ref LL_RI_PIN_6 |
| borlanic | 0:fbdae7e6d805 | 1328 | * @arg @ref LL_RI_PIN_7 |
| borlanic | 0:fbdae7e6d805 | 1329 | * @arg @ref LL_RI_PIN_8 |
| borlanic | 0:fbdae7e6d805 | 1330 | * @arg @ref LL_RI_PIN_9 |
| borlanic | 0:fbdae7e6d805 | 1331 | * @arg @ref LL_RI_PIN_10 |
| borlanic | 0:fbdae7e6d805 | 1332 | * @arg @ref LL_RI_PIN_11 |
| borlanic | 0:fbdae7e6d805 | 1333 | * @arg @ref LL_RI_PIN_12 |
| borlanic | 0:fbdae7e6d805 | 1334 | * @arg @ref LL_RI_PIN_13 |
| borlanic | 0:fbdae7e6d805 | 1335 | * @arg @ref LL_RI_PIN_14 |
| borlanic | 0:fbdae7e6d805 | 1336 | * @arg @ref LL_RI_PIN_15 |
| borlanic | 0:fbdae7e6d805 | 1337 | * @arg @ref LL_RI_PIN_ALL |
| borlanic | 0:fbdae7e6d805 | 1338 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 1339 | */ |
| borlanic | 0:fbdae7e6d805 | 1340 | __STATIC_INLINE void LL_RI_EnableHysteresis(uint32_t Port, uint32_t Pin) |
| borlanic | 0:fbdae7e6d805 | 1341 | { |
| borlanic | 0:fbdae7e6d805 | 1342 | __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->HYSCR1) + (Port >> 1)); |
| borlanic | 0:fbdae7e6d805 | 1343 | CLEAR_BIT(*reg, Pin << (16 * (Port & 1))); |
| borlanic | 0:fbdae7e6d805 | 1344 | } |
| borlanic | 0:fbdae7e6d805 | 1345 | |
| borlanic | 0:fbdae7e6d805 | 1346 | /** |
| borlanic | 0:fbdae7e6d805 | 1347 | * @brief Disable Hysteresis of the input schmitt triger of the port X |
| borlanic | 0:fbdae7e6d805 | 1348 | * @rmtoll RI_HYSCR1 PA LL_RI_DisableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1349 | * RI_HYSCR1 PB LL_RI_DisableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1350 | * RI_HYSCR1 PC LL_RI_DisableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1351 | * RI_HYSCR1 PD LL_RI_DisableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1352 | * RI_HYSCR1 PE LL_RI_DisableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1353 | * RI_HYSCR1 PF LL_RI_DisableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1354 | * RI_HYSCR1 PG LL_RI_DisableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1355 | * RI_HYSCR2 PA LL_RI_DisableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1356 | * RI_HYSCR2 PB LL_RI_DisableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1357 | * RI_HYSCR2 PC LL_RI_DisableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1358 | * RI_HYSCR2 PD LL_RI_DisableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1359 | * RI_HYSCR2 PE LL_RI_DisableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1360 | * RI_HYSCR2 PF LL_RI_DisableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1361 | * RI_HYSCR2 PG LL_RI_DisableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1362 | * RI_HYSCR3 PA LL_RI_DisableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1363 | * RI_HYSCR3 PB LL_RI_DisableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1364 | * RI_HYSCR3 PC LL_RI_DisableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1365 | * RI_HYSCR3 PD LL_RI_DisableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1366 | * RI_HYSCR3 PE LL_RI_DisableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1367 | * RI_HYSCR3 PF LL_RI_DisableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1368 | * RI_HYSCR3 PG LL_RI_DisableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1369 | * RI_HYSCR4 PA LL_RI_DisableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1370 | * RI_HYSCR4 PB LL_RI_DisableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1371 | * RI_HYSCR4 PC LL_RI_DisableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1372 | * RI_HYSCR4 PD LL_RI_DisableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1373 | * RI_HYSCR4 PE LL_RI_DisableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1374 | * RI_HYSCR4 PF LL_RI_DisableHysteresis\n |
| borlanic | 0:fbdae7e6d805 | 1375 | * RI_HYSCR4 PG LL_RI_DisableHysteresis |
| borlanic | 0:fbdae7e6d805 | 1376 | * @param Port This parameter can be one of the following values: |
| borlanic | 0:fbdae7e6d805 | 1377 | * @arg @ref LL_RI_HSYTERESIS_PORT_A |
| borlanic | 0:fbdae7e6d805 | 1378 | * @arg @ref LL_RI_HSYTERESIS_PORT_B |
| borlanic | 0:fbdae7e6d805 | 1379 | * @arg @ref LL_RI_HSYTERESIS_PORT_C |
| borlanic | 0:fbdae7e6d805 | 1380 | * @arg @ref LL_RI_HSYTERESIS_PORT_D |
| borlanic | 0:fbdae7e6d805 | 1381 | * @arg @ref LL_RI_HSYTERESIS_PORT_E (*) |
| borlanic | 0:fbdae7e6d805 | 1382 | * @arg @ref LL_RI_HSYTERESIS_PORT_F (*) |
| borlanic | 0:fbdae7e6d805 | 1383 | * @arg @ref LL_RI_HSYTERESIS_PORT_G (*) |
| borlanic | 0:fbdae7e6d805 | 1384 | * |
| borlanic | 0:fbdae7e6d805 | 1385 | * (*) value not defined in all devices. |
| borlanic | 0:fbdae7e6d805 | 1386 | * @param Pin This parameter can be a combination of the following values: |
| borlanic | 0:fbdae7e6d805 | 1387 | * @arg @ref LL_RI_PIN_0 |
| borlanic | 0:fbdae7e6d805 | 1388 | * @arg @ref LL_RI_PIN_1 |
| borlanic | 0:fbdae7e6d805 | 1389 | * @arg @ref LL_RI_PIN_2 |
| borlanic | 0:fbdae7e6d805 | 1390 | * @arg @ref LL_RI_PIN_3 |
| borlanic | 0:fbdae7e6d805 | 1391 | * @arg @ref LL_RI_PIN_4 |
| borlanic | 0:fbdae7e6d805 | 1392 | * @arg @ref LL_RI_PIN_5 |
| borlanic | 0:fbdae7e6d805 | 1393 | * @arg @ref LL_RI_PIN_6 |
| borlanic | 0:fbdae7e6d805 | 1394 | * @arg @ref LL_RI_PIN_7 |
| borlanic | 0:fbdae7e6d805 | 1395 | * @arg @ref LL_RI_PIN_8 |
| borlanic | 0:fbdae7e6d805 | 1396 | * @arg @ref LL_RI_PIN_9 |
| borlanic | 0:fbdae7e6d805 | 1397 | * @arg @ref LL_RI_PIN_10 |
| borlanic | 0:fbdae7e6d805 | 1398 | * @arg @ref LL_RI_PIN_11 |
| borlanic | 0:fbdae7e6d805 | 1399 | * @arg @ref LL_RI_PIN_12 |
| borlanic | 0:fbdae7e6d805 | 1400 | * @arg @ref LL_RI_PIN_13 |
| borlanic | 0:fbdae7e6d805 | 1401 | * @arg @ref LL_RI_PIN_14 |
| borlanic | 0:fbdae7e6d805 | 1402 | * @arg @ref LL_RI_PIN_15 |
| borlanic | 0:fbdae7e6d805 | 1403 | * @arg @ref LL_RI_PIN_ALL |
| borlanic | 0:fbdae7e6d805 | 1404 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 1405 | */ |
| borlanic | 0:fbdae7e6d805 | 1406 | __STATIC_INLINE void LL_RI_DisableHysteresis(uint32_t Port, uint32_t Pin) |
| borlanic | 0:fbdae7e6d805 | 1407 | { |
| borlanic | 0:fbdae7e6d805 | 1408 | __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->HYSCR1) + ((Port >> 1) << 2)); |
| borlanic | 0:fbdae7e6d805 | 1409 | SET_BIT(*reg, Pin << (16 * (Port & 1))); |
| borlanic | 0:fbdae7e6d805 | 1410 | } |
| borlanic | 0:fbdae7e6d805 | 1411 | |
| borlanic | 0:fbdae7e6d805 | 1412 | #if defined(RI_ASMR1_PA) |
| borlanic | 0:fbdae7e6d805 | 1413 | /** |
| borlanic | 0:fbdae7e6d805 | 1414 | * @brief Control analog switches of port X through the ADC interface or RI_ASCRx registers. |
| borlanic | 0:fbdae7e6d805 | 1415 | * @rmtoll RI_ASMR1 PA LL_RI_ControlSwitchByADC\n |
| borlanic | 0:fbdae7e6d805 | 1416 | * RI_ASMR1 PB LL_RI_ControlSwitchByADC\n |
| borlanic | 0:fbdae7e6d805 | 1417 | * RI_ASMR1 PC LL_RI_ControlSwitchByADC\n |
| borlanic | 0:fbdae7e6d805 | 1418 | * RI_ASMR1 PF LL_RI_ControlSwitchByADC\n |
| borlanic | 0:fbdae7e6d805 | 1419 | * RI_ASMR1 PG LL_RI_ControlSwitchByADC\n |
| borlanic | 0:fbdae7e6d805 | 1420 | * RI_ASMR2 PA LL_RI_ControlSwitchByADC\n |
| borlanic | 0:fbdae7e6d805 | 1421 | * RI_ASMR2 PB LL_RI_ControlSwitchByADC\n |
| borlanic | 0:fbdae7e6d805 | 1422 | * RI_ASMR2 PC LL_RI_ControlSwitchByADC\n |
| borlanic | 0:fbdae7e6d805 | 1423 | * RI_ASMR2 PF LL_RI_ControlSwitchByADC\n |
| borlanic | 0:fbdae7e6d805 | 1424 | * RI_ASMR2 PG LL_RI_ControlSwitchByADC\n |
| borlanic | 0:fbdae7e6d805 | 1425 | * RI_ASMR3 PA LL_RI_ControlSwitchByADC\n |
| borlanic | 0:fbdae7e6d805 | 1426 | * RI_ASMR3 PB LL_RI_ControlSwitchByADC\n |
| borlanic | 0:fbdae7e6d805 | 1427 | * RI_ASMR3 PC LL_RI_ControlSwitchByADC\n |
| borlanic | 0:fbdae7e6d805 | 1428 | * RI_ASMR3 PF LL_RI_ControlSwitchByADC\n |
| borlanic | 0:fbdae7e6d805 | 1429 | * RI_ASMR3 PG LL_RI_ControlSwitchByADC\n |
| borlanic | 0:fbdae7e6d805 | 1430 | * RI_ASMR4 PA LL_RI_ControlSwitchByADC\n |
| borlanic | 0:fbdae7e6d805 | 1431 | * RI_ASMR4 PB LL_RI_ControlSwitchByADC\n |
| borlanic | 0:fbdae7e6d805 | 1432 | * RI_ASMR4 PC LL_RI_ControlSwitchByADC\n |
| borlanic | 0:fbdae7e6d805 | 1433 | * RI_ASMR4 PF LL_RI_ControlSwitchByADC\n |
| borlanic | 0:fbdae7e6d805 | 1434 | * RI_ASMR4 PG LL_RI_ControlSwitchByADC\n |
| borlanic | 0:fbdae7e6d805 | 1435 | * RI_ASMR5 PA LL_RI_ControlSwitchByADC\n |
| borlanic | 0:fbdae7e6d805 | 1436 | * RI_ASMR5 PB LL_RI_ControlSwitchByADC\n |
| borlanic | 0:fbdae7e6d805 | 1437 | * RI_ASMR5 PC LL_RI_ControlSwitchByADC\n |
| borlanic | 0:fbdae7e6d805 | 1438 | * RI_ASMR5 PF LL_RI_ControlSwitchByADC\n |
| borlanic | 0:fbdae7e6d805 | 1439 | * RI_ASMR5 PG LL_RI_ControlSwitchByADC |
| borlanic | 0:fbdae7e6d805 | 1440 | * @param Port This parameter can be one of the following values: |
| borlanic | 0:fbdae7e6d805 | 1441 | * @arg @ref LL_RI_PORT_A |
| borlanic | 0:fbdae7e6d805 | 1442 | * @arg @ref LL_RI_PORT_B |
| borlanic | 0:fbdae7e6d805 | 1443 | * @arg @ref LL_RI_PORT_C |
| borlanic | 0:fbdae7e6d805 | 1444 | * @arg @ref LL_RI_PORT_F (*) |
| borlanic | 0:fbdae7e6d805 | 1445 | * @arg @ref LL_RI_PORT_G (*) |
| borlanic | 0:fbdae7e6d805 | 1446 | * |
| borlanic | 0:fbdae7e6d805 | 1447 | * (*) value not defined in all devices. |
| borlanic | 0:fbdae7e6d805 | 1448 | * @param Pin This parameter can be a combination of the following values: |
| borlanic | 0:fbdae7e6d805 | 1449 | * @arg @ref LL_RI_PIN_0 |
| borlanic | 0:fbdae7e6d805 | 1450 | * @arg @ref LL_RI_PIN_1 |
| borlanic | 0:fbdae7e6d805 | 1451 | * @arg @ref LL_RI_PIN_2 |
| borlanic | 0:fbdae7e6d805 | 1452 | * @arg @ref LL_RI_PIN_3 |
| borlanic | 0:fbdae7e6d805 | 1453 | * @arg @ref LL_RI_PIN_4 |
| borlanic | 0:fbdae7e6d805 | 1454 | * @arg @ref LL_RI_PIN_5 |
| borlanic | 0:fbdae7e6d805 | 1455 | * @arg @ref LL_RI_PIN_6 |
| borlanic | 0:fbdae7e6d805 | 1456 | * @arg @ref LL_RI_PIN_7 |
| borlanic | 0:fbdae7e6d805 | 1457 | * @arg @ref LL_RI_PIN_8 |
| borlanic | 0:fbdae7e6d805 | 1458 | * @arg @ref LL_RI_PIN_9 |
| borlanic | 0:fbdae7e6d805 | 1459 | * @arg @ref LL_RI_PIN_10 |
| borlanic | 0:fbdae7e6d805 | 1460 | * @arg @ref LL_RI_PIN_11 |
| borlanic | 0:fbdae7e6d805 | 1461 | * @arg @ref LL_RI_PIN_12 |
| borlanic | 0:fbdae7e6d805 | 1462 | * @arg @ref LL_RI_PIN_13 |
| borlanic | 0:fbdae7e6d805 | 1463 | * @arg @ref LL_RI_PIN_14 |
| borlanic | 0:fbdae7e6d805 | 1464 | * @arg @ref LL_RI_PIN_15 |
| borlanic | 0:fbdae7e6d805 | 1465 | * @arg @ref LL_RI_PIN_ALL |
| borlanic | 0:fbdae7e6d805 | 1466 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 1467 | */ |
| borlanic | 0:fbdae7e6d805 | 1468 | __STATIC_INLINE void LL_RI_ControlSwitchByADC(uint32_t Port, uint32_t Pin) |
| borlanic | 0:fbdae7e6d805 | 1469 | { |
| borlanic | 0:fbdae7e6d805 | 1470 | __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->ASMR1) + ((Port * 3U) << 2)); |
| borlanic | 0:fbdae7e6d805 | 1471 | CLEAR_BIT(*reg, Pin); |
| borlanic | 0:fbdae7e6d805 | 1472 | } |
| borlanic | 0:fbdae7e6d805 | 1473 | #endif /* RI_ASMR1_PA */ |
| borlanic | 0:fbdae7e6d805 | 1474 | |
| borlanic | 0:fbdae7e6d805 | 1475 | #if defined(RI_ASMR1_PA) |
| borlanic | 0:fbdae7e6d805 | 1476 | /** |
| borlanic | 0:fbdae7e6d805 | 1477 | * @brief Control analog switches of port X by the timer OC. |
| borlanic | 0:fbdae7e6d805 | 1478 | * @rmtoll RI_ASMR1 PA LL_RI_ControlSwitchByTIM\n |
| borlanic | 0:fbdae7e6d805 | 1479 | * RI_ASMR1 PB LL_RI_ControlSwitchByTIM\n |
| borlanic | 0:fbdae7e6d805 | 1480 | * RI_ASMR1 PC LL_RI_ControlSwitchByTIM\n |
| borlanic | 0:fbdae7e6d805 | 1481 | * RI_ASMR1 PF LL_RI_ControlSwitchByTIM\n |
| borlanic | 0:fbdae7e6d805 | 1482 | * RI_ASMR1 PG LL_RI_ControlSwitchByTIM\n |
| borlanic | 0:fbdae7e6d805 | 1483 | * RI_ASMR2 PA LL_RI_ControlSwitchByTIM\n |
| borlanic | 0:fbdae7e6d805 | 1484 | * RI_ASMR2 PB LL_RI_ControlSwitchByTIM\n |
| borlanic | 0:fbdae7e6d805 | 1485 | * RI_ASMR2 PC LL_RI_ControlSwitchByTIM\n |
| borlanic | 0:fbdae7e6d805 | 1486 | * RI_ASMR2 PF LL_RI_ControlSwitchByTIM\n |
| borlanic | 0:fbdae7e6d805 | 1487 | * RI_ASMR2 PG LL_RI_ControlSwitchByTIM\n |
| borlanic | 0:fbdae7e6d805 | 1488 | * RI_ASMR3 PA LL_RI_ControlSwitchByTIM\n |
| borlanic | 0:fbdae7e6d805 | 1489 | * RI_ASMR3 PB LL_RI_ControlSwitchByTIM\n |
| borlanic | 0:fbdae7e6d805 | 1490 | * RI_ASMR3 PC LL_RI_ControlSwitchByTIM\n |
| borlanic | 0:fbdae7e6d805 | 1491 | * RI_ASMR3 PF LL_RI_ControlSwitchByTIM\n |
| borlanic | 0:fbdae7e6d805 | 1492 | * RI_ASMR3 PG LL_RI_ControlSwitchByTIM\n |
| borlanic | 0:fbdae7e6d805 | 1493 | * RI_ASMR4 PA LL_RI_ControlSwitchByTIM\n |
| borlanic | 0:fbdae7e6d805 | 1494 | * RI_ASMR4 PB LL_RI_ControlSwitchByTIM\n |
| borlanic | 0:fbdae7e6d805 | 1495 | * RI_ASMR4 PC LL_RI_ControlSwitchByTIM\n |
| borlanic | 0:fbdae7e6d805 | 1496 | * RI_ASMR4 PF LL_RI_ControlSwitchByTIM\n |
| borlanic | 0:fbdae7e6d805 | 1497 | * RI_ASMR4 PG LL_RI_ControlSwitchByTIM\n |
| borlanic | 0:fbdae7e6d805 | 1498 | * RI_ASMR5 PA LL_RI_ControlSwitchByTIM\n |
| borlanic | 0:fbdae7e6d805 | 1499 | * RI_ASMR5 PB LL_RI_ControlSwitchByTIM\n |
| borlanic | 0:fbdae7e6d805 | 1500 | * RI_ASMR5 PC LL_RI_ControlSwitchByTIM\n |
| borlanic | 0:fbdae7e6d805 | 1501 | * RI_ASMR5 PF LL_RI_ControlSwitchByTIM\n |
| borlanic | 0:fbdae7e6d805 | 1502 | * RI_ASMR5 PG LL_RI_ControlSwitchByTIM |
| borlanic | 0:fbdae7e6d805 | 1503 | * @param Port This parameter can be one of the following values: |
| borlanic | 0:fbdae7e6d805 | 1504 | * @arg @ref LL_RI_PORT_A |
| borlanic | 0:fbdae7e6d805 | 1505 | * @arg @ref LL_RI_PORT_B |
| borlanic | 0:fbdae7e6d805 | 1506 | * @arg @ref LL_RI_PORT_C |
| borlanic | 0:fbdae7e6d805 | 1507 | * @arg @ref LL_RI_PORT_F (*) |
| borlanic | 0:fbdae7e6d805 | 1508 | * @arg @ref LL_RI_PORT_G (*) |
| borlanic | 0:fbdae7e6d805 | 1509 | * |
| borlanic | 0:fbdae7e6d805 | 1510 | * (*) value not defined in all devices. |
| borlanic | 0:fbdae7e6d805 | 1511 | * @param Pin This parameter can be a combination of the following values: |
| borlanic | 0:fbdae7e6d805 | 1512 | * @arg @ref LL_RI_PIN_0 |
| borlanic | 0:fbdae7e6d805 | 1513 | * @arg @ref LL_RI_PIN_1 |
| borlanic | 0:fbdae7e6d805 | 1514 | * @arg @ref LL_RI_PIN_2 |
| borlanic | 0:fbdae7e6d805 | 1515 | * @arg @ref LL_RI_PIN_3 |
| borlanic | 0:fbdae7e6d805 | 1516 | * @arg @ref LL_RI_PIN_4 |
| borlanic | 0:fbdae7e6d805 | 1517 | * @arg @ref LL_RI_PIN_5 |
| borlanic | 0:fbdae7e6d805 | 1518 | * @arg @ref LL_RI_PIN_6 |
| borlanic | 0:fbdae7e6d805 | 1519 | * @arg @ref LL_RI_PIN_7 |
| borlanic | 0:fbdae7e6d805 | 1520 | * @arg @ref LL_RI_PIN_8 |
| borlanic | 0:fbdae7e6d805 | 1521 | * @arg @ref LL_RI_PIN_9 |
| borlanic | 0:fbdae7e6d805 | 1522 | * @arg @ref LL_RI_PIN_10 |
| borlanic | 0:fbdae7e6d805 | 1523 | * @arg @ref LL_RI_PIN_11 |
| borlanic | 0:fbdae7e6d805 | 1524 | * @arg @ref LL_RI_PIN_12 |
| borlanic | 0:fbdae7e6d805 | 1525 | * @arg @ref LL_RI_PIN_13 |
| borlanic | 0:fbdae7e6d805 | 1526 | * @arg @ref LL_RI_PIN_14 |
| borlanic | 0:fbdae7e6d805 | 1527 | * @arg @ref LL_RI_PIN_15 |
| borlanic | 0:fbdae7e6d805 | 1528 | * @arg @ref LL_RI_PIN_ALL |
| borlanic | 0:fbdae7e6d805 | 1529 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 1530 | */ |
| borlanic | 0:fbdae7e6d805 | 1531 | __STATIC_INLINE void LL_RI_ControlSwitchByTIM(uint32_t Port, uint32_t Pin) |
| borlanic | 0:fbdae7e6d805 | 1532 | { |
| borlanic | 0:fbdae7e6d805 | 1533 | __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->ASMR1) + ((Port * 3U) << 2)); |
| borlanic | 0:fbdae7e6d805 | 1534 | SET_BIT(*reg, Pin); |
| borlanic | 0:fbdae7e6d805 | 1535 | } |
| borlanic | 0:fbdae7e6d805 | 1536 | #endif /* RI_ASMR1_PA */ |
| borlanic | 0:fbdae7e6d805 | 1537 | |
| borlanic | 0:fbdae7e6d805 | 1538 | #if defined(RI_CMR1_PA) |
| borlanic | 0:fbdae7e6d805 | 1539 | /** |
| borlanic | 0:fbdae7e6d805 | 1540 | * @brief Mask the input of port X during the capacitive sensing acquisition. |
| borlanic | 0:fbdae7e6d805 | 1541 | * @rmtoll RI_CMR1 PA LL_RI_MaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1542 | * RI_CMR1 PB LL_RI_MaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1543 | * RI_CMR1 PC LL_RI_MaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1544 | * RI_CMR1 PF LL_RI_MaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1545 | * RI_CMR1 PG LL_RI_MaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1546 | * RI_CMR2 PA LL_RI_MaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1547 | * RI_CMR2 PB LL_RI_MaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1548 | * RI_CMR2 PC LL_RI_MaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1549 | * RI_CMR2 PF LL_RI_MaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1550 | * RI_CMR2 PG LL_RI_MaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1551 | * RI_CMR3 PA LL_RI_MaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1552 | * RI_CMR3 PB LL_RI_MaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1553 | * RI_CMR3 PC LL_RI_MaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1554 | * RI_CMR3 PF LL_RI_MaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1555 | * RI_CMR3 PG LL_RI_MaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1556 | * RI_CMR4 PA LL_RI_MaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1557 | * RI_CMR4 PB LL_RI_MaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1558 | * RI_CMR4 PC LL_RI_MaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1559 | * RI_CMR4 PF LL_RI_MaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1560 | * RI_CMR4 PG LL_RI_MaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1561 | * RI_CMR5 PA LL_RI_MaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1562 | * RI_CMR5 PB LL_RI_MaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1563 | * RI_CMR5 PC LL_RI_MaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1564 | * RI_CMR5 PF LL_RI_MaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1565 | * RI_CMR5 PG LL_RI_MaskChannelDuringAcquisition |
| borlanic | 0:fbdae7e6d805 | 1566 | * @param Port This parameter can be one of the following values: |
| borlanic | 0:fbdae7e6d805 | 1567 | * @arg @ref LL_RI_PORT_A |
| borlanic | 0:fbdae7e6d805 | 1568 | * @arg @ref LL_RI_PORT_B |
| borlanic | 0:fbdae7e6d805 | 1569 | * @arg @ref LL_RI_PORT_C |
| borlanic | 0:fbdae7e6d805 | 1570 | * @arg @ref LL_RI_PORT_F (*) |
| borlanic | 0:fbdae7e6d805 | 1571 | * @arg @ref LL_RI_PORT_G (*) |
| borlanic | 0:fbdae7e6d805 | 1572 | * |
| borlanic | 0:fbdae7e6d805 | 1573 | * (*) value not defined in all devices. |
| borlanic | 0:fbdae7e6d805 | 1574 | * @param Pin This parameter can be a combination of the following values: |
| borlanic | 0:fbdae7e6d805 | 1575 | * @arg @ref LL_RI_PIN_0 |
| borlanic | 0:fbdae7e6d805 | 1576 | * @arg @ref LL_RI_PIN_1 |
| borlanic | 0:fbdae7e6d805 | 1577 | * @arg @ref LL_RI_PIN_2 |
| borlanic | 0:fbdae7e6d805 | 1578 | * @arg @ref LL_RI_PIN_3 |
| borlanic | 0:fbdae7e6d805 | 1579 | * @arg @ref LL_RI_PIN_4 |
| borlanic | 0:fbdae7e6d805 | 1580 | * @arg @ref LL_RI_PIN_5 |
| borlanic | 0:fbdae7e6d805 | 1581 | * @arg @ref LL_RI_PIN_6 |
| borlanic | 0:fbdae7e6d805 | 1582 | * @arg @ref LL_RI_PIN_7 |
| borlanic | 0:fbdae7e6d805 | 1583 | * @arg @ref LL_RI_PIN_8 |
| borlanic | 0:fbdae7e6d805 | 1584 | * @arg @ref LL_RI_PIN_9 |
| borlanic | 0:fbdae7e6d805 | 1585 | * @arg @ref LL_RI_PIN_10 |
| borlanic | 0:fbdae7e6d805 | 1586 | * @arg @ref LL_RI_PIN_11 |
| borlanic | 0:fbdae7e6d805 | 1587 | * @arg @ref LL_RI_PIN_12 |
| borlanic | 0:fbdae7e6d805 | 1588 | * @arg @ref LL_RI_PIN_13 |
| borlanic | 0:fbdae7e6d805 | 1589 | * @arg @ref LL_RI_PIN_14 |
| borlanic | 0:fbdae7e6d805 | 1590 | * @arg @ref LL_RI_PIN_15 |
| borlanic | 0:fbdae7e6d805 | 1591 | * @arg @ref LL_RI_PIN_ALL |
| borlanic | 0:fbdae7e6d805 | 1592 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 1593 | */ |
| borlanic | 0:fbdae7e6d805 | 1594 | __STATIC_INLINE void LL_RI_MaskChannelDuringAcquisition(uint32_t Port, uint32_t Pin) |
| borlanic | 0:fbdae7e6d805 | 1595 | { |
| borlanic | 0:fbdae7e6d805 | 1596 | __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->CMR1) + ((Port * 3U) << 2)); |
| borlanic | 0:fbdae7e6d805 | 1597 | CLEAR_BIT(*reg, Pin); |
| borlanic | 0:fbdae7e6d805 | 1598 | } |
| borlanic | 0:fbdae7e6d805 | 1599 | #endif /* RI_CMR1_PA */ |
| borlanic | 0:fbdae7e6d805 | 1600 | |
| borlanic | 0:fbdae7e6d805 | 1601 | #if defined(RI_CMR1_PA) |
| borlanic | 0:fbdae7e6d805 | 1602 | /** |
| borlanic | 0:fbdae7e6d805 | 1603 | * @brief Unmask the input of port X during the capacitive sensing acquisition. |
| borlanic | 0:fbdae7e6d805 | 1604 | * @rmtoll RI_CMR1 PA LL_RI_UnmaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1605 | * RI_CMR1 PB LL_RI_UnmaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1606 | * RI_CMR1 PC LL_RI_UnmaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1607 | * RI_CMR1 PF LL_RI_UnmaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1608 | * RI_CMR1 PG LL_RI_UnmaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1609 | * RI_CMR2 PA LL_RI_UnmaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1610 | * RI_CMR2 PB LL_RI_UnmaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1611 | * RI_CMR2 PC LL_RI_UnmaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1612 | * RI_CMR2 PF LL_RI_UnmaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1613 | * RI_CMR2 PG LL_RI_UnmaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1614 | * RI_CMR3 PA LL_RI_UnmaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1615 | * RI_CMR3 PB LL_RI_UnmaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1616 | * RI_CMR3 PC LL_RI_UnmaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1617 | * RI_CMR3 PF LL_RI_UnmaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1618 | * RI_CMR3 PG LL_RI_UnmaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1619 | * RI_CMR4 PA LL_RI_UnmaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1620 | * RI_CMR4 PB LL_RI_UnmaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1621 | * RI_CMR4 PC LL_RI_UnmaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1622 | * RI_CMR4 PF LL_RI_UnmaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1623 | * RI_CMR4 PG LL_RI_UnmaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1624 | * RI_CMR5 PA LL_RI_UnmaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1625 | * RI_CMR5 PB LL_RI_UnmaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1626 | * RI_CMR5 PC LL_RI_UnmaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1627 | * RI_CMR5 PF LL_RI_UnmaskChannelDuringAcquisition\n |
| borlanic | 0:fbdae7e6d805 | 1628 | * RI_CMR5 PG LL_RI_UnmaskChannelDuringAcquisition |
| borlanic | 0:fbdae7e6d805 | 1629 | * @param Port This parameter can be one of the following values: |
| borlanic | 0:fbdae7e6d805 | 1630 | * @arg @ref LL_RI_PORT_A |
| borlanic | 0:fbdae7e6d805 | 1631 | * @arg @ref LL_RI_PORT_B |
| borlanic | 0:fbdae7e6d805 | 1632 | * @arg @ref LL_RI_PORT_C |
| borlanic | 0:fbdae7e6d805 | 1633 | * @arg @ref LL_RI_PORT_F (*) |
| borlanic | 0:fbdae7e6d805 | 1634 | * @arg @ref LL_RI_PORT_G (*) |
| borlanic | 0:fbdae7e6d805 | 1635 | * |
| borlanic | 0:fbdae7e6d805 | 1636 | * (*) value not defined in all devices. |
| borlanic | 0:fbdae7e6d805 | 1637 | * @param Pin This parameter can be a combination of the following values: |
| borlanic | 0:fbdae7e6d805 | 1638 | * @arg @ref LL_RI_PIN_0 |
| borlanic | 0:fbdae7e6d805 | 1639 | * @arg @ref LL_RI_PIN_1 |
| borlanic | 0:fbdae7e6d805 | 1640 | * @arg @ref LL_RI_PIN_2 |
| borlanic | 0:fbdae7e6d805 | 1641 | * @arg @ref LL_RI_PIN_3 |
| borlanic | 0:fbdae7e6d805 | 1642 | * @arg @ref LL_RI_PIN_4 |
| borlanic | 0:fbdae7e6d805 | 1643 | * @arg @ref LL_RI_PIN_5 |
| borlanic | 0:fbdae7e6d805 | 1644 | * @arg @ref LL_RI_PIN_6 |
| borlanic | 0:fbdae7e6d805 | 1645 | * @arg @ref LL_RI_PIN_7 |
| borlanic | 0:fbdae7e6d805 | 1646 | * @arg @ref LL_RI_PIN_8 |
| borlanic | 0:fbdae7e6d805 | 1647 | * @arg @ref LL_RI_PIN_9 |
| borlanic | 0:fbdae7e6d805 | 1648 | * @arg @ref LL_RI_PIN_10 |
| borlanic | 0:fbdae7e6d805 | 1649 | * @arg @ref LL_RI_PIN_11 |
| borlanic | 0:fbdae7e6d805 | 1650 | * @arg @ref LL_RI_PIN_12 |
| borlanic | 0:fbdae7e6d805 | 1651 | * @arg @ref LL_RI_PIN_13 |
| borlanic | 0:fbdae7e6d805 | 1652 | * @arg @ref LL_RI_PIN_14 |
| borlanic | 0:fbdae7e6d805 | 1653 | * @arg @ref LL_RI_PIN_15 |
| borlanic | 0:fbdae7e6d805 | 1654 | * @arg @ref LL_RI_PIN_ALL |
| borlanic | 0:fbdae7e6d805 | 1655 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 1656 | */ |
| borlanic | 0:fbdae7e6d805 | 1657 | __STATIC_INLINE void LL_RI_UnmaskChannelDuringAcquisition(uint32_t Port, uint32_t Pin) |
| borlanic | 0:fbdae7e6d805 | 1658 | { |
| borlanic | 0:fbdae7e6d805 | 1659 | __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->CMR1) + ((Port * 3U) << 2)); |
| borlanic | 0:fbdae7e6d805 | 1660 | SET_BIT(*reg, Pin); |
| borlanic | 0:fbdae7e6d805 | 1661 | } |
| borlanic | 0:fbdae7e6d805 | 1662 | #endif /* RI_CMR1_PA */ |
| borlanic | 0:fbdae7e6d805 | 1663 | |
| borlanic | 0:fbdae7e6d805 | 1664 | #if defined(RI_CICR1_PA) |
| borlanic | 0:fbdae7e6d805 | 1665 | /** |
| borlanic | 0:fbdae7e6d805 | 1666 | * @brief Identify channel for timer input capture |
| borlanic | 0:fbdae7e6d805 | 1667 | * @rmtoll RI_CICR1 PA LL_RI_IdentifyChannelIO\n |
| borlanic | 0:fbdae7e6d805 | 1668 | * RI_CICR1 PB LL_RI_IdentifyChannelIO\n |
| borlanic | 0:fbdae7e6d805 | 1669 | * RI_CICR1 PC LL_RI_IdentifyChannelIO\n |
| borlanic | 0:fbdae7e6d805 | 1670 | * RI_CICR1 PF LL_RI_IdentifyChannelIO\n |
| borlanic | 0:fbdae7e6d805 | 1671 | * RI_CICR1 PG LL_RI_IdentifyChannelIO\n |
| borlanic | 0:fbdae7e6d805 | 1672 | * RI_CICR2 PA LL_RI_IdentifyChannelIO\n |
| borlanic | 0:fbdae7e6d805 | 1673 | * RI_CICR2 PB LL_RI_IdentifyChannelIO\n |
| borlanic | 0:fbdae7e6d805 | 1674 | * RI_CICR2 PC LL_RI_IdentifyChannelIO\n |
| borlanic | 0:fbdae7e6d805 | 1675 | * RI_CICR2 PF LL_RI_IdentifyChannelIO\n |
| borlanic | 0:fbdae7e6d805 | 1676 | * RI_CICR2 PG LL_RI_IdentifyChannelIO\n |
| borlanic | 0:fbdae7e6d805 | 1677 | * RI_CICR3 PA LL_RI_IdentifyChannelIO\n |
| borlanic | 0:fbdae7e6d805 | 1678 | * RI_CICR3 PB LL_RI_IdentifyChannelIO\n |
| borlanic | 0:fbdae7e6d805 | 1679 | * RI_CICR3 PC LL_RI_IdentifyChannelIO\n |
| borlanic | 0:fbdae7e6d805 | 1680 | * RI_CICR3 PF LL_RI_IdentifyChannelIO\n |
| borlanic | 0:fbdae7e6d805 | 1681 | * RI_CICR3 PG LL_RI_IdentifyChannelIO\n |
| borlanic | 0:fbdae7e6d805 | 1682 | * RI_CICR4 PA LL_RI_IdentifyChannelIO\n |
| borlanic | 0:fbdae7e6d805 | 1683 | * RI_CICR4 PB LL_RI_IdentifyChannelIO\n |
| borlanic | 0:fbdae7e6d805 | 1684 | * RI_CICR4 PC LL_RI_IdentifyChannelIO\n |
| borlanic | 0:fbdae7e6d805 | 1685 | * RI_CICR4 PF LL_RI_IdentifyChannelIO\n |
| borlanic | 0:fbdae7e6d805 | 1686 | * RI_CICR4 PG LL_RI_IdentifyChannelIO\n |
| borlanic | 0:fbdae7e6d805 | 1687 | * RI_CICR5 PA LL_RI_IdentifyChannelIO\n |
| borlanic | 0:fbdae7e6d805 | 1688 | * RI_CICR5 PB LL_RI_IdentifyChannelIO\n |
| borlanic | 0:fbdae7e6d805 | 1689 | * RI_CICR5 PC LL_RI_IdentifyChannelIO\n |
| borlanic | 0:fbdae7e6d805 | 1690 | * RI_CICR5 PF LL_RI_IdentifyChannelIO\n |
| borlanic | 0:fbdae7e6d805 | 1691 | * RI_CICR5 PG LL_RI_IdentifyChannelIO |
| borlanic | 0:fbdae7e6d805 | 1692 | * @param Port This parameter can be one of the following values: |
| borlanic | 0:fbdae7e6d805 | 1693 | * @arg @ref LL_RI_PORT_A |
| borlanic | 0:fbdae7e6d805 | 1694 | * @arg @ref LL_RI_PORT_B |
| borlanic | 0:fbdae7e6d805 | 1695 | * @arg @ref LL_RI_PORT_C |
| borlanic | 0:fbdae7e6d805 | 1696 | * @arg @ref LL_RI_PORT_F (*) |
| borlanic | 0:fbdae7e6d805 | 1697 | * @arg @ref LL_RI_PORT_G (*) |
| borlanic | 0:fbdae7e6d805 | 1698 | * |
| borlanic | 0:fbdae7e6d805 | 1699 | * (*) value not defined in all devices. |
| borlanic | 0:fbdae7e6d805 | 1700 | * @param Pin This parameter can be a combination of the following values: |
| borlanic | 0:fbdae7e6d805 | 1701 | * @arg @ref LL_RI_PIN_0 |
| borlanic | 0:fbdae7e6d805 | 1702 | * @arg @ref LL_RI_PIN_1 |
| borlanic | 0:fbdae7e6d805 | 1703 | * @arg @ref LL_RI_PIN_2 |
| borlanic | 0:fbdae7e6d805 | 1704 | * @arg @ref LL_RI_PIN_3 |
| borlanic | 0:fbdae7e6d805 | 1705 | * @arg @ref LL_RI_PIN_4 |
| borlanic | 0:fbdae7e6d805 | 1706 | * @arg @ref LL_RI_PIN_5 |
| borlanic | 0:fbdae7e6d805 | 1707 | * @arg @ref LL_RI_PIN_6 |
| borlanic | 0:fbdae7e6d805 | 1708 | * @arg @ref LL_RI_PIN_7 |
| borlanic | 0:fbdae7e6d805 | 1709 | * @arg @ref LL_RI_PIN_8 |
| borlanic | 0:fbdae7e6d805 | 1710 | * @arg @ref LL_RI_PIN_9 |
| borlanic | 0:fbdae7e6d805 | 1711 | * @arg @ref LL_RI_PIN_10 |
| borlanic | 0:fbdae7e6d805 | 1712 | * @arg @ref LL_RI_PIN_11 |
| borlanic | 0:fbdae7e6d805 | 1713 | * @arg @ref LL_RI_PIN_12 |
| borlanic | 0:fbdae7e6d805 | 1714 | * @arg @ref LL_RI_PIN_13 |
| borlanic | 0:fbdae7e6d805 | 1715 | * @arg @ref LL_RI_PIN_14 |
| borlanic | 0:fbdae7e6d805 | 1716 | * @arg @ref LL_RI_PIN_15 |
| borlanic | 0:fbdae7e6d805 | 1717 | * @arg @ref LL_RI_PIN_ALL |
| borlanic | 0:fbdae7e6d805 | 1718 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 1719 | */ |
| borlanic | 0:fbdae7e6d805 | 1720 | __STATIC_INLINE void LL_RI_IdentifyChannelIO(uint32_t Port, uint32_t Pin) |
| borlanic | 0:fbdae7e6d805 | 1721 | { |
| borlanic | 0:fbdae7e6d805 | 1722 | __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->CICR1) + ((Port * 3U) << 2)); |
| borlanic | 0:fbdae7e6d805 | 1723 | CLEAR_BIT(*reg, Pin); |
| borlanic | 0:fbdae7e6d805 | 1724 | } |
| borlanic | 0:fbdae7e6d805 | 1725 | #endif /* RI_CICR1_PA */ |
| borlanic | 0:fbdae7e6d805 | 1726 | |
| borlanic | 0:fbdae7e6d805 | 1727 | #if defined(RI_CICR1_PA) |
| borlanic | 0:fbdae7e6d805 | 1728 | /** |
| borlanic | 0:fbdae7e6d805 | 1729 | * @brief Identify sampling capacitor for timer input capture |
| borlanic | 0:fbdae7e6d805 | 1730 | * @rmtoll RI_CICR1 PA LL_RI_IdentifySamplingCapacitorIO\n |
| borlanic | 0:fbdae7e6d805 | 1731 | * RI_CICR1 PB LL_RI_IdentifySamplingCapacitorIO\n |
| borlanic | 0:fbdae7e6d805 | 1732 | * RI_CICR1 PC LL_RI_IdentifySamplingCapacitorIO\n |
| borlanic | 0:fbdae7e6d805 | 1733 | * RI_CICR1 PF LL_RI_IdentifySamplingCapacitorIO\n |
| borlanic | 0:fbdae7e6d805 | 1734 | * RI_CICR1 PG LL_RI_IdentifySamplingCapacitorIO\n |
| borlanic | 0:fbdae7e6d805 | 1735 | * RI_CICR2 PA LL_RI_IdentifySamplingCapacitorIO\n |
| borlanic | 0:fbdae7e6d805 | 1736 | * RI_CICR2 PB LL_RI_IdentifySamplingCapacitorIO\n |
| borlanic | 0:fbdae7e6d805 | 1737 | * RI_CICR2 PC LL_RI_IdentifySamplingCapacitorIO\n |
| borlanic | 0:fbdae7e6d805 | 1738 | * RI_CICR2 PF LL_RI_IdentifySamplingCapacitorIO\n |
| borlanic | 0:fbdae7e6d805 | 1739 | * RI_CICR2 PG LL_RI_IdentifySamplingCapacitorIO\n |
| borlanic | 0:fbdae7e6d805 | 1740 | * RI_CICR3 PA LL_RI_IdentifySamplingCapacitorIO\n |
| borlanic | 0:fbdae7e6d805 | 1741 | * RI_CICR3 PB LL_RI_IdentifySamplingCapacitorIO\n |
| borlanic | 0:fbdae7e6d805 | 1742 | * RI_CICR3 PC LL_RI_IdentifySamplingCapacitorIO\n |
| borlanic | 0:fbdae7e6d805 | 1743 | * RI_CICR3 PF LL_RI_IdentifySamplingCapacitorIO\n |
| borlanic | 0:fbdae7e6d805 | 1744 | * RI_CICR3 PG LL_RI_IdentifySamplingCapacitorIO\n |
| borlanic | 0:fbdae7e6d805 | 1745 | * RI_CICR4 PA LL_RI_IdentifySamplingCapacitorIO\n |
| borlanic | 0:fbdae7e6d805 | 1746 | * RI_CICR4 PB LL_RI_IdentifySamplingCapacitorIO\n |
| borlanic | 0:fbdae7e6d805 | 1747 | * RI_CICR4 PC LL_RI_IdentifySamplingCapacitorIO\n |
| borlanic | 0:fbdae7e6d805 | 1748 | * RI_CICR4 PF LL_RI_IdentifySamplingCapacitorIO\n |
| borlanic | 0:fbdae7e6d805 | 1749 | * RI_CICR4 PG LL_RI_IdentifySamplingCapacitorIO\n |
| borlanic | 0:fbdae7e6d805 | 1750 | * RI_CICR5 PA LL_RI_IdentifySamplingCapacitorIO\n |
| borlanic | 0:fbdae7e6d805 | 1751 | * RI_CICR5 PB LL_RI_IdentifySamplingCapacitorIO\n |
| borlanic | 0:fbdae7e6d805 | 1752 | * RI_CICR5 PC LL_RI_IdentifySamplingCapacitorIO\n |
| borlanic | 0:fbdae7e6d805 | 1753 | * RI_CICR5 PF LL_RI_IdentifySamplingCapacitorIO\n |
| borlanic | 0:fbdae7e6d805 | 1754 | * RI_CICR5 PG LL_RI_IdentifySamplingCapacitorIO |
| borlanic | 0:fbdae7e6d805 | 1755 | * @param Port This parameter can be one of the following values: |
| borlanic | 0:fbdae7e6d805 | 1756 | * @arg @ref LL_RI_PORT_A |
| borlanic | 0:fbdae7e6d805 | 1757 | * @arg @ref LL_RI_PORT_B |
| borlanic | 0:fbdae7e6d805 | 1758 | * @arg @ref LL_RI_PORT_C |
| borlanic | 0:fbdae7e6d805 | 1759 | * @arg @ref LL_RI_PORT_F (*) |
| borlanic | 0:fbdae7e6d805 | 1760 | * @arg @ref LL_RI_PORT_G (*) |
| borlanic | 0:fbdae7e6d805 | 1761 | * |
| borlanic | 0:fbdae7e6d805 | 1762 | * (*) value not defined in all devices. |
| borlanic | 0:fbdae7e6d805 | 1763 | * @param Pin This parameter can be a combination of the following values: |
| borlanic | 0:fbdae7e6d805 | 1764 | * @arg @ref LL_RI_PIN_0 |
| borlanic | 0:fbdae7e6d805 | 1765 | * @arg @ref LL_RI_PIN_1 |
| borlanic | 0:fbdae7e6d805 | 1766 | * @arg @ref LL_RI_PIN_2 |
| borlanic | 0:fbdae7e6d805 | 1767 | * @arg @ref LL_RI_PIN_3 |
| borlanic | 0:fbdae7e6d805 | 1768 | * @arg @ref LL_RI_PIN_4 |
| borlanic | 0:fbdae7e6d805 | 1769 | * @arg @ref LL_RI_PIN_5 |
| borlanic | 0:fbdae7e6d805 | 1770 | * @arg @ref LL_RI_PIN_6 |
| borlanic | 0:fbdae7e6d805 | 1771 | * @arg @ref LL_RI_PIN_7 |
| borlanic | 0:fbdae7e6d805 | 1772 | * @arg @ref LL_RI_PIN_8 |
| borlanic | 0:fbdae7e6d805 | 1773 | * @arg @ref LL_RI_PIN_9 |
| borlanic | 0:fbdae7e6d805 | 1774 | * @arg @ref LL_RI_PIN_10 |
| borlanic | 0:fbdae7e6d805 | 1775 | * @arg @ref LL_RI_PIN_11 |
| borlanic | 0:fbdae7e6d805 | 1776 | * @arg @ref LL_RI_PIN_12 |
| borlanic | 0:fbdae7e6d805 | 1777 | * @arg @ref LL_RI_PIN_13 |
| borlanic | 0:fbdae7e6d805 | 1778 | * @arg @ref LL_RI_PIN_14 |
| borlanic | 0:fbdae7e6d805 | 1779 | * @arg @ref LL_RI_PIN_15 |
| borlanic | 0:fbdae7e6d805 | 1780 | * @arg @ref LL_RI_PIN_ALL |
| borlanic | 0:fbdae7e6d805 | 1781 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 1782 | */ |
| borlanic | 0:fbdae7e6d805 | 1783 | __STATIC_INLINE void LL_RI_IdentifySamplingCapacitorIO(uint32_t Port, uint32_t Pin) |
| borlanic | 0:fbdae7e6d805 | 1784 | { |
| borlanic | 0:fbdae7e6d805 | 1785 | __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->CICR1) + ((Port * 3U) << 2)); |
| borlanic | 0:fbdae7e6d805 | 1786 | SET_BIT(*reg, Pin); |
| borlanic | 0:fbdae7e6d805 | 1787 | } |
| borlanic | 0:fbdae7e6d805 | 1788 | #endif /* RI_CICR1_PA */ |
| borlanic | 0:fbdae7e6d805 | 1789 | |
| borlanic | 0:fbdae7e6d805 | 1790 | /** |
| borlanic | 0:fbdae7e6d805 | 1791 | * @} |
| borlanic | 0:fbdae7e6d805 | 1792 | */ |
| borlanic | 0:fbdae7e6d805 | 1793 | |
| borlanic | 0:fbdae7e6d805 | 1794 | /** @defgroup SYSTEM_LL_EF_FLASH FLASH |
| borlanic | 0:fbdae7e6d805 | 1795 | * @{ |
| borlanic | 0:fbdae7e6d805 | 1796 | */ |
| borlanic | 0:fbdae7e6d805 | 1797 | |
| borlanic | 0:fbdae7e6d805 | 1798 | /** |
| borlanic | 0:fbdae7e6d805 | 1799 | * @brief Set FLASH Latency |
| borlanic | 0:fbdae7e6d805 | 1800 | * @note Latetency can be modified only when ACC64 is set. (through function @ref LL_FLASH_Enable64bitAccess) |
| borlanic | 0:fbdae7e6d805 | 1801 | * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency |
| borlanic | 0:fbdae7e6d805 | 1802 | * @param Latency This parameter can be one of the following values: |
| borlanic | 0:fbdae7e6d805 | 1803 | * @arg @ref LL_FLASH_LATENCY_0 |
| borlanic | 0:fbdae7e6d805 | 1804 | * @arg @ref LL_FLASH_LATENCY_1 |
| borlanic | 0:fbdae7e6d805 | 1805 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 1806 | */ |
| borlanic | 0:fbdae7e6d805 | 1807 | __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) |
| borlanic | 0:fbdae7e6d805 | 1808 | { |
| borlanic | 0:fbdae7e6d805 | 1809 | MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); |
| borlanic | 0:fbdae7e6d805 | 1810 | } |
| borlanic | 0:fbdae7e6d805 | 1811 | |
| borlanic | 0:fbdae7e6d805 | 1812 | /** |
| borlanic | 0:fbdae7e6d805 | 1813 | * @brief Get FLASH Latency |
| borlanic | 0:fbdae7e6d805 | 1814 | * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency |
| borlanic | 0:fbdae7e6d805 | 1815 | * @retval Returned value can be one of the following values: |
| borlanic | 0:fbdae7e6d805 | 1816 | * @arg @ref LL_FLASH_LATENCY_0 |
| borlanic | 0:fbdae7e6d805 | 1817 | * @arg @ref LL_FLASH_LATENCY_1 |
| borlanic | 0:fbdae7e6d805 | 1818 | */ |
| borlanic | 0:fbdae7e6d805 | 1819 | __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) |
| borlanic | 0:fbdae7e6d805 | 1820 | { |
| borlanic | 0:fbdae7e6d805 | 1821 | return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); |
| borlanic | 0:fbdae7e6d805 | 1822 | } |
| borlanic | 0:fbdae7e6d805 | 1823 | |
| borlanic | 0:fbdae7e6d805 | 1824 | /** |
| borlanic | 0:fbdae7e6d805 | 1825 | * @brief Enable Prefetch |
| borlanic | 0:fbdae7e6d805 | 1826 | * @note Prefetch can be enabled only when ACC64 is set. (through function @ref LL_FLASH_Enable64bitAccess) |
| borlanic | 0:fbdae7e6d805 | 1827 | * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch |
| borlanic | 0:fbdae7e6d805 | 1828 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 1829 | */ |
| borlanic | 0:fbdae7e6d805 | 1830 | __STATIC_INLINE void LL_FLASH_EnablePrefetch(void) |
| borlanic | 0:fbdae7e6d805 | 1831 | { |
| borlanic | 0:fbdae7e6d805 | 1832 | SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); |
| borlanic | 0:fbdae7e6d805 | 1833 | } |
| borlanic | 0:fbdae7e6d805 | 1834 | |
| borlanic | 0:fbdae7e6d805 | 1835 | /** |
| borlanic | 0:fbdae7e6d805 | 1836 | * @brief Disable Prefetch |
| borlanic | 0:fbdae7e6d805 | 1837 | * @note Prefetch can be disabled only when ACC64 is set. (through function @ref LL_FLASH_Enable64bitAccess) |
| borlanic | 0:fbdae7e6d805 | 1838 | * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch |
| borlanic | 0:fbdae7e6d805 | 1839 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 1840 | */ |
| borlanic | 0:fbdae7e6d805 | 1841 | __STATIC_INLINE void LL_FLASH_DisablePrefetch(void) |
| borlanic | 0:fbdae7e6d805 | 1842 | { |
| borlanic | 0:fbdae7e6d805 | 1843 | CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); |
| borlanic | 0:fbdae7e6d805 | 1844 | } |
| borlanic | 0:fbdae7e6d805 | 1845 | |
| borlanic | 0:fbdae7e6d805 | 1846 | /** |
| borlanic | 0:fbdae7e6d805 | 1847 | * @brief Check if Prefetch buffer is enabled |
| borlanic | 0:fbdae7e6d805 | 1848 | * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled |
| borlanic | 0:fbdae7e6d805 | 1849 | * @retval State of bit (1 or 0). |
| borlanic | 0:fbdae7e6d805 | 1850 | */ |
| borlanic | 0:fbdae7e6d805 | 1851 | __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) |
| borlanic | 0:fbdae7e6d805 | 1852 | { |
| borlanic | 0:fbdae7e6d805 | 1853 | return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN)); |
| borlanic | 0:fbdae7e6d805 | 1854 | } |
| borlanic | 0:fbdae7e6d805 | 1855 | |
| borlanic | 0:fbdae7e6d805 | 1856 | /** |
| borlanic | 0:fbdae7e6d805 | 1857 | * @brief Enable 64-bit access |
| borlanic | 0:fbdae7e6d805 | 1858 | * @rmtoll FLASH_ACR ACC64 LL_FLASH_Enable64bitAccess |
| borlanic | 0:fbdae7e6d805 | 1859 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 1860 | */ |
| borlanic | 0:fbdae7e6d805 | 1861 | __STATIC_INLINE void LL_FLASH_Enable64bitAccess(void) |
| borlanic | 0:fbdae7e6d805 | 1862 | { |
| borlanic | 0:fbdae7e6d805 | 1863 | SET_BIT(FLASH->ACR, FLASH_ACR_ACC64); |
| borlanic | 0:fbdae7e6d805 | 1864 | } |
| borlanic | 0:fbdae7e6d805 | 1865 | |
| borlanic | 0:fbdae7e6d805 | 1866 | /** |
| borlanic | 0:fbdae7e6d805 | 1867 | * @brief Disable 64-bit access |
| borlanic | 0:fbdae7e6d805 | 1868 | * @rmtoll FLASH_ACR ACC64 LL_FLASH_Disable64bitAccess |
| borlanic | 0:fbdae7e6d805 | 1869 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 1870 | */ |
| borlanic | 0:fbdae7e6d805 | 1871 | __STATIC_INLINE void LL_FLASH_Disable64bitAccess(void) |
| borlanic | 0:fbdae7e6d805 | 1872 | { |
| borlanic | 0:fbdae7e6d805 | 1873 | CLEAR_BIT(FLASH->ACR, FLASH_ACR_ACC64); |
| borlanic | 0:fbdae7e6d805 | 1874 | } |
| borlanic | 0:fbdae7e6d805 | 1875 | |
| borlanic | 0:fbdae7e6d805 | 1876 | /** |
| borlanic | 0:fbdae7e6d805 | 1877 | * @brief Check if 64-bit access is enabled |
| borlanic | 0:fbdae7e6d805 | 1878 | * @rmtoll FLASH_ACR ACC64 LL_FLASH_Is64bitAccessEnabled |
| borlanic | 0:fbdae7e6d805 | 1879 | * @retval State of bit (1 or 0). |
| borlanic | 0:fbdae7e6d805 | 1880 | */ |
| borlanic | 0:fbdae7e6d805 | 1881 | __STATIC_INLINE uint32_t LL_FLASH_Is64bitAccessEnabled(void) |
| borlanic | 0:fbdae7e6d805 | 1882 | { |
| borlanic | 0:fbdae7e6d805 | 1883 | return (READ_BIT(FLASH->ACR, FLASH_ACR_ACC64) == (FLASH_ACR_ACC64)); |
| borlanic | 0:fbdae7e6d805 | 1884 | } |
| borlanic | 0:fbdae7e6d805 | 1885 | |
| borlanic | 0:fbdae7e6d805 | 1886 | |
| borlanic | 0:fbdae7e6d805 | 1887 | /** |
| borlanic | 0:fbdae7e6d805 | 1888 | * @brief Enable Flash Power-down mode during run mode or Low-power run mode |
| borlanic | 0:fbdae7e6d805 | 1889 | * @note Flash memory can be put in power-down mode only when the code is executed |
| borlanic | 0:fbdae7e6d805 | 1890 | * from RAM |
| borlanic | 0:fbdae7e6d805 | 1891 | * @note Flash must not be accessed when power down is enabled |
| borlanic | 0:fbdae7e6d805 | 1892 | * @note Flash must not be put in power-down while a program or an erase operation |
| borlanic | 0:fbdae7e6d805 | 1893 | * is on-going |
| borlanic | 0:fbdae7e6d805 | 1894 | * @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n |
| borlanic | 0:fbdae7e6d805 | 1895 | * FLASH_PDKEYR PDKEY1 LL_FLASH_EnableRunPowerDown\n |
| borlanic | 0:fbdae7e6d805 | 1896 | * FLASH_PDKEYR PDKEY2 LL_FLASH_EnableRunPowerDown |
| borlanic | 0:fbdae7e6d805 | 1897 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 1898 | */ |
| borlanic | 0:fbdae7e6d805 | 1899 | __STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void) |
| borlanic | 0:fbdae7e6d805 | 1900 | { |
| borlanic | 0:fbdae7e6d805 | 1901 | /* Following values must be written consecutively to unlock the RUN_PD bit in |
| borlanic | 0:fbdae7e6d805 | 1902 | FLASH_ACR */ |
| borlanic | 0:fbdae7e6d805 | 1903 | WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); |
| borlanic | 0:fbdae7e6d805 | 1904 | WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); |
| borlanic | 0:fbdae7e6d805 | 1905 | SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); |
| borlanic | 0:fbdae7e6d805 | 1906 | } |
| borlanic | 0:fbdae7e6d805 | 1907 | |
| borlanic | 0:fbdae7e6d805 | 1908 | /** |
| borlanic | 0:fbdae7e6d805 | 1909 | * @brief Disable Flash Power-down mode during run mode or Low-power run mode |
| borlanic | 0:fbdae7e6d805 | 1910 | * @rmtoll FLASH_ACR RUN_PD LL_FLASH_DisableRunPowerDown\n |
| borlanic | 0:fbdae7e6d805 | 1911 | * FLASH_PDKEYR PDKEY1 LL_FLASH_DisableRunPowerDown\n |
| borlanic | 0:fbdae7e6d805 | 1912 | * FLASH_PDKEYR PDKEY2 LL_FLASH_DisableRunPowerDown |
| borlanic | 0:fbdae7e6d805 | 1913 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 1914 | */ |
| borlanic | 0:fbdae7e6d805 | 1915 | __STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void) |
| borlanic | 0:fbdae7e6d805 | 1916 | { |
| borlanic | 0:fbdae7e6d805 | 1917 | /* Following values must be written consecutively to unlock the RUN_PD bit in |
| borlanic | 0:fbdae7e6d805 | 1918 | FLASH_ACR */ |
| borlanic | 0:fbdae7e6d805 | 1919 | WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); |
| borlanic | 0:fbdae7e6d805 | 1920 | WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); |
| borlanic | 0:fbdae7e6d805 | 1921 | CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); |
| borlanic | 0:fbdae7e6d805 | 1922 | } |
| borlanic | 0:fbdae7e6d805 | 1923 | |
| borlanic | 0:fbdae7e6d805 | 1924 | /** |
| borlanic | 0:fbdae7e6d805 | 1925 | * @brief Enable Flash Power-down mode during Sleep or Low-power sleep mode |
| borlanic | 0:fbdae7e6d805 | 1926 | * @note Flash must not be put in power-down while a program or an erase operation |
| borlanic | 0:fbdae7e6d805 | 1927 | * is on-going |
| borlanic | 0:fbdae7e6d805 | 1928 | * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown |
| borlanic | 0:fbdae7e6d805 | 1929 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 1930 | */ |
| borlanic | 0:fbdae7e6d805 | 1931 | __STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void) |
| borlanic | 0:fbdae7e6d805 | 1932 | { |
| borlanic | 0:fbdae7e6d805 | 1933 | SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD); |
| borlanic | 0:fbdae7e6d805 | 1934 | } |
| borlanic | 0:fbdae7e6d805 | 1935 | |
| borlanic | 0:fbdae7e6d805 | 1936 | /** |
| borlanic | 0:fbdae7e6d805 | 1937 | * @brief Disable Flash Power-down mode during Sleep or Low-power sleep mode |
| borlanic | 0:fbdae7e6d805 | 1938 | * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown |
| borlanic | 0:fbdae7e6d805 | 1939 | * @retval None |
| borlanic | 0:fbdae7e6d805 | 1940 | */ |
| borlanic | 0:fbdae7e6d805 | 1941 | __STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void) |
| borlanic | 0:fbdae7e6d805 | 1942 | { |
| borlanic | 0:fbdae7e6d805 | 1943 | CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD); |
| borlanic | 0:fbdae7e6d805 | 1944 | } |
| borlanic | 0:fbdae7e6d805 | 1945 | |
| borlanic | 0:fbdae7e6d805 | 1946 | /** |
| borlanic | 0:fbdae7e6d805 | 1947 | * @} |
| borlanic | 0:fbdae7e6d805 | 1948 | */ |
| borlanic | 0:fbdae7e6d805 | 1949 | |
| borlanic | 0:fbdae7e6d805 | 1950 | /** |
| borlanic | 0:fbdae7e6d805 | 1951 | * @} |
| borlanic | 0:fbdae7e6d805 | 1952 | */ |
| borlanic | 0:fbdae7e6d805 | 1953 | |
| borlanic | 0:fbdae7e6d805 | 1954 | /** |
| borlanic | 0:fbdae7e6d805 | 1955 | * @} |
| borlanic | 0:fbdae7e6d805 | 1956 | */ |
| borlanic | 0:fbdae7e6d805 | 1957 | |
| borlanic | 0:fbdae7e6d805 | 1958 | #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined(RI) */ |
| borlanic | 0:fbdae7e6d805 | 1959 | |
| borlanic | 0:fbdae7e6d805 | 1960 | /** |
| borlanic | 0:fbdae7e6d805 | 1961 | * @} |
| borlanic | 0:fbdae7e6d805 | 1962 | */ |
| borlanic | 0:fbdae7e6d805 | 1963 | |
| borlanic | 0:fbdae7e6d805 | 1964 | #ifdef __cplusplus |
| borlanic | 0:fbdae7e6d805 | 1965 | } |
| borlanic | 0:fbdae7e6d805 | 1966 | #endif |
| borlanic | 0:fbdae7e6d805 | 1967 | |
| borlanic | 0:fbdae7e6d805 | 1968 | #endif /* __STM32L1xx_LL_SYSTEM_H */ |
| borlanic | 0:fbdae7e6d805 | 1969 | |
| borlanic | 0:fbdae7e6d805 | 1970 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |