Nicolas Borla / Mbed OS BBR_1Ebene
Committer:
borlanic
Date:
Mon May 14 11:29:06 2018 +0000
Revision:
0:fbdae7e6d805
BBR

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borlanic 0:fbdae7e6d805 1 /**
borlanic 0:fbdae7e6d805 2 ******************************************************************************
borlanic 0:fbdae7e6d805 3 * @file stm32l1xx_hal_usart.h
borlanic 0:fbdae7e6d805 4 * @author MCD Application Team
borlanic 0:fbdae7e6d805 5 * @brief This file contains all the functions prototypes for the USART
borlanic 0:fbdae7e6d805 6 * firmware library.
borlanic 0:fbdae7e6d805 7 ******************************************************************************
borlanic 0:fbdae7e6d805 8 * @attention
borlanic 0:fbdae7e6d805 9 *
borlanic 0:fbdae7e6d805 10 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
borlanic 0:fbdae7e6d805 11 *
borlanic 0:fbdae7e6d805 12 * Redistribution and use in source and binary forms, with or without modification,
borlanic 0:fbdae7e6d805 13 * are permitted provided that the following conditions are met:
borlanic 0:fbdae7e6d805 14 * 1. Redistributions of source code must retain the above copyright notice,
borlanic 0:fbdae7e6d805 15 * this list of conditions and the following disclaimer.
borlanic 0:fbdae7e6d805 16 * 2. Redistributions in binary form must reproduce the above copyright notice,
borlanic 0:fbdae7e6d805 17 * this list of conditions and the following disclaimer in the documentation
borlanic 0:fbdae7e6d805 18 * and/or other materials provided with the distribution.
borlanic 0:fbdae7e6d805 19 * 3. Neither the name of STMicroelectronics nor the names of its contributors
borlanic 0:fbdae7e6d805 20 * may be used to endorse or promote products derived from this software
borlanic 0:fbdae7e6d805 21 * without specific prior written permission.
borlanic 0:fbdae7e6d805 22 *
borlanic 0:fbdae7e6d805 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
borlanic 0:fbdae7e6d805 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
borlanic 0:fbdae7e6d805 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
borlanic 0:fbdae7e6d805 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
borlanic 0:fbdae7e6d805 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
borlanic 0:fbdae7e6d805 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
borlanic 0:fbdae7e6d805 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
borlanic 0:fbdae7e6d805 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
borlanic 0:fbdae7e6d805 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
borlanic 0:fbdae7e6d805 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
borlanic 0:fbdae7e6d805 33 *
borlanic 0:fbdae7e6d805 34 ******************************************************************************
borlanic 0:fbdae7e6d805 35 */
borlanic 0:fbdae7e6d805 36
borlanic 0:fbdae7e6d805 37 /* Define to prevent recursive inclusion -------------------------------------*/
borlanic 0:fbdae7e6d805 38 #ifndef __STM32L1xx_HAL_USART_H
borlanic 0:fbdae7e6d805 39 #define __STM32L1xx_HAL_USART_H
borlanic 0:fbdae7e6d805 40
borlanic 0:fbdae7e6d805 41 #ifdef __cplusplus
borlanic 0:fbdae7e6d805 42 extern "C" {
borlanic 0:fbdae7e6d805 43 #endif
borlanic 0:fbdae7e6d805 44
borlanic 0:fbdae7e6d805 45 /* Includes ------------------------------------------------------------------*/
borlanic 0:fbdae7e6d805 46 #include "stm32l1xx_hal_def.h"
borlanic 0:fbdae7e6d805 47
borlanic 0:fbdae7e6d805 48 /** @addtogroup STM32L1xx_HAL_Driver
borlanic 0:fbdae7e6d805 49 * @{
borlanic 0:fbdae7e6d805 50 */
borlanic 0:fbdae7e6d805 51
borlanic 0:fbdae7e6d805 52 /** @addtogroup USART
borlanic 0:fbdae7e6d805 53 * @{
borlanic 0:fbdae7e6d805 54 */
borlanic 0:fbdae7e6d805 55
borlanic 0:fbdae7e6d805 56 /* Exported types ------------------------------------------------------------*/
borlanic 0:fbdae7e6d805 57 /** @defgroup USART_Exported_Types USART Exported Types
borlanic 0:fbdae7e6d805 58 * @{
borlanic 0:fbdae7e6d805 59 */
borlanic 0:fbdae7e6d805 60
borlanic 0:fbdae7e6d805 61
borlanic 0:fbdae7e6d805 62 /**
borlanic 0:fbdae7e6d805 63 * @brief USART Init Structure definition
borlanic 0:fbdae7e6d805 64 */
borlanic 0:fbdae7e6d805 65 typedef struct
borlanic 0:fbdae7e6d805 66 {
borlanic 0:fbdae7e6d805 67 uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
borlanic 0:fbdae7e6d805 68 The baud rate is computed using the following formula:
borlanic 0:fbdae7e6d805 69 - IntegerDivider = ((PCLKx) / (8 * (husart->Init.BaudRate)))
borlanic 0:fbdae7e6d805 70 - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */
borlanic 0:fbdae7e6d805 71
borlanic 0:fbdae7e6d805 72 uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
borlanic 0:fbdae7e6d805 73 This parameter can be a value of @ref USART_Word_Length */
borlanic 0:fbdae7e6d805 74
borlanic 0:fbdae7e6d805 75 uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
borlanic 0:fbdae7e6d805 76 This parameter can be a value of @ref USART_Stop_Bits */
borlanic 0:fbdae7e6d805 77
borlanic 0:fbdae7e6d805 78 uint32_t Parity; /*!< Specifies the parity mode.
borlanic 0:fbdae7e6d805 79 This parameter can be a value of @ref USART_Parity
borlanic 0:fbdae7e6d805 80 @note When parity is enabled, the computed parity is inserted
borlanic 0:fbdae7e6d805 81 at the MSB position of the transmitted data (9th bit when
borlanic 0:fbdae7e6d805 82 the word length is set to 9 data bits; 8th bit when the
borlanic 0:fbdae7e6d805 83 word length is set to 8 data bits). */
borlanic 0:fbdae7e6d805 84
borlanic 0:fbdae7e6d805 85 uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
borlanic 0:fbdae7e6d805 86 This parameter can be a value of @ref USART_Mode */
borlanic 0:fbdae7e6d805 87
borlanic 0:fbdae7e6d805 88 uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
borlanic 0:fbdae7e6d805 89 This parameter can be a value of @ref USART_Clock_Polarity */
borlanic 0:fbdae7e6d805 90
borlanic 0:fbdae7e6d805 91 uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
borlanic 0:fbdae7e6d805 92 This parameter can be a value of @ref USART_Clock_Phase */
borlanic 0:fbdae7e6d805 93
borlanic 0:fbdae7e6d805 94 uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
borlanic 0:fbdae7e6d805 95 data bit (MSB) has to be output on the SCLK pin in synchronous mode.
borlanic 0:fbdae7e6d805 96 This parameter can be a value of @ref USART_Last_Bit */
borlanic 0:fbdae7e6d805 97 }USART_InitTypeDef;
borlanic 0:fbdae7e6d805 98
borlanic 0:fbdae7e6d805 99 /**
borlanic 0:fbdae7e6d805 100 * @brief HAL State structures definition
borlanic 0:fbdae7e6d805 101 */
borlanic 0:fbdae7e6d805 102 typedef enum
borlanic 0:fbdae7e6d805 103 {
borlanic 0:fbdae7e6d805 104 HAL_USART_STATE_RESET = 0x00, /*!< Peripheral is not initialized */
borlanic 0:fbdae7e6d805 105 HAL_USART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
borlanic 0:fbdae7e6d805 106 HAL_USART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
borlanic 0:fbdae7e6d805 107 HAL_USART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
borlanic 0:fbdae7e6d805 108 HAL_USART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
borlanic 0:fbdae7e6d805 109 HAL_USART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission Reception process is ongoing */
borlanic 0:fbdae7e6d805 110 HAL_USART_STATE_TIMEOUT = 0x03, /*!< Timeout state */
borlanic 0:fbdae7e6d805 111 HAL_USART_STATE_ERROR = 0x04 /*!< Error */
borlanic 0:fbdae7e6d805 112 }HAL_USART_StateTypeDef;
borlanic 0:fbdae7e6d805 113
borlanic 0:fbdae7e6d805 114
borlanic 0:fbdae7e6d805 115 /**
borlanic 0:fbdae7e6d805 116 * @brief USART handle Structure definition
borlanic 0:fbdae7e6d805 117 */
borlanic 0:fbdae7e6d805 118 typedef struct
borlanic 0:fbdae7e6d805 119 {
borlanic 0:fbdae7e6d805 120 USART_TypeDef *Instance; /*!< USART registers base address */
borlanic 0:fbdae7e6d805 121
borlanic 0:fbdae7e6d805 122 USART_InitTypeDef Init; /*!< Usart communication parameters */
borlanic 0:fbdae7e6d805 123
borlanic 0:fbdae7e6d805 124 uint8_t *pTxBuffPtr; /*!< Pointer to Usart Tx transfer Buffer */
borlanic 0:fbdae7e6d805 125
borlanic 0:fbdae7e6d805 126 uint16_t TxXferSize; /*!< Usart Tx Transfer size */
borlanic 0:fbdae7e6d805 127
borlanic 0:fbdae7e6d805 128 __IO uint16_t TxXferCount; /*!< Usart Tx Transfer Counter */
borlanic 0:fbdae7e6d805 129
borlanic 0:fbdae7e6d805 130 uint8_t *pRxBuffPtr; /*!< Pointer to Usart Rx transfer Buffer */
borlanic 0:fbdae7e6d805 131
borlanic 0:fbdae7e6d805 132 uint16_t RxXferSize; /*!< Usart Rx Transfer size */
borlanic 0:fbdae7e6d805 133
borlanic 0:fbdae7e6d805 134 __IO uint16_t RxXferCount; /*!< Usart Rx Transfer Counter */
borlanic 0:fbdae7e6d805 135
borlanic 0:fbdae7e6d805 136 DMA_HandleTypeDef *hdmatx; /*!< Usart Tx DMA Handle parameters */
borlanic 0:fbdae7e6d805 137
borlanic 0:fbdae7e6d805 138 DMA_HandleTypeDef *hdmarx; /*!< Usart Rx DMA Handle parameters */
borlanic 0:fbdae7e6d805 139
borlanic 0:fbdae7e6d805 140 HAL_LockTypeDef Lock; /*!< Locking object */
borlanic 0:fbdae7e6d805 141
borlanic 0:fbdae7e6d805 142 __IO HAL_USART_StateTypeDef State; /*!< Usart communication state */
borlanic 0:fbdae7e6d805 143
borlanic 0:fbdae7e6d805 144 __IO uint32_t ErrorCode; /*!< USART Error code */
borlanic 0:fbdae7e6d805 145
borlanic 0:fbdae7e6d805 146 }USART_HandleTypeDef;
borlanic 0:fbdae7e6d805 147
borlanic 0:fbdae7e6d805 148 /**
borlanic 0:fbdae7e6d805 149 * @}
borlanic 0:fbdae7e6d805 150 */
borlanic 0:fbdae7e6d805 151
borlanic 0:fbdae7e6d805 152 /* Exported constants --------------------------------------------------------*/
borlanic 0:fbdae7e6d805 153 /** @defgroup USART_Exported_Constants USART Exported constants
borlanic 0:fbdae7e6d805 154 * @{
borlanic 0:fbdae7e6d805 155 */
borlanic 0:fbdae7e6d805 156
borlanic 0:fbdae7e6d805 157 /** @defgroup USART_Error_Codes USART Error Codes
borlanic 0:fbdae7e6d805 158 * @{
borlanic 0:fbdae7e6d805 159 */
borlanic 0:fbdae7e6d805 160 #define HAL_USART_ERROR_NONE (0x00U) /*!< No error */
borlanic 0:fbdae7e6d805 161 #define HAL_USART_ERROR_PE (0x01U) /*!< Parity error */
borlanic 0:fbdae7e6d805 162 #define HAL_USART_ERROR_NE (0x02U) /*!< Noise error */
borlanic 0:fbdae7e6d805 163 #define HAL_USART_ERROR_FE (0x04U) /*!< frame error */
borlanic 0:fbdae7e6d805 164 #define HAL_USART_ERROR_ORE (0x08U) /*!< Overrun error */
borlanic 0:fbdae7e6d805 165 #define HAL_USART_ERROR_DMA (0x10U) /*!< DMA transfer error */
borlanic 0:fbdae7e6d805 166 /**
borlanic 0:fbdae7e6d805 167 * @}
borlanic 0:fbdae7e6d805 168 */
borlanic 0:fbdae7e6d805 169
borlanic 0:fbdae7e6d805 170 /** @defgroup USART_Word_Length USART Word Length
borlanic 0:fbdae7e6d805 171 * @{
borlanic 0:fbdae7e6d805 172 */
borlanic 0:fbdae7e6d805 173 #define USART_WORDLENGTH_8B (0x00000000U)
borlanic 0:fbdae7e6d805 174 #define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
borlanic 0:fbdae7e6d805 175 /**
borlanic 0:fbdae7e6d805 176 * @}
borlanic 0:fbdae7e6d805 177 */
borlanic 0:fbdae7e6d805 178
borlanic 0:fbdae7e6d805 179 /** @defgroup USART_Stop_Bits USART Number of Stop Bits
borlanic 0:fbdae7e6d805 180 * @{
borlanic 0:fbdae7e6d805 181 */
borlanic 0:fbdae7e6d805 182 #define USART_STOPBITS_1 (0x00000000U)
borlanic 0:fbdae7e6d805 183 #define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
borlanic 0:fbdae7e6d805 184 #define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
borlanic 0:fbdae7e6d805 185 #define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
borlanic 0:fbdae7e6d805 186 /**
borlanic 0:fbdae7e6d805 187 * @}
borlanic 0:fbdae7e6d805 188 */
borlanic 0:fbdae7e6d805 189
borlanic 0:fbdae7e6d805 190 /** @defgroup USART_Parity USART Parity
borlanic 0:fbdae7e6d805 191 * @{
borlanic 0:fbdae7e6d805 192 */
borlanic 0:fbdae7e6d805 193 #define USART_PARITY_NONE (0x00000000U)
borlanic 0:fbdae7e6d805 194 #define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
borlanic 0:fbdae7e6d805 195 #define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
borlanic 0:fbdae7e6d805 196 /**
borlanic 0:fbdae7e6d805 197 * @}
borlanic 0:fbdae7e6d805 198 */
borlanic 0:fbdae7e6d805 199
borlanic 0:fbdae7e6d805 200 /** @defgroup USART_Mode USART Mode
borlanic 0:fbdae7e6d805 201 * @{
borlanic 0:fbdae7e6d805 202 */
borlanic 0:fbdae7e6d805 203 #define USART_MODE_RX ((uint32_t)USART_CR1_RE)
borlanic 0:fbdae7e6d805 204 #define USART_MODE_TX ((uint32_t)USART_CR1_TE)
borlanic 0:fbdae7e6d805 205 #define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
borlanic 0:fbdae7e6d805 206
borlanic 0:fbdae7e6d805 207 /**
borlanic 0:fbdae7e6d805 208 * @}
borlanic 0:fbdae7e6d805 209 */
borlanic 0:fbdae7e6d805 210
borlanic 0:fbdae7e6d805 211 /** @defgroup USART_Clock USART Clock
borlanic 0:fbdae7e6d805 212 * @{
borlanic 0:fbdae7e6d805 213 */
borlanic 0:fbdae7e6d805 214 #define USART_CLOCK_DISABLE (0x00000000U)
borlanic 0:fbdae7e6d805 215 #define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)
borlanic 0:fbdae7e6d805 216 /**
borlanic 0:fbdae7e6d805 217 * @}
borlanic 0:fbdae7e6d805 218 */
borlanic 0:fbdae7e6d805 219
borlanic 0:fbdae7e6d805 220 /** @defgroup USART_Clock_Polarity USART Clock Polarity
borlanic 0:fbdae7e6d805 221 * @{
borlanic 0:fbdae7e6d805 222 */
borlanic 0:fbdae7e6d805 223 #define USART_POLARITY_LOW (0x00000000U)
borlanic 0:fbdae7e6d805 224 #define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
borlanic 0:fbdae7e6d805 225 /**
borlanic 0:fbdae7e6d805 226 * @}
borlanic 0:fbdae7e6d805 227 */
borlanic 0:fbdae7e6d805 228
borlanic 0:fbdae7e6d805 229 /** @defgroup USART_Clock_Phase USART Clock Phase
borlanic 0:fbdae7e6d805 230 * @{
borlanic 0:fbdae7e6d805 231 */
borlanic 0:fbdae7e6d805 232 #define USART_PHASE_1EDGE (0x00000000U)
borlanic 0:fbdae7e6d805 233 #define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
borlanic 0:fbdae7e6d805 234 /**
borlanic 0:fbdae7e6d805 235 * @}
borlanic 0:fbdae7e6d805 236 */
borlanic 0:fbdae7e6d805 237
borlanic 0:fbdae7e6d805 238 /** @defgroup USART_Last_Bit USART Last Bit
borlanic 0:fbdae7e6d805 239 * @{
borlanic 0:fbdae7e6d805 240 */
borlanic 0:fbdae7e6d805 241 #define USART_LASTBIT_DISABLE (0x00000000U)
borlanic 0:fbdae7e6d805 242 #define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
borlanic 0:fbdae7e6d805 243 /**
borlanic 0:fbdae7e6d805 244 * @}
borlanic 0:fbdae7e6d805 245 */
borlanic 0:fbdae7e6d805 246
borlanic 0:fbdae7e6d805 247 /** @defgroup USART_NACK_State USART NACK State
borlanic 0:fbdae7e6d805 248 * @{
borlanic 0:fbdae7e6d805 249 */
borlanic 0:fbdae7e6d805 250 #define USART_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
borlanic 0:fbdae7e6d805 251 #define USART_NACK_DISABLE (0x00000000U)
borlanic 0:fbdae7e6d805 252 /**
borlanic 0:fbdae7e6d805 253 * @}
borlanic 0:fbdae7e6d805 254 */
borlanic 0:fbdae7e6d805 255
borlanic 0:fbdae7e6d805 256 /** @defgroup USART_Flags USART Flags
borlanic 0:fbdae7e6d805 257 * Elements values convention: 0xXXXX
borlanic 0:fbdae7e6d805 258 * - 0xXXXX : Flag mask in the SR register
borlanic 0:fbdae7e6d805 259 * @{
borlanic 0:fbdae7e6d805 260 */
borlanic 0:fbdae7e6d805 261
borlanic 0:fbdae7e6d805 262 #define USART_FLAG_CTS ((uint32_t)USART_SR_CTS)
borlanic 0:fbdae7e6d805 263 #define USART_FLAG_LBD ((uint32_t)USART_SR_LBD)
borlanic 0:fbdae7e6d805 264 #define USART_FLAG_TXE ((uint32_t)USART_SR_TXE)
borlanic 0:fbdae7e6d805 265 #define USART_FLAG_TC ((uint32_t)USART_SR_TC)
borlanic 0:fbdae7e6d805 266 #define USART_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
borlanic 0:fbdae7e6d805 267 #define USART_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
borlanic 0:fbdae7e6d805 268 #define USART_FLAG_ORE ((uint32_t)USART_SR_ORE)
borlanic 0:fbdae7e6d805 269 #define USART_FLAG_NE ((uint32_t)USART_SR_NE)
borlanic 0:fbdae7e6d805 270 #define USART_FLAG_FE ((uint32_t)USART_SR_FE)
borlanic 0:fbdae7e6d805 271 #define USART_FLAG_PE ((uint32_t)USART_SR_PE)
borlanic 0:fbdae7e6d805 272 /**
borlanic 0:fbdae7e6d805 273 * @}
borlanic 0:fbdae7e6d805 274 */
borlanic 0:fbdae7e6d805 275
borlanic 0:fbdae7e6d805 276 /** @defgroup USART_Interrupt_definition USART Interrupts Definition
borlanic 0:fbdae7e6d805 277 * Elements values convention: 0xY000XXXX
borlanic 0:fbdae7e6d805 278 * - XXXX : Interrupt mask (16 bits) in the Y register
borlanic 0:fbdae7e6d805 279 * - Y : Interrupt source register (4bits)
borlanic 0:fbdae7e6d805 280 * - 0001: CR1 register
borlanic 0:fbdae7e6d805 281 * - 0010: CR2 register
borlanic 0:fbdae7e6d805 282 * - 0011: CR3 register
borlanic 0:fbdae7e6d805 283 *
borlanic 0:fbdae7e6d805 284 * @{
borlanic 0:fbdae7e6d805 285 */
borlanic 0:fbdae7e6d805 286
borlanic 0:fbdae7e6d805 287 #define USART_IT_PE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_PEIE))
borlanic 0:fbdae7e6d805 288 #define USART_IT_TXE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_TXEIE))
borlanic 0:fbdae7e6d805 289 #define USART_IT_TC ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_TCIE))
borlanic 0:fbdae7e6d805 290 #define USART_IT_RXNE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE))
borlanic 0:fbdae7e6d805 291 #define USART_IT_IDLE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE))
borlanic 0:fbdae7e6d805 292
borlanic 0:fbdae7e6d805 293 #define USART_IT_LBD ((uint32_t)(USART_CR2_REG_INDEX << 28 | USART_CR2_LBDIE))
borlanic 0:fbdae7e6d805 294
borlanic 0:fbdae7e6d805 295 #define USART_IT_CTS ((uint32_t)(USART_CR3_REG_INDEX << 28 | USART_CR3_CTSIE))
borlanic 0:fbdae7e6d805 296 #define USART_IT_ERR ((uint32_t)(USART_CR3_REG_INDEX << 28 | USART_CR3_EIE))
borlanic 0:fbdae7e6d805 297
borlanic 0:fbdae7e6d805 298
borlanic 0:fbdae7e6d805 299 /**
borlanic 0:fbdae7e6d805 300 * @}
borlanic 0:fbdae7e6d805 301 */
borlanic 0:fbdae7e6d805 302
borlanic 0:fbdae7e6d805 303 /**
borlanic 0:fbdae7e6d805 304 * @}
borlanic 0:fbdae7e6d805 305 */
borlanic 0:fbdae7e6d805 306
borlanic 0:fbdae7e6d805 307
borlanic 0:fbdae7e6d805 308 /* Exported macro ------------------------------------------------------------*/
borlanic 0:fbdae7e6d805 309 /** @defgroup USART_Exported_Macros USART Exported Macros
borlanic 0:fbdae7e6d805 310 * @{
borlanic 0:fbdae7e6d805 311 */
borlanic 0:fbdae7e6d805 312
borlanic 0:fbdae7e6d805 313
borlanic 0:fbdae7e6d805 314 /** @brief Reset USART handle state
borlanic 0:fbdae7e6d805 315 * @param __HANDLE__: specifies the USART Handle.
borlanic 0:fbdae7e6d805 316 * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
borlanic 0:fbdae7e6d805 317 * @retval None
borlanic 0:fbdae7e6d805 318 */
borlanic 0:fbdae7e6d805 319 #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
borlanic 0:fbdae7e6d805 320
borlanic 0:fbdae7e6d805 321 /** @brief Check whether the specified USART flag is set or not.
borlanic 0:fbdae7e6d805 322 * @param __HANDLE__: specifies the USART Handle.
borlanic 0:fbdae7e6d805 323 * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
borlanic 0:fbdae7e6d805 324 * @param __FLAG__: specifies the flag to check.
borlanic 0:fbdae7e6d805 325 * This parameter can be one of the following values:
borlanic 0:fbdae7e6d805 326 * @arg USART_FLAG_TXE: Transmit data register empty flag
borlanic 0:fbdae7e6d805 327 * @arg USART_FLAG_TC: Transmission Complete flag
borlanic 0:fbdae7e6d805 328 * @arg USART_FLAG_RXNE: Receive data register not empty flag
borlanic 0:fbdae7e6d805 329 * @arg USART_FLAG_IDLE: Idle Line detection flag
borlanic 0:fbdae7e6d805 330 * @arg USART_FLAG_ORE: OverRun Error flag
borlanic 0:fbdae7e6d805 331 * @arg USART_FLAG_NE: Noise Error flag
borlanic 0:fbdae7e6d805 332 * @arg USART_FLAG_FE: Framing Error flag
borlanic 0:fbdae7e6d805 333 * @arg USART_FLAG_PE: Parity Error flag
borlanic 0:fbdae7e6d805 334 * @retval The new state of __FLAG__ (TRUE or FALSE).
borlanic 0:fbdae7e6d805 335 */
borlanic 0:fbdae7e6d805 336
borlanic 0:fbdae7e6d805 337 #define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
borlanic 0:fbdae7e6d805 338
borlanic 0:fbdae7e6d805 339 /** @brief Clear the specified USART pending flags.
borlanic 0:fbdae7e6d805 340 * @param __HANDLE__: specifies the USART Handle.
borlanic 0:fbdae7e6d805 341 * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
borlanic 0:fbdae7e6d805 342 * @param __FLAG__: specifies the flag to check.
borlanic 0:fbdae7e6d805 343 * This parameter can be any combination of the following values:
borlanic 0:fbdae7e6d805 344 * @arg USART_FLAG_TC: Transmission Complete flag.
borlanic 0:fbdae7e6d805 345 * @arg USART_FLAG_RXNE: Receive data register not empty flag.
borlanic 0:fbdae7e6d805 346 *
borlanic 0:fbdae7e6d805 347 * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
borlanic 0:fbdae7e6d805 348 * error) and IDLE (Idle line detected) flags are cleared by software
borlanic 0:fbdae7e6d805 349 * sequence: a read operation to USART_SR register followed by a read
borlanic 0:fbdae7e6d805 350 * operation to USART_DR register.
borlanic 0:fbdae7e6d805 351 * @note RXNE flag can be also cleared by a read to the USART_DR register.
borlanic 0:fbdae7e6d805 352 * @note TC flag can be also cleared by software sequence: a read operation to
borlanic 0:fbdae7e6d805 353 * USART_SR register followed by a write operation to USART_DR register.
borlanic 0:fbdae7e6d805 354 * @note TXE flag is cleared only by a write to the USART_DR register.
borlanic 0:fbdae7e6d805 355 *
borlanic 0:fbdae7e6d805 356 * @retval None
borlanic 0:fbdae7e6d805 357 */
borlanic 0:fbdae7e6d805 358 #define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
borlanic 0:fbdae7e6d805 359
borlanic 0:fbdae7e6d805 360 /** @brief Clear the USART PE pending flag.
borlanic 0:fbdae7e6d805 361 * @param __HANDLE__: specifies the USART Handle.
borlanic 0:fbdae7e6d805 362 * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
borlanic 0:fbdae7e6d805 363 * @retval None
borlanic 0:fbdae7e6d805 364 */
borlanic 0:fbdae7e6d805 365 #define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) \
borlanic 0:fbdae7e6d805 366 do{ \
borlanic 0:fbdae7e6d805 367 __IO uint32_t tmpreg; \
borlanic 0:fbdae7e6d805 368 tmpreg = (__HANDLE__)->Instance->SR; \
borlanic 0:fbdae7e6d805 369 tmpreg = (__HANDLE__)->Instance->DR; \
borlanic 0:fbdae7e6d805 370 UNUSED(tmpreg); \
borlanic 0:fbdae7e6d805 371 }while(0)
borlanic 0:fbdae7e6d805 372
borlanic 0:fbdae7e6d805 373
borlanic 0:fbdae7e6d805 374 /** @brief Clear the USART FE pending flag.
borlanic 0:fbdae7e6d805 375 * @param __HANDLE__: specifies the USART Handle.
borlanic 0:fbdae7e6d805 376 * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
borlanic 0:fbdae7e6d805 377 * @retval None
borlanic 0:fbdae7e6d805 378 */
borlanic 0:fbdae7e6d805 379 #define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
borlanic 0:fbdae7e6d805 380
borlanic 0:fbdae7e6d805 381 /** @brief Clear the USART NE pending flag.
borlanic 0:fbdae7e6d805 382 * @param __HANDLE__: specifies the USART Handle.
borlanic 0:fbdae7e6d805 383 * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
borlanic 0:fbdae7e6d805 384 * @retval None
borlanic 0:fbdae7e6d805 385 */
borlanic 0:fbdae7e6d805 386 #define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
borlanic 0:fbdae7e6d805 387
borlanic 0:fbdae7e6d805 388 /** @brief Clear the USART ORE pending flag.
borlanic 0:fbdae7e6d805 389 * @param __HANDLE__: specifies the USART Handle.
borlanic 0:fbdae7e6d805 390 * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
borlanic 0:fbdae7e6d805 391 * @retval None
borlanic 0:fbdae7e6d805 392 */
borlanic 0:fbdae7e6d805 393 #define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
borlanic 0:fbdae7e6d805 394
borlanic 0:fbdae7e6d805 395 /** @brief Clear the USART IDLE pending flag.
borlanic 0:fbdae7e6d805 396 * @param __HANDLE__: specifies the USART Handle.
borlanic 0:fbdae7e6d805 397 * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
borlanic 0:fbdae7e6d805 398 * @retval None
borlanic 0:fbdae7e6d805 399 */
borlanic 0:fbdae7e6d805 400 #define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
borlanic 0:fbdae7e6d805 401
borlanic 0:fbdae7e6d805 402 /** @brief Enable the specified Usart interrupts.
borlanic 0:fbdae7e6d805 403 * @param __HANDLE__: specifies the USART Handle.
borlanic 0:fbdae7e6d805 404 * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
borlanic 0:fbdae7e6d805 405 * @param __INTERRUPT__: specifies the USART interrupt source to enable.
borlanic 0:fbdae7e6d805 406 * This parameter can be one of the following values:
borlanic 0:fbdae7e6d805 407 * @arg USART_IT_TXE: Transmit Data Register empty interrupt
borlanic 0:fbdae7e6d805 408 * @arg USART_IT_TC: Transmission complete interrupt
borlanic 0:fbdae7e6d805 409 * @arg USART_IT_RXNE: Receive Data register not empty interrupt
borlanic 0:fbdae7e6d805 410 * @arg USART_IT_IDLE: Idle line detection interrupt
borlanic 0:fbdae7e6d805 411 * @arg USART_IT_PE: Parity Error interrupt
borlanic 0:fbdae7e6d805 412 * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
borlanic 0:fbdae7e6d805 413 * @retval None
borlanic 0:fbdae7e6d805 414 */
borlanic 0:fbdae7e6d805 415 #define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \
borlanic 0:fbdae7e6d805 416 (((__INTERRUPT__) >> 28) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & USART_IT_MASK)): \
borlanic 0:fbdae7e6d805 417 ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK)))
borlanic 0:fbdae7e6d805 418
borlanic 0:fbdae7e6d805 419
borlanic 0:fbdae7e6d805 420 /** @brief Disable the specified Usart interrupts.
borlanic 0:fbdae7e6d805 421 * @param __HANDLE__: specifies the USART Handle.
borlanic 0:fbdae7e6d805 422 * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
borlanic 0:fbdae7e6d805 423 * @param __INTERRUPT__: specifies the USART interrupt source to disable.
borlanic 0:fbdae7e6d805 424 * This parameter can be one of the following values:
borlanic 0:fbdae7e6d805 425 * @arg USART_IT_TXE: Transmit Data Register empty interrupt
borlanic 0:fbdae7e6d805 426 * @arg USART_IT_TC: Transmission complete interrupt
borlanic 0:fbdae7e6d805 427 * @arg USART_IT_RXNE: Receive Data register not empty interrupt
borlanic 0:fbdae7e6d805 428 * @arg USART_IT_IDLE: Idle line detection interrupt
borlanic 0:fbdae7e6d805 429 * @arg USART_IT_PE: Parity Error interrupt
borlanic 0:fbdae7e6d805 430 * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
borlanic 0:fbdae7e6d805 431 * @retval None
borlanic 0:fbdae7e6d805 432 */
borlanic 0:fbdae7e6d805 433 #define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
borlanic 0:fbdae7e6d805 434 (((__INTERRUPT__) >> 28) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
borlanic 0:fbdae7e6d805 435 ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK)))
borlanic 0:fbdae7e6d805 436
borlanic 0:fbdae7e6d805 437
borlanic 0:fbdae7e6d805 438
borlanic 0:fbdae7e6d805 439 /** @brief Check whether the specified Usart interrupt has occurred or not.
borlanic 0:fbdae7e6d805 440 * @param __HANDLE__: specifies the USART Handle.
borlanic 0:fbdae7e6d805 441 * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
borlanic 0:fbdae7e6d805 442 * @param __IT__: specifies the USART interrupt source to check.
borlanic 0:fbdae7e6d805 443 * This parameter can be one of the following values:
borlanic 0:fbdae7e6d805 444 * @arg USART_IT_TXE: Transmit Data Register empty interrupt
borlanic 0:fbdae7e6d805 445 * @arg USART_IT_TC: Transmission complete interrupt
borlanic 0:fbdae7e6d805 446 * @arg USART_IT_RXNE: Receive Data register not empty interrupt
borlanic 0:fbdae7e6d805 447 * @arg USART_IT_IDLE: Idle line detection interrupt
borlanic 0:fbdae7e6d805 448 * @arg USART_IT_ERR: Error interrupt
borlanic 0:fbdae7e6d805 449 * @arg USART_IT_PE: Parity Error interrupt
borlanic 0:fbdae7e6d805 450 * @retval The new state of __IT__ (TRUE or FALSE).
borlanic 0:fbdae7e6d805 451 */
borlanic 0:fbdae7e6d805 452 #define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == USART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == USART_CR2_REG_INDEX)? \
borlanic 0:fbdae7e6d805 453 (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK))
borlanic 0:fbdae7e6d805 454
borlanic 0:fbdae7e6d805 455 /** @brief Enables the USART one bit sample method
borlanic 0:fbdae7e6d805 456 * @param __HANDLE__: specifies the USART Handle.
borlanic 0:fbdae7e6d805 457 * @retval None
borlanic 0:fbdae7e6d805 458 */
borlanic 0:fbdae7e6d805 459 #define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR3, (USART_CR3_ONEBIT))
borlanic 0:fbdae7e6d805 460
borlanic 0:fbdae7e6d805 461 /** @brief Disables the UART one bit sample method
borlanic 0:fbdae7e6d805 462 * @param __HANDLE__: specifies the UART Handle.
borlanic 0:fbdae7e6d805 463 * @retval None
borlanic 0:fbdae7e6d805 464 */
borlanic 0:fbdae7e6d805 465 #define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR3,(USART_CR3_ONEBIT))
borlanic 0:fbdae7e6d805 466
borlanic 0:fbdae7e6d805 467 /** @brief Enable USART
borlanic 0:fbdae7e6d805 468 * @param __HANDLE__: specifies the USART Handle.
borlanic 0:fbdae7e6d805 469 * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
borlanic 0:fbdae7e6d805 470 * @retval None
borlanic 0:fbdae7e6d805 471 */
borlanic 0:fbdae7e6d805 472 #define __HAL_USART_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1,(USART_CR1_UE))
borlanic 0:fbdae7e6d805 473
borlanic 0:fbdae7e6d805 474 /** @brief Disable USART
borlanic 0:fbdae7e6d805 475 * @param __HANDLE__: specifies the USART Handle.
borlanic 0:fbdae7e6d805 476 * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
borlanic 0:fbdae7e6d805 477 * @retval None
borlanic 0:fbdae7e6d805 478 */
borlanic 0:fbdae7e6d805 479 #define __HAL_USART_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1,(USART_CR1_UE))
borlanic 0:fbdae7e6d805 480
borlanic 0:fbdae7e6d805 481
borlanic 0:fbdae7e6d805 482 /**
borlanic 0:fbdae7e6d805 483 * @}
borlanic 0:fbdae7e6d805 484 */
borlanic 0:fbdae7e6d805 485
borlanic 0:fbdae7e6d805 486
borlanic 0:fbdae7e6d805 487 /* Private macros --------------------------------------------------------*/
borlanic 0:fbdae7e6d805 488 /** @defgroup USART_Private_Macros USART Private Macros
borlanic 0:fbdae7e6d805 489 * @{
borlanic 0:fbdae7e6d805 490 */
borlanic 0:fbdae7e6d805 491
borlanic 0:fbdae7e6d805 492 #define USART_CR1_REG_INDEX 1
borlanic 0:fbdae7e6d805 493 #define USART_CR2_REG_INDEX 2
borlanic 0:fbdae7e6d805 494 #define USART_CR3_REG_INDEX 3
borlanic 0:fbdae7e6d805 495
borlanic 0:fbdae7e6d805 496 #define USART_DIV(__PCLK__, __BAUD__) (((__PCLK__)*25)/(2*(__BAUD__)))
borlanic 0:fbdae7e6d805 497 #define USART_DIVMANT(__PCLK__, __BAUD__) (USART_DIV((__PCLK__), (__BAUD__))/100)
borlanic 0:fbdae7e6d805 498 #define USART_DIVFRAQ(__PCLK__, __BAUD__) (((USART_DIV((__PCLK__), (__BAUD__)) - (USART_DIVMANT((__PCLK__), (__BAUD__)) * 100)) * 16 + 50) / 100)
borlanic 0:fbdae7e6d805 499 #define USART_BRR(__PCLK__, __BAUD__) ((USART_DIVMANT((__PCLK__), (__BAUD__)) << 4)|(USART_DIVFRAQ((__PCLK__), (__BAUD__)) & 0x07))
borlanic 0:fbdae7e6d805 500
borlanic 0:fbdae7e6d805 501 /** Check USART Baud rate
borlanic 0:fbdae7e6d805 502 * __BAUDRATE__: Baudrate specified by the user
borlanic 0:fbdae7e6d805 503 * The maximum Baud Rate is derived from the maximum clock on APB (i.e. 32 MHz)
borlanic 0:fbdae7e6d805 504 * divided by the smallest oversampling used on the USART (i.e. 8)
borlanic 0:fbdae7e6d805 505 * return : TRUE or FALSE
borlanic 0:fbdae7e6d805 506 */
borlanic 0:fbdae7e6d805 507 #define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4000001)
borlanic 0:fbdae7e6d805 508
borlanic 0:fbdae7e6d805 509 #define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \
borlanic 0:fbdae7e6d805 510 ((LENGTH) == USART_WORDLENGTH_9B))
borlanic 0:fbdae7e6d805 511
borlanic 0:fbdae7e6d805 512 #define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \
borlanic 0:fbdae7e6d805 513 ((STOPBITS) == USART_STOPBITS_0_5) || \
borlanic 0:fbdae7e6d805 514 ((STOPBITS) == USART_STOPBITS_1_5) || \
borlanic 0:fbdae7e6d805 515 ((STOPBITS) == USART_STOPBITS_2))
borlanic 0:fbdae7e6d805 516
borlanic 0:fbdae7e6d805 517 #define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \
borlanic 0:fbdae7e6d805 518 ((PARITY) == USART_PARITY_EVEN) || \
borlanic 0:fbdae7e6d805 519 ((PARITY) == USART_PARITY_ODD))
borlanic 0:fbdae7e6d805 520
borlanic 0:fbdae7e6d805 521 #define IS_USART_MODE(MODE) ((((MODE) & (~((uint32_t)USART_MODE_TX_RX))) == 0x00U) && ((MODE) != 0x00000000U))
borlanic 0:fbdae7e6d805 522
borlanic 0:fbdae7e6d805 523 #define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLE) || \
borlanic 0:fbdae7e6d805 524 ((CLOCK) == USART_CLOCK_ENABLE))
borlanic 0:fbdae7e6d805 525
borlanic 0:fbdae7e6d805 526 #define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH))
borlanic 0:fbdae7e6d805 527
borlanic 0:fbdae7e6d805 528 #define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE))
borlanic 0:fbdae7e6d805 529
borlanic 0:fbdae7e6d805 530 #define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \
borlanic 0:fbdae7e6d805 531 ((LASTBIT) == USART_LASTBIT_ENABLE))
borlanic 0:fbdae7e6d805 532
borlanic 0:fbdae7e6d805 533 #define IS_USART_NACK_STATE(NACK) (((NACK) == USART_NACK_ENABLE) || \
borlanic 0:fbdae7e6d805 534 ((NACK) == USART_NACK_DISABLE))
borlanic 0:fbdae7e6d805 535
borlanic 0:fbdae7e6d805 536 /** USART interruptions flag mask
borlanic 0:fbdae7e6d805 537 *
borlanic 0:fbdae7e6d805 538 */
borlanic 0:fbdae7e6d805 539 #define USART_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
borlanic 0:fbdae7e6d805 540 USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
borlanic 0:fbdae7e6d805 541
borlanic 0:fbdae7e6d805 542 /**
borlanic 0:fbdae7e6d805 543 * @}
borlanic 0:fbdae7e6d805 544 */
borlanic 0:fbdae7e6d805 545
borlanic 0:fbdae7e6d805 546
borlanic 0:fbdae7e6d805 547 /* Exported functions --------------------------------------------------------*/
borlanic 0:fbdae7e6d805 548
borlanic 0:fbdae7e6d805 549 /** @addtogroup USART_Exported_Functions USART Exported Functions
borlanic 0:fbdae7e6d805 550 * @{
borlanic 0:fbdae7e6d805 551 */
borlanic 0:fbdae7e6d805 552
borlanic 0:fbdae7e6d805 553 /** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
borlanic 0:fbdae7e6d805 554 * @{
borlanic 0:fbdae7e6d805 555 */
borlanic 0:fbdae7e6d805 556
borlanic 0:fbdae7e6d805 557 /* Initialization and de-initialization functions ******************************/
borlanic 0:fbdae7e6d805 558 HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
borlanic 0:fbdae7e6d805 559 HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
borlanic 0:fbdae7e6d805 560 void HAL_USART_MspInit(USART_HandleTypeDef *husart);
borlanic 0:fbdae7e6d805 561 void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
borlanic 0:fbdae7e6d805 562
borlanic 0:fbdae7e6d805 563 /**
borlanic 0:fbdae7e6d805 564 * @}
borlanic 0:fbdae7e6d805 565 */
borlanic 0:fbdae7e6d805 566
borlanic 0:fbdae7e6d805 567 /** @addtogroup USART_Exported_Functions_Group2 IO operation functions
borlanic 0:fbdae7e6d805 568 * @{
borlanic 0:fbdae7e6d805 569 */
borlanic 0:fbdae7e6d805 570
borlanic 0:fbdae7e6d805 571 /* IO operation functions *******************************************************/
borlanic 0:fbdae7e6d805 572 HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
borlanic 0:fbdae7e6d805 573 HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
borlanic 0:fbdae7e6d805 574 HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
borlanic 0:fbdae7e6d805 575 HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
borlanic 0:fbdae7e6d805 576 HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
borlanic 0:fbdae7e6d805 577 HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
borlanic 0:fbdae7e6d805 578 HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
borlanic 0:fbdae7e6d805 579 HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
borlanic 0:fbdae7e6d805 580 HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
borlanic 0:fbdae7e6d805 581 HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
borlanic 0:fbdae7e6d805 582 HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
borlanic 0:fbdae7e6d805 583 HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
borlanic 0:fbdae7e6d805 584 void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
borlanic 0:fbdae7e6d805 585 void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
borlanic 0:fbdae7e6d805 586 void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
borlanic 0:fbdae7e6d805 587 void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
borlanic 0:fbdae7e6d805 588 void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
borlanic 0:fbdae7e6d805 589 void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
borlanic 0:fbdae7e6d805 590 void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
borlanic 0:fbdae7e6d805 591
borlanic 0:fbdae7e6d805 592 /**
borlanic 0:fbdae7e6d805 593 * @}
borlanic 0:fbdae7e6d805 594 */
borlanic 0:fbdae7e6d805 595
borlanic 0:fbdae7e6d805 596 /* Peripheral Control functions ***********************************************/
borlanic 0:fbdae7e6d805 597
borlanic 0:fbdae7e6d805 598 /** @addtogroup USART_Exported_Functions_Group3 Peripheral State and Errors functions
borlanic 0:fbdae7e6d805 599 * @{
borlanic 0:fbdae7e6d805 600 */
borlanic 0:fbdae7e6d805 601
borlanic 0:fbdae7e6d805 602 /* Peripheral State and Error functions ***************************************/
borlanic 0:fbdae7e6d805 603 HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
borlanic 0:fbdae7e6d805 604 uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
borlanic 0:fbdae7e6d805 605
borlanic 0:fbdae7e6d805 606 /**
borlanic 0:fbdae7e6d805 607 * @}
borlanic 0:fbdae7e6d805 608 */
borlanic 0:fbdae7e6d805 609
borlanic 0:fbdae7e6d805 610 /**
borlanic 0:fbdae7e6d805 611 * @}
borlanic 0:fbdae7e6d805 612 */
borlanic 0:fbdae7e6d805 613
borlanic 0:fbdae7e6d805 614 /**
borlanic 0:fbdae7e6d805 615 * @}
borlanic 0:fbdae7e6d805 616 */
borlanic 0:fbdae7e6d805 617
borlanic 0:fbdae7e6d805 618 /**
borlanic 0:fbdae7e6d805 619 * @}
borlanic 0:fbdae7e6d805 620 */
borlanic 0:fbdae7e6d805 621
borlanic 0:fbdae7e6d805 622 #ifdef __cplusplus
borlanic 0:fbdae7e6d805 623 }
borlanic 0:fbdae7e6d805 624 #endif
borlanic 0:fbdae7e6d805 625
borlanic 0:fbdae7e6d805 626 #endif /* __STM32L1xx_HAL_USART_H */
borlanic 0:fbdae7e6d805 627
borlanic 0:fbdae7e6d805 628 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/