Nicolas Borla / Mbed OS BBR_1Ebene

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mbed-os/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/MIMXRT1052_features.h@0:fbdae7e6d805, 2018-05-14 (annotated)

Committer:
borlanic
Date:
Mon May 14 11:29:06 2018 +0000
Revision:
0:fbdae7e6d805
BBR

Who changed what in which revision?

UserRevisionLine numberNew contents of line
borlanic 0:fbdae7e6d805 1 /*
borlanic 0:fbdae7e6d805 2 ** ###################################################################
borlanic 0:fbdae7e6d805 3 ** Version: rev. 0.1, 2017-01-10
borlanic 0:fbdae7e6d805 4 ** Build: b171017
borlanic 0:fbdae7e6d805 5 **
borlanic 0:fbdae7e6d805 6 ** Abstract:
borlanic 0:fbdae7e6d805 7 ** Chip specific module features.
borlanic 0:fbdae7e6d805 8 **
borlanic 0:fbdae7e6d805 9 ** Copyright 2016 Freescale Semiconductor, Inc.
borlanic 0:fbdae7e6d805 10 ** Copyright 2016-2017 NXP
borlanic 0:fbdae7e6d805 11 ** Redistribution and use in source and binary forms, with or without modification,
borlanic 0:fbdae7e6d805 12 ** are permitted provided that the following conditions are met:
borlanic 0:fbdae7e6d805 13 **
borlanic 0:fbdae7e6d805 14 ** 1. Redistributions of source code must retain the above copyright notice, this list
borlanic 0:fbdae7e6d805 15 ** of conditions and the following disclaimer.
borlanic 0:fbdae7e6d805 16 **
borlanic 0:fbdae7e6d805 17 ** 2. Redistributions in binary form must reproduce the above copyright notice, this
borlanic 0:fbdae7e6d805 18 ** list of conditions and the following disclaimer in the documentation and/or
borlanic 0:fbdae7e6d805 19 ** other materials provided with the distribution.
borlanic 0:fbdae7e6d805 20 **
borlanic 0:fbdae7e6d805 21 ** 3. Neither the name of the copyright holder nor the names of its
borlanic 0:fbdae7e6d805 22 ** contributors may be used to endorse or promote products derived from this
borlanic 0:fbdae7e6d805 23 ** software without specific prior written permission.
borlanic 0:fbdae7e6d805 24 **
borlanic 0:fbdae7e6d805 25 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
borlanic 0:fbdae7e6d805 26 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
borlanic 0:fbdae7e6d805 27 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
borlanic 0:fbdae7e6d805 28 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
borlanic 0:fbdae7e6d805 29 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
borlanic 0:fbdae7e6d805 30 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
borlanic 0:fbdae7e6d805 31 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
borlanic 0:fbdae7e6d805 32 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
borlanic 0:fbdae7e6d805 33 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
borlanic 0:fbdae7e6d805 34 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
borlanic 0:fbdae7e6d805 35 **
borlanic 0:fbdae7e6d805 36 ** http: www.nxp.com
borlanic 0:fbdae7e6d805 37 ** mail: support@nxp.com
borlanic 0:fbdae7e6d805 38 **
borlanic 0:fbdae7e6d805 39 ** Revisions:
borlanic 0:fbdae7e6d805 40 ** - rev. 0.1 (2017-01-10)
borlanic 0:fbdae7e6d805 41 ** Initial version.
borlanic 0:fbdae7e6d805 42 **
borlanic 0:fbdae7e6d805 43 ** ###################################################################
borlanic 0:fbdae7e6d805 44 */
borlanic 0:fbdae7e6d805 45
borlanic 0:fbdae7e6d805 46 #ifndef _MIMXRT1052_FEATURES_H_
borlanic 0:fbdae7e6d805 47 #define _MIMXRT1052_FEATURES_H_
borlanic 0:fbdae7e6d805 48
borlanic 0:fbdae7e6d805 49 /* SOC module features */
borlanic 0:fbdae7e6d805 50
borlanic 0:fbdae7e6d805 51 /* @brief ACMP availability on the SoC. */
borlanic 0:fbdae7e6d805 52 #define FSL_FEATURE_SOC_ACMP_COUNT (0)
borlanic 0:fbdae7e6d805 53 /* @brief ADC availability on the SoC. */
borlanic 0:fbdae7e6d805 54 #define FSL_FEATURE_SOC_ADC_COUNT (2)
borlanic 0:fbdae7e6d805 55 /* @brief ADC12 availability on the SoC. */
borlanic 0:fbdae7e6d805 56 #define FSL_FEATURE_SOC_ADC12_COUNT (0)
borlanic 0:fbdae7e6d805 57 /* @brief ADC16 availability on the SoC. */
borlanic 0:fbdae7e6d805 58 #define FSL_FEATURE_SOC_ADC16_COUNT (0)
borlanic 0:fbdae7e6d805 59 /* @brief ADC_5HC availability on the SoC. */
borlanic 0:fbdae7e6d805 60 #define FSL_FEATURE_SOC_ADC_5HC_COUNT (0)
borlanic 0:fbdae7e6d805 61 /* @brief AES availability on the SoC. */
borlanic 0:fbdae7e6d805 62 #define FSL_FEATURE_SOC_AES_COUNT (0)
borlanic 0:fbdae7e6d805 63 /* @brief AFE availability on the SoC. */
borlanic 0:fbdae7e6d805 64 #define FSL_FEATURE_SOC_AFE_COUNT (0)
borlanic 0:fbdae7e6d805 65 /* @brief AGC availability on the SoC. */
borlanic 0:fbdae7e6d805 66 #define FSL_FEATURE_SOC_AGC_COUNT (0)
borlanic 0:fbdae7e6d805 67 /* @brief AIPS availability on the SoC. */
borlanic 0:fbdae7e6d805 68 #define FSL_FEATURE_SOC_AIPS_COUNT (0)
borlanic 0:fbdae7e6d805 69 /* @brief AIPSTZ availability on the SoC. */
borlanic 0:fbdae7e6d805 70 #define FSL_FEATURE_SOC_AIPSTZ_COUNT (4)
borlanic 0:fbdae7e6d805 71 /* @brief ANATOP availability on the SoC. */
borlanic 0:fbdae7e6d805 72 #define FSL_FEATURE_SOC_ANATOP_COUNT (0)
borlanic 0:fbdae7e6d805 73 /* @brief AOI availability on the SoC. */
borlanic 0:fbdae7e6d805 74 #define FSL_FEATURE_SOC_AOI_COUNT (2)
borlanic 0:fbdae7e6d805 75 /* @brief APBH availability on the SoC. */
borlanic 0:fbdae7e6d805 76 #define FSL_FEATURE_SOC_APBH_COUNT (0)
borlanic 0:fbdae7e6d805 77 /* @brief ASMC availability on the SoC. */
borlanic 0:fbdae7e6d805 78 #define FSL_FEATURE_SOC_ASMC_COUNT (0)
borlanic 0:fbdae7e6d805 79 /* @brief ASRC availability on the SoC. */
borlanic 0:fbdae7e6d805 80 #define FSL_FEATURE_SOC_ASRC_COUNT (0)
borlanic 0:fbdae7e6d805 81 /* @brief ASYNC_SYSCON availability on the SoC. */
borlanic 0:fbdae7e6d805 82 #define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (0)
borlanic 0:fbdae7e6d805 83 /* @brief ATX availability on the SoC. */
borlanic 0:fbdae7e6d805 84 #define FSL_FEATURE_SOC_ATX_COUNT (0)
borlanic 0:fbdae7e6d805 85 /* @brief AXBS availability on the SoC. */
borlanic 0:fbdae7e6d805 86 #define FSL_FEATURE_SOC_AXBS_COUNT (0)
borlanic 0:fbdae7e6d805 87 /* @brief BCH availability on the SoC. */
borlanic 0:fbdae7e6d805 88 #define FSL_FEATURE_SOC_BCH_COUNT (0)
borlanic 0:fbdae7e6d805 89 /* @brief BLEDP availability on the SoC. */
borlanic 0:fbdae7e6d805 90 #define FSL_FEATURE_SOC_BLEDP_COUNT (0)
borlanic 0:fbdae7e6d805 91 /* @brief BOD availability on the SoC. */
borlanic 0:fbdae7e6d805 92 #define FSL_FEATURE_SOC_BOD_COUNT (0)
borlanic 0:fbdae7e6d805 93 /* @brief CAAM availability on the SoC. */
borlanic 0:fbdae7e6d805 94 #define FSL_FEATURE_SOC_CAAM_COUNT (0)
borlanic 0:fbdae7e6d805 95 /* @brief CADC availability on the SoC. */
borlanic 0:fbdae7e6d805 96 #define FSL_FEATURE_SOC_CADC_COUNT (0)
borlanic 0:fbdae7e6d805 97 /* @brief CALIB availability on the SoC. */
borlanic 0:fbdae7e6d805 98 #define FSL_FEATURE_SOC_CALIB_COUNT (0)
borlanic 0:fbdae7e6d805 99 /* @brief CAN availability on the SoC. */
borlanic 0:fbdae7e6d805 100 #define FSL_FEATURE_SOC_CAN_COUNT (0)
borlanic 0:fbdae7e6d805 101 /* @brief CAU availability on the SoC. */
borlanic 0:fbdae7e6d805 102 #define FSL_FEATURE_SOC_CAU_COUNT (0)
borlanic 0:fbdae7e6d805 103 /* @brief CAU3 availability on the SoC. */
borlanic 0:fbdae7e6d805 104 #define FSL_FEATURE_SOC_CAU3_COUNT (0)
borlanic 0:fbdae7e6d805 105 /* @brief CCM availability on the SoC. */
borlanic 0:fbdae7e6d805 106 #define FSL_FEATURE_SOC_CCM_COUNT (1)
borlanic 0:fbdae7e6d805 107 /* @brief CCM_ANALOG availability on the SoC. */
borlanic 0:fbdae7e6d805 108 #define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1)
borlanic 0:fbdae7e6d805 109 /* @brief CHRG availability on the SoC. */
borlanic 0:fbdae7e6d805 110 #define FSL_FEATURE_SOC_CHRG_COUNT (0)
borlanic 0:fbdae7e6d805 111 /* @brief CLKCTL0 availability on the SoC. */
borlanic 0:fbdae7e6d805 112 #define FSL_FEATURE_SOC_CLKCTL0_COUNT (0)
borlanic 0:fbdae7e6d805 113 /* @brief CLKCTL1 availability on the SoC. */
borlanic 0:fbdae7e6d805 114 #define FSL_FEATURE_SOC_CLKCTL1_COUNT (0)
borlanic 0:fbdae7e6d805 115 /* @brief CMP availability on the SoC. */
borlanic 0:fbdae7e6d805 116 #define FSL_FEATURE_SOC_CMP_COUNT (4)
borlanic 0:fbdae7e6d805 117 /* @brief CMT availability on the SoC. */
borlanic 0:fbdae7e6d805 118 #define FSL_FEATURE_SOC_CMT_COUNT (0)
borlanic 0:fbdae7e6d805 119 /* @brief CNC availability on the SoC. */
borlanic 0:fbdae7e6d805 120 #define FSL_FEATURE_SOC_CNC_COUNT (0)
borlanic 0:fbdae7e6d805 121 /* @brief COP availability on the SoC. */
borlanic 0:fbdae7e6d805 122 #define FSL_FEATURE_SOC_COP_COUNT (0)
borlanic 0:fbdae7e6d805 123 /* @brief CRC availability on the SoC. */
borlanic 0:fbdae7e6d805 124 #define FSL_FEATURE_SOC_CRC_COUNT (0)
borlanic 0:fbdae7e6d805 125 /* @brief CS availability on the SoC. */
borlanic 0:fbdae7e6d805 126 #define FSL_FEATURE_SOC_CS_COUNT (0)
borlanic 0:fbdae7e6d805 127 /* @brief CSI availability on the SoC. */
borlanic 0:fbdae7e6d805 128 #define FSL_FEATURE_SOC_CSI_COUNT (1)
borlanic 0:fbdae7e6d805 129 /* @brief CT32B availability on the SoC. */
borlanic 0:fbdae7e6d805 130 #define FSL_FEATURE_SOC_CT32B_COUNT (0)
borlanic 0:fbdae7e6d805 131 /* @brief CTI availability on the SoC. */
borlanic 0:fbdae7e6d805 132 #define FSL_FEATURE_SOC_CTI_COUNT (0)
borlanic 0:fbdae7e6d805 133 /* @brief CTIMER availability on the SoC. */
borlanic 0:fbdae7e6d805 134 #define FSL_FEATURE_SOC_CTIMER_COUNT (0)
borlanic 0:fbdae7e6d805 135 /* @brief DAC availability on the SoC. */
borlanic 0:fbdae7e6d805 136 #define FSL_FEATURE_SOC_DAC_COUNT (0)
borlanic 0:fbdae7e6d805 137 /* @brief DAC32 availability on the SoC. */
borlanic 0:fbdae7e6d805 138 #define FSL_FEATURE_SOC_DAC32_COUNT (0)
borlanic 0:fbdae7e6d805 139 /* @brief DCDC availability on the SoC. */
borlanic 0:fbdae7e6d805 140 #define FSL_FEATURE_SOC_DCDC_COUNT (1)
borlanic 0:fbdae7e6d805 141 /* @brief DCP availability on the SoC. */
borlanic 0:fbdae7e6d805 142 #define FSL_FEATURE_SOC_DCP_COUNT (1)
borlanic 0:fbdae7e6d805 143 /* @brief DDR availability on the SoC. */
borlanic 0:fbdae7e6d805 144 #define FSL_FEATURE_SOC_DDR_COUNT (0)
borlanic 0:fbdae7e6d805 145 /* @brief DDRC availability on the SoC. */
borlanic 0:fbdae7e6d805 146 #define FSL_FEATURE_SOC_DDRC_COUNT (0)
borlanic 0:fbdae7e6d805 147 /* @brief DDRC_MP availability on the SoC. */
borlanic 0:fbdae7e6d805 148 #define FSL_FEATURE_SOC_DDRC_MP_COUNT (0)
borlanic 0:fbdae7e6d805 149 /* @brief DDR_PHY availability on the SoC. */
borlanic 0:fbdae7e6d805 150 #define FSL_FEATURE_SOC_DDR_PHY_COUNT (0)
borlanic 0:fbdae7e6d805 151 /* @brief DMA availability on the SoC. */
borlanic 0:fbdae7e6d805 152 #define FSL_FEATURE_SOC_DMA_COUNT (0)
borlanic 0:fbdae7e6d805 153 /* @brief DMAMUX availability on the SoC. */
borlanic 0:fbdae7e6d805 154 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
borlanic 0:fbdae7e6d805 155 /* @brief DMIC availability on the SoC. */
borlanic 0:fbdae7e6d805 156 #define FSL_FEATURE_SOC_DMIC_COUNT (0)
borlanic 0:fbdae7e6d805 157 /* @brief DRY availability on the SoC. */
borlanic 0:fbdae7e6d805 158 #define FSL_FEATURE_SOC_DRY_COUNT (0)
borlanic 0:fbdae7e6d805 159 /* @brief DSPI availability on the SoC. */
borlanic 0:fbdae7e6d805 160 #define FSL_FEATURE_SOC_DSPI_COUNT (0)
borlanic 0:fbdae7e6d805 161 /* @brief ECSPI availability on the SoC. */
borlanic 0:fbdae7e6d805 162 #define FSL_FEATURE_SOC_ECSPI_COUNT (0)
borlanic 0:fbdae7e6d805 163 /* @brief EDMA availability on the SoC. */
borlanic 0:fbdae7e6d805 164 #define FSL_FEATURE_SOC_EDMA_COUNT (1)
borlanic 0:fbdae7e6d805 165 /* @brief EEPROM availability on the SoC. */
borlanic 0:fbdae7e6d805 166 #define FSL_FEATURE_SOC_EEPROM_COUNT (0)
borlanic 0:fbdae7e6d805 167 /* @brief EIM availability on the SoC. */
borlanic 0:fbdae7e6d805 168 #define FSL_FEATURE_SOC_EIM_COUNT (0)
borlanic 0:fbdae7e6d805 169 /* @brief EMC availability on the SoC. */
borlanic 0:fbdae7e6d805 170 #define FSL_FEATURE_SOC_EMC_COUNT (0)
borlanic 0:fbdae7e6d805 171 /* @brief EMVSIM availability on the SoC. */
borlanic 0:fbdae7e6d805 172 #define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
borlanic 0:fbdae7e6d805 173 /* @brief ENC availability on the SoC. */
borlanic 0:fbdae7e6d805 174 #define FSL_FEATURE_SOC_ENC_COUNT (4)
borlanic 0:fbdae7e6d805 175 /* @brief ENET availability on the SoC. */
borlanic 0:fbdae7e6d805 176 #define FSL_FEATURE_SOC_ENET_COUNT (1)
borlanic 0:fbdae7e6d805 177 /* @brief EPDC availability on the SoC. */
borlanic 0:fbdae7e6d805 178 #define FSL_FEATURE_SOC_EPDC_COUNT (0)
borlanic 0:fbdae7e6d805 179 /* @brief EPIT availability on the SoC. */
borlanic 0:fbdae7e6d805 180 #define FSL_FEATURE_SOC_EPIT_COUNT (0)
borlanic 0:fbdae7e6d805 181 /* @brief ESAI availability on the SoC. */
borlanic 0:fbdae7e6d805 182 #define FSL_FEATURE_SOC_ESAI_COUNT (0)
borlanic 0:fbdae7e6d805 183 /* @brief EWM availability on the SoC. */
borlanic 0:fbdae7e6d805 184 #define FSL_FEATURE_SOC_EWM_COUNT (1)
borlanic 0:fbdae7e6d805 185 /* @brief FB availability on the SoC. */
borlanic 0:fbdae7e6d805 186 #define FSL_FEATURE_SOC_FB_COUNT (0)
borlanic 0:fbdae7e6d805 187 /* @brief FGPIO availability on the SoC. */
borlanic 0:fbdae7e6d805 188 #define FSL_FEATURE_SOC_FGPIO_COUNT (0)
borlanic 0:fbdae7e6d805 189 /* @brief FLASH availability on the SoC. */
borlanic 0:fbdae7e6d805 190 #define FSL_FEATURE_SOC_FLASH_COUNT (0)
borlanic 0:fbdae7e6d805 191 /* @brief FLEXCAN availability on the SoC. */
borlanic 0:fbdae7e6d805 192 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (2)
borlanic 0:fbdae7e6d805 193 /* @brief FLEXCOMM availability on the SoC. */
borlanic 0:fbdae7e6d805 194 #define FSL_FEATURE_SOC_FLEXCOMM_COUNT (0)
borlanic 0:fbdae7e6d805 195 /* @brief FLEXIO availability on the SoC. */
borlanic 0:fbdae7e6d805 196 #define FSL_FEATURE_SOC_FLEXIO_COUNT (2)
borlanic 0:fbdae7e6d805 197 /* @brief FLEXRAM availability on the SoC. */
borlanic 0:fbdae7e6d805 198 #define FSL_FEATURE_SOC_FLEXRAM_COUNT (1)
borlanic 0:fbdae7e6d805 199 /* @brief FLEXSPI availability on the SoC. */
borlanic 0:fbdae7e6d805 200 #define FSL_FEATURE_SOC_FLEXSPI_COUNT (1)
borlanic 0:fbdae7e6d805 201 /* @brief FMC availability on the SoC. */
borlanic 0:fbdae7e6d805 202 #define FSL_FEATURE_SOC_FMC_COUNT (0)
borlanic 0:fbdae7e6d805 203 /* @brief FREQME availability on the SoC. */
borlanic 0:fbdae7e6d805 204 #define FSL_FEATURE_SOC_FREQME_COUNT (0)
borlanic 0:fbdae7e6d805 205 /* @brief FSKDT availability on the SoC. */
borlanic 0:fbdae7e6d805 206 #define FSL_FEATURE_SOC_FSKDT_COUNT (0)
borlanic 0:fbdae7e6d805 207 /* @brief FSP availability on the SoC. */
borlanic 0:fbdae7e6d805 208 #define FSL_FEATURE_SOC_FSP_COUNT (0)
borlanic 0:fbdae7e6d805 209 /* @brief FTFA availability on the SoC. */
borlanic 0:fbdae7e6d805 210 #define FSL_FEATURE_SOC_FTFA_COUNT (0)
borlanic 0:fbdae7e6d805 211 /* @brief FTFE availability on the SoC. */
borlanic 0:fbdae7e6d805 212 #define FSL_FEATURE_SOC_FTFE_COUNT (0)
borlanic 0:fbdae7e6d805 213 /* @brief FTFL availability on the SoC. */
borlanic 0:fbdae7e6d805 214 #define FSL_FEATURE_SOC_FTFL_COUNT (0)
borlanic 0:fbdae7e6d805 215 /* @brief FTM availability on the SoC. */
borlanic 0:fbdae7e6d805 216 #define FSL_FEATURE_SOC_FTM_COUNT (0)
borlanic 0:fbdae7e6d805 217 /* @brief FTMRA availability on the SoC. */
borlanic 0:fbdae7e6d805 218 #define FSL_FEATURE_SOC_FTMRA_COUNT (0)
borlanic 0:fbdae7e6d805 219 /* @brief FTMRE availability on the SoC. */
borlanic 0:fbdae7e6d805 220 #define FSL_FEATURE_SOC_FTMRE_COUNT (0)
borlanic 0:fbdae7e6d805 221 /* @brief FTMRH availability on the SoC. */
borlanic 0:fbdae7e6d805 222 #define FSL_FEATURE_SOC_FTMRH_COUNT (0)
borlanic 0:fbdae7e6d805 223 /* @brief GINT availability on the SoC. */
borlanic 0:fbdae7e6d805 224 #define FSL_FEATURE_SOC_GINT_COUNT (0)
borlanic 0:fbdae7e6d805 225 /* @brief GPC availability on the SoC. */
borlanic 0:fbdae7e6d805 226 #define FSL_FEATURE_SOC_GPC_COUNT (1)
borlanic 0:fbdae7e6d805 227 /* @brief GPC_PGC availability on the SoC. */
borlanic 0:fbdae7e6d805 228 #define FSL_FEATURE_SOC_GPC_PGC_COUNT (0)
borlanic 0:fbdae7e6d805 229 /* @brief GPIO availability on the SoC. */
borlanic 0:fbdae7e6d805 230 #define FSL_FEATURE_SOC_GPIO_COUNT (0)
borlanic 0:fbdae7e6d805 231 /* @brief GPMI availability on the SoC. */
borlanic 0:fbdae7e6d805 232 #define FSL_FEATURE_SOC_GPMI_COUNT (0)
borlanic 0:fbdae7e6d805 233 /* @brief GPT availability on the SoC. */
borlanic 0:fbdae7e6d805 234 #define FSL_FEATURE_SOC_GPT_COUNT (2)
borlanic 0:fbdae7e6d805 235 /* @brief HASH availability on the SoC. */
borlanic 0:fbdae7e6d805 236 #define FSL_FEATURE_SOC_HASH_COUNT (0)
borlanic 0:fbdae7e6d805 237 /* @brief HSADC availability on the SoC. */
borlanic 0:fbdae7e6d805 238 #define FSL_FEATURE_SOC_HSADC_COUNT (0)
borlanic 0:fbdae7e6d805 239 /* @brief I2C availability on the SoC. */
borlanic 0:fbdae7e6d805 240 #define FSL_FEATURE_SOC_I2C_COUNT (0)
borlanic 0:fbdae7e6d805 241 /* @brief I2S availability on the SoC. */
borlanic 0:fbdae7e6d805 242 #define FSL_FEATURE_SOC_I2S_COUNT (3)
borlanic 0:fbdae7e6d805 243 /* @brief ICS availability on the SoC. */
borlanic 0:fbdae7e6d805 244 #define FSL_FEATURE_SOC_ICS_COUNT (0)
borlanic 0:fbdae7e6d805 245 /* @brief IEE availability on the SoC. */
borlanic 0:fbdae7e6d805 246 #define FSL_FEATURE_SOC_IEE_COUNT (0)
borlanic 0:fbdae7e6d805 247 /* @brief IEER availability on the SoC. */
borlanic 0:fbdae7e6d805 248 #define FSL_FEATURE_SOC_IEER_COUNT (0)
borlanic 0:fbdae7e6d805 249 /* @brief IGPIO availability on the SoC. */
borlanic 0:fbdae7e6d805 250 #define FSL_FEATURE_SOC_IGPIO_COUNT (5)
borlanic 0:fbdae7e6d805 251 /* @brief II2C availability on the SoC. */
borlanic 0:fbdae7e6d805 252 #define FSL_FEATURE_SOC_II2C_COUNT (0)
borlanic 0:fbdae7e6d805 253 /* @brief INPUTMUX availability on the SoC. */
borlanic 0:fbdae7e6d805 254 #define FSL_FEATURE_SOC_INPUTMUX_COUNT (0)
borlanic 0:fbdae7e6d805 255 /* @brief INTMUX availability on the SoC. */
borlanic 0:fbdae7e6d805 256 #define FSL_FEATURE_SOC_INTMUX_COUNT (0)
borlanic 0:fbdae7e6d805 257 /* @brief IOCON availability on the SoC. */
borlanic 0:fbdae7e6d805 258 #define FSL_FEATURE_SOC_IOCON_COUNT (0)
borlanic 0:fbdae7e6d805 259 /* @brief IOMUXC availability on the SoC. */
borlanic 0:fbdae7e6d805 260 #define FSL_FEATURE_SOC_IOMUXC_COUNT (1)
borlanic 0:fbdae7e6d805 261 /* @brief IOMUXC_GPR availability on the SoC. */
borlanic 0:fbdae7e6d805 262 #define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (1)
borlanic 0:fbdae7e6d805 263 /* @brief IOMUXC_LPSR availability on the SoC. */
borlanic 0:fbdae7e6d805 264 #define FSL_FEATURE_SOC_IOMUXC_LPSR_COUNT (0)
borlanic 0:fbdae7e6d805 265 /* @brief IOMUXC_LPSR_GPR availability on the SoC. */
borlanic 0:fbdae7e6d805 266 #define FSL_FEATURE_SOC_IOMUXC_LPSR_GPR_COUNT (0)
borlanic 0:fbdae7e6d805 267 /* @brief IOMUXC_SNVS availability on the SoC. */
borlanic 0:fbdae7e6d805 268 #define FSL_FEATURE_SOC_IOMUXC_SNVS_COUNT (1)
borlanic 0:fbdae7e6d805 269 /* @brief IOPCTL availability on the SoC. */
borlanic 0:fbdae7e6d805 270 #define FSL_FEATURE_SOC_IOPCTL_COUNT (0)
borlanic 0:fbdae7e6d805 271 /* @brief IPWM availability on the SoC. */
borlanic 0:fbdae7e6d805 272 #define FSL_FEATURE_SOC_IPWM_COUNT (0)
borlanic 0:fbdae7e6d805 273 /* @brief IRQ availability on the SoC. */
borlanic 0:fbdae7e6d805 274 #define FSL_FEATURE_SOC_IRQ_COUNT (0)
borlanic 0:fbdae7e6d805 275 /* @brief IUART availability on the SoC. */
borlanic 0:fbdae7e6d805 276 #define FSL_FEATURE_SOC_IUART_COUNT (0)
borlanic 0:fbdae7e6d805 277 /* @brief KBI availability on the SoC. */
borlanic 0:fbdae7e6d805 278 #define FSL_FEATURE_SOC_KBI_COUNT (0)
borlanic 0:fbdae7e6d805 279 /* @brief KPP availability on the SoC. */
borlanic 0:fbdae7e6d805 280 #define FSL_FEATURE_SOC_KPP_COUNT (1)
borlanic 0:fbdae7e6d805 281 /* @brief L2CACHEC availability on the SoC. */
borlanic 0:fbdae7e6d805 282 #define FSL_FEATURE_SOC_L2CACHEC_COUNT (0)
borlanic 0:fbdae7e6d805 283 /* @brief LCD availability on the SoC. */
borlanic 0:fbdae7e6d805 284 #define FSL_FEATURE_SOC_LCD_COUNT (0)
borlanic 0:fbdae7e6d805 285 /* @brief LCDC availability on the SoC. */
borlanic 0:fbdae7e6d805 286 #define FSL_FEATURE_SOC_LCDC_COUNT (0)
borlanic 0:fbdae7e6d805 287 /* @brief LCDIF availability on the SoC. */
borlanic 0:fbdae7e6d805 288 #define FSL_FEATURE_SOC_LCDIF_COUNT (1)
borlanic 0:fbdae7e6d805 289 /* @brief LDO availability on the SoC. */
borlanic 0:fbdae7e6d805 290 #define FSL_FEATURE_SOC_LDO_COUNT (0)
borlanic 0:fbdae7e6d805 291 /* @brief LLWU availability on the SoC. */
borlanic 0:fbdae7e6d805 292 #define FSL_FEATURE_SOC_LLWU_COUNT (0)
borlanic 0:fbdae7e6d805 293 /* @brief LMEM availability on the SoC. */
borlanic 0:fbdae7e6d805 294 #define FSL_FEATURE_SOC_LMEM_COUNT (0)
borlanic 0:fbdae7e6d805 295 /* @brief LPADC availability on the SoC. */
borlanic 0:fbdae7e6d805 296 #define FSL_FEATURE_SOC_LPADC_COUNT (0)
borlanic 0:fbdae7e6d805 297 /* @brief LPCMP availability on the SoC. */
borlanic 0:fbdae7e6d805 298 #define FSL_FEATURE_SOC_LPCMP_COUNT (0)
borlanic 0:fbdae7e6d805 299 /* @brief LPDAC availability on the SoC. */
borlanic 0:fbdae7e6d805 300 #define FSL_FEATURE_SOC_LPDAC_COUNT (0)
borlanic 0:fbdae7e6d805 301 /* @brief LPI2C availability on the SoC. */
borlanic 0:fbdae7e6d805 302 #define FSL_FEATURE_SOC_LPI2C_COUNT (4)
borlanic 0:fbdae7e6d805 303 /* @brief LPIT availability on the SoC. */
borlanic 0:fbdae7e6d805 304 #define FSL_FEATURE_SOC_LPIT_COUNT (0)
borlanic 0:fbdae7e6d805 305 /* @brief LPSCI availability on the SoC. */
borlanic 0:fbdae7e6d805 306 #define FSL_FEATURE_SOC_LPSCI_COUNT (0)
borlanic 0:fbdae7e6d805 307 /* @brief LPSPI availability on the SoC. */
borlanic 0:fbdae7e6d805 308 #define FSL_FEATURE_SOC_LPSPI_COUNT (4)
borlanic 0:fbdae7e6d805 309 /* @brief LPTMR availability on the SoC. */
borlanic 0:fbdae7e6d805 310 #define FSL_FEATURE_SOC_LPTMR_COUNT (0)
borlanic 0:fbdae7e6d805 311 /* @brief LPTPM availability on the SoC. */
borlanic 0:fbdae7e6d805 312 #define FSL_FEATURE_SOC_LPTPM_COUNT (0)
borlanic 0:fbdae7e6d805 313 /* @brief LPUART availability on the SoC. */
borlanic 0:fbdae7e6d805 314 #define FSL_FEATURE_SOC_LPUART_COUNT (8)
borlanic 0:fbdae7e6d805 315 /* @brief LTC availability on the SoC. */
borlanic 0:fbdae7e6d805 316 #define FSL_FEATURE_SOC_LTC_COUNT (0)
borlanic 0:fbdae7e6d805 317 /* @brief MAILBOX availability on the SoC. */
borlanic 0:fbdae7e6d805 318 #define FSL_FEATURE_SOC_MAILBOX_COUNT (0)
borlanic 0:fbdae7e6d805 319 /* @brief MC availability on the SoC. */
borlanic 0:fbdae7e6d805 320 #define FSL_FEATURE_SOC_MC_COUNT (0)
borlanic 0:fbdae7e6d805 321 /* @brief MCG availability on the SoC. */
borlanic 0:fbdae7e6d805 322 #define FSL_FEATURE_SOC_MCG_COUNT (0)
borlanic 0:fbdae7e6d805 323 /* @brief MCGLITE availability on the SoC. */
borlanic 0:fbdae7e6d805 324 #define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
borlanic 0:fbdae7e6d805 325 /* @brief MCM availability on the SoC. */
borlanic 0:fbdae7e6d805 326 #define FSL_FEATURE_SOC_MCM_COUNT (0)
borlanic 0:fbdae7e6d805 327 /* @brief MIPI_CSI2 availability on the SoC. */
borlanic 0:fbdae7e6d805 328 #define FSL_FEATURE_SOC_MIPI_CSI2_COUNT (0)
borlanic 0:fbdae7e6d805 329 /* @brief MIPI_CSI2RX availability on the SoC. */
borlanic 0:fbdae7e6d805 330 #define FSL_FEATURE_SOC_MIPI_CSI2RX_COUNT (0)
borlanic 0:fbdae7e6d805 331 /* @brief MIPI_DSI availability on the SoC. */
borlanic 0:fbdae7e6d805 332 #define FSL_FEATURE_SOC_MIPI_DSI_COUNT (0)
borlanic 0:fbdae7e6d805 333 /* @brief MIPI_DSI_HOST availability on the SoC. */
borlanic 0:fbdae7e6d805 334 #define FSL_FEATURE_SOC_MIPI_DSI_HOST_COUNT (0)
borlanic 0:fbdae7e6d805 335 /* @brief MMAU availability on the SoC. */
borlanic 0:fbdae7e6d805 336 #define FSL_FEATURE_SOC_MMAU_COUNT (0)
borlanic 0:fbdae7e6d805 337 /* @brief MMCAU availability on the SoC. */
borlanic 0:fbdae7e6d805 338 #define FSL_FEATURE_SOC_MMCAU_COUNT (0)
borlanic 0:fbdae7e6d805 339 /* @brief MMDC availability on the SoC. */
borlanic 0:fbdae7e6d805 340 #define FSL_FEATURE_SOC_MMDC_COUNT (0)
borlanic 0:fbdae7e6d805 341 /* @brief MMDVSQ availability on the SoC. */
borlanic 0:fbdae7e6d805 342 #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
borlanic 0:fbdae7e6d805 343 /* @brief MPU availability on the SoC. */
borlanic 0:fbdae7e6d805 344 #define FSL_FEATURE_SOC_MPU_COUNT (0)
borlanic 0:fbdae7e6d805 345 /* @brief MRT availability on the SoC. */
borlanic 0:fbdae7e6d805 346 #define FSL_FEATURE_SOC_MRT_COUNT (0)
borlanic 0:fbdae7e6d805 347 /* @brief MSCAN availability on the SoC. */
borlanic 0:fbdae7e6d805 348 #define FSL_FEATURE_SOC_MSCAN_COUNT (0)
borlanic 0:fbdae7e6d805 349 /* @brief MSCM availability on the SoC. */
borlanic 0:fbdae7e6d805 350 #define FSL_FEATURE_SOC_MSCM_COUNT (0)
borlanic 0:fbdae7e6d805 351 /* @brief MTB availability on the SoC. */
borlanic 0:fbdae7e6d805 352 #define FSL_FEATURE_SOC_MTB_COUNT (0)
borlanic 0:fbdae7e6d805 353 /* @brief MTBDWT availability on the SoC. */
borlanic 0:fbdae7e6d805 354 #define FSL_FEATURE_SOC_MTBDWT_COUNT (0)
borlanic 0:fbdae7e6d805 355 /* @brief MU availability on the SoC. */
borlanic 0:fbdae7e6d805 356 #define FSL_FEATURE_SOC_MU_COUNT (0)
borlanic 0:fbdae7e6d805 357 /* @brief NFC availability on the SoC. */
borlanic 0:fbdae7e6d805 358 #define FSL_FEATURE_SOC_NFC_COUNT (0)
borlanic 0:fbdae7e6d805 359 /* @brief OCOTP availability on the SoC. */
borlanic 0:fbdae7e6d805 360 #define FSL_FEATURE_SOC_OCOTP_COUNT (1)
borlanic 0:fbdae7e6d805 361 /* @brief OPAMP availability on the SoC. */
borlanic 0:fbdae7e6d805 362 #define FSL_FEATURE_SOC_OPAMP_COUNT (0)
borlanic 0:fbdae7e6d805 363 /* @brief OTPC availability on the SoC. */
borlanic 0:fbdae7e6d805 364 #define FSL_FEATURE_SOC_OTPC_COUNT (0)
borlanic 0:fbdae7e6d805 365 /* @brief OSC availability on the SoC. */
borlanic 0:fbdae7e6d805 366 #define FSL_FEATURE_SOC_OSC_COUNT (0)
borlanic 0:fbdae7e6d805 367 /* @brief OSC32 availability on the SoC. */
borlanic 0:fbdae7e6d805 368 #define FSL_FEATURE_SOC_OSC32_COUNT (0)
borlanic 0:fbdae7e6d805 369 /* @brief OTFAD availability on the SoC. */
borlanic 0:fbdae7e6d805 370 #define FSL_FEATURE_SOC_OTFAD_COUNT (0)
borlanic 0:fbdae7e6d805 371 /* @brief PCC availability on the SoC. */
borlanic 0:fbdae7e6d805 372 #define FSL_FEATURE_SOC_PCC_COUNT (0)
borlanic 0:fbdae7e6d805 373 /* @brief PCIE_PHY_CMN availability on the SoC. */
borlanic 0:fbdae7e6d805 374 #define FSL_FEATURE_SOC_PCIE_PHY_CMN_COUNT (0)
borlanic 0:fbdae7e6d805 375 /* @brief PCIE_PHY_TRSV availability on the SoC. */
borlanic 0:fbdae7e6d805 376 #define FSL_FEATURE_SOC_PCIE_PHY_TRSV_COUNT (0)
borlanic 0:fbdae7e6d805 377 /* @brief PDB availability on the SoC. */
borlanic 0:fbdae7e6d805 378 #define FSL_FEATURE_SOC_PDB_COUNT (0)
borlanic 0:fbdae7e6d805 379 /* @brief PGA availability on the SoC. */
borlanic 0:fbdae7e6d805 380 #define FSL_FEATURE_SOC_PGA_COUNT (0)
borlanic 0:fbdae7e6d805 381 /* @brief PIMCTL availability on the SoC. */
borlanic 0:fbdae7e6d805 382 #define FSL_FEATURE_SOC_PIMCTL_COUNT (0)
borlanic 0:fbdae7e6d805 383 /* @brief PINT availability on the SoC. */
borlanic 0:fbdae7e6d805 384 #define FSL_FEATURE_SOC_PINT_COUNT (0)
borlanic 0:fbdae7e6d805 385 /* @brief PIT availability on the SoC. */
borlanic 0:fbdae7e6d805 386 #define FSL_FEATURE_SOC_PIT_COUNT (1)
borlanic 0:fbdae7e6d805 387 /* @brief PMC availability on the SoC. */
borlanic 0:fbdae7e6d805 388 #define FSL_FEATURE_SOC_PMC_COUNT (0)
borlanic 0:fbdae7e6d805 389 /* @brief PMU availability on the SoC. */
borlanic 0:fbdae7e6d805 390 #define FSL_FEATURE_SOC_PMU_COUNT (1)
borlanic 0:fbdae7e6d805 391 /* @brief POWERQUAD availability on the SoC. */
borlanic 0:fbdae7e6d805 392 #define FSL_FEATURE_SOC_POWERQUAD_COUNT (0)
borlanic 0:fbdae7e6d805 393 /* @brief PORT availability on the SoC. */
borlanic 0:fbdae7e6d805 394 #define FSL_FEATURE_SOC_PORT_COUNT (0)
borlanic 0:fbdae7e6d805 395 /* @brief PROP availability on the SoC. */
borlanic 0:fbdae7e6d805 396 #define FSL_FEATURE_SOC_PROP_COUNT (0)
borlanic 0:fbdae7e6d805 397 /* @brief PWM availability on the SoC. */
borlanic 0:fbdae7e6d805 398 #define FSL_FEATURE_SOC_PWM_COUNT (4)
borlanic 0:fbdae7e6d805 399 /* @brief PWT availability on the SoC. */
borlanic 0:fbdae7e6d805 400 #define FSL_FEATURE_SOC_PWT_COUNT (0)
borlanic 0:fbdae7e6d805 401 /* @brief PXP availability on the SoC. */
borlanic 0:fbdae7e6d805 402 #define FSL_FEATURE_SOC_PXP_COUNT (1)
borlanic 0:fbdae7e6d805 403 /* @brief QDDKEY availability on the SoC. */
borlanic 0:fbdae7e6d805 404 #define FSL_FEATURE_SOC_QDDKEY_COUNT (0)
borlanic 0:fbdae7e6d805 405 /* @brief QDEC availability on the SoC. */
borlanic 0:fbdae7e6d805 406 #define FSL_FEATURE_SOC_QDEC_COUNT (0)
borlanic 0:fbdae7e6d805 407 /* @brief QuadSPI availability on the SoC. */
borlanic 0:fbdae7e6d805 408 #define FSL_FEATURE_SOC_QuadSPI_COUNT (0)
borlanic 0:fbdae7e6d805 409 /* @brief RCM availability on the SoC. */
borlanic 0:fbdae7e6d805 410 #define FSL_FEATURE_SOC_RCM_COUNT (0)
borlanic 0:fbdae7e6d805 411 /* @brief RDC availability on the SoC. */
borlanic 0:fbdae7e6d805 412 #define FSL_FEATURE_SOC_RDC_COUNT (0)
borlanic 0:fbdae7e6d805 413 /* @brief RDC_SEMAPHORE availability on the SoC. */
borlanic 0:fbdae7e6d805 414 #define FSL_FEATURE_SOC_RDC_SEMAPHORE_COUNT (0)
borlanic 0:fbdae7e6d805 415 /* @brief RFSYS availability on the SoC. */
borlanic 0:fbdae7e6d805 416 #define FSL_FEATURE_SOC_RFSYS_COUNT (0)
borlanic 0:fbdae7e6d805 417 /* @brief RFVBAT availability on the SoC. */
borlanic 0:fbdae7e6d805 418 #define FSL_FEATURE_SOC_RFVBAT_COUNT (0)
borlanic 0:fbdae7e6d805 419 /* @brief RIT availability on the SoC. */
borlanic 0:fbdae7e6d805 420 #define FSL_FEATURE_SOC_RIT_COUNT (0)
borlanic 0:fbdae7e6d805 421 /* @brief RNG availability on the SoC. */
borlanic 0:fbdae7e6d805 422 #define FSL_FEATURE_SOC_RNG_COUNT (0)
borlanic 0:fbdae7e6d805 423 /* @brief RNGB availability on the SoC. */
borlanic 0:fbdae7e6d805 424 #define FSL_FEATURE_SOC_RNGB_COUNT (0)
borlanic 0:fbdae7e6d805 425 /* @brief ROM availability on the SoC. */
borlanic 0:fbdae7e6d805 426 #define FSL_FEATURE_SOC_ROM_COUNT (0)
borlanic 0:fbdae7e6d805 427 /* @brief ROMC availability on the SoC. */
borlanic 0:fbdae7e6d805 428 #define FSL_FEATURE_SOC_ROMC_COUNT (1)
borlanic 0:fbdae7e6d805 429 /* @brief RSIM availability on the SoC. */
borlanic 0:fbdae7e6d805 430 #define FSL_FEATURE_SOC_RSIM_COUNT (0)
borlanic 0:fbdae7e6d805 431 /* @brief RSTCTL0 availability on the SoC. */
borlanic 0:fbdae7e6d805 432 #define FSL_FEATURE_SOC_RSTCTL0_COUNT (0)
borlanic 0:fbdae7e6d805 433 /* @brief RSTCTL1 availability on the SoC. */
borlanic 0:fbdae7e6d805 434 #define FSL_FEATURE_SOC_RSTCTL1_COUNT (0)
borlanic 0:fbdae7e6d805 435 /* @brief RTC availability on the SoC. */
borlanic 0:fbdae7e6d805 436 #define FSL_FEATURE_SOC_RTC_COUNT (0)
borlanic 0:fbdae7e6d805 437 /* @brief SCG availability on the SoC. */
borlanic 0:fbdae7e6d805 438 #define FSL_FEATURE_SOC_SCG_COUNT (0)
borlanic 0:fbdae7e6d805 439 /* @brief SCI availability on the SoC. */
borlanic 0:fbdae7e6d805 440 #define FSL_FEATURE_SOC_SCI_COUNT (0)
borlanic 0:fbdae7e6d805 441 /* @brief SCT availability on the SoC. */
borlanic 0:fbdae7e6d805 442 #define FSL_FEATURE_SOC_SCT_COUNT (0)
borlanic 0:fbdae7e6d805 443 /* @brief SDHC availability on the SoC. */
borlanic 0:fbdae7e6d805 444 #define FSL_FEATURE_SOC_SDHC_COUNT (0)
borlanic 0:fbdae7e6d805 445 /* @brief SDIF availability on the SoC. */
borlanic 0:fbdae7e6d805 446 #define FSL_FEATURE_SOC_SDIF_COUNT (0)
borlanic 0:fbdae7e6d805 447 /* @brief SDIO availability on the SoC. */
borlanic 0:fbdae7e6d805 448 #define FSL_FEATURE_SOC_SDIO_COUNT (0)
borlanic 0:fbdae7e6d805 449 /* @brief SDMA availability on the SoC. */
borlanic 0:fbdae7e6d805 450 #define FSL_FEATURE_SOC_SDMA_COUNT (0)
borlanic 0:fbdae7e6d805 451 /* @brief SDMAARM availability on the SoC. */
borlanic 0:fbdae7e6d805 452 #define FSL_FEATURE_SOC_SDMAARM_COUNT (0)
borlanic 0:fbdae7e6d805 453 /* @brief SDMABP availability on the SoC. */
borlanic 0:fbdae7e6d805 454 #define FSL_FEATURE_SOC_SDMABP_COUNT (0)
borlanic 0:fbdae7e6d805 455 /* @brief SDMACORE availability on the SoC. */
borlanic 0:fbdae7e6d805 456 #define FSL_FEATURE_SOC_SDMACORE_COUNT (0)
borlanic 0:fbdae7e6d805 457 /* @brief SDMCORE availability on the SoC. */
borlanic 0:fbdae7e6d805 458 #define FSL_FEATURE_SOC_SDMCORE_COUNT (0)
borlanic 0:fbdae7e6d805 459 /* @brief SDRAM availability on the SoC. */
borlanic 0:fbdae7e6d805 460 #define FSL_FEATURE_SOC_SDRAM_COUNT (0)
borlanic 0:fbdae7e6d805 461 /* @brief SEMA4 availability on the SoC. */
borlanic 0:fbdae7e6d805 462 #define FSL_FEATURE_SOC_SEMA4_COUNT (0)
borlanic 0:fbdae7e6d805 463 /* @brief SEMA42 availability on the SoC. */
borlanic 0:fbdae7e6d805 464 #define FSL_FEATURE_SOC_SEMA42_COUNT (0)
borlanic 0:fbdae7e6d805 465 /* @brief SEMC availability on the SoC. */
borlanic 0:fbdae7e6d805 466 #define FSL_FEATURE_SOC_SEMC_COUNT (1)
borlanic 0:fbdae7e6d805 467 /* @brief SHA availability on the SoC. */
borlanic 0:fbdae7e6d805 468 #define FSL_FEATURE_SOC_SHA_COUNT (0)
borlanic 0:fbdae7e6d805 469 /* @brief SIM availability on the SoC. */
borlanic 0:fbdae7e6d805 470 #define FSL_FEATURE_SOC_SIM_COUNT (0)
borlanic 0:fbdae7e6d805 471 /* @brief SJC availability on the SoC. */
borlanic 0:fbdae7e6d805 472 #define FSL_FEATURE_SOC_SJC_COUNT (0)
borlanic 0:fbdae7e6d805 473 /* @brief SLCD availability on the SoC. */
borlanic 0:fbdae7e6d805 474 #define FSL_FEATURE_SOC_SLCD_COUNT (0)
borlanic 0:fbdae7e6d805 475 /* @brief SMARTCARD availability on the SoC. */
borlanic 0:fbdae7e6d805 476 #define FSL_FEATURE_SOC_SMARTCARD_COUNT (0)
borlanic 0:fbdae7e6d805 477 /* @brief SMC availability on the SoC. */
borlanic 0:fbdae7e6d805 478 #define FSL_FEATURE_SOC_SMC_COUNT (0)
borlanic 0:fbdae7e6d805 479 /* @brief SNVS availability on the SoC. */
borlanic 0:fbdae7e6d805 480 #define FSL_FEATURE_SOC_SNVS_COUNT (1)
borlanic 0:fbdae7e6d805 481 /* @brief SPBA availability on the SoC. */
borlanic 0:fbdae7e6d805 482 #define FSL_FEATURE_SOC_SPBA_COUNT (0)
borlanic 0:fbdae7e6d805 483 /* @brief SPDIF availability on the SoC. */
borlanic 0:fbdae7e6d805 484 #define FSL_FEATURE_SOC_SPDIF_COUNT (1)
borlanic 0:fbdae7e6d805 485 /* @brief SPI availability on the SoC. */
borlanic 0:fbdae7e6d805 486 #define FSL_FEATURE_SOC_SPI_COUNT (0)
borlanic 0:fbdae7e6d805 487 /* @brief SPIFI availability on the SoC. */
borlanic 0:fbdae7e6d805 488 #define FSL_FEATURE_SOC_SPIFI_COUNT (0)
borlanic 0:fbdae7e6d805 489 /* @brief SPM availability on the SoC. */
borlanic 0:fbdae7e6d805 490 #define FSL_FEATURE_SOC_SPM_COUNT (0)
borlanic 0:fbdae7e6d805 491 /* @brief SRC availability on the SoC. */
borlanic 0:fbdae7e6d805 492 #define FSL_FEATURE_SOC_SRC_COUNT (1)
borlanic 0:fbdae7e6d805 493 /* @brief SYSCON availability on the SoC. */
borlanic 0:fbdae7e6d805 494 #define FSL_FEATURE_SOC_SYSCON_COUNT (0)
borlanic 0:fbdae7e6d805 495 /* @brief SYSCTL0 availability on the SoC. */
borlanic 0:fbdae7e6d805 496 #define FSL_FEATURE_SOC_SYSCTL0_COUNT (0)
borlanic 0:fbdae7e6d805 497 /* @brief SYSCTL1 availability on the SoC. */
borlanic 0:fbdae7e6d805 498 #define FSL_FEATURE_SOC_SYSCTL1_COUNT (0)
borlanic 0:fbdae7e6d805 499 /* @brief TEMPMON availability on the SoC. */
borlanic 0:fbdae7e6d805 500 #define FSL_FEATURE_SOC_TEMPMON_COUNT (1)
borlanic 0:fbdae7e6d805 501 /* @brief TMR availability on the SoC. */
borlanic 0:fbdae7e6d805 502 #define FSL_FEATURE_SOC_TMR_COUNT (4)
borlanic 0:fbdae7e6d805 503 /* @brief TPM availability on the SoC. */
borlanic 0:fbdae7e6d805 504 #define FSL_FEATURE_SOC_TPM_COUNT (0)
borlanic 0:fbdae7e6d805 505 /* @brief TRGMUX availability on the SoC. */
borlanic 0:fbdae7e6d805 506 #define FSL_FEATURE_SOC_TRGMUX_COUNT (0)
borlanic 0:fbdae7e6d805 507 /* @brief TRIAMP availability on the SoC. */
borlanic 0:fbdae7e6d805 508 #define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
borlanic 0:fbdae7e6d805 509 /* @brief TRNG availability on the SoC. */
borlanic 0:fbdae7e6d805 510 #define FSL_FEATURE_SOC_TRNG_COUNT (1)
borlanic 0:fbdae7e6d805 511 /* @brief TSC availability on the SoC. */
borlanic 0:fbdae7e6d805 512 #define FSL_FEATURE_SOC_TSC_COUNT (1)
borlanic 0:fbdae7e6d805 513 /* @brief TSI availability on the SoC. */
borlanic 0:fbdae7e6d805 514 #define FSL_FEATURE_SOC_TSI_COUNT (0)
borlanic 0:fbdae7e6d805 515 /* @brief TSTMR availability on the SoC. */
borlanic 0:fbdae7e6d805 516 #define FSL_FEATURE_SOC_TSTMR_COUNT (0)
borlanic 0:fbdae7e6d805 517 /* @brief UART availability on the SoC. */
borlanic 0:fbdae7e6d805 518 #define FSL_FEATURE_SOC_UART_COUNT (0)
borlanic 0:fbdae7e6d805 519 /* @brief USART availability on the SoC. */
borlanic 0:fbdae7e6d805 520 #define FSL_FEATURE_SOC_USART_COUNT (0)
borlanic 0:fbdae7e6d805 521 /* @brief USB availability on the SoC. */
borlanic 0:fbdae7e6d805 522 #define FSL_FEATURE_SOC_USB_COUNT (0)
borlanic 0:fbdae7e6d805 523 /* @brief USBHS availability on the SoC. */
borlanic 0:fbdae7e6d805 524 #define FSL_FEATURE_SOC_USBHS_COUNT (2)
borlanic 0:fbdae7e6d805 525 /* @brief USBDCD availability on the SoC. */
borlanic 0:fbdae7e6d805 526 #define FSL_FEATURE_SOC_USBDCD_COUNT (0)
borlanic 0:fbdae7e6d805 527 /* @brief USBFSH availability on the SoC. */
borlanic 0:fbdae7e6d805 528 #define FSL_FEATURE_SOC_USBFSH_COUNT (0)
borlanic 0:fbdae7e6d805 529 /* @brief USBHSD availability on the SoC. */
borlanic 0:fbdae7e6d805 530 #define FSL_FEATURE_SOC_USBHSD_COUNT (0)
borlanic 0:fbdae7e6d805 531 /* @brief USBHSDCD availability on the SoC. */
borlanic 0:fbdae7e6d805 532 #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
borlanic 0:fbdae7e6d805 533 /* @brief USBHSH availability on the SoC. */
borlanic 0:fbdae7e6d805 534 #define FSL_FEATURE_SOC_USBHSH_COUNT (0)
borlanic 0:fbdae7e6d805 535 /* @brief USBNC availability on the SoC. */
borlanic 0:fbdae7e6d805 536 #define FSL_FEATURE_SOC_USBNC_COUNT (2)
borlanic 0:fbdae7e6d805 537 /* @brief USBPHY availability on the SoC. */
borlanic 0:fbdae7e6d805 538 #define FSL_FEATURE_SOC_USBPHY_COUNT (2)
borlanic 0:fbdae7e6d805 539 /* @brief USB_HSIC availability on the SoC. */
borlanic 0:fbdae7e6d805 540 #define FSL_FEATURE_SOC_USB_HSIC_COUNT (0)
borlanic 0:fbdae7e6d805 541 /* @brief USB_OTG availability on the SoC. */
borlanic 0:fbdae7e6d805 542 #define FSL_FEATURE_SOC_USB_OTG_COUNT (0)
borlanic 0:fbdae7e6d805 543 /* @brief USBVREG availability on the SoC. */
borlanic 0:fbdae7e6d805 544 #define FSL_FEATURE_SOC_USBVREG_COUNT (0)
borlanic 0:fbdae7e6d805 545 /* @brief USDHC availability on the SoC. */
borlanic 0:fbdae7e6d805 546 #define FSL_FEATURE_SOC_USDHC_COUNT (2)
borlanic 0:fbdae7e6d805 547 /* @brief UTICK availability on the SoC. */
borlanic 0:fbdae7e6d805 548 #define FSL_FEATURE_SOC_UTICK_COUNT (0)
borlanic 0:fbdae7e6d805 549 /* @brief VIU availability on the SoC. */
borlanic 0:fbdae7e6d805 550 #define FSL_FEATURE_SOC_VIU_COUNT (0)
borlanic 0:fbdae7e6d805 551 /* @brief VREF availability on the SoC. */
borlanic 0:fbdae7e6d805 552 #define FSL_FEATURE_SOC_VREF_COUNT (0)
borlanic 0:fbdae7e6d805 553 /* @brief VFIFO availability on the SoC. */
borlanic 0:fbdae7e6d805 554 #define FSL_FEATURE_SOC_VFIFO_COUNT (0)
borlanic 0:fbdae7e6d805 555 /* @brief WDOG availability on the SoC. */
borlanic 0:fbdae7e6d805 556 #define FSL_FEATURE_SOC_WDOG_COUNT (2)
borlanic 0:fbdae7e6d805 557 /* @brief WKPU availability on the SoC. */
borlanic 0:fbdae7e6d805 558 #define FSL_FEATURE_SOC_WKPU_COUNT (0)
borlanic 0:fbdae7e6d805 559 /* @brief WWDT availability on the SoC. */
borlanic 0:fbdae7e6d805 560 #define FSL_FEATURE_SOC_WWDT_COUNT (0)
borlanic 0:fbdae7e6d805 561 /* @brief XBAR availability on the SoC. */
borlanic 0:fbdae7e6d805 562 #define FSL_FEATURE_SOC_XBAR_COUNT (0)
borlanic 0:fbdae7e6d805 563 /* @brief XBARA availability on the SoC. */
borlanic 0:fbdae7e6d805 564 #define FSL_FEATURE_SOC_XBARA_COUNT (1)
borlanic 0:fbdae7e6d805 565 /* @brief XBARB availability on the SoC. */
borlanic 0:fbdae7e6d805 566 #define FSL_FEATURE_SOC_XBARB_COUNT (2)
borlanic 0:fbdae7e6d805 567 /* @brief XCVR availability on the SoC. */
borlanic 0:fbdae7e6d805 568 #define FSL_FEATURE_SOC_XCVR_COUNT (0)
borlanic 0:fbdae7e6d805 569 /* @brief XRDC availability on the SoC. */
borlanic 0:fbdae7e6d805 570 #define FSL_FEATURE_SOC_XRDC_COUNT (0)
borlanic 0:fbdae7e6d805 571 /* @brief XTALOSC availability on the SoC. */
borlanic 0:fbdae7e6d805 572 #define FSL_FEATURE_SOC_XTALOSC_COUNT (0)
borlanic 0:fbdae7e6d805 573 /* @brief XTALOSC24M availability on the SoC. */
borlanic 0:fbdae7e6d805 574 #define FSL_FEATURE_SOC_XTALOSC24M_COUNT (1)
borlanic 0:fbdae7e6d805 575 /* @brief ZLL availability on the SoC. */
borlanic 0:fbdae7e6d805 576 #define FSL_FEATURE_SOC_ZLL_COUNT (0)
borlanic 0:fbdae7e6d805 577
borlanic 0:fbdae7e6d805 578 /* ADC module features */
borlanic 0:fbdae7e6d805 579
borlanic 0:fbdae7e6d805 580 /* @brief Remove Hardware Trigger feature. */
borlanic 0:fbdae7e6d805 581 #define FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE (0)
borlanic 0:fbdae7e6d805 582 /* @brief Remove ALT Clock selection feature. */
borlanic 0:fbdae7e6d805 583 #define FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE (1)
borlanic 0:fbdae7e6d805 584
borlanic 0:fbdae7e6d805 585 /* AOI module features */
borlanic 0:fbdae7e6d805 586
borlanic 0:fbdae7e6d805 587 /* @brief Maximum value of input mux. */
borlanic 0:fbdae7e6d805 588 #define FSL_FEATURE_AOI_MODULE_INPUTS (4)
borlanic 0:fbdae7e6d805 589 /* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */
borlanic 0:fbdae7e6d805 590 #define FSL_FEATURE_AOI_EVENT_COUNT (4)
borlanic 0:fbdae7e6d805 591
borlanic 0:fbdae7e6d805 592 /* FLEXCAN module features */
borlanic 0:fbdae7e6d805 593
borlanic 0:fbdae7e6d805 594 /* @brief Message buffer size */
borlanic 0:fbdae7e6d805 595 #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (64)
borlanic 0:fbdae7e6d805 596 /* @brief Has doze mode support (register bit field MCR[DOZE]). */
borlanic 0:fbdae7e6d805 597 #define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0)
borlanic 0:fbdae7e6d805 598 /* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */
borlanic 0:fbdae7e6d805 599 #define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1)
borlanic 0:fbdae7e6d805 600 /* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */
borlanic 0:fbdae7e6d805 601 #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (1)
borlanic 0:fbdae7e6d805 602 /* @brief Has extended bit timing register (register CBT). */
borlanic 0:fbdae7e6d805 603 #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0)
borlanic 0:fbdae7e6d805 604 /* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */
borlanic 0:fbdae7e6d805 605 #define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0)
borlanic 0:fbdae7e6d805 606 /* @brief Remove CAN Engine Clock Source Selection from unsupported part. */
borlanic 0:fbdae7e6d805 607 #define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1)
borlanic 0:fbdae7e6d805 608 /* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */
borlanic 0:fbdae7e6d805 609 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0)
borlanic 0:fbdae7e6d805 610 /* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */
borlanic 0:fbdae7e6d805 611 #define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (0)
borlanic 0:fbdae7e6d805 612 /* @brief Has extra MB interrupt or common one. */
borlanic 0:fbdae7e6d805 613 #define FSL_FEATURE_FLEXCAN_HAS_EXTRA_MB_INT (1)
borlanic 0:fbdae7e6d805 614
borlanic 0:fbdae7e6d805 615 /* CMP module features */
borlanic 0:fbdae7e6d805 616
borlanic 0:fbdae7e6d805 617 /* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
borlanic 0:fbdae7e6d805 618 #define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (0)
borlanic 0:fbdae7e6d805 619 /* @brief Has Window mode in CMP (register bit field CR1[WE]). */
borlanic 0:fbdae7e6d805 620 #define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1)
borlanic 0:fbdae7e6d805 621 /* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
borlanic 0:fbdae7e6d805 622 #define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1)
borlanic 0:fbdae7e6d805 623 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
borlanic 0:fbdae7e6d805 624 #define FSL_FEATURE_CMP_HAS_DMA (1)
borlanic 0:fbdae7e6d805 625 /* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
borlanic 0:fbdae7e6d805 626 #define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0)
borlanic 0:fbdae7e6d805 627 /* @brief Has DAC Test function in CMP (register DACTEST). */
borlanic 0:fbdae7e6d805 628 #define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
borlanic 0:fbdae7e6d805 629
borlanic 0:fbdae7e6d805 630 /* EDMA module features */
borlanic 0:fbdae7e6d805 631
borlanic 0:fbdae7e6d805 632 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
borlanic 0:fbdae7e6d805 633 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (32)
borlanic 0:fbdae7e6d805 634 /* @brief Total number of DMA channels on all modules. */
borlanic 0:fbdae7e6d805 635 #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (32)
borlanic 0:fbdae7e6d805 636 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
borlanic 0:fbdae7e6d805 637 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
borlanic 0:fbdae7e6d805 638 /* @brief Has DMA_Error interrupt vector. */
borlanic 0:fbdae7e6d805 639 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1)
borlanic 0:fbdae7e6d805 640 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
borlanic 0:fbdae7e6d805 641 #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32)
borlanic 0:fbdae7e6d805 642
borlanic 0:fbdae7e6d805 643 /* DMAMUX module features */
borlanic 0:fbdae7e6d805 644
borlanic 0:fbdae7e6d805 645 /* @brief Number of DMA channels (related to number of register CHCFGn). */
borlanic 0:fbdae7e6d805 646 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (32)
borlanic 0:fbdae7e6d805 647 /* @brief Total number of DMA channels on all modules. */
borlanic 0:fbdae7e6d805 648 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 32)
borlanic 0:fbdae7e6d805 649 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
borlanic 0:fbdae7e6d805 650 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
borlanic 0:fbdae7e6d805 651 /* @brief Has DMA Channel Always ON function (register bit CHCFG0[A_ON]). */
borlanic 0:fbdae7e6d805 652 #define FSL_FEATURE_DMAMUX_HAS_A_ON (1)
borlanic 0:fbdae7e6d805 653
borlanic 0:fbdae7e6d805 654 /* ENET module features */
borlanic 0:fbdae7e6d805 655
borlanic 0:fbdae7e6d805 656 /* @brief Support Interrupt Coalesce */
borlanic 0:fbdae7e6d805 657 #define FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE (1)
borlanic 0:fbdae7e6d805 658 /* @brief Queue Size. */
borlanic 0:fbdae7e6d805 659 #define FSL_FEATURE_ENET_QUEUE (1)
borlanic 0:fbdae7e6d805 660 /* @brief Has AVB Support. */
borlanic 0:fbdae7e6d805 661 #define FSL_FEATURE_ENET_HAS_AVB (0)
borlanic 0:fbdae7e6d805 662 /* @brief Has Timer Pulse Width control. */
borlanic 0:fbdae7e6d805 663 #define FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL (1)
borlanic 0:fbdae7e6d805 664 /* @brief Has Extend MDIO Support. */
borlanic 0:fbdae7e6d805 665 #define FSL_FEATURE_ENET_HAS_EXTEND_MDIO (1)
borlanic 0:fbdae7e6d805 666 /* @brief Has Additional 1588 Timer Channel Interrupt. */
borlanic 0:fbdae7e6d805 667 #define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (0)
borlanic 0:fbdae7e6d805 668
borlanic 0:fbdae7e6d805 669 /* FLEXRAM module features */
borlanic 0:fbdae7e6d805 670
borlanic 0:fbdae7e6d805 671 /* @brief Bank size */
borlanic 0:fbdae7e6d805 672 #define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32 * 1024)
borlanic 0:fbdae7e6d805 673 /* @brief Total Bank numbers */
borlanic 0:fbdae7e6d805 674 #define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS (16)
borlanic 0:fbdae7e6d805 675
borlanic 0:fbdae7e6d805 676 /* FLEXSPI module features */
borlanic 0:fbdae7e6d805 677
borlanic 0:fbdae7e6d805 678 /* @brief FlexSPI AHB buffer count */
borlanic 0:fbdae7e6d805 679 #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (4)
borlanic 0:fbdae7e6d805 680 /* @brief FlexSPI has no data learn. */
borlanic 0:fbdae7e6d805 681 #define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (1)
borlanic 0:fbdae7e6d805 682
borlanic 0:fbdae7e6d805 683 /* GPC module features */
borlanic 0:fbdae7e6d805 684
borlanic 0:fbdae7e6d805 685 /* @brief Has DVFS0 Change Request. */
borlanic 0:fbdae7e6d805 686 #define FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR (0)
borlanic 0:fbdae7e6d805 687 /* @brief Has GPC interrupt/event masking. */
borlanic 0:fbdae7e6d805 688 #define FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM (0)
borlanic 0:fbdae7e6d805 689 /* @brief Has L2 cache power control. */
borlanic 0:fbdae7e6d805 690 #define FSL_FEATURE_GPC_HAS_CNTR_L2PGE (0)
borlanic 0:fbdae7e6d805 691 /* @brief Has FLEXRAM PDRAM0(bank1-7) power control. */
borlanic 0:fbdae7e6d805 692 #define FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE (1)
borlanic 0:fbdae7e6d805 693 /* @brief Has VADC power control. */
borlanic 0:fbdae7e6d805 694 #define FSL_FEATURE_GPC_HAS_CNTR_VADC (0)
borlanic 0:fbdae7e6d805 695 /* @brief Has Display power control. */
borlanic 0:fbdae7e6d805 696 #define FSL_FEATURE_GPC_HAS_CNTR_DISPLAY (0)
borlanic 0:fbdae7e6d805 697 /* @brief Supports IRQ 0-31. */
borlanic 0:fbdae7e6d805 698 #define FSL_FEATURE_GPC_HAS_IRQ_0_31 (1)
borlanic 0:fbdae7e6d805 699
borlanic 0:fbdae7e6d805 700 /* LCDIF module features */
borlanic 0:fbdae7e6d805 701
borlanic 0:fbdae7e6d805 702 /* @brief LCDIF does not support alpha support. */
borlanic 0:fbdae7e6d805 703 #define FSL_FEATURE_LCDIF_HAS_NO_AS (1)
borlanic 0:fbdae7e6d805 704 /* @brief LCDIF does not support output reset pin to LCD panel. */
borlanic 0:fbdae7e6d805 705 #define FSL_FEATURE_LCDIF_HAS_NO_RESET_PIN (1)
borlanic 0:fbdae7e6d805 706 /* @brief LCDIF supports LUT. */
borlanic 0:fbdae7e6d805 707 #define FSL_FEATURE_LCDIF_HAS_LUT (1)
borlanic 0:fbdae7e6d805 708
borlanic 0:fbdae7e6d805 709 /* LPI2C module features */
borlanic 0:fbdae7e6d805 710
borlanic 0:fbdae7e6d805 711 /* @brief Has separate DMA RX and TX requests. */
borlanic 0:fbdae7e6d805 712 #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0)
borlanic 0:fbdae7e6d805 713 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
borlanic 0:fbdae7e6d805 714 #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4)
borlanic 0:fbdae7e6d805 715
borlanic 0:fbdae7e6d805 716 /* LPSPI module features */
borlanic 0:fbdae7e6d805 717
borlanic 0:fbdae7e6d805 718 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
borlanic 0:fbdae7e6d805 719 #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (16)
borlanic 0:fbdae7e6d805 720 /* @brief Has separate DMA RX and TX requests. */
borlanic 0:fbdae7e6d805 721 #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
borlanic 0:fbdae7e6d805 722
borlanic 0:fbdae7e6d805 723 /* LPUART module features */
borlanic 0:fbdae7e6d805 724
borlanic 0:fbdae7e6d805 725 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
borlanic 0:fbdae7e6d805 726 #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
borlanic 0:fbdae7e6d805 727 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
borlanic 0:fbdae7e6d805 728 #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
borlanic 0:fbdae7e6d805 729 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
borlanic 0:fbdae7e6d805 730 #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
borlanic 0:fbdae7e6d805 731 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
borlanic 0:fbdae7e6d805 732 #define FSL_FEATURE_LPUART_HAS_FIFO (1)
borlanic 0:fbdae7e6d805 733 /* @brief Has 32-bit register MODIR */
borlanic 0:fbdae7e6d805 734 #define FSL_FEATURE_LPUART_HAS_MODIR (1)
borlanic 0:fbdae7e6d805 735 /* @brief Hardware flow control (RTS, CTS) is supported. */
borlanic 0:fbdae7e6d805 736 #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
borlanic 0:fbdae7e6d805 737 /* @brief Infrared (modulation) is supported. */
borlanic 0:fbdae7e6d805 738 #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1)
borlanic 0:fbdae7e6d805 739 /* @brief 2 bits long stop bit is available. */
borlanic 0:fbdae7e6d805 740 #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
borlanic 0:fbdae7e6d805 741 /* @brief If 10-bit mode is supported. */
borlanic 0:fbdae7e6d805 742 #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
borlanic 0:fbdae7e6d805 743 /* @brief If 7-bit mode is supported. */
borlanic 0:fbdae7e6d805 744 #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1)
borlanic 0:fbdae7e6d805 745 /* @brief Baud rate fine adjustment is available. */
borlanic 0:fbdae7e6d805 746 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
borlanic 0:fbdae7e6d805 747 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
borlanic 0:fbdae7e6d805 748 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
borlanic 0:fbdae7e6d805 749 /* @brief Baud rate oversampling is available. */
borlanic 0:fbdae7e6d805 750 #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
borlanic 0:fbdae7e6d805 751 /* @brief Baud rate oversampling is available. */
borlanic 0:fbdae7e6d805 752 #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
borlanic 0:fbdae7e6d805 753 /* @brief Peripheral type. */
borlanic 0:fbdae7e6d805 754 #define FSL_FEATURE_LPUART_IS_SCI (1)
borlanic 0:fbdae7e6d805 755 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
borlanic 0:fbdae7e6d805 756 #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4)
borlanic 0:fbdae7e6d805 757 /* @brief Maximal data width without parity bit. */
borlanic 0:fbdae7e6d805 758 #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10)
borlanic 0:fbdae7e6d805 759 /* @brief Maximal data width with parity bit. */
borlanic 0:fbdae7e6d805 760 #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9)
borlanic 0:fbdae7e6d805 761 /* @brief Supports two match addresses to filter incoming frames. */
borlanic 0:fbdae7e6d805 762 #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
borlanic 0:fbdae7e6d805 763 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
borlanic 0:fbdae7e6d805 764 #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
borlanic 0:fbdae7e6d805 765 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
borlanic 0:fbdae7e6d805 766 #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
borlanic 0:fbdae7e6d805 767 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
borlanic 0:fbdae7e6d805 768 #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
borlanic 0:fbdae7e6d805 769 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
borlanic 0:fbdae7e6d805 770 #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
borlanic 0:fbdae7e6d805 771 /* @brief Has improved smart card (ISO7816 protocol) support. */
borlanic 0:fbdae7e6d805 772 #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
borlanic 0:fbdae7e6d805 773 /* @brief Has local operation network (CEA709.1-B protocol) support. */
borlanic 0:fbdae7e6d805 774 #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
borlanic 0:fbdae7e6d805 775 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
borlanic 0:fbdae7e6d805 776 #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
borlanic 0:fbdae7e6d805 777 /* @brief Lin break detect available (has bit BAUD[LBKDIE]). */
borlanic 0:fbdae7e6d805 778 #define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1)
borlanic 0:fbdae7e6d805 779 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
borlanic 0:fbdae7e6d805 780 #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
borlanic 0:fbdae7e6d805 781 /* @brief Has separate DMA RX and TX requests. */
borlanic 0:fbdae7e6d805 782 #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
borlanic 0:fbdae7e6d805 783 /* @brief Has separate RX and TX interrupts. */
borlanic 0:fbdae7e6d805 784 #define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0)
borlanic 0:fbdae7e6d805 785 /* @brief Has LPAURT_PARAM. */
borlanic 0:fbdae7e6d805 786 #define FSL_FEATURE_LPUART_HAS_PARAM (1)
borlanic 0:fbdae7e6d805 787 /* @brief Has LPUART_VERID. */
borlanic 0:fbdae7e6d805 788 #define FSL_FEATURE_LPUART_HAS_VERID (1)
borlanic 0:fbdae7e6d805 789 /* @brief Has LPUART_GLOBAL. */
borlanic 0:fbdae7e6d805 790 #define FSL_FEATURE_LPUART_HAS_GLOBAL (1)
borlanic 0:fbdae7e6d805 791 /* @brief Has LPUART_PINCFG. */
borlanic 0:fbdae7e6d805 792 #define FSL_FEATURE_LPUART_HAS_PINCFG (1)
borlanic 0:fbdae7e6d805 793
borlanic 0:fbdae7e6d805 794 /* interrupt module features */
borlanic 0:fbdae7e6d805 795
borlanic 0:fbdae7e6d805 796 /* @brief Lowest interrupt request number. */
borlanic 0:fbdae7e6d805 797 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
borlanic 0:fbdae7e6d805 798 /* @brief Highest interrupt request number. */
borlanic 0:fbdae7e6d805 799 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (159)
borlanic 0:fbdae7e6d805 800
borlanic 0:fbdae7e6d805 801 /* OCOTP module features */
borlanic 0:fbdae7e6d805 802
borlanic 0:fbdae7e6d805 803 /* No feature definitions */
borlanic 0:fbdae7e6d805 804
borlanic 0:fbdae7e6d805 805 /* PIT module features */
borlanic 0:fbdae7e6d805 806
borlanic 0:fbdae7e6d805 807 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
borlanic 0:fbdae7e6d805 808 #define FSL_FEATURE_PIT_TIMER_COUNT (4)
borlanic 0:fbdae7e6d805 809 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
borlanic 0:fbdae7e6d805 810 #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1)
borlanic 0:fbdae7e6d805 811 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
borlanic 0:fbdae7e6d805 812 #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
borlanic 0:fbdae7e6d805 813 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
borlanic 0:fbdae7e6d805 814 #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1)
borlanic 0:fbdae7e6d805 815 /* @brief Has timer enable control. */
borlanic 0:fbdae7e6d805 816 #define FSL_FEATURE_PIT_HAS_MDIS (1)
borlanic 0:fbdae7e6d805 817
borlanic 0:fbdae7e6d805 818 /* PMU module features */
borlanic 0:fbdae7e6d805 819
borlanic 0:fbdae7e6d805 820 /* @brief PMU supports lower power control. */
borlanic 0:fbdae7e6d805 821 #define FSL_FEATURE_PMU_HAS_LOWPWR_CTRL (0)
borlanic 0:fbdae7e6d805 822
borlanic 0:fbdae7e6d805 823 /* PWM module features */
borlanic 0:fbdae7e6d805 824
borlanic 0:fbdae7e6d805 825 /* @brief Number of each EflexPWM module channels (outputs). */
borlanic 0:fbdae7e6d805 826 #define FSL_FEATURE_PWM_CHANNEL_COUNT (12U)
borlanic 0:fbdae7e6d805 827 /* @brief Number of EflexPWM module A channels (outputs). */
borlanic 0:fbdae7e6d805 828 #define FSL_FEATURE_PWM_CHANNELA_COUNT (4U)
borlanic 0:fbdae7e6d805 829 /* @brief Number of EflexPWM module B channels (outputs). */
borlanic 0:fbdae7e6d805 830 #define FSL_FEATURE_PWM_CHANNELB_COUNT (4U)
borlanic 0:fbdae7e6d805 831 /* @brief Number of EflexPWM module X channels (outputs). */
borlanic 0:fbdae7e6d805 832 #define FSL_FEATURE_PWM_CHANNELX_COUNT (4U)
borlanic 0:fbdae7e6d805 833 /* @brief Number of each EflexPWM module compare channels interrupts. */
borlanic 0:fbdae7e6d805 834 #define FSL_FEATURE_PWM_CMP_INT_HANDLER_COUNT (4U)
borlanic 0:fbdae7e6d805 835 /* @brief Number of each EflexPWM module reload channels interrupts. */
borlanic 0:fbdae7e6d805 836 #define FSL_FEATURE_PWM_RELOAD_INT_HANDLER_COUNT (4U)
borlanic 0:fbdae7e6d805 837 /* @brief Number of each EflexPWM module capture channels interrupts. */
borlanic 0:fbdae7e6d805 838 #define FSL_FEATURE_PWM_CAP_INT_HANDLER_COUNT (1U)
borlanic 0:fbdae7e6d805 839 /* @brief Number of each EflexPWM module reload error channels interrupts. */
borlanic 0:fbdae7e6d805 840 #define FSL_FEATURE_PWM_RERR_INT_HANDLER_COUNT (1U)
borlanic 0:fbdae7e6d805 841 /* @brief Number of each EflexPWM module fault channels interrupts. */
borlanic 0:fbdae7e6d805 842 #define FSL_FEATURE_PWM_FAULT_INT_HANDLER_COUNT (1U)
borlanic 0:fbdae7e6d805 843 /* @brief Number of submodules in each EflexPWM module. */
borlanic 0:fbdae7e6d805 844 #define FSL_FEATURE_PWM_SUBMODULE_COUNT (4U)
borlanic 0:fbdae7e6d805 845
borlanic 0:fbdae7e6d805 846 /* PXP module features */
borlanic 0:fbdae7e6d805 847
borlanic 0:fbdae7e6d805 848 /* @brief PXP module has dither engine. */
borlanic 0:fbdae7e6d805 849 #define FSL_FEATURE_PXP_HAS_DITHER (0)
borlanic 0:fbdae7e6d805 850 /* @brief PXP module supports repeat run */
borlanic 0:fbdae7e6d805 851 #define FSL_FEATURE_PXP_HAS_EN_REPEAT (1)
borlanic 0:fbdae7e6d805 852 /* @brief PXP doesn't have CSC */
borlanic 0:fbdae7e6d805 853 #define FSL_FEATURE_PXP_HAS_NO_CSC2 (1)
borlanic 0:fbdae7e6d805 854 /* @brief PXP doesn't have LUT */
borlanic 0:fbdae7e6d805 855 #define FSL_FEATURE_PXP_HAS_NO_LUT (1)
borlanic 0:fbdae7e6d805 856
borlanic 0:fbdae7e6d805 857 /* RTWDOG module features */
borlanic 0:fbdae7e6d805 858
borlanic 0:fbdae7e6d805 859 /* @brief Watchdog is available. */
borlanic 0:fbdae7e6d805 860 #define FSL_FEATURE_RTWDOG_HAS_WATCHDOG (1)
borlanic 0:fbdae7e6d805 861 /* @brief RTWDOG_CNT can be 32-bit written. */
borlanic 0:fbdae7e6d805 862 #define FSL_FEATURE_RTWDOG_HAS_32BIT_ACCESS (1)
borlanic 0:fbdae7e6d805 863
borlanic 0:fbdae7e6d805 864 /* SAI module features */
borlanic 0:fbdae7e6d805 865
borlanic 0:fbdae7e6d805 866 /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
borlanic 0:fbdae7e6d805 867 #define FSL_FEATURE_SAI_FIFO_COUNT (32)
borlanic 0:fbdae7e6d805 868 /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
borlanic 0:fbdae7e6d805 869 #define FSL_FEATURE_SAI_CHANNEL_COUNT (4)
borlanic 0:fbdae7e6d805 870 /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
borlanic 0:fbdae7e6d805 871 #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32)
borlanic 0:fbdae7e6d805 872 /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
borlanic 0:fbdae7e6d805 873 #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1)
borlanic 0:fbdae7e6d805 874 /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
borlanic 0:fbdae7e6d805 875 #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1)
borlanic 0:fbdae7e6d805 876 /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
borlanic 0:fbdae7e6d805 877 #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1)
borlanic 0:fbdae7e6d805 878 /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
borlanic 0:fbdae7e6d805 879 #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1)
borlanic 0:fbdae7e6d805 880 /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
borlanic 0:fbdae7e6d805 881 #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
borlanic 0:fbdae7e6d805 882 /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
borlanic 0:fbdae7e6d805 883 #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0)
borlanic 0:fbdae7e6d805 884 /* @brief Interrupt source number */
borlanic 0:fbdae7e6d805 885 #define FSL_FEATURE_SAI_INT_SOURCE_NUM (2)
borlanic 0:fbdae7e6d805 886 /* @brief Has register of MCR. */
borlanic 0:fbdae7e6d805 887 #define FSL_FEATURE_SAI_HAS_MCR (0)
borlanic 0:fbdae7e6d805 888 /* @brief Has register of MDR */
borlanic 0:fbdae7e6d805 889 #define FSL_FEATURE_SAI_HAS_MDR (0)
borlanic 0:fbdae7e6d805 890
borlanic 0:fbdae7e6d805 891 /* SNVS module features */
borlanic 0:fbdae7e6d805 892
borlanic 0:fbdae7e6d805 893 /* @brief Has Secure Real Time Counter Enabled and Valid (bit field LPCR[SRTC_ENV]). */
borlanic 0:fbdae7e6d805 894 #define FSL_FEATURE_SNVS_HAS_SRTC (1)
borlanic 0:fbdae7e6d805 895
borlanic 0:fbdae7e6d805 896 /* SRC module features */
borlanic 0:fbdae7e6d805 897
borlanic 0:fbdae7e6d805 898 /* @brief There is MASK_WDOG3_RST bit in SCR register. */
borlanic 0:fbdae7e6d805 899 #define FSL_FEATURE_SRC_HAS_SCR_MASK_WDOG3_RST (1)
borlanic 0:fbdae7e6d805 900 /* @brief There is MIX_RST_STRCH bit in SCR register. */
borlanic 0:fbdae7e6d805 901 #define FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH (0)
borlanic 0:fbdae7e6d805 902 /* @brief There is DBG_RST_MSK_PG bit in SCR register. */
borlanic 0:fbdae7e6d805 903 #define FSL_FEATURE_SRC_HAS_SCR_DBG_RST_MSK_PG (1)
borlanic 0:fbdae7e6d805 904 /* @brief There is WDOG3_RST_OPTN bit in SCR register. */
borlanic 0:fbdae7e6d805 905 #define FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN (0)
borlanic 0:fbdae7e6d805 906 /* @brief There is CORES_DBG_RST bit in SCR register. */
borlanic 0:fbdae7e6d805 907 #define FSL_FEATURE_SRC_HAS_SCR_CORES_DBG_RST (0)
borlanic 0:fbdae7e6d805 908 /* @brief There is MTSR bit in SCR register. */
borlanic 0:fbdae7e6d805 909 #define FSL_FEATURE_SRC_HAS_SCR_MTSR (0)
borlanic 0:fbdae7e6d805 910 /* @brief There is CORE0_DBG_RST bit in SCR register. */
borlanic 0:fbdae7e6d805 911 #define FSL_FEATURE_SRC_HAS_SCR_CORE0_DBG_RST (1)
borlanic 0:fbdae7e6d805 912 /* @brief There is CORE0_RST bit in SCR register. */
borlanic 0:fbdae7e6d805 913 #define FSL_FEATURE_SRC_HAS_SCR_CORE0_RST (1)
borlanic 0:fbdae7e6d805 914 /* @brief There is LOCKUP_RST bit in SCR register. */
borlanic 0:fbdae7e6d805 915 #define FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST (1)
borlanic 0:fbdae7e6d805 916 /* @brief There is SWRC bit in SCR register. */
borlanic 0:fbdae7e6d805 917 #define FSL_FEATURE_SRC_HAS_SCR_SWRC (0)
borlanic 0:fbdae7e6d805 918 /* @brief There is EIM_RST bit in SCR register. */
borlanic 0:fbdae7e6d805 919 #define FSL_FEATURE_SRC_HAS_SCR_EIM_RST (0)
borlanic 0:fbdae7e6d805 920 /* @brief There is LUEN bit in SCR register. */
borlanic 0:fbdae7e6d805 921 #define FSL_FEATURE_SRC_HAS_SCR_LUEN (0)
borlanic 0:fbdae7e6d805 922 /* @brief There is no WRBC bit in SCR register. */
borlanic 0:fbdae7e6d805 923 #define FSL_FEATURE_SRC_HAS_NO_SCR_WRBC (1)
borlanic 0:fbdae7e6d805 924 /* @brief There is no WRE bit in SCR register. */
borlanic 0:fbdae7e6d805 925 #define FSL_FEATURE_SRC_HAS_NO_SCR_WRE (1)
borlanic 0:fbdae7e6d805 926 /* @brief There is SISR register. */
borlanic 0:fbdae7e6d805 927 #define FSL_FEATURE_SRC_HAS_SISR (0)
borlanic 0:fbdae7e6d805 928 /* @brief There is RESET_OUT bit in SRSR register. */
borlanic 0:fbdae7e6d805 929 #define FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT (0)
borlanic 0:fbdae7e6d805 930 /* @brief There is WDOG3_RST_B bit in SRSR register. */
borlanic 0:fbdae7e6d805 931 #define FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B (1)
borlanic 0:fbdae7e6d805 932 /* @brief There is SW bit in SRSR register. */
borlanic 0:fbdae7e6d805 933 #define FSL_FEATURE_SRC_HAS_SRSR_SW (0)
borlanic 0:fbdae7e6d805 934 /* @brief There is IPP_USER_RESET_B bit in SRSR register. */
borlanic 0:fbdae7e6d805 935 #define FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B (1)
borlanic 0:fbdae7e6d805 936 /* @brief There is SNVS bit in SRSR register. */
borlanic 0:fbdae7e6d805 937 #define FSL_FEATURE_SRC_HAS_SRSR_SNVS (0)
borlanic 0:fbdae7e6d805 938 /* @brief There is CSU_RESET_B bit in SRSR register. */
borlanic 0:fbdae7e6d805 939 #define FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B (1)
borlanic 0:fbdae7e6d805 940 /* @brief There is LOCKUP bit in SRSR register. */
borlanic 0:fbdae7e6d805 941 #define FSL_FEATURE_SRC_HAS_SRSR_LOCKUP (0)
borlanic 0:fbdae7e6d805 942 /* @brief There is LOCKUP_SYSRESETREQ bit in SRSR register. */
borlanic 0:fbdae7e6d805 943 #define FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ (1)
borlanic 0:fbdae7e6d805 944 /* @brief There is POR bit in SRSR register. */
borlanic 0:fbdae7e6d805 945 #define FSL_FEATURE_SRC_HAS_SRSR_POR (0)
borlanic 0:fbdae7e6d805 946 /* @brief There is IPP_RESET_B bit in SRSR register. */
borlanic 0:fbdae7e6d805 947 #define FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B (1)
borlanic 0:fbdae7e6d805 948 /* @brief There is no WBI bit in SCR register. */
borlanic 0:fbdae7e6d805 949 #define FSL_FEATURE_SRC_HAS_NO_SRSR_WBI (1)
borlanic 0:fbdae7e6d805 950
borlanic 0:fbdae7e6d805 951 /* SCB module features */
borlanic 0:fbdae7e6d805 952
borlanic 0:fbdae7e6d805 953 /* @brief L1 ICACHE line size in byte. */
borlanic 0:fbdae7e6d805 954 #define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (32)
borlanic 0:fbdae7e6d805 955 /* @brief L1 DCACHE line size in byte. */
borlanic 0:fbdae7e6d805 956 #define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (32)
borlanic 0:fbdae7e6d805 957
borlanic 0:fbdae7e6d805 958 /* TRNG module features */
borlanic 0:fbdae7e6d805 959
borlanic 0:fbdae7e6d805 960 /* @brief TRNG has no TRNG_ACC bitfield. */
borlanic 0:fbdae7e6d805 961 #define FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC (1)
borlanic 0:fbdae7e6d805 962
borlanic 0:fbdae7e6d805 963 /* USBHS module features */
borlanic 0:fbdae7e6d805 964
borlanic 0:fbdae7e6d805 965 /* @brief EHCI module instance count */
borlanic 0:fbdae7e6d805 966 #define FSL_FEATURE_USBHS_EHCI_COUNT (2)
borlanic 0:fbdae7e6d805 967 /* @brief Number of endpoints supported */
borlanic 0:fbdae7e6d805 968 #define FSL_FEATURE_USBHS_ENDPT_COUNT (8)
borlanic 0:fbdae7e6d805 969
borlanic 0:fbdae7e6d805 970 /* USDHC module features */
borlanic 0:fbdae7e6d805 971
borlanic 0:fbdae7e6d805 972 /* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */
borlanic 0:fbdae7e6d805 973 #define FSL_FEATURE_USDHC_HAS_EXT_DMA (0)
borlanic 0:fbdae7e6d805 974 /* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */
borlanic 0:fbdae7e6d805 975 #define FSL_FEATURE_USDHC_HAS_HS400_MODE (0)
borlanic 0:fbdae7e6d805 976 /* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */
borlanic 0:fbdae7e6d805 977 #define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1)
borlanic 0:fbdae7e6d805 978 /* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */
borlanic 0:fbdae7e6d805 979 #define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1)
borlanic 0:fbdae7e6d805 980
borlanic 0:fbdae7e6d805 981 /* XBARA module features */
borlanic 0:fbdae7e6d805 982
borlanic 0:fbdae7e6d805 983 /* @brief DMA_CH_MUX_REQ_30. */
borlanic 0:fbdae7e6d805 984 #define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_30 (1)
borlanic 0:fbdae7e6d805 985 /* @brief DMA_CH_MUX_REQ_31. */
borlanic 0:fbdae7e6d805 986 #define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_31 (1)
borlanic 0:fbdae7e6d805 987 /* @brief DMA_CH_MUX_REQ_94. */
borlanic 0:fbdae7e6d805 988 #define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_94 (1)
borlanic 0:fbdae7e6d805 989 /* @brief DMA_CH_MUX_REQ_95. */
borlanic 0:fbdae7e6d805 990 #define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_95 (1)
borlanic 0:fbdae7e6d805 991
borlanic 0:fbdae7e6d805 992 #endif /* _MIMXRT1052_FEATURES_H_ */
borlanic 0:fbdae7e6d805 993