Nicolas Borla
/
BBR_1Ebene
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mbed-os/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_clk.c@0:fbdae7e6d805, 2018-05-14 (annotated)
- Committer:
- borlanic
- Date:
- Mon May 14 11:29:06 2018 +0000
- Revision:
- 0:fbdae7e6d805
BBR
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| borlanic | 0:fbdae7e6d805 | 1 | /**************************************************************************//** |
| borlanic | 0:fbdae7e6d805 | 2 | * @file clk.c |
| borlanic | 0:fbdae7e6d805 | 3 | * @version V1.00 |
| borlanic | 0:fbdae7e6d805 | 4 | * $Revision: 35 $ |
| borlanic | 0:fbdae7e6d805 | 5 | * $Date: 16/03/04 3:42p $ |
| borlanic | 0:fbdae7e6d805 | 6 | * @brief NUC472/NUC442 CLK driver source file |
| borlanic | 0:fbdae7e6d805 | 7 | * |
| borlanic | 0:fbdae7e6d805 | 8 | * @note |
| borlanic | 0:fbdae7e6d805 | 9 | * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. |
| borlanic | 0:fbdae7e6d805 | 10 | *****************************************************************************/ |
| borlanic | 0:fbdae7e6d805 | 11 | |
| borlanic | 0:fbdae7e6d805 | 12 | #include "NUC472_442.h" |
| borlanic | 0:fbdae7e6d805 | 13 | /** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver |
| borlanic | 0:fbdae7e6d805 | 14 | @{ |
| borlanic | 0:fbdae7e6d805 | 15 | */ |
| borlanic | 0:fbdae7e6d805 | 16 | |
| borlanic | 0:fbdae7e6d805 | 17 | /** @addtogroup NUC472_442_CLK_Driver CLK Driver |
| borlanic | 0:fbdae7e6d805 | 18 | @{ |
| borlanic | 0:fbdae7e6d805 | 19 | */ |
| borlanic | 0:fbdae7e6d805 | 20 | |
| borlanic | 0:fbdae7e6d805 | 21 | |
| borlanic | 0:fbdae7e6d805 | 22 | /** @addtogroup NUC472_442_CLK_EXPORTED_FUNCTIONS CLK Exported Functions |
| borlanic | 0:fbdae7e6d805 | 23 | @{ |
| borlanic | 0:fbdae7e6d805 | 24 | */ |
| borlanic | 0:fbdae7e6d805 | 25 | |
| borlanic | 0:fbdae7e6d805 | 26 | |
| borlanic | 0:fbdae7e6d805 | 27 | /** |
| borlanic | 0:fbdae7e6d805 | 28 | * @brief Disable frequency output function |
| borlanic | 0:fbdae7e6d805 | 29 | * @return None |
| borlanic | 0:fbdae7e6d805 | 30 | * @details This function disable frequency output function. |
| borlanic | 0:fbdae7e6d805 | 31 | */ |
| borlanic | 0:fbdae7e6d805 | 32 | void CLK_DisableCKO(void) |
| borlanic | 0:fbdae7e6d805 | 33 | { |
| borlanic | 0:fbdae7e6d805 | 34 | /* Disable CKO clock source */ |
| borlanic | 0:fbdae7e6d805 | 35 | CLK->APBCLK0 &= (~CLK_APBCLK0_CLKOCKEN_Msk); |
| borlanic | 0:fbdae7e6d805 | 36 | } |
| borlanic | 0:fbdae7e6d805 | 37 | |
| borlanic | 0:fbdae7e6d805 | 38 | /** |
| borlanic | 0:fbdae7e6d805 | 39 | * @brief This function enable frequency divider module clock, |
| borlanic | 0:fbdae7e6d805 | 40 | * enable frequency divider clock function and configure frequency divider. |
| borlanic | 0:fbdae7e6d805 | 41 | * @param[in] u32ClkSrc is frequency divider function clock source |
| borlanic | 0:fbdae7e6d805 | 42 | * - \ref CLK_CLKSEL1_CLKOSEL_HXT |
| borlanic | 0:fbdae7e6d805 | 43 | * - \ref CLK_CLKSEL1_CLKOSEL_LXT |
| borlanic | 0:fbdae7e6d805 | 44 | * - \ref CLK_CLKSEL1_CLKOSEL_HCLK |
| borlanic | 0:fbdae7e6d805 | 45 | * - \ref CLK_CLKSEL1_CLKOSEL_HIRC |
| borlanic | 0:fbdae7e6d805 | 46 | * @param[in] u32ClkDiv is system reset source |
| borlanic | 0:fbdae7e6d805 | 47 | * @param[in] u32ClkDivBy1En is frequency divided by one enable. |
| borlanic | 0:fbdae7e6d805 | 48 | * @return None |
| borlanic | 0:fbdae7e6d805 | 49 | * |
| borlanic | 0:fbdae7e6d805 | 50 | * @details Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv. |
| borlanic | 0:fbdae7e6d805 | 51 | * The formula is: |
| borlanic | 0:fbdae7e6d805 | 52 | * CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1) |
| borlanic | 0:fbdae7e6d805 | 53 | * This function is just used to set CKO clock. |
| borlanic | 0:fbdae7e6d805 | 54 | * User must enable I/O for CKO clock output pin by themselves. |
| borlanic | 0:fbdae7e6d805 | 55 | */ |
| borlanic | 0:fbdae7e6d805 | 56 | void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En) |
| borlanic | 0:fbdae7e6d805 | 57 | { |
| borlanic | 0:fbdae7e6d805 | 58 | /* CKO = clock source / 2^(u32ClkDiv + 1) */ |
| borlanic | 0:fbdae7e6d805 | 59 | CLK->CLKOCTL = CLK_CLKOCTL_CLKOEN_Msk | u32ClkDiv | u32ClkDivBy1En<<CLK_CLKOCTL_DIV1EN_Pos; |
| borlanic | 0:fbdae7e6d805 | 60 | |
| borlanic | 0:fbdae7e6d805 | 61 | /* Enable CKO clock source */ |
| borlanic | 0:fbdae7e6d805 | 62 | CLK->APBCLK0 |= CLK_APBCLK0_CLKOCKEN_Msk; |
| borlanic | 0:fbdae7e6d805 | 63 | |
| borlanic | 0:fbdae7e6d805 | 64 | /* Select CKO clock source */ |
| borlanic | 0:fbdae7e6d805 | 65 | CLK->CLKSEL1 = (CLK->CLKSEL1 & (~CLK_CLKSEL1_CLKOSEL_Msk)) | u32ClkSrc; |
| borlanic | 0:fbdae7e6d805 | 66 | } |
| borlanic | 0:fbdae7e6d805 | 67 | |
| borlanic | 0:fbdae7e6d805 | 68 | /** |
| borlanic | 0:fbdae7e6d805 | 69 | * @brief Enter to Power-down mode |
| borlanic | 0:fbdae7e6d805 | 70 | * @return None |
| borlanic | 0:fbdae7e6d805 | 71 | * @details This function let system enter to Power-down mode. |
| borlanic | 0:fbdae7e6d805 | 72 | */ |
| borlanic | 0:fbdae7e6d805 | 73 | void CLK_PowerDown(void) |
| borlanic | 0:fbdae7e6d805 | 74 | { |
| borlanic | 0:fbdae7e6d805 | 75 | SCB->SCR = SCB_SCR_SLEEPDEEP_Msk; |
| borlanic | 0:fbdae7e6d805 | 76 | CLK->PWRCTL |= (CLK_PWRCTL_PDEN_Msk | CLK_PWRCTL_PDWKDLY_Msk ); |
| borlanic | 0:fbdae7e6d805 | 77 | __WFI(); |
| borlanic | 0:fbdae7e6d805 | 78 | } |
| borlanic | 0:fbdae7e6d805 | 79 | |
| borlanic | 0:fbdae7e6d805 | 80 | /** |
| borlanic | 0:fbdae7e6d805 | 81 | * @brief Enter to Idle mode. |
| borlanic | 0:fbdae7e6d805 | 82 | * @return None |
| borlanic | 0:fbdae7e6d805 | 83 | * @details This function let system enter to Idle mode. |
| borlanic | 0:fbdae7e6d805 | 84 | */ |
| borlanic | 0:fbdae7e6d805 | 85 | void CLK_Idle(void) |
| borlanic | 0:fbdae7e6d805 | 86 | { |
| borlanic | 0:fbdae7e6d805 | 87 | /* Set the processor uses sleep as its low power mode */ |
| borlanic | 0:fbdae7e6d805 | 88 | SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; |
| borlanic | 0:fbdae7e6d805 | 89 | |
| borlanic | 0:fbdae7e6d805 | 90 | /* Set chip in idle mode because of WFI command */ |
| borlanic | 0:fbdae7e6d805 | 91 | CLK->PWRCTL &= ~(CLK_PWRCTL_PDEN_Msk ); |
| borlanic | 0:fbdae7e6d805 | 92 | |
| borlanic | 0:fbdae7e6d805 | 93 | /* Chip enter idle mode after CPU run WFI instruction */ |
| borlanic | 0:fbdae7e6d805 | 94 | __WFI(); |
| borlanic | 0:fbdae7e6d805 | 95 | } |
| borlanic | 0:fbdae7e6d805 | 96 | |
| borlanic | 0:fbdae7e6d805 | 97 | |
| borlanic | 0:fbdae7e6d805 | 98 | /** |
| borlanic | 0:fbdae7e6d805 | 99 | * @brief This function get PCLK frequency. The frequency unit is Hz. |
| borlanic | 0:fbdae7e6d805 | 100 | * @return PCLK frequency |
| borlanic | 0:fbdae7e6d805 | 101 | */ |
| borlanic | 0:fbdae7e6d805 | 102 | uint32_t CLK_GetPCLKFreq(void) |
| borlanic | 0:fbdae7e6d805 | 103 | { |
| borlanic | 0:fbdae7e6d805 | 104 | SystemCoreClockUpdate(); |
| borlanic | 0:fbdae7e6d805 | 105 | if(CLK->CLKSEL0 & CLK_CLKSEL0_PCLKSEL_Msk) |
| borlanic | 0:fbdae7e6d805 | 106 | return SystemCoreClock/2; |
| borlanic | 0:fbdae7e6d805 | 107 | else |
| borlanic | 0:fbdae7e6d805 | 108 | return SystemCoreClock; |
| borlanic | 0:fbdae7e6d805 | 109 | } |
| borlanic | 0:fbdae7e6d805 | 110 | |
| borlanic | 0:fbdae7e6d805 | 111 | /** |
| borlanic | 0:fbdae7e6d805 | 112 | * @brief Get external high speed crystal clock frequency |
| borlanic | 0:fbdae7e6d805 | 113 | * @return External high frequency crystal frequency |
| borlanic | 0:fbdae7e6d805 | 114 | * @details This function get external high frequency crystal frequency. The frequency unit is Hz. |
| borlanic | 0:fbdae7e6d805 | 115 | */ |
| borlanic | 0:fbdae7e6d805 | 116 | uint32_t CLK_GetHXTFreq(void) |
| borlanic | 0:fbdae7e6d805 | 117 | { |
| borlanic | 0:fbdae7e6d805 | 118 | if(CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk ) |
| borlanic | 0:fbdae7e6d805 | 119 | return __HXT; |
| borlanic | 0:fbdae7e6d805 | 120 | else |
| borlanic | 0:fbdae7e6d805 | 121 | return 0; |
| borlanic | 0:fbdae7e6d805 | 122 | } |
| borlanic | 0:fbdae7e6d805 | 123 | |
| borlanic | 0:fbdae7e6d805 | 124 | /** |
| borlanic | 0:fbdae7e6d805 | 125 | * @brief Get external low speed crystal clock frequency |
| borlanic | 0:fbdae7e6d805 | 126 | * @return External low speed crystal clock frequency |
| borlanic | 0:fbdae7e6d805 | 127 | * @details This function get external low frequency crystal frequency. The frequency unit is Hz. |
| borlanic | 0:fbdae7e6d805 | 128 | */ |
| borlanic | 0:fbdae7e6d805 | 129 | uint32_t CLK_GetLXTFreq(void) |
| borlanic | 0:fbdae7e6d805 | 130 | { |
| borlanic | 0:fbdae7e6d805 | 131 | if(CLK->PWRCTL & CLK_PWRCTL_LXTEN_Msk ) |
| borlanic | 0:fbdae7e6d805 | 132 | return __LXT; |
| borlanic | 0:fbdae7e6d805 | 133 | else |
| borlanic | 0:fbdae7e6d805 | 134 | return 0; |
| borlanic | 0:fbdae7e6d805 | 135 | } |
| borlanic | 0:fbdae7e6d805 | 136 | |
| borlanic | 0:fbdae7e6d805 | 137 | |
| borlanic | 0:fbdae7e6d805 | 138 | /** |
| borlanic | 0:fbdae7e6d805 | 139 | * @brief Get HCLK frequency |
| borlanic | 0:fbdae7e6d805 | 140 | * @return HCLK frequency |
| borlanic | 0:fbdae7e6d805 | 141 | * @details This function get HCLK frequency. The frequency unit is Hz. |
| borlanic | 0:fbdae7e6d805 | 142 | */ |
| borlanic | 0:fbdae7e6d805 | 143 | uint32_t CLK_GetHCLKFreq(void) |
| borlanic | 0:fbdae7e6d805 | 144 | { |
| borlanic | 0:fbdae7e6d805 | 145 | SystemCoreClockUpdate(); |
| borlanic | 0:fbdae7e6d805 | 146 | return SystemCoreClock; |
| borlanic | 0:fbdae7e6d805 | 147 | } |
| borlanic | 0:fbdae7e6d805 | 148 | |
| borlanic | 0:fbdae7e6d805 | 149 | /** |
| borlanic | 0:fbdae7e6d805 | 150 | * @brief Get CPU frequency |
| borlanic | 0:fbdae7e6d805 | 151 | * @return CPU frequency |
| borlanic | 0:fbdae7e6d805 | 152 | * @details This function get CPU frequency. The frequency unit is Hz. |
| borlanic | 0:fbdae7e6d805 | 153 | */ |
| borlanic | 0:fbdae7e6d805 | 154 | uint32_t CLK_GetCPUFreq(void) |
| borlanic | 0:fbdae7e6d805 | 155 | { |
| borlanic | 0:fbdae7e6d805 | 156 | SystemCoreClockUpdate(); |
| borlanic | 0:fbdae7e6d805 | 157 | return SystemCoreClock; |
| borlanic | 0:fbdae7e6d805 | 158 | } |
| borlanic | 0:fbdae7e6d805 | 159 | |
| borlanic | 0:fbdae7e6d805 | 160 | /** |
| borlanic | 0:fbdae7e6d805 | 161 | * @brief This function get PLL frequency. The frequency unit is Hz. |
| borlanic | 0:fbdae7e6d805 | 162 | * @return PLL frequency |
| borlanic | 0:fbdae7e6d805 | 163 | */ |
| borlanic | 0:fbdae7e6d805 | 164 | uint32_t CLK_GetPLLClockFreq(void) |
| borlanic | 0:fbdae7e6d805 | 165 | { |
| borlanic | 0:fbdae7e6d805 | 166 | uint32_t u32Freq =0, u32PLLSrc; |
| borlanic | 0:fbdae7e6d805 | 167 | uint32_t u32NO,u32NF,u32NR,u32PllReg; |
| borlanic | 0:fbdae7e6d805 | 168 | |
| borlanic | 0:fbdae7e6d805 | 169 | u32PllReg = CLK->PLLCTL; |
| borlanic | 0:fbdae7e6d805 | 170 | |
| borlanic | 0:fbdae7e6d805 | 171 | if(u32PllReg & (CLK_PLLCTL_PD_Msk | CLK_PLLCTL_OE_Msk)) |
| borlanic | 0:fbdae7e6d805 | 172 | return 0; /* PLL is in power down mode or fix low */ |
| borlanic | 0:fbdae7e6d805 | 173 | |
| borlanic | 0:fbdae7e6d805 | 174 | if(u32PllReg & CLK_PLLCTL_PLLSRC_Msk) |
| borlanic | 0:fbdae7e6d805 | 175 | u32PLLSrc = __HIRC; |
| borlanic | 0:fbdae7e6d805 | 176 | else |
| borlanic | 0:fbdae7e6d805 | 177 | u32PLLSrc = __HXT; |
| borlanic | 0:fbdae7e6d805 | 178 | |
| borlanic | 0:fbdae7e6d805 | 179 | u32NO=(u32PllReg & CLK_PLLCTL_OUTDV_Msk)>>CLK_PLLCTL_OUTDV_Pos; |
| borlanic | 0:fbdae7e6d805 | 180 | switch(u32NO) { |
| borlanic | 0:fbdae7e6d805 | 181 | case 0: |
| borlanic | 0:fbdae7e6d805 | 182 | u32NO=1; |
| borlanic | 0:fbdae7e6d805 | 183 | break; |
| borlanic | 0:fbdae7e6d805 | 184 | case 1: |
| borlanic | 0:fbdae7e6d805 | 185 | case 2: |
| borlanic | 0:fbdae7e6d805 | 186 | u32NO=2; |
| borlanic | 0:fbdae7e6d805 | 187 | break; |
| borlanic | 0:fbdae7e6d805 | 188 | case 3: |
| borlanic | 0:fbdae7e6d805 | 189 | u32NO=4; |
| borlanic | 0:fbdae7e6d805 | 190 | break; |
| borlanic | 0:fbdae7e6d805 | 191 | } |
| borlanic | 0:fbdae7e6d805 | 192 | |
| borlanic | 0:fbdae7e6d805 | 193 | u32NF = (u32PllReg & CLK_PLLCTL_FBDIV_Msk) + 2; |
| borlanic | 0:fbdae7e6d805 | 194 | u32NR = ( (u32PllReg & CLK_PLLCTL_INDIV_Msk)>>CLK_PLLCTL_INDIV_Pos ) + 2; |
| borlanic | 0:fbdae7e6d805 | 195 | |
| borlanic | 0:fbdae7e6d805 | 196 | /* u32PLLSrc is shifted 2 bits to avoid overflow */ |
| borlanic | 0:fbdae7e6d805 | 197 | u32Freq = (((u32PLLSrc >> 2) * u32NF) / (u32NR * u32NO) << 2); |
| borlanic | 0:fbdae7e6d805 | 198 | return u32Freq; |
| borlanic | 0:fbdae7e6d805 | 199 | } |
| borlanic | 0:fbdae7e6d805 | 200 | |
| borlanic | 0:fbdae7e6d805 | 201 | /** |
| borlanic | 0:fbdae7e6d805 | 202 | * @brief Set HCLK frequency |
| borlanic | 0:fbdae7e6d805 | 203 | * @param[in] u32Hclk is HCLK frequency |
| borlanic | 0:fbdae7e6d805 | 204 | * @return HCLK frequency |
| borlanic | 0:fbdae7e6d805 | 205 | * @details This function set HCLK frequency. The frequency unit is Hz. The range of u32Hclk is 24 MHz ~ 96 MHz. |
| borlanic | 0:fbdae7e6d805 | 206 | */ |
| borlanic | 0:fbdae7e6d805 | 207 | uint32_t CLK_SetCoreClock(uint32_t u32Hclk) |
| borlanic | 0:fbdae7e6d805 | 208 | { |
| borlanic | 0:fbdae7e6d805 | 209 | uint32_t u32ClkSrc,u32NR, u32NF,u32Register; |
| borlanic | 0:fbdae7e6d805 | 210 | u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk; |
| borlanic | 0:fbdae7e6d805 | 211 | |
| borlanic | 0:fbdae7e6d805 | 212 | if(u32Hclk < FREQ_24MHZ) |
| borlanic | 0:fbdae7e6d805 | 213 | u32Hclk =FREQ_24MHZ; |
| borlanic | 0:fbdae7e6d805 | 214 | |
| borlanic | 0:fbdae7e6d805 | 215 | if(CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk) { |
| borlanic | 0:fbdae7e6d805 | 216 | u32Register = 0<<CLK_PLLCTL_PLLSRC_Pos; |
| borlanic | 0:fbdae7e6d805 | 217 | u32ClkSrc = __HXT; |
| borlanic | 0:fbdae7e6d805 | 218 | } else { |
| borlanic | 0:fbdae7e6d805 | 219 | u32Register = 1<<CLK_PLLCTL_PLLSRC_Pos; |
| borlanic | 0:fbdae7e6d805 | 220 | u32ClkSrc = __HIRC; |
| borlanic | 0:fbdae7e6d805 | 221 | } |
| borlanic | 0:fbdae7e6d805 | 222 | |
| borlanic | 0:fbdae7e6d805 | 223 | if(u32Hclk<FREQ_50MHZ) { |
| borlanic | 0:fbdae7e6d805 | 224 | u32Hclk <<=2; |
| borlanic | 0:fbdae7e6d805 | 225 | u32Register |= (0x3<<CLK_PLLCTL_OUTDV_Pos); |
| borlanic | 0:fbdae7e6d805 | 226 | } else { |
| borlanic | 0:fbdae7e6d805 | 227 | u32Hclk <<=1; |
| borlanic | 0:fbdae7e6d805 | 228 | u32Register |= (0x1<<CLK_PLLCTL_OUTDV_Pos); |
| borlanic | 0:fbdae7e6d805 | 229 | } |
| borlanic | 0:fbdae7e6d805 | 230 | u32NF = u32Hclk / 1000000; |
| borlanic | 0:fbdae7e6d805 | 231 | u32NR = u32ClkSrc / 1000000; |
| borlanic | 0:fbdae7e6d805 | 232 | while( u32NR>(0xF+2) || u32NF>(0xFF+2) ) { |
| borlanic | 0:fbdae7e6d805 | 233 | u32NR = u32NR>>1; |
| borlanic | 0:fbdae7e6d805 | 234 | u32NF = u32NF>>1; |
| borlanic | 0:fbdae7e6d805 | 235 | } |
| borlanic | 0:fbdae7e6d805 | 236 | CLK->PLLCTL = u32Register | ((u32NR - 2)<<9) | (u32NF - 2) ; |
| borlanic | 0:fbdae7e6d805 | 237 | CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk); |
| borlanic | 0:fbdae7e6d805 | 238 | |
| borlanic | 0:fbdae7e6d805 | 239 | CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL,CLK_CLKDIV0_HCLK(1)); |
| borlanic | 0:fbdae7e6d805 | 240 | |
| borlanic | 0:fbdae7e6d805 | 241 | /* Update System Core Clock */ |
| borlanic | 0:fbdae7e6d805 | 242 | SystemCoreClockUpdate(); |
| borlanic | 0:fbdae7e6d805 | 243 | |
| borlanic | 0:fbdae7e6d805 | 244 | return SystemCoreClock; |
| borlanic | 0:fbdae7e6d805 | 245 | } |
| borlanic | 0:fbdae7e6d805 | 246 | |
| borlanic | 0:fbdae7e6d805 | 247 | /** |
| borlanic | 0:fbdae7e6d805 | 248 | * @brief This function set HCLK clock source and HCLK clock divider |
| borlanic | 0:fbdae7e6d805 | 249 | * @param[in] u32ClkSrc is HCLK clock source. Including : |
| borlanic | 0:fbdae7e6d805 | 250 | * - \ref CLK_CLKSEL0_HCLKSEL_HXT |
| borlanic | 0:fbdae7e6d805 | 251 | * - \ref CLK_CLKSEL0_HCLKSEL_LXT |
| borlanic | 0:fbdae7e6d805 | 252 | * - \ref CLK_CLKSEL0_HCLKSEL_PLL |
| borlanic | 0:fbdae7e6d805 | 253 | * - \ref CLK_CLKSEL0_HCLKSEL_LIRC |
| borlanic | 0:fbdae7e6d805 | 254 | * - \ref CLK_CLKSEL0_HCLKSEL_HIRC |
| borlanic | 0:fbdae7e6d805 | 255 | * @param[in] u32ClkDiv is HCLK clock divider. Including : |
| borlanic | 0:fbdae7e6d805 | 256 | * - \ref CLK_CLKDIV0_HCLK(x) |
| borlanic | 0:fbdae7e6d805 | 257 | * @return None |
| borlanic | 0:fbdae7e6d805 | 258 | */ |
| borlanic | 0:fbdae7e6d805 | 259 | void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv) |
| borlanic | 0:fbdae7e6d805 | 260 | { |
| borlanic | 0:fbdae7e6d805 | 261 | CLK->CLKDIV0 = (CLK->CLKDIV0 & ~CLK_CLKDIV0_HCLKDIV_Msk) | u32ClkDiv; |
| borlanic | 0:fbdae7e6d805 | 262 | CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_HCLKSEL_Msk) | u32ClkSrc; |
| borlanic | 0:fbdae7e6d805 | 263 | SystemCoreClockUpdate(); |
| borlanic | 0:fbdae7e6d805 | 264 | } |
| borlanic | 0:fbdae7e6d805 | 265 | |
| borlanic | 0:fbdae7e6d805 | 266 | /** |
| borlanic | 0:fbdae7e6d805 | 267 | * @brief This function set selected module clock source and module clock divider |
| borlanic | 0:fbdae7e6d805 | 268 | * @param[in] u32ModuleIdx is module index. |
| borlanic | 0:fbdae7e6d805 | 269 | * @param[in] u32ClkSrc is module clock source. |
| borlanic | 0:fbdae7e6d805 | 270 | * @param[in] u32ClkDiv is module clock divider. |
| borlanic | 0:fbdae7e6d805 | 271 | * @return None |
| borlanic | 0:fbdae7e6d805 | 272 | * @details Valid parameter combinations listed in following table: |
| borlanic | 0:fbdae7e6d805 | 273 | * |
| borlanic | 0:fbdae7e6d805 | 274 | * |Module index |Clock source |Divider | |
| borlanic | 0:fbdae7e6d805 | 275 | * | :------------------- | :------------------------------- | :------------------------- | |
| borlanic | 0:fbdae7e6d805 | 276 | * |\ref PDMA_MODULE | x | x | |
| borlanic | 0:fbdae7e6d805 | 277 | * |\ref ISP_MODULE | x | x | |
| borlanic | 0:fbdae7e6d805 | 278 | * |\ref EBI_MODULE | x | x | |
| borlanic | 0:fbdae7e6d805 | 279 | * |\ref USBH_MODULE |\ref CLK_CLKSEL0_USBHSEL_PLL |\ref CLK_CLKDIV0_USB(x) | |
| borlanic | 0:fbdae7e6d805 | 280 | * |\ref USBH_MODULE |\ref CLK_CLKSEL0_USBHSEL_PLL2 |\ref CLK_CLKDIV0_USB(x) | |
| borlanic | 0:fbdae7e6d805 | 281 | * |\ref EMAC_MODULE | x |\ref CLK_CLKDIV3_EMAC(x) | |
| borlanic | 0:fbdae7e6d805 | 282 | * |\ref SDH_MODULE |\ref CLK_CLKSEL0_SDHSEL_HXT |\ref CLK_CLKDIV0_SDH(x) | |
| borlanic | 0:fbdae7e6d805 | 283 | * |\ref SDH_MODULE |\ref CLK_CLKSEL0_SDHSEL_PLL |\ref CLK_CLKDIV0_SDH(x) | |
| borlanic | 0:fbdae7e6d805 | 284 | * |\ref SDH_MODULE |\ref CLK_CLKSEL0_SDHSEL_HCLK |\ref CLK_CLKDIV0_SDH(x) | |
| borlanic | 0:fbdae7e6d805 | 285 | * |\ref SDH_MODULE |\ref CLK_CLKSEL0_SDHSEL_HIRC |\ref CLK_CLKDIV0_SDH(x) | |
| borlanic | 0:fbdae7e6d805 | 286 | * |\ref CRC_MODULE | x | x | |
| borlanic | 0:fbdae7e6d805 | 287 | * |\ref CAP_MODULE |\ref CLK_CLKSEL0_CAPSEL_HXT |\ref CLK_CLKDIV3_CAP(x) | |
| borlanic | 0:fbdae7e6d805 | 288 | * |\ref CAP_MODULE |\ref CLK_CLKSEL0_CAPSEL_PLL2 |\ref CLK_CLKDIV3_CAP(x) | |
| borlanic | 0:fbdae7e6d805 | 289 | * |\ref CAP_MODULE |\ref CLK_CLKSEL0_CAPSEL_HCLK |\ref CLK_CLKDIV3_CAP(x) | |
| borlanic | 0:fbdae7e6d805 | 290 | * |\ref CAP_MODULE |\ref CLK_CLKSEL0_CAPSEL_HIRC |\ref CLK_CLKDIV3_CAP(x) | |
| borlanic | 0:fbdae7e6d805 | 291 | * |\ref SEN_MODULE | x | x | |
| borlanic | 0:fbdae7e6d805 | 292 | * |\ref USBD_MODULE | x | x | |
| borlanic | 0:fbdae7e6d805 | 293 | * |\ref CRPT_MODULE | x | x | |
| borlanic | 0:fbdae7e6d805 | 294 | * |\ref ECAP1_MODULE | x | x | |
| borlanic | 0:fbdae7e6d805 | 295 | * |\ref ECAP0_MODULE | x | x | |
| borlanic | 0:fbdae7e6d805 | 296 | * |\ref EADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_HXT |\ref CLK_CLKDIV0_ADC(x) | |
| borlanic | 0:fbdae7e6d805 | 297 | * |\ref EADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_PLL |\ref CLK_CLKDIV0_ADC(x) | |
| borlanic | 0:fbdae7e6d805 | 298 | * |\ref EADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_PCLK |\ref CLK_CLKDIV0_ADC(x) | |
| borlanic | 0:fbdae7e6d805 | 299 | * |\ref EADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_HIRC |\ref CLK_CLKDIV0_ADC(x) | |
| borlanic | 0:fbdae7e6d805 | 300 | * |\ref OPA_MODULE | x | x | |
| borlanic | 0:fbdae7e6d805 | 301 | * |\ref QEI1_MODULE | x | x | |
| borlanic | 0:fbdae7e6d805 | 302 | * |\ref QEI0_MODULE | x | x | |
| borlanic | 0:fbdae7e6d805 | 303 | * |\ref PWM1CH45_MODULE |\ref CLK_CLKSEL2_PWM1CH45SEL_HXT | x | |
| borlanic | 0:fbdae7e6d805 | 304 | * |\ref PWM1CH45_MODULE |\ref CLK_CLKSEL2_PWM1CH45SEL_LXT | x | |
| borlanic | 0:fbdae7e6d805 | 305 | * |\ref PWM1CH45_MODULE |\ref CLK_CLKSEL2_PWM1CH45SEL_PCLK | x | |
| borlanic | 0:fbdae7e6d805 | 306 | * |\ref PWM1CH45_MODULE |\ref CLK_CLKSEL2_PWM1CH45SEL_LIRC | x | |
| borlanic | 0:fbdae7e6d805 | 307 | * |\ref PWM1CH45_MODULE |\ref CLK_CLKSEL2_PWM1CH45SEL_HIRC | x | |
| borlanic | 0:fbdae7e6d805 | 308 | * |\ref PWM1CH23_MODULE |\ref CLK_CLKSEL2_PWM1CH23SEL_HXT | x | |
| borlanic | 0:fbdae7e6d805 | 309 | * |\ref PWM1CH23_MODULE |\ref CLK_CLKSEL2_PWM1CH23SEL_LXT | x | |
| borlanic | 0:fbdae7e6d805 | 310 | * |\ref PWM1CH23_MODULE |\ref CLK_CLKSEL2_PWM1CH23SEL_PCLK | x | |
| borlanic | 0:fbdae7e6d805 | 311 | * |\ref PWM1CH23_MODULE |\ref CLK_CLKSEL2_PWM1CH23SEL_LIRC | x | |
| borlanic | 0:fbdae7e6d805 | 312 | * |\ref PWM1CH23_MODULE |\ref CLK_CLKSEL2_PWM1CH23SEL_HIRC | x | |
| borlanic | 0:fbdae7e6d805 | 313 | * |\ref PWM1CH01_MODULE |\ref CLK_CLKSEL2_PWM1CH01SEL_HXT | x | |
| borlanic | 0:fbdae7e6d805 | 314 | * |\ref PWM1CH01_MODULE |\ref CLK_CLKSEL2_PWM1CH01SEL_LXT | x | |
| borlanic | 0:fbdae7e6d805 | 315 | * |\ref PWM1CH01_MODULE |\ref CLK_CLKSEL2_PWM1CH01SEL_PCLK | x | |
| borlanic | 0:fbdae7e6d805 | 316 | * |\ref PWM1CH01_MODULE |\ref CLK_CLKSEL2_PWM1CH01SEL_LIRC | x | |
| borlanic | 0:fbdae7e6d805 | 317 | * |\ref PWM1CH01_MODULE |\ref CLK_CLKSEL2_PWM1CH01SEL_HIRC | x | |
| borlanic | 0:fbdae7e6d805 | 318 | * |\ref PWM0CH45_MODULE |\ref CLK_CLKSEL2_PWM0CH45SEL_HXT | x | |
| borlanic | 0:fbdae7e6d805 | 319 | * |\ref PWM0CH45_MODULE |\ref CLK_CLKSEL2_PWM0CH45SEL_LXT | x | |
| borlanic | 0:fbdae7e6d805 | 320 | * |\ref PWM0CH45_MODULE |\ref CLK_CLKSEL2_PWM0CH45SEL_PCLK | x | |
| borlanic | 0:fbdae7e6d805 | 321 | * |\ref PWM0CH45_MODULE |\ref CLK_CLKSEL2_PWM0CH45SEL_LIRC | x | |
| borlanic | 0:fbdae7e6d805 | 322 | * |\ref PWM0CH45_MODULE |\ref CLK_CLKSEL2_PWM0CH45SEL_HIRC | x | |
| borlanic | 0:fbdae7e6d805 | 323 | * |\ref PWM0CH23_MODULE |\ref CLK_CLKSEL2_PWM0CH23SEL_HXT | x | |
| borlanic | 0:fbdae7e6d805 | 324 | * |\ref PWM0CH23_MODULE |\ref CLK_CLKSEL2_PWM0CH23SEL_LXT | x | |
| borlanic | 0:fbdae7e6d805 | 325 | * |\ref PWM0CH23_MODULE |\ref CLK_CLKSEL2_PWM0CH23SEL_PCLK | x | |
| borlanic | 0:fbdae7e6d805 | 326 | * |\ref PWM0CH23_MODULE |\ref CLK_CLKSEL2_PWM0CH23SEL_LIRC | x | |
| borlanic | 0:fbdae7e6d805 | 327 | * |\ref PWM0CH23_MODULE |\ref CLK_CLKSEL2_PWM0CH23SEL_HIRC | x | |
| borlanic | 0:fbdae7e6d805 | 328 | * |\ref PWM0CH01_MODULE |\ref CLK_CLKSEL2_PWM0CH01SEL_HXT | x | |
| borlanic | 0:fbdae7e6d805 | 329 | * |\ref PWM0CH01_MODULE |\ref CLK_CLKSEL2_PWM0CH01SEL_LXT | x | |
| borlanic | 0:fbdae7e6d805 | 330 | * |\ref PWM0CH01_MODULE |\ref CLK_CLKSEL2_PWM0CH01SEL_PCLK | x | |
| borlanic | 0:fbdae7e6d805 | 331 | * |\ref PWM0CH01_MODULE |\ref CLK_CLKSEL2_PWM0CH01SEL_LIRC | x | |
| borlanic | 0:fbdae7e6d805 | 332 | * |\ref PWM0CH01_MODULE |\ref CLK_CLKSEL2_PWM0CH01SEL_HIRC | x | |
| borlanic | 0:fbdae7e6d805 | 333 | * |\ref I2C4_MODULE | x | x | |
| borlanic | 0:fbdae7e6d805 | 334 | * |\ref SC5_MODULE | x | x | |
| borlanic | 0:fbdae7e6d805 | 335 | * |\ref SC4_MODULE | x | x | |
| borlanic | 0:fbdae7e6d805 | 336 | * |\ref SC3_MODULE | x | x | |
| borlanic | 0:fbdae7e6d805 | 337 | * |\ref SC2_MODULE | x | x | |
| borlanic | 0:fbdae7e6d805 | 338 | * |\ref SC5_MODULE |\ref CLK_CLKSEL3_SC5SEL_HXT |\ref CLK_CLKDIV2_SC5(x) | |
| borlanic | 0:fbdae7e6d805 | 339 | * |\ref SC5_MODULE |\ref CLK_CLKSEL3_SC5SEL_PLL |\ref CLK_CLKDIV2_SC5(x) | |
| borlanic | 0:fbdae7e6d805 | 340 | * |\ref SC5_MODULE |\ref CLK_CLKSEL3_SC5SEL_PCLK |\ref CLK_CLKDIV2_SC5(x) | |
| borlanic | 0:fbdae7e6d805 | 341 | * |\ref SC5_MODULE |\ref CLK_CLKSEL3_SC5SEL_HIRC |\ref CLK_CLKDIV2_SC5(x) | |
| borlanic | 0:fbdae7e6d805 | 342 | * |\ref SC4_MODULE |\ref CLK_CLKSEL3_SC4SEL_HXT |\ref CLK_CLKDIV2_SC4(x) | |
| borlanic | 0:fbdae7e6d805 | 343 | * |\ref SC4_MODULE |\ref CLK_CLKSEL3_SC4SEL_PLL |\ref CLK_CLKDIV2_SC4(x) | |
| borlanic | 0:fbdae7e6d805 | 344 | * |\ref SC4_MODULE |\ref CLK_CLKSEL3_SC4SEL_PCLK |\ref CLK_CLKDIV2_SC4(x) | |
| borlanic | 0:fbdae7e6d805 | 345 | * |\ref SC4_MODULE |\ref CLK_CLKSEL3_SC4SEL_HIRC |\ref CLK_CLKDIV2_SC4(x) | |
| borlanic | 0:fbdae7e6d805 | 346 | * |\ref SC3_MODULE |\ref CLK_CLKSEL3_SC3SEL_HXT |\ref CLK_CLKDIV1_SC3(x) | |
| borlanic | 0:fbdae7e6d805 | 347 | * |\ref SC3_MODULE |\ref CLK_CLKSEL3_SC3SEL_PLL |\ref CLK_CLKDIV1_SC3(x) | |
| borlanic | 0:fbdae7e6d805 | 348 | * |\ref SC3_MODULE |\ref CLK_CLKSEL3_SC3SEL_PCLK |\ref CLK_CLKDIV1_SC3(x) | |
| borlanic | 0:fbdae7e6d805 | 349 | * |\ref SC3_MODULE |\ref CLK_CLKSEL3_SC3SEL_HIRC |\ref CLK_CLKDIV1_SC3(x) | |
| borlanic | 0:fbdae7e6d805 | 350 | * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HXT |\ref CLK_CLKDIV1_SC2(x) | |
| borlanic | 0:fbdae7e6d805 | 351 | * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PLL |\ref CLK_CLKDIV1_SC2(x) | |
| borlanic | 0:fbdae7e6d805 | 352 | * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PCLK |\ref CLK_CLKDIV1_SC2(x) | |
| borlanic | 0:fbdae7e6d805 | 353 | * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HIRC |\ref CLK_CLKDIV1_SC2(x) | |
| borlanic | 0:fbdae7e6d805 | 354 | * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_HXT |\ref CLK_CLKDIV1_SC1(x) | |
| borlanic | 0:fbdae7e6d805 | 355 | * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_PLL |\ref CLK_CLKDIV1_SC1(x) | |
| borlanic | 0:fbdae7e6d805 | 356 | * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_PCLK |\ref CLK_CLKDIV1_SC1(x) | |
| borlanic | 0:fbdae7e6d805 | 357 | * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_HIRC |\ref CLK_CLKDIV1_SC1(x) | |
| borlanic | 0:fbdae7e6d805 | 358 | * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HXT |\ref CLK_CLKDIV1_SC0(x) | |
| borlanic | 0:fbdae7e6d805 | 359 | * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PLL |\ref CLK_CLKDIV1_SC0(x) | |
| borlanic | 0:fbdae7e6d805 | 360 | * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PCLK |\ref CLK_CLKDIV1_SC0(x) | |
| borlanic | 0:fbdae7e6d805 | 361 | * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HIRC |\ref CLK_CLKDIV1_SC0(x) | |
| borlanic | 0:fbdae7e6d805 | 362 | * |\ref PS2_MODULE |\ref CLK_CLKSEL3_I2S1SEL_HXT | x | |
| borlanic | 0:fbdae7e6d805 | 363 | * |\ref I2S1_MODULE |\ref CLK_CLKSEL3_I2S1SEL_HXT | x | |
| borlanic | 0:fbdae7e6d805 | 364 | * |\ref I2S1_MODULE |\ref CLK_CLKSEL3_I2S1SEL_PLL | x | |
| borlanic | 0:fbdae7e6d805 | 365 | * |\ref I2S1_MODULE |\ref CLK_CLKSEL3_I2S1SEL_PCLK | x | |
| borlanic | 0:fbdae7e6d805 | 366 | * |\ref I2S1_MODULE |\ref CLK_CLKSEL3_I2S1SEL_HIRC | x | |
| borlanic | 0:fbdae7e6d805 | 367 | * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_HXT | x | |
| borlanic | 0:fbdae7e6d805 | 368 | * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_PLL | x | |
| borlanic | 0:fbdae7e6d805 | 369 | * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_PCLK | x | |
| borlanic | 0:fbdae7e6d805 | 370 | * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_HIRC | x | |
| borlanic | 0:fbdae7e6d805 | 371 | * |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_HXT |\ref CLK_CLKDIV0_ADC(x) | |
| borlanic | 0:fbdae7e6d805 | 372 | * |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_PLL |\ref CLK_CLKDIV0_ADC(x) | |
| borlanic | 0:fbdae7e6d805 | 373 | * |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_PCLK |\ref CLK_CLKDIV0_ADC(x) | |
| borlanic | 0:fbdae7e6d805 | 374 | * |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_HIRC |\ref CLK_CLKDIV0_ADC(x) | |
| borlanic | 0:fbdae7e6d805 | 375 | * |\ref OTG_MODULE | x | x | |
| borlanic | 0:fbdae7e6d805 | 376 | * |\ref CAN1_MODULE | x | x | |
| borlanic | 0:fbdae7e6d805 | 377 | * |\ref CAN0_MODULE | x | x | |
| borlanic | 0:fbdae7e6d805 | 378 | * |\ref UART5_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) | |
| borlanic | 0:fbdae7e6d805 | 379 | * |\ref UART5_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) | |
| borlanic | 0:fbdae7e6d805 | 380 | * |\ref UART5_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) | |
| borlanic | 0:fbdae7e6d805 | 381 | * |\ref UART4_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) | |
| borlanic | 0:fbdae7e6d805 | 382 | * |\ref UART4_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) | |
| borlanic | 0:fbdae7e6d805 | 383 | * |\ref UART4_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) | |
| borlanic | 0:fbdae7e6d805 | 384 | * |\ref UART3_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) | |
| borlanic | 0:fbdae7e6d805 | 385 | * |\ref UART3_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) | |
| borlanic | 0:fbdae7e6d805 | 386 | * |\ref UART3_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) | |
| borlanic | 0:fbdae7e6d805 | 387 | * |\ref UART2_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) | |
| borlanic | 0:fbdae7e6d805 | 388 | * |\ref UART2_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) | |
| borlanic | 0:fbdae7e6d805 | 389 | * |\ref UART2_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) | |
| borlanic | 0:fbdae7e6d805 | 390 | * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) | |
| borlanic | 0:fbdae7e6d805 | 391 | * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) | |
| borlanic | 0:fbdae7e6d805 | 392 | * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) | |
| borlanic | 0:fbdae7e6d805 | 393 | * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) | |
| borlanic | 0:fbdae7e6d805 | 394 | * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) | |
| borlanic | 0:fbdae7e6d805 | 395 | * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) | |
| borlanic | 0:fbdae7e6d805 | 396 | * |\ref SPI3_MODULE |\ref CLK_CLKSEL1_SPI3SEL_PLL | x | |
| borlanic | 0:fbdae7e6d805 | 397 | * |\ref SPI3_MODULE |\ref CLK_CLKSEL1_SPI3SEL_PCLK | x | |
| borlanic | 0:fbdae7e6d805 | 398 | * |\ref SPI2_MODULE |\ref CLK_CLKSEL1_SPI2SEL_PLL | x | |
| borlanic | 0:fbdae7e6d805 | 399 | * |\ref SPI2_MODULE |\ref CLK_CLKSEL1_SPI2SEL_PCLK | x | |
| borlanic | 0:fbdae7e6d805 | 400 | * |\ref SPI1_MODULE |\ref CLK_CLKSEL1_SPI1SEL_PLL | x | |
| borlanic | 0:fbdae7e6d805 | 401 | * |\ref SPI1_MODULE |\ref CLK_CLKSEL1_SPI1SEL_PCLK | x | |
| borlanic | 0:fbdae7e6d805 | 402 | * |\ref SPI0_MODULE |\ref CLK_CLKSEL1_SPI0SEL_PLL | x | |
| borlanic | 0:fbdae7e6d805 | 403 | * |\ref SPI0_MODULE |\ref CLK_CLKSEL1_SPI0SEL_PCLK | x | |
| borlanic | 0:fbdae7e6d805 | 404 | * |\ref I2C3_MODULE | x | x | |
| borlanic | 0:fbdae7e6d805 | 405 | * |\ref I2C2_MODULE | x | x | |
| borlanic | 0:fbdae7e6d805 | 406 | * |\ref I2C1_MODULE | x | x | |
| borlanic | 0:fbdae7e6d805 | 407 | * |\ref I2C0_MODULE | x | x | |
| borlanic | 0:fbdae7e6d805 | 408 | * |\ref ACMP_MODULE | x | x | |
| borlanic | 0:fbdae7e6d805 | 409 | * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HXT | x | |
| borlanic | 0:fbdae7e6d805 | 410 | * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_LXT | x | |
| borlanic | 0:fbdae7e6d805 | 411 | * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HCLK | x | |
| borlanic | 0:fbdae7e6d805 | 412 | * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HIRC | x | |
| borlanic | 0:fbdae7e6d805 | 413 | * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HXT | x | |
| borlanic | 0:fbdae7e6d805 | 414 | * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LXT | x | |
| borlanic | 0:fbdae7e6d805 | 415 | * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_PCLK | x | |
| borlanic | 0:fbdae7e6d805 | 416 | * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LIRC | x | |
| borlanic | 0:fbdae7e6d805 | 417 | * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_EXT | x | |
| borlanic | 0:fbdae7e6d805 | 418 | * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HIRC | x | |
| borlanic | 0:fbdae7e6d805 | 419 | * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HXT | x | |
| borlanic | 0:fbdae7e6d805 | 420 | * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LXT | x | |
| borlanic | 0:fbdae7e6d805 | 421 | * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_PCLK | x | |
| borlanic | 0:fbdae7e6d805 | 422 | * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LIRC | x | |
| borlanic | 0:fbdae7e6d805 | 423 | * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_EXT | x | |
| borlanic | 0:fbdae7e6d805 | 424 | * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HIRC | x | |
| borlanic | 0:fbdae7e6d805 | 425 | * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HXT | x | |
| borlanic | 0:fbdae7e6d805 | 426 | * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LXT | x | |
| borlanic | 0:fbdae7e6d805 | 427 | * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_PCLK | x | |
| borlanic | 0:fbdae7e6d805 | 428 | * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LIRC | x | |
| borlanic | 0:fbdae7e6d805 | 429 | * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_EXT | x | |
| borlanic | 0:fbdae7e6d805 | 430 | * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HIRC | x | |
| borlanic | 0:fbdae7e6d805 | 431 | * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HXT | x | |
| borlanic | 0:fbdae7e6d805 | 432 | * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LXT | x | |
| borlanic | 0:fbdae7e6d805 | 433 | * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_PCLK | x | |
| borlanic | 0:fbdae7e6d805 | 434 | * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LIRC | x | |
| borlanic | 0:fbdae7e6d805 | 435 | * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_EXT | x | |
| borlanic | 0:fbdae7e6d805 | 436 | * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HIRC | x | |
| borlanic | 0:fbdae7e6d805 | 437 | * |\ref RTC_MODULE | x | x | |
| borlanic | 0:fbdae7e6d805 | 438 | * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 | x | |
| borlanic | 0:fbdae7e6d805 | 439 | * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_LIRC | x | |
| borlanic | 0:fbdae7e6d805 | 440 | * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LXT | x | |
| borlanic | 0:fbdae7e6d805 | 441 | * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 | x | |
| borlanic | 0:fbdae7e6d805 | 442 | * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LIRC | x | |
| borlanic | 0:fbdae7e6d805 | 443 | * |
| borlanic | 0:fbdae7e6d805 | 444 | */ |
| borlanic | 0:fbdae7e6d805 | 445 | |
| borlanic | 0:fbdae7e6d805 | 446 | void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv) |
| borlanic | 0:fbdae7e6d805 | 447 | { |
| borlanic | 0:fbdae7e6d805 | 448 | uint32_t u32tmp=0,u32sel=0,u32div=0; |
| borlanic | 0:fbdae7e6d805 | 449 | |
| borlanic | 0:fbdae7e6d805 | 450 | if(MODULE_CLKDIV_Msk(u32ModuleIdx)!=MODULE_NoMsk) { |
| borlanic | 0:fbdae7e6d805 | 451 | u32div =(uint32_t)&CLK->CLKDIV0+((MODULE_CLKDIV(u32ModuleIdx))*4); |
| borlanic | 0:fbdae7e6d805 | 452 | u32tmp = *(volatile uint32_t *)(u32div); |
| borlanic | 0:fbdae7e6d805 | 453 | u32tmp = ( u32tmp & ~(MODULE_CLKDIV_Msk(u32ModuleIdx)<<MODULE_CLKDIV_Pos(u32ModuleIdx)) ) | u32ClkDiv; |
| borlanic | 0:fbdae7e6d805 | 454 | *(volatile uint32_t *)(u32div) = u32tmp; |
| borlanic | 0:fbdae7e6d805 | 455 | } |
| borlanic | 0:fbdae7e6d805 | 456 | |
| borlanic | 0:fbdae7e6d805 | 457 | if(MODULE_CLKSEL_Msk(u32ModuleIdx)!=MODULE_NoMsk) { |
| borlanic | 0:fbdae7e6d805 | 458 | u32sel = (uint32_t)&CLK->CLKSEL0+((MODULE_CLKSEL(u32ModuleIdx))*4); |
| borlanic | 0:fbdae7e6d805 | 459 | u32tmp = *(volatile uint32_t *)(u32sel); |
| borlanic | 0:fbdae7e6d805 | 460 | u32tmp = ( u32tmp & ~(MODULE_CLKSEL_Msk(u32ModuleIdx)<<MODULE_CLKSEL_Pos(u32ModuleIdx)) ) | u32ClkSrc; |
| borlanic | 0:fbdae7e6d805 | 461 | *(volatile uint32_t *)(u32sel) = u32tmp; |
| borlanic | 0:fbdae7e6d805 | 462 | } |
| borlanic | 0:fbdae7e6d805 | 463 | } |
| borlanic | 0:fbdae7e6d805 | 464 | |
| borlanic | 0:fbdae7e6d805 | 465 | /** |
| borlanic | 0:fbdae7e6d805 | 466 | * @brief This function enable clock source |
| borlanic | 0:fbdae7e6d805 | 467 | * @param u32ClkMask is clock source mask. Including: |
| borlanic | 0:fbdae7e6d805 | 468 | * - \ref CLK_PWRCTL_HXTEN_Msk |
| borlanic | 0:fbdae7e6d805 | 469 | * - \ref CLK_PWRCTL_LXTEN_Msk |
| borlanic | 0:fbdae7e6d805 | 470 | * - \ref CLK_PWRCTL_HIRCEN_Msk |
| borlanic | 0:fbdae7e6d805 | 471 | * - \ref CLK_PWRCTL_LIRCEN_Msk |
| borlanic | 0:fbdae7e6d805 | 472 | * @return None |
| borlanic | 0:fbdae7e6d805 | 473 | */ |
| borlanic | 0:fbdae7e6d805 | 474 | void CLK_EnableXtalRC(uint32_t u32ClkMask) |
| borlanic | 0:fbdae7e6d805 | 475 | { |
| borlanic | 0:fbdae7e6d805 | 476 | CLK->PWRCTL |= u32ClkMask; |
| borlanic | 0:fbdae7e6d805 | 477 | } |
| borlanic | 0:fbdae7e6d805 | 478 | |
| borlanic | 0:fbdae7e6d805 | 479 | /** |
| borlanic | 0:fbdae7e6d805 | 480 | * @brief This function disable clock source |
| borlanic | 0:fbdae7e6d805 | 481 | * @param u32ClkMask is clock source mask. Including: |
| borlanic | 0:fbdae7e6d805 | 482 | * - \ref CLK_PWRCTL_HXTEN_Msk |
| borlanic | 0:fbdae7e6d805 | 483 | * - \ref CLK_PWRCTL_LXTEN_Msk |
| borlanic | 0:fbdae7e6d805 | 484 | * - \ref CLK_PWRCTL_HIRCEN_Msk |
| borlanic | 0:fbdae7e6d805 | 485 | * - \ref CLK_PWRCTL_LIRCEN_Msk |
| borlanic | 0:fbdae7e6d805 | 486 | * @return None |
| borlanic | 0:fbdae7e6d805 | 487 | */ |
| borlanic | 0:fbdae7e6d805 | 488 | void CLK_DisableXtalRC(uint32_t u32ClkMask) |
| borlanic | 0:fbdae7e6d805 | 489 | { |
| borlanic | 0:fbdae7e6d805 | 490 | CLK->PWRCTL &= ~u32ClkMask; |
| borlanic | 0:fbdae7e6d805 | 491 | } |
| borlanic | 0:fbdae7e6d805 | 492 | |
| borlanic | 0:fbdae7e6d805 | 493 | /** |
| borlanic | 0:fbdae7e6d805 | 494 | * @brief This function enable module clock |
| borlanic | 0:fbdae7e6d805 | 495 | * @param[in] u32ModuleIdx is module index. Including : |
| borlanic | 0:fbdae7e6d805 | 496 | * - \ref PDMA_MODULE |
| borlanic | 0:fbdae7e6d805 | 497 | * - \ref ISP_MODULE |
| borlanic | 0:fbdae7e6d805 | 498 | * - \ref EBI_MODULE |
| borlanic | 0:fbdae7e6d805 | 499 | * - \ref USBH_MODULE |
| borlanic | 0:fbdae7e6d805 | 500 | * - \ref EMAC_MODULE |
| borlanic | 0:fbdae7e6d805 | 501 | * - \ref SDH_MODULE |
| borlanic | 0:fbdae7e6d805 | 502 | * - \ref CRC_MODULE |
| borlanic | 0:fbdae7e6d805 | 503 | * - \ref CAP_MODULE |
| borlanic | 0:fbdae7e6d805 | 504 | * - \ref USBD_MODULE |
| borlanic | 0:fbdae7e6d805 | 505 | * - \ref CRPT_MODULE |
| borlanic | 0:fbdae7e6d805 | 506 | * - \ref WDT_MODULE |
| borlanic | 0:fbdae7e6d805 | 507 | * - \ref WWDT_MODULE |
| borlanic | 0:fbdae7e6d805 | 508 | * - \ref RTC_MODULE |
| borlanic | 0:fbdae7e6d805 | 509 | * - \ref TMR0_MODULE |
| borlanic | 0:fbdae7e6d805 | 510 | * - \ref TMR1_MODULE |
| borlanic | 0:fbdae7e6d805 | 511 | * - \ref TMR2_MODULE |
| borlanic | 0:fbdae7e6d805 | 512 | * - \ref TMR3_MODULE |
| borlanic | 0:fbdae7e6d805 | 513 | * - \ref CLKO_MODULE |
| borlanic | 0:fbdae7e6d805 | 514 | * - \ref ACMP_MODULE |
| borlanic | 0:fbdae7e6d805 | 515 | * - \ref I2C0_MODULE |
| borlanic | 0:fbdae7e6d805 | 516 | * - \ref I2C1_MODULE |
| borlanic | 0:fbdae7e6d805 | 517 | * - \ref I2C2_MODULE |
| borlanic | 0:fbdae7e6d805 | 518 | * - \ref I2C3_MODULE |
| borlanic | 0:fbdae7e6d805 | 519 | * - \ref SPI0_MODULE |
| borlanic | 0:fbdae7e6d805 | 520 | * - \ref SPI1_MODULE |
| borlanic | 0:fbdae7e6d805 | 521 | * - \ref SPI2_MODULE |
| borlanic | 0:fbdae7e6d805 | 522 | * - \ref SPI3_MODULE |
| borlanic | 0:fbdae7e6d805 | 523 | * - \ref UART0_MODULE |
| borlanic | 0:fbdae7e6d805 | 524 | * - \ref UART1_MODULE |
| borlanic | 0:fbdae7e6d805 | 525 | * - \ref UART2_MODULE |
| borlanic | 0:fbdae7e6d805 | 526 | * - \ref UART3_MODULE |
| borlanic | 0:fbdae7e6d805 | 527 | * - \ref UART4_MODULE |
| borlanic | 0:fbdae7e6d805 | 528 | * - \ref UART5_MODULE |
| borlanic | 0:fbdae7e6d805 | 529 | * - \ref CAN0_MODULE |
| borlanic | 0:fbdae7e6d805 | 530 | * - \ref CAN1_MODULE |
| borlanic | 0:fbdae7e6d805 | 531 | * - \ref OTG_MODULE |
| borlanic | 0:fbdae7e6d805 | 532 | * - \ref ADC_MODULE |
| borlanic | 0:fbdae7e6d805 | 533 | * - \ref I2S0_MODULE |
| borlanic | 0:fbdae7e6d805 | 534 | * - \ref I2S1_MODULE |
| borlanic | 0:fbdae7e6d805 | 535 | * - \ref PS2_MODULE |
| borlanic | 0:fbdae7e6d805 | 536 | * - \ref SC0_MODULE |
| borlanic | 0:fbdae7e6d805 | 537 | * - \ref SC1_MODULE |
| borlanic | 0:fbdae7e6d805 | 538 | * - \ref SC2_MODULE |
| borlanic | 0:fbdae7e6d805 | 539 | * - \ref SC3_MODULE |
| borlanic | 0:fbdae7e6d805 | 540 | * - \ref SC4_MODULE |
| borlanic | 0:fbdae7e6d805 | 541 | * - \ref SC5_MODULE |
| borlanic | 0:fbdae7e6d805 | 542 | * - \ref I2C4_MODULE |
| borlanic | 0:fbdae7e6d805 | 543 | * - \ref PWM0CH01_MODULE |
| borlanic | 0:fbdae7e6d805 | 544 | * - \ref PWM0CH23_MODULE |
| borlanic | 0:fbdae7e6d805 | 545 | * - \ref PWM0CH45_MODULE |
| borlanic | 0:fbdae7e6d805 | 546 | * - \ref PWM1CH01_MODULE |
| borlanic | 0:fbdae7e6d805 | 547 | * - \ref PWM1CH23_MODULE |
| borlanic | 0:fbdae7e6d805 | 548 | * - \ref PWM1CH45_MODULE |
| borlanic | 0:fbdae7e6d805 | 549 | * - \ref QEI0_MODULE |
| borlanic | 0:fbdae7e6d805 | 550 | * - \ref QEI1_MODULE |
| borlanic | 0:fbdae7e6d805 | 551 | * - \ref ECAP0_MODULE |
| borlanic | 0:fbdae7e6d805 | 552 | * - \ref ECAP1_MODULE |
| borlanic | 0:fbdae7e6d805 | 553 | * - \ref EPWM0_MODULE |
| borlanic | 0:fbdae7e6d805 | 554 | * - \ref EPWM1_MODULE |
| borlanic | 0:fbdae7e6d805 | 555 | * - \ref OPA_MODULE |
| borlanic | 0:fbdae7e6d805 | 556 | * - \ref EADC_MODULE |
| borlanic | 0:fbdae7e6d805 | 557 | * @return None |
| borlanic | 0:fbdae7e6d805 | 558 | */ |
| borlanic | 0:fbdae7e6d805 | 559 | void CLK_EnableModuleClock(uint32_t u32ModuleIdx) |
| borlanic | 0:fbdae7e6d805 | 560 | { |
| borlanic | 0:fbdae7e6d805 | 561 | *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK+(MODULE_APBCLK(u32ModuleIdx)*4)) |= 1<<MODULE_IP_EN_Pos(u32ModuleIdx); |
| borlanic | 0:fbdae7e6d805 | 562 | } |
| borlanic | 0:fbdae7e6d805 | 563 | |
| borlanic | 0:fbdae7e6d805 | 564 | /** |
| borlanic | 0:fbdae7e6d805 | 565 | * @brief This function disable module clock |
| borlanic | 0:fbdae7e6d805 | 566 | * @param[in] u32ModuleIdx is module index. Including : |
| borlanic | 0:fbdae7e6d805 | 567 | * - \ref PDMA_MODULE |
| borlanic | 0:fbdae7e6d805 | 568 | * - \ref ISP_MODULE |
| borlanic | 0:fbdae7e6d805 | 569 | * - \ref EBI_MODULE |
| borlanic | 0:fbdae7e6d805 | 570 | * - \ref USBH_MODULE |
| borlanic | 0:fbdae7e6d805 | 571 | * - \ref EMAC_MODULE |
| borlanic | 0:fbdae7e6d805 | 572 | * - \ref SDH_MODULE |
| borlanic | 0:fbdae7e6d805 | 573 | * - \ref CRC_MODULE |
| borlanic | 0:fbdae7e6d805 | 574 | * - \ref CAP_MODULE |
| borlanic | 0:fbdae7e6d805 | 575 | * - \ref USBD_MODULE |
| borlanic | 0:fbdae7e6d805 | 576 | * - \ref CRPT_MODULE |
| borlanic | 0:fbdae7e6d805 | 577 | * - \ref WDT_MODULE |
| borlanic | 0:fbdae7e6d805 | 578 | * - \ref WWDT_MODULE |
| borlanic | 0:fbdae7e6d805 | 579 | * - \ref RTC_MODULE |
| borlanic | 0:fbdae7e6d805 | 580 | * - \ref TMR0_MODULE |
| borlanic | 0:fbdae7e6d805 | 581 | * - \ref TMR1_MODULE |
| borlanic | 0:fbdae7e6d805 | 582 | * - \ref TMR2_MODULE |
| borlanic | 0:fbdae7e6d805 | 583 | * - \ref TMR3_MODULE |
| borlanic | 0:fbdae7e6d805 | 584 | * - \ref CLKO_MODULE |
| borlanic | 0:fbdae7e6d805 | 585 | * - \ref ACMP_MODULE |
| borlanic | 0:fbdae7e6d805 | 586 | * - \ref I2C0_MODULE |
| borlanic | 0:fbdae7e6d805 | 587 | * - \ref I2C1_MODULE |
| borlanic | 0:fbdae7e6d805 | 588 | * - \ref I2C2_MODULE |
| borlanic | 0:fbdae7e6d805 | 589 | * - \ref I2C3_MODULE |
| borlanic | 0:fbdae7e6d805 | 590 | * - \ref SPI0_MODULE |
| borlanic | 0:fbdae7e6d805 | 591 | * - \ref SPI1_MODULE |
| borlanic | 0:fbdae7e6d805 | 592 | * - \ref SPI2_MODULE |
| borlanic | 0:fbdae7e6d805 | 593 | * - \ref SPI3_MODULE |
| borlanic | 0:fbdae7e6d805 | 594 | * - \ref UART0_MODULE |
| borlanic | 0:fbdae7e6d805 | 595 | * - \ref UART1_MODULE |
| borlanic | 0:fbdae7e6d805 | 596 | * - \ref UART2_MODULE |
| borlanic | 0:fbdae7e6d805 | 597 | * - \ref UART3_MODULE |
| borlanic | 0:fbdae7e6d805 | 598 | * - \ref UART4_MODULE |
| borlanic | 0:fbdae7e6d805 | 599 | * - \ref UART5_MODULE |
| borlanic | 0:fbdae7e6d805 | 600 | * - \ref CAN0_MODULE |
| borlanic | 0:fbdae7e6d805 | 601 | * - \ref CAN1_MODULE |
| borlanic | 0:fbdae7e6d805 | 602 | * - \ref OTG_MODULE |
| borlanic | 0:fbdae7e6d805 | 603 | * - \ref ADC_MODULE |
| borlanic | 0:fbdae7e6d805 | 604 | * - \ref I2S0_MODULE |
| borlanic | 0:fbdae7e6d805 | 605 | * - \ref I2S1_MODULE |
| borlanic | 0:fbdae7e6d805 | 606 | * - \ref PS2_MODULE |
| borlanic | 0:fbdae7e6d805 | 607 | * - \ref SC0_MODULE |
| borlanic | 0:fbdae7e6d805 | 608 | * - \ref SC1_MODULE |
| borlanic | 0:fbdae7e6d805 | 609 | * - \ref SC2_MODULE |
| borlanic | 0:fbdae7e6d805 | 610 | * - \ref SC3_MODULE |
| borlanic | 0:fbdae7e6d805 | 611 | * - \ref SC4_MODULE |
| borlanic | 0:fbdae7e6d805 | 612 | * - \ref SC5_MODULE |
| borlanic | 0:fbdae7e6d805 | 613 | * - \ref I2C4_MODULE |
| borlanic | 0:fbdae7e6d805 | 614 | * - \ref PWM0CH01_MODULE |
| borlanic | 0:fbdae7e6d805 | 615 | * - \ref PWM0CH23_MODULE |
| borlanic | 0:fbdae7e6d805 | 616 | * - \ref PWM0CH45_MODULE |
| borlanic | 0:fbdae7e6d805 | 617 | * - \ref PWM1CH01_MODULE |
| borlanic | 0:fbdae7e6d805 | 618 | * - \ref PWM1CH23_MODULE |
| borlanic | 0:fbdae7e6d805 | 619 | * - \ref PWM1CH45_MODULE |
| borlanic | 0:fbdae7e6d805 | 620 | * - \ref QEI0_MODULE |
| borlanic | 0:fbdae7e6d805 | 621 | * - \ref QEI1_MODULE |
| borlanic | 0:fbdae7e6d805 | 622 | * - \ref ECAP0_MODULE |
| borlanic | 0:fbdae7e6d805 | 623 | * - \ref ECAP1_MODULE |
| borlanic | 0:fbdae7e6d805 | 624 | * - \ref EPWM0_MODULE |
| borlanic | 0:fbdae7e6d805 | 625 | * - \ref EPWM1_MODULE |
| borlanic | 0:fbdae7e6d805 | 626 | * - \ref OPA_MODULE |
| borlanic | 0:fbdae7e6d805 | 627 | * - \ref EADC_MODULE |
| borlanic | 0:fbdae7e6d805 | 628 | * @return None |
| borlanic | 0:fbdae7e6d805 | 629 | */ |
| borlanic | 0:fbdae7e6d805 | 630 | void CLK_DisableModuleClock(uint32_t u32ModuleIdx) |
| borlanic | 0:fbdae7e6d805 | 631 | { |
| borlanic | 0:fbdae7e6d805 | 632 | *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK+(MODULE_APBCLK(u32ModuleIdx)*4)) &= ~(1<<MODULE_IP_EN_Pos(u32ModuleIdx)); |
| borlanic | 0:fbdae7e6d805 | 633 | } |
| borlanic | 0:fbdae7e6d805 | 634 | |
| borlanic | 0:fbdae7e6d805 | 635 | /** |
| borlanic | 0:fbdae7e6d805 | 636 | * @brief This function set PLL frequency |
| borlanic | 0:fbdae7e6d805 | 637 | * @param[in] u32PllClkSrc is PLL clock source. Including : |
| borlanic | 0:fbdae7e6d805 | 638 | * - \ref CLK_PLLCTL_PLLSRC_HIRC |
| borlanic | 0:fbdae7e6d805 | 639 | * - \ref CLK_PLLCTL_PLLSRC_HXT |
| borlanic | 0:fbdae7e6d805 | 640 | * @param[in] u32PllFreq is PLL frequency |
| borlanic | 0:fbdae7e6d805 | 641 | * @return None |
| borlanic | 0:fbdae7e6d805 | 642 | */ |
| borlanic | 0:fbdae7e6d805 | 643 | uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq) |
| borlanic | 0:fbdae7e6d805 | 644 | { |
| borlanic | 0:fbdae7e6d805 | 645 | uint32_t u32PllSrcClk, u32NR, u32NF, u32NO, u32CLK_SRC; |
| borlanic | 0:fbdae7e6d805 | 646 | uint32_t u32Tmp, u32Tmp2, u32Tmp3, u32Min, u32MinNF, u32MinNR; |
| borlanic | 0:fbdae7e6d805 | 647 | |
| borlanic | 0:fbdae7e6d805 | 648 | /* Disable PLL first to avoid unstable when setting PLL */ |
| borlanic | 0:fbdae7e6d805 | 649 | CLK_DisablePLL(); |
| borlanic | 0:fbdae7e6d805 | 650 | |
| borlanic | 0:fbdae7e6d805 | 651 | /* PLL source clock is from HXT */ |
| borlanic | 0:fbdae7e6d805 | 652 | if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT) { |
| borlanic | 0:fbdae7e6d805 | 653 | /* Enable HXT clock */ |
| borlanic | 0:fbdae7e6d805 | 654 | CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk; |
| borlanic | 0:fbdae7e6d805 | 655 | |
| borlanic | 0:fbdae7e6d805 | 656 | /* Wait for HXT clock ready */ |
| borlanic | 0:fbdae7e6d805 | 657 | CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); |
| borlanic | 0:fbdae7e6d805 | 658 | |
| borlanic | 0:fbdae7e6d805 | 659 | /* Select PLL source clock from HXT */ |
| borlanic | 0:fbdae7e6d805 | 660 | u32CLK_SRC = CLK_PLLCTL_PLLSRC_HXT; |
| borlanic | 0:fbdae7e6d805 | 661 | u32PllSrcClk = __HXT; |
| borlanic | 0:fbdae7e6d805 | 662 | |
| borlanic | 0:fbdae7e6d805 | 663 | /* u32NR start from 2 */ |
| borlanic | 0:fbdae7e6d805 | 664 | u32NR = 2; |
| borlanic | 0:fbdae7e6d805 | 665 | } |
| borlanic | 0:fbdae7e6d805 | 666 | |
| borlanic | 0:fbdae7e6d805 | 667 | /* PLL source clock is from HIRC */ |
| borlanic | 0:fbdae7e6d805 | 668 | else { |
| borlanic | 0:fbdae7e6d805 | 669 | /* Enable HIRC clock */ |
| borlanic | 0:fbdae7e6d805 | 670 | CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk; |
| borlanic | 0:fbdae7e6d805 | 671 | |
| borlanic | 0:fbdae7e6d805 | 672 | /* Wait for HIRC clock ready */ |
| borlanic | 0:fbdae7e6d805 | 673 | CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); |
| borlanic | 0:fbdae7e6d805 | 674 | |
| borlanic | 0:fbdae7e6d805 | 675 | /* Select PLL source clock from HIRC */ |
| borlanic | 0:fbdae7e6d805 | 676 | u32CLK_SRC = CLK_PLLCTL_PLLSRC_HIRC; |
| borlanic | 0:fbdae7e6d805 | 677 | u32PllSrcClk = __HIRC; |
| borlanic | 0:fbdae7e6d805 | 678 | |
| borlanic | 0:fbdae7e6d805 | 679 | /* u32NR start from 4 when FIN = 22.1184MHz to avoid calculation overflow */ |
| borlanic | 0:fbdae7e6d805 | 680 | u32NR = 4; |
| borlanic | 0:fbdae7e6d805 | 681 | } |
| borlanic | 0:fbdae7e6d805 | 682 | |
| borlanic | 0:fbdae7e6d805 | 683 | /* Select "NO" according to request frequency */ |
| borlanic | 0:fbdae7e6d805 | 684 | if((u32PllFreq <= FREQ_500MHZ) && (u32PllFreq > FREQ_250MHZ)) { |
| borlanic | 0:fbdae7e6d805 | 685 | u32NO = 0; |
| borlanic | 0:fbdae7e6d805 | 686 | } else if((u32PllFreq <= FREQ_250MHZ) && (u32PllFreq > FREQ_125MHZ)) { |
| borlanic | 0:fbdae7e6d805 | 687 | u32NO = 1; |
| borlanic | 0:fbdae7e6d805 | 688 | u32PllFreq = u32PllFreq << 1; |
| borlanic | 0:fbdae7e6d805 | 689 | } else if((u32PllFreq <= FREQ_125MHZ) && (u32PllFreq >= FREQ_50MHZ)) { |
| borlanic | 0:fbdae7e6d805 | 690 | u32NO = 3; |
| borlanic | 0:fbdae7e6d805 | 691 | u32PllFreq = u32PllFreq << 2; |
| borlanic | 0:fbdae7e6d805 | 692 | } else { |
| borlanic | 0:fbdae7e6d805 | 693 | /* Wrong frequency request. Just return default setting. */ |
| borlanic | 0:fbdae7e6d805 | 694 | goto lexit; |
| borlanic | 0:fbdae7e6d805 | 695 | } |
| borlanic | 0:fbdae7e6d805 | 696 | |
| borlanic | 0:fbdae7e6d805 | 697 | /* Find best solution */ |
| borlanic | 0:fbdae7e6d805 | 698 | u32Min = (uint32_t) - 1; |
| borlanic | 0:fbdae7e6d805 | 699 | u32MinNR = 0; |
| borlanic | 0:fbdae7e6d805 | 700 | u32MinNF = 0; |
| borlanic | 0:fbdae7e6d805 | 701 | for(; u32NR <= 33; u32NR++) { |
| borlanic | 0:fbdae7e6d805 | 702 | u32Tmp = u32PllSrcClk / u32NR; |
| borlanic | 0:fbdae7e6d805 | 703 | if((u32Tmp > 1600000) && (u32Tmp < 16000000)) { |
| borlanic | 0:fbdae7e6d805 | 704 | for(u32NF = 2; u32NF <= 513; u32NF++) { |
| borlanic | 0:fbdae7e6d805 | 705 | u32Tmp2 = u32Tmp * u32NF; |
| borlanic | 0:fbdae7e6d805 | 706 | if((u32Tmp2 >= 200000000) && (u32Tmp2 <= 500000000)) { |
| borlanic | 0:fbdae7e6d805 | 707 | u32Tmp3 = (u32Tmp2 > u32PllFreq) ? u32Tmp2 - u32PllFreq : u32PllFreq - u32Tmp2; |
| borlanic | 0:fbdae7e6d805 | 708 | if(u32Tmp3 < u32Min) { |
| borlanic | 0:fbdae7e6d805 | 709 | u32Min = u32Tmp3; |
| borlanic | 0:fbdae7e6d805 | 710 | u32MinNR = u32NR; |
| borlanic | 0:fbdae7e6d805 | 711 | u32MinNF = u32NF; |
| borlanic | 0:fbdae7e6d805 | 712 | |
| borlanic | 0:fbdae7e6d805 | 713 | /* Break when get good results */ |
| borlanic | 0:fbdae7e6d805 | 714 | if(u32Min == 0) |
| borlanic | 0:fbdae7e6d805 | 715 | break; |
| borlanic | 0:fbdae7e6d805 | 716 | } |
| borlanic | 0:fbdae7e6d805 | 717 | } |
| borlanic | 0:fbdae7e6d805 | 718 | } |
| borlanic | 0:fbdae7e6d805 | 719 | } |
| borlanic | 0:fbdae7e6d805 | 720 | } |
| borlanic | 0:fbdae7e6d805 | 721 | |
| borlanic | 0:fbdae7e6d805 | 722 | /* Enable and apply new PLL setting. */ |
| borlanic | 0:fbdae7e6d805 | 723 | CLK->PLLCTL = u32CLK_SRC | (u32NO << 14) | ((u32MinNR - 2) << 9) | (u32MinNF - 2); |
| borlanic | 0:fbdae7e6d805 | 724 | |
| borlanic | 0:fbdae7e6d805 | 725 | /* Wait for PLL clock stable */ |
| borlanic | 0:fbdae7e6d805 | 726 | CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk); |
| borlanic | 0:fbdae7e6d805 | 727 | |
| borlanic | 0:fbdae7e6d805 | 728 | /* Return actual PLL output clock frequency */ |
| borlanic | 0:fbdae7e6d805 | 729 | return u32PllSrcClk / ((u32NO + 1) * u32MinNR) * u32MinNF; |
| borlanic | 0:fbdae7e6d805 | 730 | |
| borlanic | 0:fbdae7e6d805 | 731 | lexit: |
| borlanic | 0:fbdae7e6d805 | 732 | |
| borlanic | 0:fbdae7e6d805 | 733 | /* Apply default PLL setting and return */ |
| borlanic | 0:fbdae7e6d805 | 734 | if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT) |
| borlanic | 0:fbdae7e6d805 | 735 | CLK->PLLCTL = CLK_PLLCTL_84MHz_HXT; /* 84MHz */ |
| borlanic | 0:fbdae7e6d805 | 736 | else |
| borlanic | 0:fbdae7e6d805 | 737 | CLK->PLLCTL = CLK_PLLCTL_50MHz_HIRC; /* 50MHz */ |
| borlanic | 0:fbdae7e6d805 | 738 | |
| borlanic | 0:fbdae7e6d805 | 739 | /* Wait for PLL clock stable */ |
| borlanic | 0:fbdae7e6d805 | 740 | CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk); |
| borlanic | 0:fbdae7e6d805 | 741 | |
| borlanic | 0:fbdae7e6d805 | 742 | return CLK_GetPLLClockFreq(); |
| borlanic | 0:fbdae7e6d805 | 743 | } |
| borlanic | 0:fbdae7e6d805 | 744 | |
| borlanic | 0:fbdae7e6d805 | 745 | /** |
| borlanic | 0:fbdae7e6d805 | 746 | * @brief This function disable PLL |
| borlanic | 0:fbdae7e6d805 | 747 | * @return None |
| borlanic | 0:fbdae7e6d805 | 748 | */ |
| borlanic | 0:fbdae7e6d805 | 749 | void CLK_DisablePLL(void) |
| borlanic | 0:fbdae7e6d805 | 750 | { |
| borlanic | 0:fbdae7e6d805 | 751 | CLK->PLLCTL |= CLK_PLLCTL_PD_Msk; |
| borlanic | 0:fbdae7e6d805 | 752 | } |
| borlanic | 0:fbdae7e6d805 | 753 | |
| borlanic | 0:fbdae7e6d805 | 754 | /** |
| borlanic | 0:fbdae7e6d805 | 755 | * @brief This function set SysTick clock source |
| borlanic | 0:fbdae7e6d805 | 756 | * @param[in] u32ClkSrc is SysTick clock source. Including : |
| borlanic | 0:fbdae7e6d805 | 757 | * - \ref CLK_CLKSEL0_STCLKSEL_HXT |
| borlanic | 0:fbdae7e6d805 | 758 | * - \ref CLK_CLKSEL0_STCLKSEL_LXT |
| borlanic | 0:fbdae7e6d805 | 759 | * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2 |
| borlanic | 0:fbdae7e6d805 | 760 | * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 |
| borlanic | 0:fbdae7e6d805 | 761 | * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 |
| borlanic | 0:fbdae7e6d805 | 762 | * @return None |
| borlanic | 0:fbdae7e6d805 | 763 | */ |
| borlanic | 0:fbdae7e6d805 | 764 | void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc) |
| borlanic | 0:fbdae7e6d805 | 765 | { |
| borlanic | 0:fbdae7e6d805 | 766 | CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc ; |
| borlanic | 0:fbdae7e6d805 | 767 | } |
| borlanic | 0:fbdae7e6d805 | 768 | /** |
| borlanic | 0:fbdae7e6d805 | 769 | * @brief This function execute delay function. |
| borlanic | 0:fbdae7e6d805 | 770 | * @param[in] us Delay time. The Max value is 2^24 / CPU Clock(MHz). Ex: |
| borlanic | 0:fbdae7e6d805 | 771 | * 50MHz => 335544us, 48MHz => 349525us, 28MHz => 699050us ... |
| borlanic | 0:fbdae7e6d805 | 772 | * @return None |
| borlanic | 0:fbdae7e6d805 | 773 | * @details Use the SysTick to generate the delay time and the UNIT is in us. |
| borlanic | 0:fbdae7e6d805 | 774 | * The SysTick clock source is from HCLK, i.e the same as system core clock. |
| borlanic | 0:fbdae7e6d805 | 775 | */ |
| borlanic | 0:fbdae7e6d805 | 776 | void CLK_SysTickDelay(uint32_t us) |
| borlanic | 0:fbdae7e6d805 | 777 | { |
| borlanic | 0:fbdae7e6d805 | 778 | SysTick->LOAD = us * CyclesPerUs; |
| borlanic | 0:fbdae7e6d805 | 779 | SysTick->VAL = (0x00); |
| borlanic | 0:fbdae7e6d805 | 780 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; |
| borlanic | 0:fbdae7e6d805 | 781 | |
| borlanic | 0:fbdae7e6d805 | 782 | /* Waiting for down-count to zero */ |
| borlanic | 0:fbdae7e6d805 | 783 | while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0); |
| borlanic | 0:fbdae7e6d805 | 784 | SysTick->CTRL = 0 ; |
| borlanic | 0:fbdae7e6d805 | 785 | } |
| borlanic | 0:fbdae7e6d805 | 786 | |
| borlanic | 0:fbdae7e6d805 | 787 | /** |
| borlanic | 0:fbdae7e6d805 | 788 | * @brief This function check selected clock source status |
| borlanic | 0:fbdae7e6d805 | 789 | * @param[in] u32ClkMask is selected clock source. Including |
| borlanic | 0:fbdae7e6d805 | 790 | * - \ref CLK_STATUS_CLKSFAIL_Msk |
| borlanic | 0:fbdae7e6d805 | 791 | * - \ref CLK_STATUS_HIRCSTB_Msk |
| borlanic | 0:fbdae7e6d805 | 792 | * - \ref CLK_STATUS_LIRCSTB_Msk |
| borlanic | 0:fbdae7e6d805 | 793 | * - \ref CLK_STATUS_PLLSTB_Msk |
| borlanic | 0:fbdae7e6d805 | 794 | * - \ref CLK_STATUS_LXTSTB_Msk |
| borlanic | 0:fbdae7e6d805 | 795 | * - \ref CLK_STATUS_HXTSTB_Msk |
| borlanic | 0:fbdae7e6d805 | 796 | * |
| borlanic | 0:fbdae7e6d805 | 797 | * @return 0 clock is not stable |
| borlanic | 0:fbdae7e6d805 | 798 | * 1 clock is stable |
| borlanic | 0:fbdae7e6d805 | 799 | * |
| borlanic | 0:fbdae7e6d805 | 800 | * @details To wait for clock ready by specified CLKSTATUS bit or timeout (~300ms) |
| borlanic | 0:fbdae7e6d805 | 801 | */ |
| borlanic | 0:fbdae7e6d805 | 802 | uint32_t CLK_WaitClockReady(uint32_t u32ClkMask) |
| borlanic | 0:fbdae7e6d805 | 803 | { |
| borlanic | 0:fbdae7e6d805 | 804 | int32_t i32TimeOutCnt = 2160000; |
| borlanic | 0:fbdae7e6d805 | 805 | |
| borlanic | 0:fbdae7e6d805 | 806 | while((CLK->STATUS & u32ClkMask) != u32ClkMask) { |
| borlanic | 0:fbdae7e6d805 | 807 | if(i32TimeOutCnt-- <= 0) |
| borlanic | 0:fbdae7e6d805 | 808 | return 0; |
| borlanic | 0:fbdae7e6d805 | 809 | } |
| borlanic | 0:fbdae7e6d805 | 810 | |
| borlanic | 0:fbdae7e6d805 | 811 | return 1; |
| borlanic | 0:fbdae7e6d805 | 812 | } |
| borlanic | 0:fbdae7e6d805 | 813 | |
| borlanic | 0:fbdae7e6d805 | 814 | /** |
| borlanic | 0:fbdae7e6d805 | 815 | * @brief Enable System Tick counter |
| borlanic | 0:fbdae7e6d805 | 816 | * @param[in] u32ClkSrc is System Tick clock source. Including: |
| borlanic | 0:fbdae7e6d805 | 817 | * - \ref CLK_CLKSEL0_STCLKSEL_HXT |
| borlanic | 0:fbdae7e6d805 | 818 | * - \ref CLK_CLKSEL0_STCLKSEL_LXT |
| borlanic | 0:fbdae7e6d805 | 819 | * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2 |
| borlanic | 0:fbdae7e6d805 | 820 | * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 |
| borlanic | 0:fbdae7e6d805 | 821 | * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 |
| borlanic | 0:fbdae7e6d805 | 822 | * - \ref CLK_CLKSEL0_STCLKSEL_HCLK |
| borlanic | 0:fbdae7e6d805 | 823 | * @param[in] u32Count is System Tick reload value. It could be 0~0xFFFFFF. |
| borlanic | 0:fbdae7e6d805 | 824 | * @return None |
| borlanic | 0:fbdae7e6d805 | 825 | * @details This function set System Tick clock source, reload value, enable System Tick counter and interrupt. \n |
| borlanic | 0:fbdae7e6d805 | 826 | * The register write-protection function should be disabled before using this function. |
| borlanic | 0:fbdae7e6d805 | 827 | */ |
| borlanic | 0:fbdae7e6d805 | 828 | void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count) |
| borlanic | 0:fbdae7e6d805 | 829 | { |
| borlanic | 0:fbdae7e6d805 | 830 | /* Set System Tick counter disabled */ |
| borlanic | 0:fbdae7e6d805 | 831 | SysTick->CTRL = 0; |
| borlanic | 0:fbdae7e6d805 | 832 | |
| borlanic | 0:fbdae7e6d805 | 833 | /* Set System Tick clock source */ |
| borlanic | 0:fbdae7e6d805 | 834 | if( u32ClkSrc == CLK_CLKSEL0_STCLKSEL_HCLK ) |
| borlanic | 0:fbdae7e6d805 | 835 | SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk; |
| borlanic | 0:fbdae7e6d805 | 836 | else |
| borlanic | 0:fbdae7e6d805 | 837 | CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc; |
| borlanic | 0:fbdae7e6d805 | 838 | |
| borlanic | 0:fbdae7e6d805 | 839 | /* Set System Tick reload value */ |
| borlanic | 0:fbdae7e6d805 | 840 | SysTick->LOAD = u32Count; |
| borlanic | 0:fbdae7e6d805 | 841 | |
| borlanic | 0:fbdae7e6d805 | 842 | /* Clear System Tick current value and counter flag */ |
| borlanic | 0:fbdae7e6d805 | 843 | SysTick->VAL = 0; |
| borlanic | 0:fbdae7e6d805 | 844 | |
| borlanic | 0:fbdae7e6d805 | 845 | /* Set System Tick interrupt enabled and counter enabled */ |
| borlanic | 0:fbdae7e6d805 | 846 | SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; |
| borlanic | 0:fbdae7e6d805 | 847 | } |
| borlanic | 0:fbdae7e6d805 | 848 | |
| borlanic | 0:fbdae7e6d805 | 849 | /** |
| borlanic | 0:fbdae7e6d805 | 850 | * @brief Disable System Tick counter |
| borlanic | 0:fbdae7e6d805 | 851 | * @param None |
| borlanic | 0:fbdae7e6d805 | 852 | * @return None |
| borlanic | 0:fbdae7e6d805 | 853 | * @details This function disable System Tick counter. |
| borlanic | 0:fbdae7e6d805 | 854 | */ |
| borlanic | 0:fbdae7e6d805 | 855 | void CLK_DisableSysTick(void) |
| borlanic | 0:fbdae7e6d805 | 856 | { |
| borlanic | 0:fbdae7e6d805 | 857 | /* Set System Tick counter disabled */ |
| borlanic | 0:fbdae7e6d805 | 858 | SysTick->CTRL = 0; |
| borlanic | 0:fbdae7e6d805 | 859 | } |
| borlanic | 0:fbdae7e6d805 | 860 | |
| borlanic | 0:fbdae7e6d805 | 861 | /*@}*/ /* end of group NUC472_442_CLK_EXPORTED_FUNCTIONS */ |
| borlanic | 0:fbdae7e6d805 | 862 | |
| borlanic | 0:fbdae7e6d805 | 863 | /*@}*/ /* end of group NUC472_442_CLK_Driver */ |
| borlanic | 0:fbdae7e6d805 | 864 | |
| borlanic | 0:fbdae7e6d805 | 865 | /*@}*/ /* end of group NUC472_442_Device_Driver */ |
| borlanic | 0:fbdae7e6d805 | 866 | |
| borlanic | 0:fbdae7e6d805 | 867 | /*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ |
| borlanic | 0:fbdae7e6d805 | 868 |