Nicolas Borla / Mbed OS BBR_1Ebene

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mbed-os/targets/TARGET_ARM_SSG/TARGET_BEETLE/spi_def.h@0:fbdae7e6d805, 2018-05-14 (annotated)

Committer:
borlanic
Date:
Mon May 14 11:29:06 2018 +0000
Revision:
0:fbdae7e6d805
BBR

Who changed what in which revision?

UserRevisionLine numberNew contents of line
borlanic 0:fbdae7e6d805 1 /* mbed Microcontroller Library
borlanic 0:fbdae7e6d805 2 * Copyright (c) 2015 ARM Limited
borlanic 0:fbdae7e6d805 3 *
borlanic 0:fbdae7e6d805 4 * Licensed under the Apache License, Version 2.0 (the "License");
borlanic 0:fbdae7e6d805 5 * you may not use this file except in compliance with the License.
borlanic 0:fbdae7e6d805 6 * You may obtain a copy of the License at
borlanic 0:fbdae7e6d805 7 *
borlanic 0:fbdae7e6d805 8 * http://www.apache.org/licenses/LICENSE-2.0
borlanic 0:fbdae7e6d805 9 *
borlanic 0:fbdae7e6d805 10 * Unless required by applicable law or agreed to in writing, software
borlanic 0:fbdae7e6d805 11 * distributed under the License is distributed on an "AS IS" BASIS,
borlanic 0:fbdae7e6d805 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
borlanic 0:fbdae7e6d805 13 * See the License for the specific language governing permissions and
borlanic 0:fbdae7e6d805 14 * limitations under the License.
borlanic 0:fbdae7e6d805 15 */
borlanic 0:fbdae7e6d805 16 /*
borlanic 0:fbdae7e6d805 17 * SSP interface Support
borlanic 0:fbdae7e6d805 18 * =====================
borlanic 0:fbdae7e6d805 19 */
borlanic 0:fbdae7e6d805 20
borlanic 0:fbdae7e6d805 21 #ifndef MBED_SPI_DEF_H
borlanic 0:fbdae7e6d805 22 #define MBED_SPI_DEF_H
borlanic 0:fbdae7e6d805 23
borlanic 0:fbdae7e6d805 24 #include <stdint.h> /* standard types definitions */
borlanic 0:fbdae7e6d805 25
borlanic 0:fbdae7e6d805 26 #define Module_ID 0x00090108
borlanic 0:fbdae7e6d805 27
borlanic 0:fbdae7e6d805 28 typedef struct beetle_spi
borlanic 0:fbdae7e6d805 29 {
borlanic 0:fbdae7e6d805 30 __IO uint32_t CONFIG; /* 0x00 RW Configuration Register */
borlanic 0:fbdae7e6d805 31 __I uint32_t IRQ_STATUS; /* 0x04 RO Interrupt Status Register*/
borlanic 0:fbdae7e6d805 32 __O uint32_t IRQ_ENABLE; /* 0x08 WO Interrupt Enable Register*/
borlanic 0:fbdae7e6d805 33 __O uint32_t IRQ_DISABLE; /* 0x0C WO Interrupt Disable Register */
borlanic 0:fbdae7e6d805 34 __I uint32_t IRQ_MASK; /* 0x10 RO Interrupt Mask Register */
borlanic 0:fbdae7e6d805 35 __IO uint32_t SPI_ENABLE; /* 0x14 RW SPI Enable Register */
borlanic 0:fbdae7e6d805 36 __IO uint32_t DELAY; /* 0x18 RW Delay Register */
borlanic 0:fbdae7e6d805 37 __O uint32_t TX_DATA; /* 0x1C WO Transmit Data Register */
borlanic 0:fbdae7e6d805 38 __I uint32_t RX_DATA; /* 0x20 RO Receive Data Register */
borlanic 0:fbdae7e6d805 39 __IO uint32_t SLAVE_IDLE_COUNT; /* 0x24 RW Slave Idle Count Register */
borlanic 0:fbdae7e6d805 40 __IO uint32_t TX_THRESHOLD; /* 0x28 RW TX Threshold Register */
borlanic 0:fbdae7e6d805 41 __IO uint32_t RX_THRESHOLD; /* 0x2C RW RX Threshold Register */
borlanic 0:fbdae7e6d805 42 uint32_t reserved[208];
borlanic 0:fbdae7e6d805 43 __I uint32_t MID; /* 0xFC RO Module ID Register */
borlanic 0:fbdae7e6d805 44 }SPI_TypeDef;
borlanic 0:fbdae7e6d805 45
borlanic 0:fbdae7e6d805 46
borlanic 0:fbdae7e6d805 47 #define SPI0_BASE (0x4000C000ul) /* Shield Header SPI Base Address */
borlanic 0:fbdae7e6d805 48 #define SPI1_BASE (0x4000D000ul) /* ADC SPI Base Address */
borlanic 0:fbdae7e6d805 49
borlanic 0:fbdae7e6d805 50 #define SHIELD_SPI ((SPI_TypeDef *) SPI0_BASE )
borlanic 0:fbdae7e6d805 51 #define ADC_SPI ((SPI_TypeDef *) SPI1_BASE )
borlanic 0:fbdae7e6d805 52
borlanic 0:fbdae7e6d805 53 /* Configuration Register Bit Masks */
borlanic 0:fbdae7e6d805 54 #define CONFIG_MSEL 0x00001 // Bit [00] MSEL Mode Select
borlanic 0:fbdae7e6d805 55 #define CONFIG_CPOL 0x00002 // Bit [01] CPOL External Clock Edge
borlanic 0:fbdae7e6d805 56 #define CONFIG_CPHA 0x00004 // Bit [02] CPHA Clock Phase
borlanic 0:fbdae7e6d805 57 #define CONFIG_MBRD 0x00038 // Bits [05:03] MBRD Master Baud Rate Divisor (2 to 256)
borlanic 0:fbdae7e6d805 58 #define CONFIG_MBRD_0 0x00008
borlanic 0:fbdae7e6d805 59 #define CONFIG_MBRD_1 0x00010
borlanic 0:fbdae7e6d805 60 #define CONFIG_MBRD_2 0x00020
borlanic 0:fbdae7e6d805 61 #define CONFIG_MBRD_SHIFT 3
borlanic 0:fbdae7e6d805 62 #define CONFIG_TWS 0x000C0 // Bits [07:06] TWS Transfer Word Size
borlanic 0:fbdae7e6d805 63 #define CONFIG_TWS_0 0x00000
borlanic 0:fbdae7e6d805 64 #define CONFIG_TWS_1 0x00040
borlanic 0:fbdae7e6d805 65 #define CONFIG_MRCS 0x00100 // Bit [08] MRCS Reference Clock Select
borlanic 0:fbdae7e6d805 66 #define CONFIG_PSD 0x00200 // Bit [09] PSD Peripheral Select Decode
borlanic 0:fbdae7e6d805 67 #define CONFIG_PCSL 0x03C00 // Bits [13:10] PCSL Peripheral Chip Select Lines (master mode only)
borlanic 0:fbdae7e6d805 68 #define CONFIG_MCSE 0x04000 // Bit [14] MCSE Manual Chip Select Enable
borlanic 0:fbdae7e6d805 69 #define CONFIG_MSE 0x08000 // Bit [15] MSE Manual Start Enable
borlanic 0:fbdae7e6d805 70 #define CONFIG_MSC 0x10000 // Bit [16] MSC Manual Start Command
borlanic 0:fbdae7e6d805 71 #define CONFIG_MFGE 0x20000 // Bit [17] MFGE Mode Fail Generation Enable
borlanic 0:fbdae7e6d805 72 #define CONFIG_SPSE 0x40000 // Bit [18] SPSE Sample Point Shift Enable
borlanic 0:fbdae7e6d805 73
borlanic 0:fbdae7e6d805 74 /* Interrupt Status Register Bit Masks */
borlanic 0:fbdae7e6d805 75 #define IRQ_STATUS_ROF 0x01 // Bit [00] ROF RX FIFO Overflow
borlanic 0:fbdae7e6d805 76 #define IRQ_STATUS_MF 0x02 // Bit [01] MF Mode Fail
borlanic 0:fbdae7e6d805 77 #define IRQ_STATUS_TNF 0x04 // Bit [02] TNF TX FIFO Not Full (current FIFO status)
borlanic 0:fbdae7e6d805 78 #define IRQ_STATUS_TF 0x08 // Bit [03] TF TX FIFO Full (current FIFO status)
borlanic 0:fbdae7e6d805 79 #define IRQ_STATUS_RNE 0x10 // Bit [04] RNE RX FIFO Not Empty (current FIFO status)
borlanic 0:fbdae7e6d805 80 #define IRQ_STATUS_RF 0x20 // Bit [05] RF RX FIFO Full (current FIFO status)
borlanic 0:fbdae7e6d805 81 #define IRQ_STATUS_TUF 0x40 // Bit [06] TUF TX FIFO Underflow
borlanic 0:fbdae7e6d805 82
borlanic 0:fbdae7e6d805 83 /* Interrupt Enable Register Bit Masks */
borlanic 0:fbdae7e6d805 84 #define IRQ_ENABLE_ROFE 0x01 // Bit [00] ROFE RX FIFO Overflow Enable
borlanic 0:fbdae7e6d805 85 #define IRQ_ENABLE_MFE 0x02 // Bit [01] MFE Mode Fail Enable
borlanic 0:fbdae7e6d805 86 #define IRQ_ENABLE_TNFE 0x04 // Bit [02] TNFE TX FIFO Not Full Enable
borlanic 0:fbdae7e6d805 87 #define IRQ_ENABLE_TFE 0x08 // Bit [03] TFE TX FIFO Full Enable
borlanic 0:fbdae7e6d805 88 #define IRQ_ENABLE_RNEE 0x10 // Bit [04] RNEE RX FIFO Not Empty Enable
borlanic 0:fbdae7e6d805 89 #define IRQ_ENABLE_RFE 0x20 // Bit [05] RFE RX FIFO Full Enable
borlanic 0:fbdae7e6d805 90 #define IRQ_ENABLE_TUFE 0x40 // Bit [06] TUFE TX FIFO Underflow Enable
borlanic 0:fbdae7e6d805 91
borlanic 0:fbdae7e6d805 92 /* Interrupt Disable Register Bit Masks */
borlanic 0:fbdae7e6d805 93 #define IRQ_DISABLE_ROFD 0x01 // Bit [00] ROFD RX FIFO Overflow Disable
borlanic 0:fbdae7e6d805 94 #define IRQ_DISABLE_MFD 0x02 // Bit [01] MFD Mode Fail Disable
borlanic 0:fbdae7e6d805 95 #define IRQ_DISABLE_TNFD 0x04 // Bit [02] TNFD TX FIFO Not Full Disable
borlanic 0:fbdae7e6d805 96 #define IRQ_DISABLE_TFD 0x08 // Bit [03] TFD TX FIFO Full Disable
borlanic 0:fbdae7e6d805 97 #define IRQ_DISABLE_RNED 0x10 // Bit [04] RNED RX FIFO Not Empty Disable
borlanic 0:fbdae7e6d805 98 #define IRQ_DISABLE_RFD 0x20 // Bit [05] RFD RX FIFO Full Disable
borlanic 0:fbdae7e6d805 99 #define IRQ_DISABLE_TUFD 0x40 // Bit [06] TUFD TX FIFO Underflow Disable
borlanic 0:fbdae7e6d805 100
borlanic 0:fbdae7e6d805 101 /* Interrupt Mask Register Bit Masks */
borlanic 0:fbdae7e6d805 102 #define IRQ_MASK_ROFM 0x01 // Bit [00] ROFM RX FIFO Overflow Mask
borlanic 0:fbdae7e6d805 103 #define IRQ_MASK_MFM 0x02 // Bit [01] MFM Mode Fail Mask
borlanic 0:fbdae7e6d805 104 #define IRQ_MASK_TNFM 0x04 // Bit [02] TNFM TX FIFO Not Full Mask
borlanic 0:fbdae7e6d805 105 #define IRQ_MASK_TFM 0x08 // Bit [03] TFM TX FIFO Full Mask
borlanic 0:fbdae7e6d805 106 #define IRQ_MASK_RNEM 0x10 // Bit [04] RNEM RX FIFO Not Empty Mask
borlanic 0:fbdae7e6d805 107 #define IRQ_MASK_RFM 0x20 // Bit [05] RFM RX FIFO Full Mask
borlanic 0:fbdae7e6d805 108 #define IRQ_MASK_TUFM 0x40 // Bit [06] TUFM TX FIFO Underflow Mask
borlanic 0:fbdae7e6d805 109
borlanic 0:fbdae7e6d805 110 /* SPI Enable Register Bit Masks */
borlanic 0:fbdae7e6d805 111 #define SPI_ENABLE_SPIE 0x01 // Bit [00] SPIE SPI Enable
borlanic 0:fbdae7e6d805 112
borlanic 0:fbdae7e6d805 113 /* Delay Register Bit Masks */
borlanic 0:fbdae7e6d805 114 #define DELAY_D_INIT 0x000000FF // Bits [07:00] D_INIT Delay Init
borlanic 0:fbdae7e6d805 115 #define DELAY_D_AFTER 0x0000FF00 // Bits [15:08] D_AFTER Delay After
borlanic 0:fbdae7e6d805 116 #define DELAY_D_BTWN 0x00FF0000 // Bits [23:16] D_BTWN Delay Between
borlanic 0:fbdae7e6d805 117 #define DELAY_D_NSS 0xFF000000 // Bits [31:24] D_NSS Delay NSS
borlanic 0:fbdae7e6d805 118
borlanic 0:fbdae7e6d805 119 /* Transmit Data Register Bit Masks */
borlanic 0:fbdae7e6d805 120 #define TX_DATA_TDATA 0xFF
borlanic 0:fbdae7e6d805 121
borlanic 0:fbdae7e6d805 122 /* Receive Data Register Bit Masks */
borlanic 0:fbdae7e6d805 123 #define RX_DATA_RDATA 0xFF
borlanic 0:fbdae7e6d805 124
borlanic 0:fbdae7e6d805 125 /* Slave Idle Count Register Bit Masks */
borlanic 0:fbdae7e6d805 126 #define SLAVE_IDLE_COUNT_SICNT 0xFF // Bits [07:00] SICNT Slave Idle Count
borlanic 0:fbdae7e6d805 127
borlanic 0:fbdae7e6d805 128 /* TX Threshold Register Bit Masks */
borlanic 0:fbdae7e6d805 129 #define TX_THRESHOLD_TTRSH 0x07 // Bits [N:00] TTRSH TX Threshold
borlanic 0:fbdae7e6d805 130
borlanic 0:fbdae7e6d805 131 /* RX Threshold Register Bit Masks */
borlanic 0:fbdae7e6d805 132 #define RX_THRESHOLD_RTRSH 0x07 // Bits [N:00] RTRSH RX Threshold
borlanic 0:fbdae7e6d805 133
borlanic 0:fbdae7e6d805 134 #endif