Nicolas Borla / Mbed OS BBR_1Ebene

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mbed-os/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_xbara.c@0:fbdae7e6d805, 2018-05-14 (annotated)

Committer:
borlanic
Date:
Mon May 14 11:29:06 2018 +0000
Revision:
0:fbdae7e6d805
BBR

Who changed what in which revision?

UserRevisionLine numberNew contents of line
borlanic 0:fbdae7e6d805 1 /*
borlanic 0:fbdae7e6d805 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
borlanic 0:fbdae7e6d805 3 * Copyright 2016-2017 NXP
borlanic 0:fbdae7e6d805 4 *
borlanic 0:fbdae7e6d805 5 * Redistribution and use in source and binary forms, with or without modification,
borlanic 0:fbdae7e6d805 6 * are permitted provided that the following conditions are met:
borlanic 0:fbdae7e6d805 7 *
borlanic 0:fbdae7e6d805 8 * o Redistributions of source code must retain the above copyright notice, this list
borlanic 0:fbdae7e6d805 9 * of conditions and the following disclaimer.
borlanic 0:fbdae7e6d805 10 *
borlanic 0:fbdae7e6d805 11 * o Redistributions in binary form must reproduce the above copyright notice, this
borlanic 0:fbdae7e6d805 12 * list of conditions and the following disclaimer in the documentation and/or
borlanic 0:fbdae7e6d805 13 * other materials provided with the distribution.
borlanic 0:fbdae7e6d805 14 *
borlanic 0:fbdae7e6d805 15 * o Neither the name of the copyright holder nor the names of its
borlanic 0:fbdae7e6d805 16 * contributors may be used to endorse or promote products derived from this
borlanic 0:fbdae7e6d805 17 * software without specific prior written permission.
borlanic 0:fbdae7e6d805 18 *
borlanic 0:fbdae7e6d805 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
borlanic 0:fbdae7e6d805 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
borlanic 0:fbdae7e6d805 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
borlanic 0:fbdae7e6d805 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
borlanic 0:fbdae7e6d805 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
borlanic 0:fbdae7e6d805 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
borlanic 0:fbdae7e6d805 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
borlanic 0:fbdae7e6d805 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
borlanic 0:fbdae7e6d805 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
borlanic 0:fbdae7e6d805 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
borlanic 0:fbdae7e6d805 29 */
borlanic 0:fbdae7e6d805 30
borlanic 0:fbdae7e6d805 31 #include "fsl_xbara.h"
borlanic 0:fbdae7e6d805 32
borlanic 0:fbdae7e6d805 33 /*******************************************************************************
borlanic 0:fbdae7e6d805 34 * Definitions
borlanic 0:fbdae7e6d805 35 ******************************************************************************/
borlanic 0:fbdae7e6d805 36
borlanic 0:fbdae7e6d805 37 /*******************************************************************************
borlanic 0:fbdae7e6d805 38 * Prototypes
borlanic 0:fbdae7e6d805 39 ******************************************************************************/
borlanic 0:fbdae7e6d805 40
borlanic 0:fbdae7e6d805 41 /*!
borlanic 0:fbdae7e6d805 42 * @brief Get the XBARA instance from peripheral base address.
borlanic 0:fbdae7e6d805 43 *
borlanic 0:fbdae7e6d805 44 * @param base XBARA peripheral base address.
borlanic 0:fbdae7e6d805 45 * @return XBARA instance.
borlanic 0:fbdae7e6d805 46 */
borlanic 0:fbdae7e6d805 47 static uint32_t XBARA_GetInstance(XBARA_Type *base);
borlanic 0:fbdae7e6d805 48
borlanic 0:fbdae7e6d805 49 /*******************************************************************************
borlanic 0:fbdae7e6d805 50 * Variables
borlanic 0:fbdae7e6d805 51 ******************************************************************************/
borlanic 0:fbdae7e6d805 52
borlanic 0:fbdae7e6d805 53 /* Array of XBARA peripheral base address. */
borlanic 0:fbdae7e6d805 54 static XBARA_Type *const s_xbaraBases[] = XBARA_BASE_PTRS;
borlanic 0:fbdae7e6d805 55
borlanic 0:fbdae7e6d805 56 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
borlanic 0:fbdae7e6d805 57 /* Array of XBARA clock name. */
borlanic 0:fbdae7e6d805 58 static const clock_ip_name_t s_xbaraClock[] = XBARA_CLOCKS;
borlanic 0:fbdae7e6d805 59 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
borlanic 0:fbdae7e6d805 60
borlanic 0:fbdae7e6d805 61 /*******************************************************************************
borlanic 0:fbdae7e6d805 62 * Code
borlanic 0:fbdae7e6d805 63 ******************************************************************************/
borlanic 0:fbdae7e6d805 64
borlanic 0:fbdae7e6d805 65 static uint32_t XBARA_GetInstance(XBARA_Type *base)
borlanic 0:fbdae7e6d805 66 {
borlanic 0:fbdae7e6d805 67 uint32_t instance;
borlanic 0:fbdae7e6d805 68
borlanic 0:fbdae7e6d805 69 /* Find the instance index from base address mappings. */
borlanic 0:fbdae7e6d805 70 for (instance = 0; instance < ARRAY_SIZE(s_xbaraBases); instance++)
borlanic 0:fbdae7e6d805 71 {
borlanic 0:fbdae7e6d805 72 if (s_xbaraBases[instance] == base)
borlanic 0:fbdae7e6d805 73 {
borlanic 0:fbdae7e6d805 74 break;
borlanic 0:fbdae7e6d805 75 }
borlanic 0:fbdae7e6d805 76 }
borlanic 0:fbdae7e6d805 77
borlanic 0:fbdae7e6d805 78 assert(instance < ARRAY_SIZE(s_xbaraBases));
borlanic 0:fbdae7e6d805 79
borlanic 0:fbdae7e6d805 80 return instance;
borlanic 0:fbdae7e6d805 81 }
borlanic 0:fbdae7e6d805 82
borlanic 0:fbdae7e6d805 83 void XBARA_Init(XBARA_Type *base)
borlanic 0:fbdae7e6d805 84 {
borlanic 0:fbdae7e6d805 85 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
borlanic 0:fbdae7e6d805 86 /* Enable XBARA module clock. */
borlanic 0:fbdae7e6d805 87 CLOCK_EnableClock(s_xbaraClock[XBARA_GetInstance(base)]);
borlanic 0:fbdae7e6d805 88 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
borlanic 0:fbdae7e6d805 89 }
borlanic 0:fbdae7e6d805 90
borlanic 0:fbdae7e6d805 91 void XBARA_Deinit(XBARA_Type *base)
borlanic 0:fbdae7e6d805 92 {
borlanic 0:fbdae7e6d805 93 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
borlanic 0:fbdae7e6d805 94 /* Disable XBARA module clock. */
borlanic 0:fbdae7e6d805 95 CLOCK_DisableClock(s_xbaraClock[XBARA_GetInstance(base)]);
borlanic 0:fbdae7e6d805 96 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
borlanic 0:fbdae7e6d805 97 }
borlanic 0:fbdae7e6d805 98
borlanic 0:fbdae7e6d805 99 void XBARA_SetSignalsConnection(XBARA_Type *base, xbar_input_signal_t input, xbar_output_signal_t output)
borlanic 0:fbdae7e6d805 100 {
borlanic 0:fbdae7e6d805 101 XBARA_WR_SELx_SELx(base, (((uint16_t)input) & 0xFFU), (((uint16_t)output) & 0xFFU));
borlanic 0:fbdae7e6d805 102 }
borlanic 0:fbdae7e6d805 103
borlanic 0:fbdae7e6d805 104 uint32_t XBARA_GetStatusFlags(XBARA_Type *base)
borlanic 0:fbdae7e6d805 105 {
borlanic 0:fbdae7e6d805 106 uint32_t status_flag;
borlanic 0:fbdae7e6d805 107
borlanic 0:fbdae7e6d805 108 status_flag = ((base->CTRL0 & (XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK)) |
borlanic 0:fbdae7e6d805 109 ((base->CTRL1 & (XBARA_CTRL1_STS2_MASK | XBARA_CTRL1_STS3_MASK)) << 16U));
borlanic 0:fbdae7e6d805 110
borlanic 0:fbdae7e6d805 111 return status_flag;
borlanic 0:fbdae7e6d805 112 }
borlanic 0:fbdae7e6d805 113
borlanic 0:fbdae7e6d805 114 void XBARA_ClearStatusFlags(XBARA_Type *base, uint32_t mask)
borlanic 0:fbdae7e6d805 115 {
borlanic 0:fbdae7e6d805 116 uint16_t regVal;
borlanic 0:fbdae7e6d805 117
borlanic 0:fbdae7e6d805 118 /* Assign regVal to CTRL0 register's value */
borlanic 0:fbdae7e6d805 119 regVal = (base->CTRL0);
borlanic 0:fbdae7e6d805 120 /* Perform this command to avoid writing 1 into interrupt flag bits */
borlanic 0:fbdae7e6d805 121 regVal &= (uint16_t)(~(XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK));
borlanic 0:fbdae7e6d805 122 /* Write 1 to interrupt flag bits corresponding to mask */
borlanic 0:fbdae7e6d805 123 regVal |= (uint16_t)(mask & (XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK));
borlanic 0:fbdae7e6d805 124 /* Write regVal value into CTRL0 register */
borlanic 0:fbdae7e6d805 125 base->CTRL0 = regVal;
borlanic 0:fbdae7e6d805 126
borlanic 0:fbdae7e6d805 127 /* Assign regVal to CTRL1 register's value */
borlanic 0:fbdae7e6d805 128 regVal = (base->CTRL1);
borlanic 0:fbdae7e6d805 129 /* Perform this command to avoid writing 1 into interrupt flag bits */
borlanic 0:fbdae7e6d805 130 regVal &= (uint16_t)(~(XBARA_CTRL1_STS2_MASK | XBARA_CTRL1_STS3_MASK));
borlanic 0:fbdae7e6d805 131 /* Write 1 to interrupt flag bits corresponding to mask */
borlanic 0:fbdae7e6d805 132 regVal |= (uint16_t)((mask >> 16U) & (XBARA_CTRL1_STS2_MASK | XBARA_CTRL1_STS3_MASK));
borlanic 0:fbdae7e6d805 133 /* Write regVal value into CTRL1 register */
borlanic 0:fbdae7e6d805 134 base->CTRL1 = regVal;
borlanic 0:fbdae7e6d805 135 }
borlanic 0:fbdae7e6d805 136
borlanic 0:fbdae7e6d805 137 void XBARA_SetOutputSignalConfig(XBARA_Type *base,
borlanic 0:fbdae7e6d805 138 xbar_output_signal_t output,
borlanic 0:fbdae7e6d805 139 const xbara_control_config_t *controlConfig)
borlanic 0:fbdae7e6d805 140 {
borlanic 0:fbdae7e6d805 141 uint16_t regVal;
borlanic 0:fbdae7e6d805 142 /* Set active edge for edge detection, set interrupt or DMA function. */
borlanic 0:fbdae7e6d805 143 switch ((uint16_t)output)
borlanic 0:fbdae7e6d805 144 {
borlanic 0:fbdae7e6d805 145 #if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_30) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_30
borlanic 0:fbdae7e6d805 146 case kXBARA1_OutputDmaChMuxReq30:
borlanic 0:fbdae7e6d805 147 #else
borlanic 0:fbdae7e6d805 148 case kXBARA_OutputDmamux18:
borlanic 0:fbdae7e6d805 149 #endif
borlanic 0:fbdae7e6d805 150 /* Assign regVal to CTRL0 register's value */
borlanic 0:fbdae7e6d805 151 regVal = (base->CTRL0);
borlanic 0:fbdae7e6d805 152 /* Perform this command to avoid writing 1 into interrupt flag bits and clears bit DEN0, IEN0 */
borlanic 0:fbdae7e6d805 153 regVal &= (uint16_t)(
borlanic 0:fbdae7e6d805 154 ~(XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK | XBARA_CTRL0_DEN0_MASK | XBARA_CTRL0_IEN0_MASK));
borlanic 0:fbdae7e6d805 155 /* Configure edge and request type */
borlanic 0:fbdae7e6d805 156 regVal |= (uint16_t)(XBARA_CTRL0_EDGE0(controlConfig->activeEdge) |
borlanic 0:fbdae7e6d805 157 ((controlConfig->requestType) << XBARA_CTRL0_DEN0_SHIFT));
borlanic 0:fbdae7e6d805 158 /* Write regVal value into CTRL0 register */
borlanic 0:fbdae7e6d805 159 base->CTRL0 = regVal;
borlanic 0:fbdae7e6d805 160 break;
borlanic 0:fbdae7e6d805 161 #if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_31) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_31
borlanic 0:fbdae7e6d805 162 case kXBARA1_OutputDmaChMuxReq31:
borlanic 0:fbdae7e6d805 163 #else
borlanic 0:fbdae7e6d805 164 case kXBARA_OutputDmamux19:
borlanic 0:fbdae7e6d805 165 #endif
borlanic 0:fbdae7e6d805 166 /* Assign regVal to CTRL0 register's value */
borlanic 0:fbdae7e6d805 167 regVal = (base->CTRL0);
borlanic 0:fbdae7e6d805 168 /* Perform this command to avoid writing 1 into interrupt flag bits and clears bit DEN1, IEN1 */
borlanic 0:fbdae7e6d805 169 regVal &= (uint16_t)(
borlanic 0:fbdae7e6d805 170 ~(XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK | XBARA_CTRL0_DEN1_MASK | XBARA_CTRL0_IEN1_MASK));
borlanic 0:fbdae7e6d805 171 /* Configure edge and request type */
borlanic 0:fbdae7e6d805 172 regVal |= (uint16_t)(XBARA_CTRL0_EDGE1(controlConfig->activeEdge) |
borlanic 0:fbdae7e6d805 173 ((controlConfig->requestType) << XBARA_CTRL0_DEN1_SHIFT));
borlanic 0:fbdae7e6d805 174 /* Write regVal value into CTRL0 register */
borlanic 0:fbdae7e6d805 175 base->CTRL0 = regVal;
borlanic 0:fbdae7e6d805 176 break;
borlanic 0:fbdae7e6d805 177 #if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_94) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_94
borlanic 0:fbdae7e6d805 178 case kXBARA1_OutputDmaChMuxReq94:
borlanic 0:fbdae7e6d805 179 #else
borlanic 0:fbdae7e6d805 180 case kXBARA_OutputDmamux20:
borlanic 0:fbdae7e6d805 181 #endif
borlanic 0:fbdae7e6d805 182 /* Assign regVal to CTRL1 register's value */
borlanic 0:fbdae7e6d805 183 regVal = (base->CTRL1);
borlanic 0:fbdae7e6d805 184 /* Perform this command to avoid writing 1 into interrupt flag bits and clears bit DEN2, IEN2 */
borlanic 0:fbdae7e6d805 185 regVal &= (uint16_t)(
borlanic 0:fbdae7e6d805 186 ~(XBARA_CTRL1_STS2_MASK | XBARA_CTRL1_STS3_MASK | XBARA_CTRL1_DEN2_MASK | XBARA_CTRL1_IEN2_MASK));
borlanic 0:fbdae7e6d805 187 /* Configure edge and request type */
borlanic 0:fbdae7e6d805 188 regVal |= (uint16_t)(XBARA_CTRL1_EDGE2(controlConfig->activeEdge) |
borlanic 0:fbdae7e6d805 189 ((controlConfig->requestType) << XBARA_CTRL1_DEN2_SHIFT));
borlanic 0:fbdae7e6d805 190 /* Write regVal value into CTRL1 register */
borlanic 0:fbdae7e6d805 191 base->CTRL1 = regVal;
borlanic 0:fbdae7e6d805 192 break;
borlanic 0:fbdae7e6d805 193 #if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_95) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_95
borlanic 0:fbdae7e6d805 194 case kXBARA1_OutputDmaChMuxReq95:
borlanic 0:fbdae7e6d805 195 #else
borlanic 0:fbdae7e6d805 196 case kXBARA_OutputDmamux21:
borlanic 0:fbdae7e6d805 197 #endif
borlanic 0:fbdae7e6d805 198 /* Assign regVal to CTRL1 register's value */
borlanic 0:fbdae7e6d805 199 regVal = (base->CTRL1);
borlanic 0:fbdae7e6d805 200 /* Perform this command to avoid writing 1 into interrupt flag bits and clears bit DEN3, IEN3 */
borlanic 0:fbdae7e6d805 201 regVal &= (uint16_t)(
borlanic 0:fbdae7e6d805 202 ~(XBARA_CTRL1_STS2_MASK | XBARA_CTRL1_STS3_MASK | XBARA_CTRL1_DEN3_MASK | XBARA_CTRL1_IEN3_MASK));
borlanic 0:fbdae7e6d805 203 /* Configure edge and request type */
borlanic 0:fbdae7e6d805 204 regVal |= (uint16_t)(XBARA_CTRL1_EDGE3(controlConfig->activeEdge) |
borlanic 0:fbdae7e6d805 205 ((controlConfig->requestType) << XBARA_CTRL1_DEN3_SHIFT));
borlanic 0:fbdae7e6d805 206 /* Write regVal value into CTRL1 register */
borlanic 0:fbdae7e6d805 207 base->CTRL1 = regVal;
borlanic 0:fbdae7e6d805 208 break;
borlanic 0:fbdae7e6d805 209 default:
borlanic 0:fbdae7e6d805 210 break;
borlanic 0:fbdae7e6d805 211 }
borlanic 0:fbdae7e6d805 212 }