marco valli / TFT_ILI9163C

for Arduino TFT LCD Screen 160x128

Dependents:   TFTLCDSCREEN Pong_ILI9163C

Fork of TFT_ILI9163C by _ peu605

TFT_ILI9163C_F411RE_DMA_IT.cpp@12:f0799be044ff, 2016-03-04 (annotated)

Committer:
billycorgan123
Date:
Fri Mar 04 08:55:32 2016 +0000
Revision:
12:f0799be044ff
Parent:
8:8dea70cf3ae8 
first trial with Arduino TFT LCD Screen, ILI9163

Who changed what in which revision?

UserRevisionLine numberNew contents of line
peu605 7:3dcb98ecf29f 1 #include "TFT_ILI9163C.h"
peu605 7:3dcb98ecf29f 2 #if defined(__F411RE_DMA_IT__)
peu605 7:3dcb98ecf29f 3
peu605 7:3dcb98ecf29f 4 /**
peu605 7:3dcb98ecf29f 5 * TFT_ILI9163C library for ST Nucleo F411RE DMA Interrupt
peu605 7:3dcb98ecf29f 6 *
peu605 7:3dcb98ecf29f 7 * @author Copyright (c) 2014, .S.U.M.O.T.O.Y., coded by Max MC Costa
peu605 7:3dcb98ecf29f 8 * https://github.com/sumotoy/TFT_ILI9163C
peu605 7:3dcb98ecf29f 9 *
peu605 7:3dcb98ecf29f 10 * @author modified by masuda, Masuda Naika
peu605 7:3dcb98ecf29f 11 */
peu605 7:3dcb98ecf29f 12
peu605 7:3dcb98ecf29f 13 //Serial pc(SERIAL_TX, SERIAL_RX);
peu605 7:3dcb98ecf29f 14
peu605 7:3dcb98ecf29f 15 //constructors
peu605 7:3dcb98ecf29f 16 TFT_ILI9163C::TFT_ILI9163C(PinName mosi, PinName miso, PinName sclk, PinName cs, PinName dc, PinName reset)
peu605 7:3dcb98ecf29f 17 : TFT_ILI9163C_BASE(mosi, miso, sclk, cs, dc, reset) {
peu605 7:3dcb98ecf29f 18
peu605 7:3dcb98ecf29f 19 _resetPinName = reset;
peu605 7:3dcb98ecf29f 20 init(cs, dc);
peu605 7:3dcb98ecf29f 21 }
peu605 7:3dcb98ecf29f 22
peu605 7:3dcb98ecf29f 23 TFT_ILI9163C::TFT_ILI9163C(PinName mosi, PinName miso, PinName sclk, PinName cs, PinName dc)
peu605 7:3dcb98ecf29f 24 : TFT_ILI9163C_BASE(mosi, miso, sclk, cs, dc) {
peu605 7:3dcb98ecf29f 25
peu605 7:3dcb98ecf29f 26 _resetPinName = NC;
peu605 7:3dcb98ecf29f 27 init(cs, dc);
peu605 7:3dcb98ecf29f 28 }
peu605 7:3dcb98ecf29f 29
peu605 7:3dcb98ecf29f 30
peu605 7:3dcb98ecf29f 31 void DmaIrqHandler1() {
peu605 7:3dcb98ecf29f 32 tftPtr[0]->dmaIrqHandler();
peu605 7:3dcb98ecf29f 33 }
peu605 7:3dcb98ecf29f 34
peu605 7:3dcb98ecf29f 35 void DmaIrqHandler2() {
peu605 7:3dcb98ecf29f 36 tftPtr[1]->dmaIrqHandler();
peu605 7:3dcb98ecf29f 37 }
peu605 7:3dcb98ecf29f 38
peu605 7:3dcb98ecf29f 39 void DmaIrqHandler3() {
peu605 7:3dcb98ecf29f 40 tftPtr[2]->dmaIrqHandler();
peu605 7:3dcb98ecf29f 41 }
peu605 7:3dcb98ecf29f 42
peu605 7:3dcb98ecf29f 43 void DmaIrqHandler4() {
peu605 7:3dcb98ecf29f 44 tftPtr[3]->dmaIrqHandler();
peu605 7:3dcb98ecf29f 45 }
peu605 7:3dcb98ecf29f 46
peu605 7:3dcb98ecf29f 47 void DmaIrqHandler5() {
peu605 7:3dcb98ecf29f 48 tftPtr[4]->dmaIrqHandler();
peu605 7:3dcb98ecf29f 49 }
peu605 7:3dcb98ecf29f 50
peu605 7:3dcb98ecf29f 51 void TFT_ILI9163C::dmaIrqHandler() {
peu605 7:3dcb98ecf29f 52 // if(__HAL_DMA_GET_FLAG(&hdma, __HAL_DMA_GET_TC_FLAG_INDEX(&hdma)) != RESET) {
peu605 7:3dcb98ecf29f 53 // if(__HAL_DMA_GET_IT_SOURCE(&hdma, DMA_IT_TC) != RESET) {
peu605 7:3dcb98ecf29f 54 if ((*dma_state_reg & dma_tc_flag_mask) != RESET) {
peu605 7:3dcb98ecf29f 55 if ((hdma.Instance->CR & DMA_IT_TC) != RESET) {
peu605 7:3dcb98ecf29f 56 // disable SPI-DMA
peu605 7:3dcb98ecf29f 57 *bb_spi_txdmaen = 0;
peu605 7:3dcb98ecf29f 58 // disable DMA
peu605 7:3dcb98ecf29f 59 *bb_dma_sxcr_en = 0;
peu605 7:3dcb98ecf29f 60 while (*bb_dma_sxcr_en);
peu605 7:3dcb98ecf29f 61 // Disable the transfer complete interrupt
peu605 7:3dcb98ecf29f 62 // __HAL_DMA_DISABLE_IT(&hdma, DMA_IT_TC);
peu605 7:3dcb98ecf29f 63 // hdma.Instance->CR &= ~(DMA_IT_TC);
peu605 7:3dcb98ecf29f 64 *bb_dma_tcie = 0;
peu605 7:3dcb98ecf29f 65
peu605 7:3dcb98ecf29f 66 waitSpiFree();
peu605 7:3dcb98ecf29f 67 deselectSlave();
peu605 7:3dcb98ecf29f 68 }
peu605 7:3dcb98ecf29f 69 }
peu605 7:3dcb98ecf29f 70 }
peu605 7:3dcb98ecf29f 71
peu605 7:3dcb98ecf29f 72 inline void TFT_ILI9163C::waitCsFree() {
peu605 7:3dcb98ecf29f 73 while ((cs_port_reg->IDR & cs_reg_mask) == 0);
peu605 7:3dcb98ecf29f 74 }
peu605 7:3dcb98ecf29f 75
peu605 7:3dcb98ecf29f 76 void TFT_ILI9163C::init(PinName cs, PinName dc){
peu605 7:3dcb98ecf29f 77
peu605 7:3dcb98ecf29f 78 SPI_TypeDef *spi_ptr = (SPI_TypeDef*) _spi.spi;
peu605 7:3dcb98ecf29f 79
peu605 7:3dcb98ecf29f 80 uint32_t cs_port_index = (uint32_t) cs >> 4;
peu605 7:3dcb98ecf29f 81 uint32_t dc_port_index = (uint32_t) dc >> 4;
peu605 7:3dcb98ecf29f 82
peu605 7:3dcb98ecf29f 83 //set cs/dc port addresses and masks
peu605 7:3dcb98ecf29f 84 cs_port_reg = (GPIO_TypeDef *) (GPIOA_BASE + (cs_port_index << 10));
peu605 7:3dcb98ecf29f 85 cs_reg_mask = 1 << ((uint32_t) cs & 0xf);
peu605 7:3dcb98ecf29f 86 dc_port_reg = (GPIO_TypeDef *) (GPIOA_BASE + (dc_port_index << 10));
peu605 7:3dcb98ecf29f 87 dc_reg_mask = 1 << ((uint32_t) dc & 0xf);
peu605 7:3dcb98ecf29f 88
peu605 7:3dcb98ecf29f 89 // set bit band addresses
peu605 7:3dcb98ecf29f 90 // GPIO_TypeDef *cs_port_reg = (GPIO_TypeDef *) (GPIOA_BASE + (cs_port_index << 10));
peu605 7:3dcb98ecf29f 91 // GPIO_TypeDef *dc_port_reg = (GPIO_TypeDef *) (GPIOA_BASE + (dc_port_index << 10));
peu605 7:3dcb98ecf29f 92 // uint8_t cs_port_bit = (uint32_t) cs & 0xf;
peu605 7:3dcb98ecf29f 93 // uint8_t dc_port_bit = (uint32_t) dc & 0xf;
peu605 7:3dcb98ecf29f 94 // bb_cs_port = BITBAND_PERIPH(&cs_port_reg->ODR, cs_port_bit);
peu605 7:3dcb98ecf29f 95 // bb_dc_port = BITBAND_PERIPH(&dc_port_reg->ODR, dc_port_bit);
peu605 7:3dcb98ecf29f 96
peu605 7:3dcb98ecf29f 97 bb_spi_txe = BITBAND_PERIPH(&spi_ptr->SR, MASK_TO_BITNUM(SPI_SR_TXE));
peu605 7:3dcb98ecf29f 98 bb_spi_bsy = BITBAND_PERIPH(&spi_ptr->SR, MASK_TO_BITNUM(SPI_SR_BSY));
peu605 7:3dcb98ecf29f 99 bb_spi_spe = BITBAND_PERIPH(&spi_ptr->CR1, MASK_TO_BITNUM(SPI_CR1_SPE));
peu605 7:3dcb98ecf29f 100 bb_spi_dff = BITBAND_PERIPH(&spi_ptr->CR1, MASK_TO_BITNUM(SPI_CR1_DFF));
peu605 8:8dea70cf3ae8 101 bb_spi_txdmaen = BITBAND_PERIPH(&spi_ptr->CR2, MASK_TO_BITNUM(SPI_CR2_TXDMAEN));
peu605 7:3dcb98ecf29f 102
peu605 7:3dcb98ecf29f 103 // init DMA
peu605 7:3dcb98ecf29f 104 hdma.Init.Direction = DMA_MEMORY_TO_PERIPH;
peu605 7:3dcb98ecf29f 105 hdma.Init.PeriphInc = DMA_PINC_DISABLE;
peu605 7:3dcb98ecf29f 106 hdma.Init.MemInc = DMA_MINC_DISABLE;
peu605 7:3dcb98ecf29f 107 hdma.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
peu605 7:3dcb98ecf29f 108 hdma.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
peu605 7:3dcb98ecf29f 109 hdma.Init.Mode = DMA_NORMAL;
peu605 7:3dcb98ecf29f 110 hdma.Init.Priority = DMA_PRIORITY_MEDIUM;
peu605 7:3dcb98ecf29f 111 hdma.Init.FIFOMode = DMA_FIFOMODE_ENABLE;
peu605 7:3dcb98ecf29f 112 hdma.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_HALFFULL;
peu605 7:3dcb98ecf29f 113 hdma.Init.MemBurst = DMA_MBURST_SINGLE;
peu605 7:3dcb98ecf29f 114 hdma.Init.PeriphBurst = DMA_PBURST_SINGLE;
peu605 7:3dcb98ecf29f 115
peu605 7:3dcb98ecf29f 116 if(_spi.spi == SPI_1){
peu605 7:3dcb98ecf29f 117 hdma.Instance = DMA2_Stream3; // DMA2_Stream2
peu605 7:3dcb98ecf29f 118 hdma.Init.Channel = DMA_CHANNEL_3; // DMA_CHANNEL_2
peu605 7:3dcb98ecf29f 119 dma_tc_flag_mask = DMA_LISR_TCIF3;
peu605 7:3dcb98ecf29f 120 dma_state_reg = &DMA2->LISR;
peu605 7:3dcb98ecf29f 121 dma_tc_clear_mask = DMA_LIFCR_CTCIF3;
peu605 7:3dcb98ecf29f 122 dma_state_clear_reg = &DMA2->LIFCR;
peu605 7:3dcb98ecf29f 123 NVIC_SetPriority(DMA2_Stream3_IRQn, 0);
peu605 7:3dcb98ecf29f 124 NVIC_SetVector(DMA2_Stream3_IRQn, (uint32_t) &DmaIrqHandler1);
peu605 7:3dcb98ecf29f 125 NVIC_EnableIRQ(DMA2_Stream3_IRQn);
peu605 7:3dcb98ecf29f 126 __DMA2_CLK_ENABLE();
peu605 7:3dcb98ecf29f 127 tftPtr[0] = this;
peu605 7:3dcb98ecf29f 128 } else if(_spi.spi == SPI_2){
peu605 7:3dcb98ecf29f 129 hdma.Instance = DMA1_Stream4;
peu605 7:3dcb98ecf29f 130 hdma.Init.Channel = DMA_CHANNEL_0;
peu605 7:3dcb98ecf29f 131 dma_tc_flag_mask = DMA_HISR_TCIF4;
peu605 7:3dcb98ecf29f 132 dma_state_reg = &DMA1->HISR;
peu605 7:3dcb98ecf29f 133 dma_tc_clear_mask = DMA_HIFCR_CTCIF4;
peu605 7:3dcb98ecf29f 134 dma_state_clear_reg = &DMA1->HIFCR;
peu605 7:3dcb98ecf29f 135 NVIC_SetPriority(DMA1_Stream4_IRQn, 0);
peu605 7:3dcb98ecf29f 136 NVIC_SetVector(DMA1_Stream4_IRQn, (uint32_t) &DmaIrqHandler2);
peu605 7:3dcb98ecf29f 137 NVIC_EnableIRQ(DMA1_Stream4_IRQn);
peu605 7:3dcb98ecf29f 138 __DMA1_CLK_ENABLE();
peu605 7:3dcb98ecf29f 139 tftPtr[1] = this;
peu605 7:3dcb98ecf29f 140 } else if(_spi.spi == SPI_3){
peu605 7:3dcb98ecf29f 141 hdma.Instance = DMA1_Stream5; // DMA1_Stream7
peu605 7:3dcb98ecf29f 142 hdma.Init.Channel = DMA_CHANNEL_0; // DMA_CHANNEL0
peu605 7:3dcb98ecf29f 143 dma_tc_flag_mask = DMA_HISR_TCIF5;
peu605 7:3dcb98ecf29f 144 dma_state_reg = &DMA1->HISR;
peu605 7:3dcb98ecf29f 145 dma_tc_clear_mask = DMA_HIFCR_CTCIF5;
peu605 7:3dcb98ecf29f 146 dma_state_clear_reg = &DMA1->HIFCR;
peu605 7:3dcb98ecf29f 147 NVIC_SetPriority(DMA1_Stream5_IRQn, 0);
peu605 7:3dcb98ecf29f 148 NVIC_SetVector(DMA1_Stream5_IRQn, (uint32_t) &DmaIrqHandler3);
peu605 7:3dcb98ecf29f 149 NVIC_EnableIRQ(DMA1_Stream5_IRQn);
peu605 7:3dcb98ecf29f 150 __DMA1_CLK_ENABLE();
peu605 7:3dcb98ecf29f 151 tftPtr[2] = this;
peu605 7:3dcb98ecf29f 152 } else if(_spi.spi == SPI_4){
peu605 7:3dcb98ecf29f 153 hdma.Instance = DMA2_Stream1; // DMA2_Stream4
peu605 7:3dcb98ecf29f 154 hdma.Init.Channel = DMA_CHANNEL_4; // DMA_CHANNEL_5
peu605 7:3dcb98ecf29f 155 dma_tc_flag_mask = DMA_LISR_TCIF1;
peu605 7:3dcb98ecf29f 156 dma_state_reg = &DMA2->LISR;
peu605 7:3dcb98ecf29f 157 dma_tc_clear_mask = DMA_LIFCR_CTCIF1;
peu605 7:3dcb98ecf29f 158 dma_state_clear_reg = &DMA1->LIFCR;
peu605 7:3dcb98ecf29f 159 NVIC_SetPriority(DMA2_Stream1_IRQn, 0);
peu605 7:3dcb98ecf29f 160 NVIC_SetVector(DMA2_Stream1_IRQn, (uint32_t) &DmaIrqHandler4);
peu605 7:3dcb98ecf29f 161 NVIC_EnableIRQ(DMA2_Stream1_IRQn);
peu605 7:3dcb98ecf29f 162 __DMA2_CLK_ENABLE();
peu605 7:3dcb98ecf29f 163 tftPtr[3] = this;
peu605 7:3dcb98ecf29f 164 } else if(_spi.spi == SPI_5){
peu605 7:3dcb98ecf29f 165 hdma.Instance = DMA2_Stream4; // DMA2_Stream5, DMA2_Stream6
peu605 7:3dcb98ecf29f 166 hdma.Init.Channel = DMA_CHANNEL_2; // DMA_CHANNEL5, DMA_CHANNEL7
peu605 7:3dcb98ecf29f 167 dma_tc_flag_mask = DMA_HISR_TCIF4;
peu605 7:3dcb98ecf29f 168 dma_state_reg = &DMA2->HISR;
peu605 7:3dcb98ecf29f 169 dma_tc_clear_mask = DMA_HIFCR_CTCIF4;
peu605 7:3dcb98ecf29f 170 dma_state_clear_reg = &DMA2->HIFCR;
peu605 7:3dcb98ecf29f 171 NVIC_SetPriority(DMA2_Stream4_IRQn, 0);
peu605 7:3dcb98ecf29f 172 NVIC_SetVector(DMA2_Stream4_IRQn, (uint32_t) &DmaIrqHandler5);
peu605 7:3dcb98ecf29f 173 NVIC_EnableIRQ(DMA2_Stream4_IRQn);
peu605 7:3dcb98ecf29f 174 __DMA2_CLK_ENABLE();
peu605 7:3dcb98ecf29f 175 tftPtr[4] = this;
peu605 7:3dcb98ecf29f 176 }
peu605 7:3dcb98ecf29f 177
peu605 7:3dcb98ecf29f 178 HAL_DMA_Init(&hdma);
peu605 7:3dcb98ecf29f 179
peu605 7:3dcb98ecf29f 180 // set SPI DR
peu605 7:3dcb98ecf29f 181 hdma.Instance->PAR = (uint32_t) &spi_ptr->DR;
peu605 7:3dcb98ecf29f 182 // set SPI MAR
peu605 7:3dcb98ecf29f 183 hdma.Instance->M0AR = (uint32_t) &dmaBuff;
peu605 7:3dcb98ecf29f 184
peu605 7:3dcb98ecf29f 185 // set bit band addresses
peu605 7:3dcb98ecf29f 186 bb_dma_sxcr_en = BITBAND_PERIPH(&hdma.Instance->CR, MASK_TO_BITNUM(DMA_SxCR_EN));
peu605 7:3dcb98ecf29f 187 bb_dma_tcie = BITBAND_PERIPH(&hdma.Instance->CR, MASK_TO_BITNUM(DMA_SxCR_TCIE));
peu605 7:3dcb98ecf29f 188 }
peu605 7:3dcb98ecf29f 189
peu605 7:3dcb98ecf29f 190 inline void TFT_ILI9163C::selectSlave() {
peu605 7:3dcb98ecf29f 191 cs_port_reg->BSRRH = cs_reg_mask; // Use BSRR register
peu605 7:3dcb98ecf29f 192 }
peu605 7:3dcb98ecf29f 193
peu605 7:3dcb98ecf29f 194 inline void TFT_ILI9163C::deselectSlave() {
peu605 7:3dcb98ecf29f 195 cs_port_reg->BSRRL = cs_reg_mask;
peu605 7:3dcb98ecf29f 196 }
peu605 7:3dcb98ecf29f 197
peu605 7:3dcb98ecf29f 198 inline void TFT_ILI9163C::setCommandMode() {
peu605 7:3dcb98ecf29f 199 dc_port_reg->BSRRH = dc_reg_mask;
peu605 7:3dcb98ecf29f 200 }
peu605 7:3dcb98ecf29f 201
peu605 7:3dcb98ecf29f 202 inline void TFT_ILI9163C::setDataMode() {
peu605 7:3dcb98ecf29f 203 dc_port_reg->BSRRL = dc_reg_mask;
peu605 7:3dcb98ecf29f 204 }
peu605 7:3dcb98ecf29f 205
peu605 7:3dcb98ecf29f 206 inline void TFT_ILI9163C::waitSpiFree() {
peu605 7:3dcb98ecf29f 207 while (*bb_spi_txe == 0);
peu605 7:3dcb98ecf29f 208 while (*bb_spi_bsy != 0);
peu605 7:3dcb98ecf29f 209 }
peu605 7:3dcb98ecf29f 210
peu605 7:3dcb98ecf29f 211 inline void TFT_ILI9163C::waitBufferFree() {
peu605 7:3dcb98ecf29f 212 while (*bb_spi_txe == 0);
peu605 7:3dcb98ecf29f 213 }
peu605 7:3dcb98ecf29f 214
peu605 7:3dcb98ecf29f 215 inline void TFT_ILI9163C::set8bitMode() {
peu605 7:3dcb98ecf29f 216 *bb_spi_spe = 0;
peu605 7:3dcb98ecf29f 217 *bb_spi_dff = 0;
peu605 7:3dcb98ecf29f 218 *bb_spi_spe = 1;
peu605 7:3dcb98ecf29f 219 }
peu605 7:3dcb98ecf29f 220
peu605 7:3dcb98ecf29f 221 inline void TFT_ILI9163C::set16bitMode() {
peu605 7:3dcb98ecf29f 222 *bb_spi_spe = 0;
peu605 7:3dcb98ecf29f 223 *bb_spi_dff = 1;
peu605 7:3dcb98ecf29f 224 *bb_spi_spe = 1;
peu605 7:3dcb98ecf29f 225 }
peu605 7:3dcb98ecf29f 226
peu605 7:3dcb98ecf29f 227 void TFT_ILI9163C::writecommand(uint8_t c){
peu605 7:3dcb98ecf29f 228
peu605 7:3dcb98ecf29f 229 waitCsFree();
peu605 7:3dcb98ecf29f 230
peu605 7:3dcb98ecf29f 231 set8bitMode();
peu605 7:3dcb98ecf29f 232 setCommandMode();
peu605 7:3dcb98ecf29f 233 selectSlave();
peu605 7:3dcb98ecf29f 234
peu605 7:3dcb98ecf29f 235 SPI_TypeDef *spi_ptr = (SPI_TypeDef*) _spi.spi;
peu605 7:3dcb98ecf29f 236 spi_ptr->DR = c;
peu605 7:3dcb98ecf29f 237
peu605 7:3dcb98ecf29f 238 waitSpiFree();
peu605 7:3dcb98ecf29f 239 deselectSlave();
peu605 7:3dcb98ecf29f 240 }
peu605 7:3dcb98ecf29f 241
peu605 7:3dcb98ecf29f 242 void TFT_ILI9163C::writedata(uint8_t c){
peu605 7:3dcb98ecf29f 243
peu605 7:3dcb98ecf29f 244 waitCsFree();
peu605 7:3dcb98ecf29f 245
peu605 7:3dcb98ecf29f 246 set8bitMode();
peu605 7:3dcb98ecf29f 247 setDataMode();
peu605 7:3dcb98ecf29f 248 selectSlave();
peu605 7:3dcb98ecf29f 249
peu605 7:3dcb98ecf29f 250 SPI_TypeDef *spi_ptr = (SPI_TypeDef*) _spi.spi;
peu605 7:3dcb98ecf29f 251 spi_ptr->DR = c;
peu605 7:3dcb98ecf29f 252
peu605 7:3dcb98ecf29f 253 waitSpiFree();
peu605 7:3dcb98ecf29f 254 deselectSlave();
peu605 7:3dcb98ecf29f 255 }
peu605 7:3dcb98ecf29f 256
peu605 7:3dcb98ecf29f 257 void TFT_ILI9163C::writedata16(uint16_t d){
peu605 7:3dcb98ecf29f 258
peu605 7:3dcb98ecf29f 259 waitCsFree();
peu605 7:3dcb98ecf29f 260
peu605 7:3dcb98ecf29f 261 set16bitMode();
peu605 7:3dcb98ecf29f 262 setDataMode();
peu605 7:3dcb98ecf29f 263 selectSlave();
peu605 7:3dcb98ecf29f 264
peu605 7:3dcb98ecf29f 265 SPI_TypeDef *spi_ptr = (SPI_TypeDef*) _spi.spi;
peu605 7:3dcb98ecf29f 266 spi_ptr->DR = d;
peu605 7:3dcb98ecf29f 267
peu605 7:3dcb98ecf29f 268 waitSpiFree();
peu605 7:3dcb98ecf29f 269 deselectSlave();
peu605 7:3dcb98ecf29f 270 }
peu605 7:3dcb98ecf29f 271
peu605 7:3dcb98ecf29f 272
peu605 7:3dcb98ecf29f 273 void TFT_ILI9163C::writedata32(uint16_t d1, uint16_t d2){
peu605 7:3dcb98ecf29f 274
peu605 7:3dcb98ecf29f 275 waitCsFree();
peu605 7:3dcb98ecf29f 276
peu605 7:3dcb98ecf29f 277 set16bitMode();
peu605 7:3dcb98ecf29f 278 setDataMode();
peu605 7:3dcb98ecf29f 279 selectSlave();
peu605 7:3dcb98ecf29f 280
peu605 7:3dcb98ecf29f 281 SPI_TypeDef *spi_ptr = (SPI_TypeDef*) _spi.spi;
peu605 7:3dcb98ecf29f 282 spi_ptr->DR = d1;
peu605 7:3dcb98ecf29f 283 waitBufferFree();
peu605 7:3dcb98ecf29f 284 spi_ptr->DR = d2;
peu605 7:3dcb98ecf29f 285
peu605 7:3dcb98ecf29f 286 waitSpiFree();
peu605 7:3dcb98ecf29f 287 deselectSlave();
peu605 7:3dcb98ecf29f 288 }
peu605 7:3dcb98ecf29f 289
peu605 7:3dcb98ecf29f 290 // use DMA, Interrupt
peu605 7:3dcb98ecf29f 291 void TFT_ILI9163C::writedata16burst(uint16_t d, int32_t len) {
peu605 7:3dcb98ecf29f 292
peu605 7:3dcb98ecf29f 293 len = len < 0 ? -len : len;
peu605 7:3dcb98ecf29f 294
peu605 7:3dcb98ecf29f 295 if (len > 0) {
peu605 7:3dcb98ecf29f 296 waitCsFree();
peu605 7:3dcb98ecf29f 297 set16bitMode();
peu605 7:3dcb98ecf29f 298 setDataMode();
peu605 7:3dcb98ecf29f 299 selectSlave();
peu605 7:3dcb98ecf29f 300
peu605 7:3dcb98ecf29f 301 // clear DMA flags
peu605 7:3dcb98ecf29f 302 // __HAL_DMA_CLEAR_FLAG(&hdma, __HAL_DMA_GET_TC_FLAG_INDEX(&hdma));
peu605 7:3dcb98ecf29f 303 *dma_state_clear_reg = dma_tc_clear_mask;
peu605 7:3dcb98ecf29f 304
peu605 7:3dcb98ecf29f 305 dmaBuff = d;
peu605 7:3dcb98ecf29f 306 hdma.Instance->NDTR = len;
peu605 7:3dcb98ecf29f 307
peu605 7:3dcb98ecf29f 308 /* Enable the transfer complete interrupt */
peu605 7:3dcb98ecf29f 309 // __HAL_DMA_ENABLE_IT(&hdma, DMA_IT_TC);
peu605 7:3dcb98ecf29f 310 // hdma.Instance->CR |= DMA_IT_TC;
peu605 7:3dcb98ecf29f 311 *bb_dma_tcie = 1;
peu605 7:3dcb98ecf29f 312
peu605 7:3dcb98ecf29f 313 // enable DMA
peu605 7:3dcb98ecf29f 314 *bb_dma_sxcr_en = 1;
peu605 7:3dcb98ecf29f 315 // enable DMA request from SPI
peu605 7:3dcb98ecf29f 316 *bb_spi_txdmaen = 1;
peu605 7:3dcb98ecf29f 317 }
peu605 7:3dcb98ecf29f 318 }
peu605 7:3dcb98ecf29f 319
peu605 7:3dcb98ecf29f 320 #endif