Ned Konz / Multi_WS2811

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Dependents:   Multi_WS2811_test

WS2811.cpp@2:9447404f2d16, 2015-06-11 (annotated)

Committer:
bikeNomad
Date:
Thu Jun 11 15:32:07 2015 +0000
Revision:
2:9447404f2d16
Parent:
1:86a910560879
Child:
3:df4319053bfa
fixed offline compilation by adding struct

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bikeNomad 0:a8535703f23b 1 // 800 KHz WS2811 driver driving potentially many LED strings.
bikeNomad 0:a8535703f23b 2 // Uses 3-phase DMA
bikeNomad 0:a8535703f23b 3 // 16K SRAM less stack, etc.
bikeNomad 0:a8535703f23b 4 //
bikeNomad 0:a8535703f23b 5 // Per LED: 3 bytes (malloc'd) for RGB data
bikeNomad 0:a8535703f23b 6 //
bikeNomad 0:a8535703f23b 7 // Per LED strip / per LED
bikeNomad 0:a8535703f23b 8 // 96 bytes (static) for bit data
bikeNomad 0:a8535703f23b 9 // + 96 bytes (static) for ones data
bikeNomad 0:a8535703f23b 10 // = 192 bytes
bikeNomad 0:a8535703f23b 11 //
bikeNomad 0:a8535703f23b 12 // 40 LEDs max per string = 7680 bytes static
bikeNomad 0:a8535703f23b 13 //
bikeNomad 0:a8535703f23b 14 // 40 LEDs: 7680 + 40*3 = 7800 bytes
bikeNomad 0:a8535703f23b 15 // 80 LEDs: 7680 + 80*3 = 7920 bytes
bikeNomad 1:86a910560879 16 #include <mbed.h>
bikeNomad 0:a8535703f23b 17 #include "MKL25Z4.h"
bikeNomad 0:a8535703f23b 18
bikeNomad 1:86a910560879 19 #ifndef MBED_WS2811_H
bikeNomad 1:86a910560879 20 #include "WS2811.h"
bikeNomad 0:a8535703f23b 21 #endif
bikeNomad 0:a8535703f23b 22
bikeNomad 1:86a910560879 23 #if defined(WS2811_DEBUG_PIN)
bikeNomad 1:86a910560879 24 #define DEBUG 1
bikeNomad 1:86a910560879 25 #define DEBUG_MASK (1<<WS2811_DEBUG_PIN)
bikeNomad 1:86a910560879 26 #define RESET_DEBUG (WS2811_IO_GPIO->PDOR &= ~DEBUG_MASK)
bikeNomad 1:86a910560879 27 #define SET_DEBUG (WS2811_IO_GPIO->PDOR |= DEBUG_MASK)
bikeNomad 0:a8535703f23b 28 #else
bikeNomad 0:a8535703f23b 29 #define DEBUG_MASK 0
bikeNomad 0:a8535703f23b 30 #define RESET_DEBUG (void)0
bikeNomad 0:a8535703f23b 31 #define SET_DEBUG (void)0
bikeNomad 0:a8535703f23b 32 #endif
bikeNomad 0:a8535703f23b 33
bikeNomad 1:86a910560879 34 static volatile bool dma_done = true;
bikeNomad 0:a8535703f23b 35
bikeNomad 0:a8535703f23b 36 // 48 MHz clock, no prescaling.
bikeNomad 0:a8535703f23b 37 #define NSEC_TO_TICKS(nsec) ((nsec)*48/1000)
bikeNomad 0:a8535703f23b 38 #define USEC_TO_TICKS(usec) ((usec)*48)
bikeNomad 1:86a910560879 39 #define CLK_NSEC 1250
bikeNomad 1:86a910560879 40 #define tpm_period NSEC_TO_TICKS(CLK_NSEC)
bikeNomad 1:86a910560879 41 #define tpm_p0_period NSEC_TO_TICKS(250)
bikeNomad 1:86a910560879 42 #define tpm_p1_period NSEC_TO_TICKS(650)
bikeNomad 1:86a910560879 43 #define guardtime_period USEC_TO_TICKS(55) /* guardtime minimum 50 usec. */
bikeNomad 0:a8535703f23b 44
bikeNomad 0:a8535703f23b 45 enum DMA_MUX_SRC {
bikeNomad 0:a8535703f23b 46 DMA_MUX_SRC_TPM0_CH_0 = 24,
bikeNomad 0:a8535703f23b 47 DMA_MUX_SRC_TPM0_CH_1,
bikeNomad 0:a8535703f23b 48 DMA_MUX_SRC_TPM0_Overflow = 54,
bikeNomad 0:a8535703f23b 49 };
bikeNomad 0:a8535703f23b 50
bikeNomad 0:a8535703f23b 51 enum DMA_CHAN {
bikeNomad 0:a8535703f23b 52 DMA_CHAN_START = 0,
bikeNomad 0:a8535703f23b 53 DMA_CHAN_0_LOW = 1,
bikeNomad 0:a8535703f23b 54 DMA_CHAN_1_LOW = 2,
bikeNomad 0:a8535703f23b 55 N_DMA_CHANNELS
bikeNomad 0:a8535703f23b 56 };
bikeNomad 0:a8535703f23b 57
bikeNomad 1:86a910560879 58 // class static
bikeNomad 1:86a910560879 59 template <unsigned MAX_LEDS_PER_STRIP>
bikeNomad 1:86a910560879 60 void WS2811<MAX_LEDS_PER_STRIP>::wait_for_dma_done() { while (!dma_done) __WFI(); }
bikeNomad 0:a8535703f23b 61
bikeNomad 0:a8535703f23b 62 // class static
bikeNomad 1:86a910560879 63 template <unsigned MAX_LEDS_PER_STRIP>
bikeNomad 1:86a910560879 64 bool WS2811<MAX_LEDS_PER_STRIP>::initialized = false;
bikeNomad 0:a8535703f23b 65
bikeNomad 0:a8535703f23b 66 // class static
bikeNomad 1:86a910560879 67 template <unsigned MAX_LEDS_PER_STRIP>
bikeNomad 1:86a910560879 68 uint32_t WS2811<MAX_LEDS_PER_STRIP>::enabledPins = 0;
bikeNomad 0:a8535703f23b 69
bikeNomad 0:a8535703f23b 70 #define WORD_ALIGNED __attribute__ ((aligned(4)))
bikeNomad 0:a8535703f23b 71
bikeNomad 1:86a910560879 72 // class static
bikeNomad 1:86a910560879 73 template <unsigned MAX_LEDS_PER_STRIP>
bikeNomad 2:9447404f2d16 74 struct WS2811<MAX_LEDS_PER_STRIP>::DMALayout WS2811<MAX_LEDS_PER_STRIP>::dmaData WORD_ALIGNED;
bikeNomad 0:a8535703f23b 75
bikeNomad 0:a8535703f23b 76 // class static
bikeNomad 1:86a910560879 77 template <unsigned MAX_LEDS_PER_STRIP>
bikeNomad 1:86a910560879 78 void WS2811<MAX_LEDS_PER_STRIP>::hw_init()
bikeNomad 0:a8535703f23b 79 {
bikeNomad 0:a8535703f23b 80 if (initialized) return;
bikeNomad 0:a8535703f23b 81
bikeNomad 0:a8535703f23b 82 dma_data_init();
bikeNomad 0:a8535703f23b 83 clock_init();
bikeNomad 0:a8535703f23b 84 dma_init();
bikeNomad 0:a8535703f23b 85 io_init();
bikeNomad 0:a8535703f23b 86 tpm_init();
bikeNomad 0:a8535703f23b 87
bikeNomad 0:a8535703f23b 88 initialized = true;
bikeNomad 0:a8535703f23b 89
bikeNomad 0:a8535703f23b 90 SET_DEBUG;
bikeNomad 0:a8535703f23b 91 RESET_DEBUG;
bikeNomad 0:a8535703f23b 92 }
bikeNomad 0:a8535703f23b 93
bikeNomad 0:a8535703f23b 94 // class static
bikeNomad 1:86a910560879 95 template <unsigned MAX_LEDS_PER_STRIP>
bikeNomad 1:86a910560879 96 void WS2811<MAX_LEDS_PER_STRIP>::dma_data_init()
bikeNomad 0:a8535703f23b 97 {
bikeNomad 0:a8535703f23b 98 memset(dmaData.allOnes, 0xFF, sizeof(dmaData.allOnes));
bikeNomad 0:a8535703f23b 99
bikeNomad 0:a8535703f23b 100 #if DEBUG
bikeNomad 0:a8535703f23b 101 for (unsigned i = 0; i < BITS_PER_RGB * MAX_LEDS_PER_STRIP; i++)
bikeNomad 0:a8535703f23b 102 dmaData.dmaWords[i] = DEBUG_MASK;
bikeNomad 0:a8535703f23b 103 #endif
bikeNomad 0:a8535703f23b 104 }
bikeNomad 0:a8535703f23b 105
bikeNomad 0:a8535703f23b 106 // class static
bikeNomad 0:a8535703f23b 107
bikeNomad 0:a8535703f23b 108 /// Enable PORTD, DMA and TPM0 clocking
bikeNomad 1:86a910560879 109 template <unsigned MAX_LEDS_PER_STRIP>
bikeNomad 1:86a910560879 110 void WS2811<MAX_LEDS_PER_STRIP>::clock_init()
bikeNomad 0:a8535703f23b 111 {
bikeNomad 0:a8535703f23b 112 SIM->SCGC5 |= SIM_SCGC5_PORTD_MASK;
bikeNomad 0:a8535703f23b 113 SIM->SCGC6 |= SIM_SCGC6_DMAMUX_MASK | SIM_SCGC6_TPM0_MASK; // Enable clock to DMA mux and TPM0
bikeNomad 0:a8535703f23b 114 SIM->SCGC7 |= SIM_SCGC7_DMA_MASK; // Enable clock to DMA
bikeNomad 0:a8535703f23b 115
bikeNomad 0:a8535703f23b 116 SIM->SOPT2 |= SIM_SOPT2_TPMSRC(1); // Clock source: MCGFLLCLK or MCGPLLCLK
bikeNomad 0:a8535703f23b 117 }
bikeNomad 0:a8535703f23b 118
bikeNomad 0:a8535703f23b 119 // class static
bikeNomad 0:a8535703f23b 120
bikeNomad 0:a8535703f23b 121 /// Configure GPIO output pins
bikeNomad 1:86a910560879 122 template <unsigned MAX_LEDS_PER_STRIP>
bikeNomad 1:86a910560879 123 void WS2811<MAX_LEDS_PER_STRIP>::io_init()
bikeNomad 0:a8535703f23b 124 {
bikeNomad 0:a8535703f23b 125 uint32_t m = 1;
bikeNomad 0:a8535703f23b 126 for (uint32_t i = 0; i < 32; i++) {
bikeNomad 0:a8535703f23b 127 // set up each pin
bikeNomad 0:a8535703f23b 128 if (m & enabledPins) {
bikeNomad 1:86a910560879 129 WS2811_IO_PORT->PCR[i] = PORT_PCR_MUX(1) // GPIO
bikeNomad 0:a8535703f23b 130 | PORT_PCR_DSE_MASK; // high drive strength
bikeNomad 0:a8535703f23b 131 }
bikeNomad 0:a8535703f23b 132 m <<= 1;
bikeNomad 0:a8535703f23b 133 }
bikeNomad 0:a8535703f23b 134
bikeNomad 1:86a910560879 135 WS2811_IO_GPIO->PDDR |= enabledPins; // set as outputs
bikeNomad 0:a8535703f23b 136
bikeNomad 1:86a910560879 137 #if WS2811_MONITOR_TPM0_PWM
bikeNomad 0:a8535703f23b 138 // PTD0 CH0 monitor: TPM0, high drive strength
bikeNomad 1:86a910560879 139 WS2811_IO_PORT->PCR[0] = PORT_PCR_MUX(4) | PORT_PCR_DSE_MASK;
bikeNomad 0:a8535703f23b 140 // PTD1 CH1 monitor: TPM0, high drive strength
bikeNomad 1:86a910560879 141 WS2811_IO_PORT->PCR[1] = PORT_PCR_MUX(4) | PORT_PCR_DSE_MASK;
bikeNomad 1:86a910560879 142 WS2811_IO_GPIO->PDDR |= 3; // set as outputs
bikeNomad 1:86a910560879 143 WS2811_IO_GPIO->PDOR &= ~(enabledPins | 3); // initially low
bikeNomad 0:a8535703f23b 144 #else
bikeNomad 1:86a910560879 145 WS2811_IO_GPIO->PDOR &= ~enabledPins; // initially low
bikeNomad 0:a8535703f23b 146 #endif
bikeNomad 0:a8535703f23b 147
bikeNomad 0:a8535703f23b 148 #if DEBUG
bikeNomad 1:86a910560879 149 WS2811_IO_PORT->PCR[WS2811_DEBUG_PIN] = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
bikeNomad 1:86a910560879 150 WS2811_IO_GPIO->PDDR |= DEBUG_MASK;
bikeNomad 1:86a910560879 151 WS2811_IO_GPIO->PDOR &= ~DEBUG_MASK;
bikeNomad 0:a8535703f23b 152 #endif
bikeNomad 0:a8535703f23b 153 }
bikeNomad 0:a8535703f23b 154
bikeNomad 0:a8535703f23b 155 // class static
bikeNomad 0:a8535703f23b 156
bikeNomad 0:a8535703f23b 157 /// Configure DMA and DMAMUX
bikeNomad 1:86a910560879 158 template <unsigned MAX_LEDS_PER_STRIP>
bikeNomad 1:86a910560879 159 void WS2811<MAX_LEDS_PER_STRIP>::dma_init()
bikeNomad 0:a8535703f23b 160 {
bikeNomad 0:a8535703f23b 161 // reset DMAMUX
bikeNomad 0:a8535703f23b 162 DMAMUX0->CHCFG[DMA_CHAN_START] = 0;
bikeNomad 0:a8535703f23b 163 DMAMUX0->CHCFG[DMA_CHAN_0_LOW] = 0;
bikeNomad 0:a8535703f23b 164 DMAMUX0->CHCFG[DMA_CHAN_1_LOW] = 0;
bikeNomad 0:a8535703f23b 165
bikeNomad 0:a8535703f23b 166 // wire our DMA event sources into the first three DMA channels
bikeNomad 0:a8535703f23b 167 // t=0: all enabled outputs go high on TPM0 overflow
bikeNomad 0:a8535703f23b 168 DMAMUX0->CHCFG[DMA_CHAN_START] = DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(DMA_MUX_SRC_TPM0_Overflow);
bikeNomad 0:a8535703f23b 169 // t=tpm_p0_period: all of the 0 bits go low.
bikeNomad 0:a8535703f23b 170 DMAMUX0->CHCFG[DMA_CHAN_0_LOW] = DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(DMA_MUX_SRC_TPM0_CH_0);
bikeNomad 0:a8535703f23b 171 // t=tpm_p1_period: all outputs go low.
bikeNomad 0:a8535703f23b 172 DMAMUX0->CHCFG[DMA_CHAN_1_LOW] = DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(DMA_MUX_SRC_TPM0_CH_1);
bikeNomad 0:a8535703f23b 173
bikeNomad 0:a8535703f23b 174 NVIC_SetVector(DMA0_IRQn, (uint32_t)&DMA0_IRQHandler);
bikeNomad 0:a8535703f23b 175 NVIC_EnableIRQ(DMA0_IRQn);
bikeNomad 0:a8535703f23b 176 }
bikeNomad 0:a8535703f23b 177
bikeNomad 0:a8535703f23b 178 // class static
bikeNomad 0:a8535703f23b 179
bikeNomad 0:a8535703f23b 180 /// Configure TPM0 to do two different PWM periods at 800kHz rate
bikeNomad 1:86a910560879 181 template <unsigned MAX_LEDS_PER_STRIP>
bikeNomad 1:86a910560879 182 void WS2811<MAX_LEDS_PER_STRIP>::tpm_init()
bikeNomad 0:a8535703f23b 183 {
bikeNomad 0:a8535703f23b 184 // set up TPM0 for proper period (800 kHz = 1.25 usec ±600nsec)
bikeNomad 0:a8535703f23b 185 TPM_Type volatile *tpm = TPM0;
bikeNomad 0:a8535703f23b 186 tpm->SC = TPM_SC_DMA_MASK // enable DMA
bikeNomad 0:a8535703f23b 187 | TPM_SC_TOF_MASK // reset TOF flag if set
bikeNomad 0:a8535703f23b 188 | TPM_SC_CMOD(0) // disable clocks
bikeNomad 0:a8535703f23b 189 | TPM_SC_PS(0); // 48MHz / 1 = 48MHz clock
bikeNomad 0:a8535703f23b 190 tpm->MOD = tpm_period - 1; // 48MHz / 800kHz
bikeNomad 0:a8535703f23b 191
bikeNomad 0:a8535703f23b 192 // No Interrupts; High True pulses on Edge Aligned PWM
bikeNomad 0:a8535703f23b 193 tpm->CONTROLS[0].CnSC = TPM_CnSC_MSB_MASK | TPM_CnSC_ELSB_MASK | TPM_CnSC_DMA_MASK;
bikeNomad 0:a8535703f23b 194 tpm->CONTROLS[1].CnSC = TPM_CnSC_MSB_MASK | TPM_CnSC_ELSB_MASK | TPM_CnSC_DMA_MASK;
bikeNomad 0:a8535703f23b 195
bikeNomad 0:a8535703f23b 196 // set TPM0 channel 0 for 0.35 usec (±150nsec) (0 code)
bikeNomad 0:a8535703f23b 197 // 1.25 usec * 1/3 = 417 nsec
bikeNomad 0:a8535703f23b 198 tpm->CONTROLS[0].CnV = tpm_p0_period;
bikeNomad 0:a8535703f23b 199
bikeNomad 0:a8535703f23b 200 // set TPM0 channel 1 for 0.7 usec (±150nsec) (1 code)
bikeNomad 0:a8535703f23b 201 // 1.25 usec * 2/3 = 833 nsec
bikeNomad 0:a8535703f23b 202 tpm->CONTROLS[1].CnV = tpm_p1_period;
bikeNomad 0:a8535703f23b 203
bikeNomad 0:a8535703f23b 204 NVIC_SetVector(TPM0_IRQn, (uint32_t)&TPM0_IRQHandler);
bikeNomad 0:a8535703f23b 205 NVIC_EnableIRQ(TPM0_IRQn);
bikeNomad 0:a8535703f23b 206 }
bikeNomad 0:a8535703f23b 207
bikeNomad 1:86a910560879 208 // class static
bikeNomad 1:86a910560879 209 template <unsigned MAX_LEDS_PER_STRIP>
bikeNomad 1:86a910560879 210 void WS2811<MAX_LEDS_PER_STRIP>::startDMA()
bikeNomad 0:a8535703f23b 211 {
bikeNomad 1:86a910560879 212 if (!initialized) hw_init();
bikeNomad 0:a8535703f23b 213
bikeNomad 0:a8535703f23b 214 wait_for_dma_done();
bikeNomad 0:a8535703f23b 215 dma_done = false;
bikeNomad 0:a8535703f23b 216
bikeNomad 0:a8535703f23b 217 DMA_Type volatile * dma = DMA0;
bikeNomad 0:a8535703f23b 218 TPM_Type volatile *tpm = TPM0;
bikeNomad 0:a8535703f23b 219 uint32_t nBytes = sizeof(dmaData.start_t1_low)
bikeNomad 0:a8535703f23b 220 + sizeof(dmaData.dmaWords)
bikeNomad 0:a8535703f23b 221 + sizeof(dmaData.trailing_zeros_1);
bikeNomad 0:a8535703f23b 222
bikeNomad 0:a8535703f23b 223 tpm->SC = TPM_SC_DMA_MASK // enable DMA
bikeNomad 0:a8535703f23b 224 | TPM_SC_TOF_MASK // reset TOF flag if set
bikeNomad 0:a8535703f23b 225 | TPM_SC_CMOD(0) // disable clocks
bikeNomad 0:a8535703f23b 226 | TPM_SC_PS(0); // 48MHz / 1 = 48MHz clock
bikeNomad 0:a8535703f23b 227 tpm->MOD = tpm_period - 1; // 48MHz / 800kHz
bikeNomad 0:a8535703f23b 228
bikeNomad 0:a8535703f23b 229 tpm->CNT = tpm_p0_period - 2 ;
bikeNomad 0:a8535703f23b 230 tpm->STATUS = 0xFFFFFFFF;
bikeNomad 0:a8535703f23b 231
bikeNomad 0:a8535703f23b 232 dma->DMA[DMA_CHAN_START].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status
bikeNomad 0:a8535703f23b 233 dma->DMA[DMA_CHAN_0_LOW].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status
bikeNomad 0:a8535703f23b 234 dma->DMA[DMA_CHAN_1_LOW].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status
bikeNomad 0:a8535703f23b 235
bikeNomad 0:a8535703f23b 236 // t=0: all outputs go high
bikeNomad 0:a8535703f23b 237 // triggered by TPM0_Overflow
bikeNomad 0:a8535703f23b 238 // source is one word of 0 then 24 x 0xffffffff, then another 0 word
bikeNomad 0:a8535703f23b 239 dma->DMA[DMA_CHAN_START].SAR = (uint32_t)(void*)dmaData.start_t0_high;
bikeNomad 0:a8535703f23b 240 dma->DMA[DMA_CHAN_START].DSR_BCR = DMA_DSR_BCR_BCR_MASK & nBytes; // length of transfer in bytes
bikeNomad 0:a8535703f23b 241
bikeNomad 0:a8535703f23b 242 // t=tpm_p0_period: some outputs (the 0 bits) go low.
bikeNomad 0:a8535703f23b 243 // Triggered by TPM0_CH0
bikeNomad 0:a8535703f23b 244 // Start 2 words before the actual data to avoid garbage pulses.
bikeNomad 0:a8535703f23b 245 dma->DMA[DMA_CHAN_0_LOW].SAR = (uint32_t)(void*)dmaData.start_t1_low; // set source address
bikeNomad 0:a8535703f23b 246 dma->DMA[DMA_CHAN_0_LOW].DSR_BCR = DMA_DSR_BCR_BCR_MASK & nBytes; // length of transfer in bytes
bikeNomad 0:a8535703f23b 247
bikeNomad 0:a8535703f23b 248 // t=tpm_p1_period: all outputs go low.
bikeNomad 0:a8535703f23b 249 // Triggered by TPM0_CH1
bikeNomad 0:a8535703f23b 250 // source is constant 0x00000000 (first word of dmaWords)
bikeNomad 0:a8535703f23b 251 dma->DMA[DMA_CHAN_1_LOW].SAR = (uint32_t)(void*)dmaData.start_t1_low; // set source address
bikeNomad 0:a8535703f23b 252 dma->DMA[DMA_CHAN_1_LOW].DSR_BCR = DMA_DSR_BCR_BCR_MASK & nBytes; // length of transfer in bytes
bikeNomad 0:a8535703f23b 253
bikeNomad 0:a8535703f23b 254 dma->DMA[DMA_CHAN_0_LOW].DAR
bikeNomad 0:a8535703f23b 255 = dma->DMA[DMA_CHAN_1_LOW].DAR
bikeNomad 0:a8535703f23b 256 = dma->DMA[DMA_CHAN_START].DAR
bikeNomad 1:86a910560879 257 = (uint32_t)(void*)&WS2811_IO_GPIO->PDOR;
bikeNomad 0:a8535703f23b 258
bikeNomad 0:a8535703f23b 259 SET_DEBUG;
bikeNomad 0:a8535703f23b 260
bikeNomad 0:a8535703f23b 261 dma->DMA[DMA_CHAN_0_LOW].DCR = DMA_DCR_EINT_MASK // enable interrupt on end of transfer
bikeNomad 0:a8535703f23b 262 | DMA_DCR_ERQ_MASK
bikeNomad 0:a8535703f23b 263 | DMA_DCR_D_REQ_MASK // clear ERQ on end of transfer
bikeNomad 0:a8535703f23b 264 | DMA_DCR_SINC_MASK // increment source each transfer
bikeNomad 0:a8535703f23b 265 | DMA_DCR_CS_MASK
bikeNomad 0:a8535703f23b 266 | DMA_DCR_SSIZE(0) // 32-bit source transfers
bikeNomad 0:a8535703f23b 267 | DMA_DCR_DSIZE(0); // 32-bit destination transfers
bikeNomad 0:a8535703f23b 268
bikeNomad 0:a8535703f23b 269 dma->DMA[DMA_CHAN_1_LOW].DCR = DMA_DCR_EINT_MASK // enable interrupt on end of transfer
bikeNomad 0:a8535703f23b 270 | DMA_DCR_ERQ_MASK
bikeNomad 0:a8535703f23b 271 | DMA_DCR_D_REQ_MASK // clear ERQ on end of transfer
bikeNomad 0:a8535703f23b 272 | DMA_DCR_CS_MASK
bikeNomad 0:a8535703f23b 273 | DMA_DCR_SSIZE(0) // 32-bit source transfers
bikeNomad 0:a8535703f23b 274 | DMA_DCR_DSIZE(0); // 32-bit destination transfers
bikeNomad 0:a8535703f23b 275
bikeNomad 0:a8535703f23b 276 dma->DMA[DMA_CHAN_START].DCR = DMA_DCR_EINT_MASK // enable interrupt on end of transfer
bikeNomad 0:a8535703f23b 277 | DMA_DCR_ERQ_MASK
bikeNomad 0:a8535703f23b 278 | DMA_DCR_D_REQ_MASK // clear ERQ on end of transfer
bikeNomad 0:a8535703f23b 279 | DMA_DCR_SINC_MASK // increment source each transfer
bikeNomad 0:a8535703f23b 280 | DMA_DCR_CS_MASK
bikeNomad 0:a8535703f23b 281 | DMA_DCR_SSIZE(0) // 32-bit source transfers
bikeNomad 0:a8535703f23b 282 | DMA_DCR_DSIZE(0);
bikeNomad 0:a8535703f23b 283
bikeNomad 0:a8535703f23b 284 tpm->SC |= TPM_SC_CMOD(1); // enable internal clocking
bikeNomad 0:a8535703f23b 285 }
bikeNomad 0:a8535703f23b 286
bikeNomad 1:86a910560879 287 #if !INSTANTIATE_TEMPLATES
bikeNomad 0:a8535703f23b 288
bikeNomad 0:a8535703f23b 289 extern "C" void DMA0_IRQHandler()
bikeNomad 0:a8535703f23b 290 {
bikeNomad 0:a8535703f23b 291 DMA_Type volatile *dma = DMA0;
bikeNomad 0:a8535703f23b 292 TPM_Type volatile *tpm = TPM0;
bikeNomad 0:a8535703f23b 293
bikeNomad 0:a8535703f23b 294 uint32_t db;
bikeNomad 0:a8535703f23b 295
bikeNomad 0:a8535703f23b 296 db = dma->DMA[DMA_CHAN_0_LOW].DSR_BCR;
bikeNomad 0:a8535703f23b 297 if (db & DMA_DSR_BCR_DONE_MASK) {
bikeNomad 0:a8535703f23b 298 dma->DMA[DMA_CHAN_0_LOW].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status
bikeNomad 0:a8535703f23b 299 }
bikeNomad 0:a8535703f23b 300
bikeNomad 0:a8535703f23b 301 db = dma->DMA[DMA_CHAN_1_LOW].DSR_BCR;
bikeNomad 0:a8535703f23b 302 if (db & DMA_DSR_BCR_DONE_MASK) {
bikeNomad 0:a8535703f23b 303 dma->DMA[DMA_CHAN_1_LOW].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status
bikeNomad 0:a8535703f23b 304 }
bikeNomad 0:a8535703f23b 305
bikeNomad 0:a8535703f23b 306 db = dma->DMA[DMA_CHAN_START].DSR_BCR;
bikeNomad 0:a8535703f23b 307 if (db & DMA_DSR_BCR_DONE_MASK) {
bikeNomad 0:a8535703f23b 308 dma->DMA[DMA_CHAN_START].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status
bikeNomad 0:a8535703f23b 309 }
bikeNomad 0:a8535703f23b 310
bikeNomad 0:a8535703f23b 311 tpm->SC = TPM_SC_TOF_MASK; // reset TOF flag; disable internal clocking
bikeNomad 0:a8535703f23b 312
bikeNomad 0:a8535703f23b 313 SET_DEBUG;
bikeNomad 0:a8535703f23b 314
bikeNomad 0:a8535703f23b 315 // set TPM0 to interrrupt after guardtime
bikeNomad 0:a8535703f23b 316 tpm->MOD = guardtime_period - 1; // 48MHz * 55 usec
bikeNomad 0:a8535703f23b 317 tpm->CNT = 0;
bikeNomad 0:a8535703f23b 318 tpm->SC = TPM_SC_PS(0) // 48MHz / 1 = 48MHz clock
bikeNomad 0:a8535703f23b 319 | TPM_SC_TOIE_MASK // enable interrupts
bikeNomad 0:a8535703f23b 320 | TPM_SC_CMOD(1); // and internal clocking
bikeNomad 0:a8535703f23b 321 }
bikeNomad 0:a8535703f23b 322
bikeNomad 0:a8535703f23b 323 extern "C" void TPM0_IRQHandler()
bikeNomad 0:a8535703f23b 324 {
bikeNomad 0:a8535703f23b 325 TPM0->SC = 0; // disable internal clocking
bikeNomad 0:a8535703f23b 326 TPM0->SC = TPM_SC_TOF_MASK;
bikeNomad 0:a8535703f23b 327 RESET_DEBUG;
bikeNomad 1:86a910560879 328 dma_done = true;
bikeNomad 0:a8535703f23b 329 }
bikeNomad 1:86a910560879 330
bikeNomad 1:86a910560879 331 #endif