mbed-dev_spine

Users » benkatz » Code » mbed-dev_spine

Dependents: SPIne CH_Communicatuin_Test CH_Communicatuin_Test2 MCP_SPIne ... more

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_uart.h@179:97f825502e2a, 2018-05-02 (annotated)

Committer:: benkatz
Date:: Wed May 02 18:08:16 2018 +0000
Revision:: 179:97f825502e2a
Parent:: 168:9672193075cf

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f7xx_hal_uart.h
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
AnnaBridge	168:9672193075cf	5	* @version V1.2.2
AnnaBridge	168:9672193075cf	6	* @date 14-April-2017
<>	144:ef7eb2e8f9f7	7	* @brief Header file of UART HAL module.
<>	144:ef7eb2e8f9f7	8	******************************************************************************
<>	144:ef7eb2e8f9f7	9	* @attention
<>	144:ef7eb2e8f9f7	10	*
AnnaBridge	168:9672193075cf	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	12	*
<>	144:ef7eb2e8f9f7	13	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	14	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	16	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	18	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	19	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	21	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	22	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	23	*
<>	144:ef7eb2e8f9f7	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	34	*
<>	144:ef7eb2e8f9f7	35	******************************************************************************
<>	144:ef7eb2e8f9f7	36	*/
<>	144:ef7eb2e8f9f7	37
<>	144:ef7eb2e8f9f7	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	144:ef7eb2e8f9f7	39	#ifndef __STM32F7xx_HAL_UART_H
<>	144:ef7eb2e8f9f7	40	#define __STM32F7xx_HAL_UART_H
<>	144:ef7eb2e8f9f7	41
<>	144:ef7eb2e8f9f7	42	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	43	extern "C" {
<>	144:ef7eb2e8f9f7	44	#endif
<>	144:ef7eb2e8f9f7	45
<>	144:ef7eb2e8f9f7	46	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	47	#include "stm32f7xx_hal_def.h"
<>	144:ef7eb2e8f9f7	48
<>	144:ef7eb2e8f9f7	49	/** @addtogroup STM32F7xx_HAL_Driver
<>	144:ef7eb2e8f9f7	50	* @{
<>	144:ef7eb2e8f9f7	51	*/
<>	144:ef7eb2e8f9f7	52
<>	144:ef7eb2e8f9f7	53	/** @addtogroup UART
<>	144:ef7eb2e8f9f7	54	* @{
<>	144:ef7eb2e8f9f7	55	*/
<>	144:ef7eb2e8f9f7	56
<>	144:ef7eb2e8f9f7	57	/* Exported types ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	58	/** @defgroup UART_Exported_Types UART Exported Types
<>	144:ef7eb2e8f9f7	59	* @{
<>	144:ef7eb2e8f9f7	60	*/
<>	144:ef7eb2e8f9f7	61
<>	144:ef7eb2e8f9f7	62	/**
<>	144:ef7eb2e8f9f7	63	* @brief UART Init Structure definition
<>	144:ef7eb2e8f9f7	64	*/
<>	144:ef7eb2e8f9f7	65	typedef struct
<>	144:ef7eb2e8f9f7	66	{
<>	144:ef7eb2e8f9f7	67	uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
<>	144:ef7eb2e8f9f7	68	The baud rate register is computed using the following formula:
<>	144:ef7eb2e8f9f7	69	- If oversampling is 16 or in LIN mode,
<>	144:ef7eb2e8f9f7	70	Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate)))
<>	144:ef7eb2e8f9f7	71	- If oversampling is 8,
<>	144:ef7eb2e8f9f7	72	Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4]
<>	144:ef7eb2e8f9f7	73	Baud Rate Register[3] = 0
<>	144:ef7eb2e8f9f7	74	Baud Rate Register[2:0] = (((2 * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1 */
<>	144:ef7eb2e8f9f7	75
<>	144:ef7eb2e8f9f7	76	uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
<>	144:ef7eb2e8f9f7	77	This parameter can be a value of @ref UARTEx_Word_Length */
<>	144:ef7eb2e8f9f7	78
<>	144:ef7eb2e8f9f7	79	uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
<>	144:ef7eb2e8f9f7	80	This parameter can be a value of @ref UART_Stop_Bits */
<>	144:ef7eb2e8f9f7	81
<>	144:ef7eb2e8f9f7	82	uint32_t Parity; /*!< Specifies the parity mode.
<>	144:ef7eb2e8f9f7	83	This parameter can be a value of @ref UART_Parity
<>	144:ef7eb2e8f9f7	84	@note When parity is enabled, the computed parity is inserted
<>	144:ef7eb2e8f9f7	85	at the MSB position of the transmitted data (9th bit when
<>	144:ef7eb2e8f9f7	86	the word length is set to 9 data bits; 8th bit when the
<>	144:ef7eb2e8f9f7	87	word length is set to 8 data bits). */
<>	144:ef7eb2e8f9f7	88
<>	144:ef7eb2e8f9f7	89	uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
<>	144:ef7eb2e8f9f7	90	This parameter can be a value of @ref UART_Mode */
<>	144:ef7eb2e8f9f7	91
<>	144:ef7eb2e8f9f7	92	uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled
<>	144:ef7eb2e8f9f7	93	or disabled.
<>	144:ef7eb2e8f9f7	94	This parameter can be a value of @ref UART_Hardware_Flow_Control */
<>	144:ef7eb2e8f9f7	95
<>	144:ef7eb2e8f9f7	96	uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
<>	144:ef7eb2e8f9f7	97	This parameter can be a value of @ref UART_Over_Sampling */
<>	144:ef7eb2e8f9f7	98
<>	144:ef7eb2e8f9f7	99	uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
<>	144:ef7eb2e8f9f7	100	Selecting the single sample method increases the receiver tolerance to clock
<>	144:ef7eb2e8f9f7	101	deviations. This parameter can be a value of @ref UART_OneBit_Sampling */
<>	144:ef7eb2e8f9f7	102	}UART_InitTypeDef;
<>	144:ef7eb2e8f9f7	103
<>	144:ef7eb2e8f9f7	104	/**
<>	144:ef7eb2e8f9f7	105	* @brief UART Advanced Features initialization structure definition
<>	144:ef7eb2e8f9f7	106	*/
<>	144:ef7eb2e8f9f7	107	typedef struct
<>	144:ef7eb2e8f9f7	108	{
<>	144:ef7eb2e8f9f7	109	uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several
<>	144:ef7eb2e8f9f7	110	Advanced Features may be initialized at the same time .
<>	144:ef7eb2e8f9f7	111	This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type */
<>	144:ef7eb2e8f9f7	112
<>	144:ef7eb2e8f9f7	113	uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
<>	144:ef7eb2e8f9f7	114	This parameter can be a value of @ref UART_Tx_Inv */
<>	144:ef7eb2e8f9f7	115
<>	144:ef7eb2e8f9f7	116	uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted.
<>	144:ef7eb2e8f9f7	117	This parameter can be a value of @ref UART_Rx_Inv */
<>	144:ef7eb2e8f9f7	118
<>	144:ef7eb2e8f9f7	119	uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic
<>	144:ef7eb2e8f9f7	120	vs negative/inverted logic).
<>	144:ef7eb2e8f9f7	121	This parameter can be a value of @ref UART_Data_Inv */
<>	144:ef7eb2e8f9f7	122
<>	144:ef7eb2e8f9f7	123	uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.
<>	144:ef7eb2e8f9f7	124	This parameter can be a value of @ref UART_Rx_Tx_Swap */
<>	144:ef7eb2e8f9f7	125
<>	144:ef7eb2e8f9f7	126	uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.
<>	144:ef7eb2e8f9f7	127	This parameter can be a value of @ref UART_Overrun_Disable */
<>	144:ef7eb2e8f9f7	128
<>	144:ef7eb2e8f9f7	129	uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.
<>	144:ef7eb2e8f9f7	130	This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error */
<>	144:ef7eb2e8f9f7	131
<>	144:ef7eb2e8f9f7	132	uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled.
<>	144:ef7eb2e8f9f7	133	This parameter can be a value of @ref UART_AutoBaudRate_Enable */
<>	144:ef7eb2e8f9f7	134
<>	144:ef7eb2e8f9f7	135	uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate
<>	144:ef7eb2e8f9f7	136	detection is carried out.
<>	144:ef7eb2e8f9f7	137	This parameter can be a value of @ref UART_AutoBaud_Rate_Mode */
<>	144:ef7eb2e8f9f7	138
<>	144:ef7eb2e8f9f7	139	uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
<>	144:ef7eb2e8f9f7	140	This parameter can be a value of @ref UART_MSB_First */
<>	144:ef7eb2e8f9f7	141	} UART_AdvFeatureInitTypeDef;
<>	144:ef7eb2e8f9f7	142
<>	144:ef7eb2e8f9f7	143
<>	144:ef7eb2e8f9f7	144
<>	144:ef7eb2e8f9f7	145	/**
<>	144:ef7eb2e8f9f7	146	* @brief HAL UART State structures definition
<>	144:ef7eb2e8f9f7	147	* @note HAL UART State value is a combination of 2 different substates: gState and RxState.
<>	144:ef7eb2e8f9f7	148	* - gState contains UART state information related to global Handle management
<>	144:ef7eb2e8f9f7	149	* and also information related to Tx operations.
<>	144:ef7eb2e8f9f7	150	* gState value coding follow below described bitmap :
<>	144:ef7eb2e8f9f7	151	* b7-b6 Error information
<>	144:ef7eb2e8f9f7	152	* 00 : No Error
<>	144:ef7eb2e8f9f7	153	* 01 : (Not Used)
<>	144:ef7eb2e8f9f7	154	* 10 : Timeout
<>	144:ef7eb2e8f9f7	155	* 11 : Error
<>	144:ef7eb2e8f9f7	156	* b5 IP initilisation status
<>	144:ef7eb2e8f9f7	157	* 0 : Reset (IP not initialized)
<>	144:ef7eb2e8f9f7	158	* 1 : Init done (IP not initialized. HAL UART Init function already called)
<>	144:ef7eb2e8f9f7	159	* b4-b3 (not used)
<>	144:ef7eb2e8f9f7	160	* xx : Should be set to 00
<>	144:ef7eb2e8f9f7	161	* b2 Intrinsic process state
<>	144:ef7eb2e8f9f7	162	* 0 : Ready
<>	144:ef7eb2e8f9f7	163	* 1 : Busy (IP busy with some configuration or internal operations)
<>	144:ef7eb2e8f9f7	164	* b1 (not used)
<>	144:ef7eb2e8f9f7	165	* x : Should be set to 0
<>	144:ef7eb2e8f9f7	166	* b0 Tx state
<>	144:ef7eb2e8f9f7	167	* 0 : Ready (no Tx operation ongoing)
<>	144:ef7eb2e8f9f7	168	* 1 : Busy (Tx operation ongoing)
<>	144:ef7eb2e8f9f7	169	* - RxState contains information related to Rx operations.
<>	144:ef7eb2e8f9f7	170	* RxState value coding follow below described bitmap :
<>	144:ef7eb2e8f9f7	171	* b7-b6 (not used)
<>	144:ef7eb2e8f9f7	172	* xx : Should be set to 00
<>	144:ef7eb2e8f9f7	173	* b5 IP initilisation status
<>	144:ef7eb2e8f9f7	174	* 0 : Reset (IP not initialized)
<>	144:ef7eb2e8f9f7	175	* 1 : Init done (IP not initialized)
<>	144:ef7eb2e8f9f7	176	* b4-b2 (not used)
<>	144:ef7eb2e8f9f7	177	* xxx : Should be set to 000
<>	144:ef7eb2e8f9f7	178	* b1 Rx state
<>	144:ef7eb2e8f9f7	179	* 0 : Ready (no Rx operation ongoing)
<>	144:ef7eb2e8f9f7	180	* 1 : Busy (Rx operation ongoing)
<>	144:ef7eb2e8f9f7	181	* b0 (not used)
<>	144:ef7eb2e8f9f7	182	* x : Should be set to 0.
<>	144:ef7eb2e8f9f7	183	*/
<>	144:ef7eb2e8f9f7	184	typedef enum
<>	144:ef7eb2e8f9f7	185	{
<>	144:ef7eb2e8f9f7	186	HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized
<>	144:ef7eb2e8f9f7	187	Value is allowed for gState and RxState */
<>	144:ef7eb2e8f9f7	188	HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
<>	144:ef7eb2e8f9f7	189	Value is allowed for gState and RxState */
<>	144:ef7eb2e8f9f7	190	HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
<>	144:ef7eb2e8f9f7	191	Value is allowed for gState only */
<>	144:ef7eb2e8f9f7	192	HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
<>	144:ef7eb2e8f9f7	193	Value is allowed for gState only */
<>	144:ef7eb2e8f9f7	194	HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
<>	144:ef7eb2e8f9f7	195	Value is allowed for RxState only */
<>	144:ef7eb2e8f9f7	196	HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
<>	144:ef7eb2e8f9f7	197	Not to be used for neither gState nor RxState.
<>	144:ef7eb2e8f9f7	198	Value is result of combination (Or) between gState and RxState values */
<>	144:ef7eb2e8f9f7	199	HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
<>	144:ef7eb2e8f9f7	200	Value is allowed for gState only */
<>	144:ef7eb2e8f9f7	201	HAL_UART_STATE_ERROR = 0xE0U /*!< Error
<>	144:ef7eb2e8f9f7	202	Value is allowed for gState only */
<>	144:ef7eb2e8f9f7	203	}HAL_UART_StateTypeDef;
<>	144:ef7eb2e8f9f7	204
<>	144:ef7eb2e8f9f7	205	/**
<>	144:ef7eb2e8f9f7	206	* @brief UART clock sources definition
<>	144:ef7eb2e8f9f7	207	*/
<>	144:ef7eb2e8f9f7	208	typedef enum
<>	144:ef7eb2e8f9f7	209	{
<>	144:ef7eb2e8f9f7	210	UART_CLOCKSOURCE_PCLK1 = 0x00U, /!< PCLK1 clock source /
<>	144:ef7eb2e8f9f7	211	UART_CLOCKSOURCE_PCLK2 = 0x01U, /!< PCLK2 clock source /
<>	144:ef7eb2e8f9f7	212	UART_CLOCKSOURCE_HSI = 0x02U, /!< HSI clock source /
<>	144:ef7eb2e8f9f7	213	UART_CLOCKSOURCE_SYSCLK = 0x04U, /!< SYSCLK clock source /
<>	144:ef7eb2e8f9f7	214	UART_CLOCKSOURCE_LSE = 0x08U, /!< LSE clock source /
<>	144:ef7eb2e8f9f7	215	UART_CLOCKSOURCE_UNDEFINED = 0x10U /!< Undefined clock source /
<>	144:ef7eb2e8f9f7	216	}UART_ClockSourceTypeDef;
<>	144:ef7eb2e8f9f7	217
<>	144:ef7eb2e8f9f7	218	/**
<>	144:ef7eb2e8f9f7	219	* @brief UART handle Structure definition
<>	144:ef7eb2e8f9f7	220	*/
<>	144:ef7eb2e8f9f7	221	typedef struct
<>	144:ef7eb2e8f9f7	222	{
<>	144:ef7eb2e8f9f7	223	USART_TypeDef Instance; /!< UART registers base address */
<>	144:ef7eb2e8f9f7	224
<>	144:ef7eb2e8f9f7	225	UART_InitTypeDef Init; /!< UART communication parameters /
<>	144:ef7eb2e8f9f7	226
<>	144:ef7eb2e8f9f7	227	UART_AdvFeatureInitTypeDef AdvancedInit; /!< UART Advanced Features initialization parameters /
<>	144:ef7eb2e8f9f7	228
<>	144:ef7eb2e8f9f7	229	uint8_t pTxBuffPtr; /!< Pointer to UART Tx transfer Buffer */
<>	144:ef7eb2e8f9f7	230
<>	144:ef7eb2e8f9f7	231	uint16_t TxXferSize; /!< UART Tx Transfer size /
<>	144:ef7eb2e8f9f7	232
<>	157:ff67d9f36b67	233	__IO uint16_t TxXferCount; /!< UART Tx Transfer Counter /
<>	144:ef7eb2e8f9f7	234
<>	144:ef7eb2e8f9f7	235	uint8_t pRxBuffPtr; /!< Pointer to UART Rx transfer Buffer */
<>	144:ef7eb2e8f9f7	236
<>	144:ef7eb2e8f9f7	237	uint16_t RxXferSize; /!< UART Rx Transfer size /
<>	144:ef7eb2e8f9f7	238
<>	157:ff67d9f36b67	239	__IO uint16_t RxXferCount; /!< UART Rx Transfer Counter /
<>	144:ef7eb2e8f9f7	240
<>	144:ef7eb2e8f9f7	241	uint16_t Mask; /!< UART Rx RDR register mask /
<>	144:ef7eb2e8f9f7	242
<>	144:ef7eb2e8f9f7	243	DMA_HandleTypeDef hdmatx; /!< UART Tx DMA Handle parameters */
<>	144:ef7eb2e8f9f7	244
<>	144:ef7eb2e8f9f7	245	DMA_HandleTypeDef hdmarx; /!< UART Rx DMA Handle parameters */
<>	144:ef7eb2e8f9f7	246
<>	144:ef7eb2e8f9f7	247	HAL_LockTypeDef Lock; /!< Locking object /
<>	144:ef7eb2e8f9f7	248
<>	144:ef7eb2e8f9f7	249	__IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management
<>	144:ef7eb2e8f9f7	250	and also related to Tx operations.
<>	144:ef7eb2e8f9f7	251	This parameter can be a value of @ref HAL_UART_StateTypeDef */
<>	144:ef7eb2e8f9f7	252
<>	144:ef7eb2e8f9f7	253	__IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations.
<>	144:ef7eb2e8f9f7	254	This parameter can be a value of @ref HAL_UART_StateTypeDef */
<>	144:ef7eb2e8f9f7	255
<>	144:ef7eb2e8f9f7	256	__IO uint32_t ErrorCode; /!< UART Error code /
<>	144:ef7eb2e8f9f7	257
<>	144:ef7eb2e8f9f7	258	}UART_HandleTypeDef;
<>	144:ef7eb2e8f9f7	259
<>	144:ef7eb2e8f9f7	260	/**
<>	144:ef7eb2e8f9f7	261	* @}
<>	144:ef7eb2e8f9f7	262	*/
<>	144:ef7eb2e8f9f7	263
<>	144:ef7eb2e8f9f7	264	/* Exported constants --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	265	/** @defgroup UART_Exported_Constants UART Exported Constants
<>	144:ef7eb2e8f9f7	266	* @{
<>	144:ef7eb2e8f9f7	267	*/
<>	144:ef7eb2e8f9f7	268	/** @defgroup UART_Error_Definition UART Error Definition
<>	144:ef7eb2e8f9f7	269	* @{
<>	144:ef7eb2e8f9f7	270	*/
<>	144:ef7eb2e8f9f7	271	#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U) /!< No error /
<>	144:ef7eb2e8f9f7	272	#define HAL_UART_ERROR_PE ((uint32_t)0x00000001U) /!< Parity error /
<>	144:ef7eb2e8f9f7	273	#define HAL_UART_ERROR_NE ((uint32_t)0x00000002U) /!< Noise error /
<>	144:ef7eb2e8f9f7	274	#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /!< frame error /
<>	144:ef7eb2e8f9f7	275	#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /!< Overrun error /
<>	144:ef7eb2e8f9f7	276	#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /!< DMA transfer error /
<>	144:ef7eb2e8f9f7	277	/**
<>	144:ef7eb2e8f9f7	278	* @}
<>	144:ef7eb2e8f9f7	279	*/
<>	144:ef7eb2e8f9f7	280	/** @defgroup UART_Stop_Bits UART Number of Stop Bits
<>	144:ef7eb2e8f9f7	281	* @{
<>	144:ef7eb2e8f9f7	282	*/
<>	144:ef7eb2e8f9f7	283	#define UART_STOPBITS_1 ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	284	#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
<>	144:ef7eb2e8f9f7	285	/**
<>	144:ef7eb2e8f9f7	286	* @}
<>	144:ef7eb2e8f9f7	287	*/
<>	144:ef7eb2e8f9f7	288
<>	144:ef7eb2e8f9f7	289	/** @defgroup UART_Parity UART Parity
<>	144:ef7eb2e8f9f7	290	* @{
<>	144:ef7eb2e8f9f7	291	*/
<>	144:ef7eb2e8f9f7	292	#define UART_PARITY_NONE ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	293	#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
<>	144:ef7eb2e8f9f7	294	#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE \| USART_CR1_PS))
<>	144:ef7eb2e8f9f7	295	/**
<>	144:ef7eb2e8f9f7	296	* @}
<>	144:ef7eb2e8f9f7	297	*/
<>	144:ef7eb2e8f9f7	298
<>	144:ef7eb2e8f9f7	299	/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
<>	144:ef7eb2e8f9f7	300	* @{
<>	144:ef7eb2e8f9f7	301	*/
<>	144:ef7eb2e8f9f7	302	#define UART_HWCONTROL_NONE ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	303	#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)
<>	144:ef7eb2e8f9f7	304	#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)
<>	144:ef7eb2e8f9f7	305	#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE \| USART_CR3_CTSE))
<>	144:ef7eb2e8f9f7	306	/**
<>	144:ef7eb2e8f9f7	307	* @}
<>	144:ef7eb2e8f9f7	308	*/
<>	144:ef7eb2e8f9f7	309
<>	144:ef7eb2e8f9f7	310	/** @defgroup UART_Mode UART Transfer Mode
<>	144:ef7eb2e8f9f7	311	* @{
<>	144:ef7eb2e8f9f7	312	*/
<>	144:ef7eb2e8f9f7	313	#define UART_MODE_RX ((uint32_t)USART_CR1_RE)
<>	144:ef7eb2e8f9f7	314	#define UART_MODE_TX ((uint32_t)USART_CR1_TE)
<>	144:ef7eb2e8f9f7	315	#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE \|USART_CR1_RE))
<>	144:ef7eb2e8f9f7	316	/**
<>	144:ef7eb2e8f9f7	317	* @}
<>	144:ef7eb2e8f9f7	318	*/
<>	144:ef7eb2e8f9f7	319
<>	144:ef7eb2e8f9f7	320	/** @defgroup UART_State UART State
<>	144:ef7eb2e8f9f7	321	* @{
<>	144:ef7eb2e8f9f7	322	*/
<>	144:ef7eb2e8f9f7	323	#define UART_STATE_DISABLE ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	324	#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)
<>	144:ef7eb2e8f9f7	325	/**
<>	144:ef7eb2e8f9f7	326	* @}
<>	144:ef7eb2e8f9f7	327	*/
<>	144:ef7eb2e8f9f7	328
<>	144:ef7eb2e8f9f7	329	/** @defgroup UART_Over_Sampling UART Over Sampling
<>	144:ef7eb2e8f9f7	330	* @{
<>	144:ef7eb2e8f9f7	331	*/
<>	144:ef7eb2e8f9f7	332	#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	333	#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)
<>	144:ef7eb2e8f9f7	334	/**
<>	144:ef7eb2e8f9f7	335	* @}
<>	144:ef7eb2e8f9f7	336	*/
<>	144:ef7eb2e8f9f7	337
<>	144:ef7eb2e8f9f7	338	/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
<>	144:ef7eb2e8f9f7	339	* @{
<>	144:ef7eb2e8f9f7	340	*/
<>	144:ef7eb2e8f9f7	341	#define UART_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	342	#define UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)
<>	144:ef7eb2e8f9f7	343	/**
<>	144:ef7eb2e8f9f7	344	* @}
<>	144:ef7eb2e8f9f7	345	*/
<>	144:ef7eb2e8f9f7	346
<>	144:ef7eb2e8f9f7	347	/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode
<>	144:ef7eb2e8f9f7	348	* @{
<>	144:ef7eb2e8f9f7	349	*/
<>	144:ef7eb2e8f9f7	350	#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x0000U)
<>	144:ef7eb2e8f9f7	351	#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0)
<>	144:ef7eb2e8f9f7	352	#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1)
<>	144:ef7eb2e8f9f7	353	#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE)
<>	144:ef7eb2e8f9f7	354	/**
<>	144:ef7eb2e8f9f7	355	* @}
<>	144:ef7eb2e8f9f7	356	*/
<>	144:ef7eb2e8f9f7	357
<>	144:ef7eb2e8f9f7	358	/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut
<>	144:ef7eb2e8f9f7	359	* @{
<>	144:ef7eb2e8f9f7	360	*/
<>	144:ef7eb2e8f9f7	361	#define UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	362	#define UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)
<>	144:ef7eb2e8f9f7	363	/**
<>	144:ef7eb2e8f9f7	364	* @}
<>	144:ef7eb2e8f9f7	365	*/
<>	144:ef7eb2e8f9f7	366
<>	144:ef7eb2e8f9f7	367	/** @defgroup UART_LIN UART Local Interconnection Network mode
<>	144:ef7eb2e8f9f7	368	* @{
<>	144:ef7eb2e8f9f7	369	*/
<>	144:ef7eb2e8f9f7	370	#define UART_LIN_DISABLE ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	371	#define UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN)
<>	144:ef7eb2e8f9f7	372	/**
<>	144:ef7eb2e8f9f7	373	* @}
<>	144:ef7eb2e8f9f7	374	*/
<>	144:ef7eb2e8f9f7	375
<>	144:ef7eb2e8f9f7	376	/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection
<>	144:ef7eb2e8f9f7	377	* @{
<>	144:ef7eb2e8f9f7	378	*/
<>	144:ef7eb2e8f9f7	379	#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	380	#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)
<>	144:ef7eb2e8f9f7	381	/**
<>	144:ef7eb2e8f9f7	382	* @}
<>	144:ef7eb2e8f9f7	383	*/
<>	144:ef7eb2e8f9f7	384
<>	144:ef7eb2e8f9f7	385	/** @defgroup UART_DMA_Tx UART DMA Tx
<>	144:ef7eb2e8f9f7	386	* @{
<>	144:ef7eb2e8f9f7	387	*/
<>	144:ef7eb2e8f9f7	388	#define UART_DMA_TX_DISABLE ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	389	#define UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)
<>	144:ef7eb2e8f9f7	390	/**
<>	144:ef7eb2e8f9f7	391	* @}
<>	144:ef7eb2e8f9f7	392	*/
<>	144:ef7eb2e8f9f7	393
<>	144:ef7eb2e8f9f7	394	/** @defgroup UART_DMA_Rx UART DMA Rx
<>	144:ef7eb2e8f9f7	395	* @{
<>	144:ef7eb2e8f9f7	396	*/
<>	144:ef7eb2e8f9f7	397	#define UART_DMA_RX_DISABLE ((uint32_t)0x0000U)
<>	144:ef7eb2e8f9f7	398	#define UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)
<>	144:ef7eb2e8f9f7	399	/**
<>	144:ef7eb2e8f9f7	400	* @}
<>	144:ef7eb2e8f9f7	401	*/
<>	144:ef7eb2e8f9f7	402
<>	144:ef7eb2e8f9f7	403	/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection
<>	144:ef7eb2e8f9f7	404	* @{
<>	144:ef7eb2e8f9f7	405	*/
<>	144:ef7eb2e8f9f7	406	#define UART_HALF_DUPLEX_DISABLE ((uint32_t)0x0000U)
<>	144:ef7eb2e8f9f7	407	#define UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL)
<>	144:ef7eb2e8f9f7	408	/**
<>	144:ef7eb2e8f9f7	409	* @}
<>	144:ef7eb2e8f9f7	410	*/
<>	144:ef7eb2e8f9f7	411
<>	144:ef7eb2e8f9f7	412	/** @defgroup UART_WakeUp_Methods UART WakeUp Methods
<>	144:ef7eb2e8f9f7	413	* @{
<>	144:ef7eb2e8f9f7	414	*/
<>	144:ef7eb2e8f9f7	415	#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	416	#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)
<>	144:ef7eb2e8f9f7	417	/**
<>	144:ef7eb2e8f9f7	418	* @}
<>	144:ef7eb2e8f9f7	419	*/
<>	144:ef7eb2e8f9f7	420
<>	144:ef7eb2e8f9f7	421	/** @defgroup UART_Request_Parameters UART Request Parameters
<>	144:ef7eb2e8f9f7	422	* @{
<>	144:ef7eb2e8f9f7	423	*/
<>	144:ef7eb2e8f9f7	424	#define UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /!< Auto-Baud Rate Request /
<>	144:ef7eb2e8f9f7	425	#define UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ) /!< Send Break Request /
<>	144:ef7eb2e8f9f7	426	#define UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ) /!< Mute Mode Request /
<>	144:ef7eb2e8f9f7	427	#define UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /!< Receive Data flush Request /
<>	144:ef7eb2e8f9f7	428	#define UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /!< Transmit data flush Request /
<>	144:ef7eb2e8f9f7	429	/**
<>	144:ef7eb2e8f9f7	430	* @}
<>	144:ef7eb2e8f9f7	431	*/
<>	144:ef7eb2e8f9f7	432
<>	144:ef7eb2e8f9f7	433	/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type
<>	144:ef7eb2e8f9f7	434	* @{
<>	144:ef7eb2e8f9f7	435	*/
<>	144:ef7eb2e8f9f7	436	#define UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	437	#define UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001U)
<>	144:ef7eb2e8f9f7	438	#define UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002U)
<>	144:ef7eb2e8f9f7	439	#define UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004U)
<>	144:ef7eb2e8f9f7	440	#define UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008U)
<>	144:ef7eb2e8f9f7	441	#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010U)
<>	144:ef7eb2e8f9f7	442	#define UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020U)
<>	144:ef7eb2e8f9f7	443	#define UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040U)
<>	144:ef7eb2e8f9f7	444	#define UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080U)
<>	144:ef7eb2e8f9f7	445	/**
<>	144:ef7eb2e8f9f7	446	* @}
<>	144:ef7eb2e8f9f7	447	*/
<>	144:ef7eb2e8f9f7	448
<>	144:ef7eb2e8f9f7	449	/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
<>	144:ef7eb2e8f9f7	450	* @{
<>	144:ef7eb2e8f9f7	451	*/
<>	144:ef7eb2e8f9f7	452	#define UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	453	#define UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)
<>	144:ef7eb2e8f9f7	454	/**
<>	144:ef7eb2e8f9f7	455	* @}
<>	144:ef7eb2e8f9f7	456	*/
<>	144:ef7eb2e8f9f7	457
<>	144:ef7eb2e8f9f7	458	/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
<>	144:ef7eb2e8f9f7	459	* @{
<>	144:ef7eb2e8f9f7	460	*/
<>	144:ef7eb2e8f9f7	461	#define UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	462	#define UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)
<>	144:ef7eb2e8f9f7	463	/**
<>	144:ef7eb2e8f9f7	464	* @}
<>	144:ef7eb2e8f9f7	465	*/
<>	144:ef7eb2e8f9f7	466
<>	144:ef7eb2e8f9f7	467	/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion
<>	144:ef7eb2e8f9f7	468	* @{
<>	144:ef7eb2e8f9f7	469	*/
<>	144:ef7eb2e8f9f7	470	#define UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	471	#define UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)
<>	144:ef7eb2e8f9f7	472	/**
<>	144:ef7eb2e8f9f7	473	* @}
<>	144:ef7eb2e8f9f7	474	*/
<>	144:ef7eb2e8f9f7	475
<>	144:ef7eb2e8f9f7	476	/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
<>	144:ef7eb2e8f9f7	477	* @{
<>	144:ef7eb2e8f9f7	478	*/
<>	144:ef7eb2e8f9f7	479	#define UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	480	#define UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)
<>	144:ef7eb2e8f9f7	481	/**
<>	144:ef7eb2e8f9f7	482	* @}
<>	144:ef7eb2e8f9f7	483	*/
<>	144:ef7eb2e8f9f7	484
<>	144:ef7eb2e8f9f7	485	/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable
<>	144:ef7eb2e8f9f7	486	* @{
<>	144:ef7eb2e8f9f7	487	*/
<>	144:ef7eb2e8f9f7	488	#define UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	489	#define UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)
<>	144:ef7eb2e8f9f7	490	/**
<>	144:ef7eb2e8f9f7	491	* @}
<>	144:ef7eb2e8f9f7	492	*/
<>	144:ef7eb2e8f9f7	493
<>	144:ef7eb2e8f9f7	494	/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable
<>	144:ef7eb2e8f9f7	495	* @{
<>	144:ef7eb2e8f9f7	496	*/
<>	144:ef7eb2e8f9f7	497	#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	498	#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN)
<>	144:ef7eb2e8f9f7	499	/**
<>	144:ef7eb2e8f9f7	500	* @}
<>	144:ef7eb2e8f9f7	501	*/
<>	144:ef7eb2e8f9f7	502
<>	144:ef7eb2e8f9f7	503	/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error
<>	144:ef7eb2e8f9f7	504	* @{
<>	144:ef7eb2e8f9f7	505	*/
<>	144:ef7eb2e8f9f7	506	#define UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	507	#define UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)
<>	144:ef7eb2e8f9f7	508	/**
<>	144:ef7eb2e8f9f7	509	* @}
<>	144:ef7eb2e8f9f7	510	*/
<>	144:ef7eb2e8f9f7	511
<>	144:ef7eb2e8f9f7	512	/** @defgroup UART_MSB_First UART Advanced Feature MSB First
<>	144:ef7eb2e8f9f7	513	* @{
<>	144:ef7eb2e8f9f7	514	*/
<>	144:ef7eb2e8f9f7	515	#define UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	516	#define UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)
<>	144:ef7eb2e8f9f7	517	/**
<>	144:ef7eb2e8f9f7	518	* @}
<>	144:ef7eb2e8f9f7	519	*/
<>	144:ef7eb2e8f9f7	520
<>	144:ef7eb2e8f9f7	521	/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable
<>	144:ef7eb2e8f9f7	522	* @{
<>	144:ef7eb2e8f9f7	523	*/
<>	144:ef7eb2e8f9f7	524	#define UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	525	#define UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME)
<>	144:ef7eb2e8f9f7	526	/**
<>	144:ef7eb2e8f9f7	527	* @}
<>	144:ef7eb2e8f9f7	528	*/
<>	144:ef7eb2e8f9f7	529
<>	144:ef7eb2e8f9f7	530	/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register
<>	144:ef7eb2e8f9f7	531	* @{
<>	144:ef7eb2e8f9f7	532	*/
<>	144:ef7eb2e8f9f7	533	#define UART_CR2_ADDRESS_LSB_POS ((uint32_t) 24U)
<>	144:ef7eb2e8f9f7	534	/**
<>	144:ef7eb2e8f9f7	535	* @}
<>	144:ef7eb2e8f9f7	536	*/
<>	144:ef7eb2e8f9f7	537
<>	144:ef7eb2e8f9f7	538	/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity
<>	144:ef7eb2e8f9f7	539	* @{
<>	144:ef7eb2e8f9f7	540	*/
<>	144:ef7eb2e8f9f7	541	#define UART_DE_POLARITY_HIGH ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	542	#define UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP)
<>	144:ef7eb2e8f9f7	543	/**
<>	144:ef7eb2e8f9f7	544	* @}
<>	144:ef7eb2e8f9f7	545	*/
<>	144:ef7eb2e8f9f7	546
<>	144:ef7eb2e8f9f7	547	/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register
<>	144:ef7eb2e8f9f7	548	* @{
<>	144:ef7eb2e8f9f7	549	*/
<>	144:ef7eb2e8f9f7	550	#define UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21U)
<>	144:ef7eb2e8f9f7	551	/**
<>	144:ef7eb2e8f9f7	552	* @}
<>	144:ef7eb2e8f9f7	553	*/
<>	144:ef7eb2e8f9f7	554
<>	144:ef7eb2e8f9f7	555	/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register
<>	144:ef7eb2e8f9f7	556	* @{
<>	144:ef7eb2e8f9f7	557	*/
<>	144:ef7eb2e8f9f7	558	#define UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16U)
<>	144:ef7eb2e8f9f7	559	/**
<>	144:ef7eb2e8f9f7	560	* @}
<>	144:ef7eb2e8f9f7	561	*/
<>	144:ef7eb2e8f9f7	562
<>	144:ef7eb2e8f9f7	563	/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask
<>	144:ef7eb2e8f9f7	564	* @{
<>	144:ef7eb2e8f9f7	565	*/
<>	144:ef7eb2e8f9f7	566	#define UART_IT_MASK ((uint32_t)0x001FU)
<>	144:ef7eb2e8f9f7	567	/**
<>	144:ef7eb2e8f9f7	568	* @}
<>	144:ef7eb2e8f9f7	569	*/
<>	144:ef7eb2e8f9f7	570
<>	144:ef7eb2e8f9f7	571	/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value
<>	144:ef7eb2e8f9f7	572	* @{
<>	144:ef7eb2e8f9f7	573	*/
<>	144:ef7eb2e8f9f7	574	#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU
<>	144:ef7eb2e8f9f7	575	/**
<>	144:ef7eb2e8f9f7	576	* @}
<>	144:ef7eb2e8f9f7	577	*/
<>	144:ef7eb2e8f9f7	578
<>	144:ef7eb2e8f9f7	579	/** @defgroup UART_Flags UART Status Flags
<>	144:ef7eb2e8f9f7	580	* Elements values convention: 0xXXXX
<>	144:ef7eb2e8f9f7	581	* - 0xXXXX : Flag mask in the ISR register
<>	144:ef7eb2e8f9f7	582	* @{
<>	144:ef7eb2e8f9f7	583	*/
<>	144:ef7eb2e8f9f7	584	#define UART_FLAG_TEACK ((uint32_t)0x00200000U)
<>	144:ef7eb2e8f9f7	585	#define UART_FLAG_SBKF ((uint32_t)0x00040000U)
<>	144:ef7eb2e8f9f7	586	#define UART_FLAG_CMF ((uint32_t)0x00020000U)
<>	144:ef7eb2e8f9f7	587	#define UART_FLAG_BUSY ((uint32_t)0x00010000U)
<>	144:ef7eb2e8f9f7	588	#define UART_FLAG_ABRF ((uint32_t)0x00008000U)
<>	144:ef7eb2e8f9f7	589	#define UART_FLAG_ABRE ((uint32_t)0x00004000U)
<>	144:ef7eb2e8f9f7	590	#define UART_FLAG_EOBF ((uint32_t)0x00001000U)
<>	144:ef7eb2e8f9f7	591	#define UART_FLAG_RTOF ((uint32_t)0x00000800U)
<>	144:ef7eb2e8f9f7	592	#define UART_FLAG_CTS ((uint32_t)0x00000400U)
<>	144:ef7eb2e8f9f7	593	#define UART_FLAG_CTSIF ((uint32_t)0x00000200U)
<>	144:ef7eb2e8f9f7	594	#define UART_FLAG_LBDF ((uint32_t)0x00000100U)
<>	144:ef7eb2e8f9f7	595	#define UART_FLAG_TXE ((uint32_t)0x00000080U)
<>	144:ef7eb2e8f9f7	596	#define UART_FLAG_TC ((uint32_t)0x00000040U)
<>	144:ef7eb2e8f9f7	597	#define UART_FLAG_RXNE ((uint32_t)0x00000020U)
<>	144:ef7eb2e8f9f7	598	#define UART_FLAG_IDLE ((uint32_t)0x00000010U)
<>	144:ef7eb2e8f9f7	599	#define UART_FLAG_ORE ((uint32_t)0x00000008U)
<>	144:ef7eb2e8f9f7	600	#define UART_FLAG_NE ((uint32_t)0x00000004U)
<>	144:ef7eb2e8f9f7	601	#define UART_FLAG_FE ((uint32_t)0x00000002U)
<>	144:ef7eb2e8f9f7	602	#define UART_FLAG_PE ((uint32_t)0x00000001U)
<>	144:ef7eb2e8f9f7	603	/**
<>	144:ef7eb2e8f9f7	604	* @}
<>	144:ef7eb2e8f9f7	605	*/
<>	144:ef7eb2e8f9f7	606
<>	144:ef7eb2e8f9f7	607	/** @defgroup UART_Interrupt_definition UART Interrupts Definition
<>	144:ef7eb2e8f9f7	608	* Elements values convention: 0000ZZZZ0XXYYYYYb
<>	144:ef7eb2e8f9f7	609	* - YYYYY : Interrupt source position in the XX register (5bits)
<>	144:ef7eb2e8f9f7	610	* - XX : Interrupt source register (2bits)
<>	144:ef7eb2e8f9f7	611	* - 01: CR1 register
<>	144:ef7eb2e8f9f7	612	* - 10: CR2 register
<>	144:ef7eb2e8f9f7	613	* - 11: CR3 register
<>	144:ef7eb2e8f9f7	614	* - ZZZZ : Flag position in the ISR register(4bits)
<>	144:ef7eb2e8f9f7	615	* @{
<>	144:ef7eb2e8f9f7	616	*/
<>	144:ef7eb2e8f9f7	617	#define UART_IT_PE ((uint32_t)0x0028U)
<>	144:ef7eb2e8f9f7	618	#define UART_IT_TXE ((uint32_t)0x0727U)
<>	144:ef7eb2e8f9f7	619	#define UART_IT_TC ((uint32_t)0x0626U)
<>	144:ef7eb2e8f9f7	620	#define UART_IT_RXNE ((uint32_t)0x0525U)
<>	144:ef7eb2e8f9f7	621	#define UART_IT_IDLE ((uint32_t)0x0424U)
<>	144:ef7eb2e8f9f7	622	#define UART_IT_LBD ((uint32_t)0x0846U)
<>	144:ef7eb2e8f9f7	623	#define UART_IT_CTS ((uint32_t)0x096AU)
<>	144:ef7eb2e8f9f7	624	#define UART_IT_CM ((uint32_t)0x112EU)
<>	144:ef7eb2e8f9f7	625
<>	144:ef7eb2e8f9f7	626	/** Elements values convention: 000000000XXYYYYYb
<>	144:ef7eb2e8f9f7	627	* - YYYYY : Interrupt source position in the XX register (5bits)
<>	144:ef7eb2e8f9f7	628	* - XX : Interrupt source register (2bits)
<>	144:ef7eb2e8f9f7	629	* - 01: CR1 register
<>	144:ef7eb2e8f9f7	630	* - 10: CR2 register
<>	144:ef7eb2e8f9f7	631	* - 11: CR3 register
<>	144:ef7eb2e8f9f7	632	*/
<>	144:ef7eb2e8f9f7	633	#define UART_IT_ERR ((uint32_t)0x0060U)
<>	144:ef7eb2e8f9f7	634
<>	144:ef7eb2e8f9f7	635	/** Elements values convention: 0000ZZZZ00000000b
<>	144:ef7eb2e8f9f7	636	* - ZZZZ : Flag position in the ISR register(4bits)
<>	144:ef7eb2e8f9f7	637	*/
<>	144:ef7eb2e8f9f7	638	#define UART_IT_ORE ((uint32_t)0x0300U)
<>	144:ef7eb2e8f9f7	639	#define UART_IT_NE ((uint32_t)0x0200U)
<>	144:ef7eb2e8f9f7	640	#define UART_IT_FE ((uint32_t)0x0100U)
<>	144:ef7eb2e8f9f7	641	/**
<>	144:ef7eb2e8f9f7	642	* @}
<>	144:ef7eb2e8f9f7	643	*/
<>	144:ef7eb2e8f9f7	644
<>	144:ef7eb2e8f9f7	645	/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags
<>	144:ef7eb2e8f9f7	646	* @{
<>	144:ef7eb2e8f9f7	647	*/
<>	144:ef7eb2e8f9f7	648	#define UART_CLEAR_PEF USART_ICR_PECF /!< Parity Error Clear Flag /
<>	144:ef7eb2e8f9f7	649	#define UART_CLEAR_FEF USART_ICR_FECF /!< Framing Error Clear Flag /
<>	144:ef7eb2e8f9f7	650	#define UART_CLEAR_NEF USART_ICR_NCF /!< Noise detected Clear Flag /
<>	144:ef7eb2e8f9f7	651	#define UART_CLEAR_OREF USART_ICR_ORECF /!< OverRun Error Clear Flag /
<>	144:ef7eb2e8f9f7	652	#define UART_CLEAR_IDLEF USART_ICR_IDLECF /!< IDLE line detected Clear Flag /
<>	144:ef7eb2e8f9f7	653	#define UART_CLEAR_TCF USART_ICR_TCCF /!< Transmission Complete Clear Flag /
<>	144:ef7eb2e8f9f7	654	#define UART_CLEAR_LBDF USART_ICR_LBDCF /!< LIN Break Detection Clear Flag /
<>	144:ef7eb2e8f9f7	655	#define UART_CLEAR_CTSF USART_ICR_CTSCF /!< CTS Interrupt Clear Flag /
<>	144:ef7eb2e8f9f7	656	#define UART_CLEAR_RTOF USART_ICR_RTOCF /!< Receiver Time Out Clear Flag /
<>	144:ef7eb2e8f9f7	657	#define UART_CLEAR_EOBF USART_ICR_EOBCF /!< End Of Block Clear Flag /
<>	144:ef7eb2e8f9f7	658	#define UART_CLEAR_CMF USART_ICR_CMCF /!< Character Match Clear Flag /
<>	144:ef7eb2e8f9f7	659	/**
<>	144:ef7eb2e8f9f7	660	* @}
<>	144:ef7eb2e8f9f7	661	*/
<>	144:ef7eb2e8f9f7	662
<>	144:ef7eb2e8f9f7	663
<>	144:ef7eb2e8f9f7	664	/**
<>	144:ef7eb2e8f9f7	665	* @}
<>	144:ef7eb2e8f9f7	666	*/
<>	144:ef7eb2e8f9f7	667
<>	144:ef7eb2e8f9f7	668	/* Exported macros -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	669	/** @defgroup UART_Exported_Macros UART Exported Macros
<>	144:ef7eb2e8f9f7	670	* @{
<>	144:ef7eb2e8f9f7	671	*/
<>	144:ef7eb2e8f9f7	672
<>	144:ef7eb2e8f9f7	673	/** @brief Reset UART handle state
<>	144:ef7eb2e8f9f7	674	* @param __HANDLE__: UART handle.
<>	144:ef7eb2e8f9f7	675	* @retval None
<>	144:ef7eb2e8f9f7	676	*/
<>	144:ef7eb2e8f9f7	677	#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
<>	144:ef7eb2e8f9f7	678	(__HANDLE__)->gState = HAL_UART_STATE_RESET; \
<>	144:ef7eb2e8f9f7	679	(__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
<>	144:ef7eb2e8f9f7	680	} while(0)
<>	144:ef7eb2e8f9f7	681
<>	144:ef7eb2e8f9f7	682	/** @brief Flush the UART Data registers
<>	144:ef7eb2e8f9f7	683	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	684	*/
<>	144:ef7eb2e8f9f7	685	#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \
<>	144:ef7eb2e8f9f7	686	do{ \
<>	144:ef7eb2e8f9f7	687	SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
<>	144:ef7eb2e8f9f7	688	SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
<>	144:ef7eb2e8f9f7	689	} while(0)
<>	144:ef7eb2e8f9f7	690
<>	144:ef7eb2e8f9f7	691	/** @brief Clears the specified UART ISR flag, in setting the proper ICR register flag.
<>	144:ef7eb2e8f9f7	692	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	693	* @param __FLAG__: specifies the interrupt clear register flag that needs to be set
<>	144:ef7eb2e8f9f7	694	* to clear the corresponding interrupt
<>	144:ef7eb2e8f9f7	695	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	696	* @arg UART_CLEAR_PEF: Parity Error Clear Flag
<>	144:ef7eb2e8f9f7	697	* @arg UART_CLEAR_FEF: Framing Error Clear Flag
<>	144:ef7eb2e8f9f7	698	* @arg UART_CLEAR_NEF: Noise detected Clear Flag
<>	144:ef7eb2e8f9f7	699	* @arg UART_CLEAR_OREF: OverRun Error Clear Flag
<>	144:ef7eb2e8f9f7	700	* @arg UART_CLEAR_IDLEF: IDLE line detected Clear Flag
<>	144:ef7eb2e8f9f7	701	* @arg UART_CLEAR_TCF: Transmission Complete Clear Flag
<>	144:ef7eb2e8f9f7	702	* @arg UART_CLEAR_LBDF: LIN Break Detection Clear Flag
<>	144:ef7eb2e8f9f7	703	* @arg UART_CLEAR_CTSF: CTS Interrupt Clear Flag
<>	144:ef7eb2e8f9f7	704	* @arg UART_CLEAR_RTOF: Receiver Time Out Clear Flag
<>	144:ef7eb2e8f9f7	705	* @arg UART_CLEAR_EOBF: End Of Block Clear Flag
<>	144:ef7eb2e8f9f7	706	* @arg UART_CLEAR_CMF: Character Match Clear Flag
<>	144:ef7eb2e8f9f7	707	* @retval None
<>	144:ef7eb2e8f9f7	708	*/
<>	144:ef7eb2e8f9f7	709	#define __HAL_UART_CLEAR_IT(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__FLAG__))
<>	144:ef7eb2e8f9f7	710
<>	144:ef7eb2e8f9f7	711	/** @brief Clear the UART PE pending flag.
<>	144:ef7eb2e8f9f7	712	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	713	* @retval None
<>	144:ef7eb2e8f9f7	714	*/
<>	144:ef7eb2e8f9f7	715	#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_PEF)
<>	144:ef7eb2e8f9f7	716
<>	144:ef7eb2e8f9f7	717	/** @brief Clear the UART FE pending flag.
<>	144:ef7eb2e8f9f7	718	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	719	* @retval None
<>	144:ef7eb2e8f9f7	720	*/
<>	144:ef7eb2e8f9f7	721	#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_FEF)
<>	144:ef7eb2e8f9f7	722
<>	144:ef7eb2e8f9f7	723	/** @brief Clear the UART NE pending flag.
<>	144:ef7eb2e8f9f7	724	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	725	* @retval None
<>	144:ef7eb2e8f9f7	726	*/
<>	144:ef7eb2e8f9f7	727	#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_NEF)
<>	144:ef7eb2e8f9f7	728
<>	144:ef7eb2e8f9f7	729	/** @brief Clear the UART ORE pending flag.
<>	144:ef7eb2e8f9f7	730	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	731	* @retval None
<>	144:ef7eb2e8f9f7	732	*/
<>	144:ef7eb2e8f9f7	733	#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_OREF)
<>	144:ef7eb2e8f9f7	734
<>	144:ef7eb2e8f9f7	735	/** @brief Clear the UART IDLE pending flag.
<>	144:ef7eb2e8f9f7	736	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	737	* @retval None
<>	144:ef7eb2e8f9f7	738	*/
<>	144:ef7eb2e8f9f7	739	#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_IDLEF)
<>	144:ef7eb2e8f9f7	740
<>	144:ef7eb2e8f9f7	741	/** @brief Checks whether the specified UART flag is set or not.
<>	144:ef7eb2e8f9f7	742	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	743	* @param __FLAG__: specifies the flag to check.
<>	144:ef7eb2e8f9f7	744	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	745	* @arg UART_FLAG_REACK: Receive enable acknowledge flag
<>	144:ef7eb2e8f9f7	746	* @arg UART_FLAG_TEACK: Transmit enable acknowledge flag
<>	144:ef7eb2e8f9f7	747	* @arg UART_FLAG_WUF: Wake up from stop mode flag
<>	144:ef7eb2e8f9f7	748	* @arg UART_FLAG_RWU: Receiver wake up flag (is the UART in mute mode)
<>	144:ef7eb2e8f9f7	749	* @arg UART_FLAG_SBKF: Send Break flag
<>	144:ef7eb2e8f9f7	750	* @arg UART_FLAG_CMF: Character match flag
<>	144:ef7eb2e8f9f7	751	* @arg UART_FLAG_BUSY: Busy flag
<>	144:ef7eb2e8f9f7	752	* @arg UART_FLAG_ABRF: Auto Baud rate detection flag
<>	144:ef7eb2e8f9f7	753	* @arg UART_FLAG_ABRE: Auto Baud rate detection error flag
<>	144:ef7eb2e8f9f7	754	* @arg UART_FLAG_EOBF: End of block flag
<>	144:ef7eb2e8f9f7	755	* @arg UART_FLAG_RTOF: Receiver timeout flag
<>	144:ef7eb2e8f9f7	756	* @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
<>	144:ef7eb2e8f9f7	757	* @arg UART_FLAG_LBD: LIN Break detection flag
<>	144:ef7eb2e8f9f7	758	* @arg UART_FLAG_TXE: Transmit data register empty flag
<>	144:ef7eb2e8f9f7	759	* @arg UART_FLAG_TC: Transmission Complete flag
<>	144:ef7eb2e8f9f7	760	* @arg UART_FLAG_RXNE: Receive data register not empty flag
<>	144:ef7eb2e8f9f7	761	* @arg UART_FLAG_IDLE: Idle Line detection flag
<>	144:ef7eb2e8f9f7	762	* @arg UART_FLAG_ORE: OverRun Error flag
<>	144:ef7eb2e8f9f7	763	* @arg UART_FLAG_NE: Noise Error flag
<>	144:ef7eb2e8f9f7	764	* @arg UART_FLAG_FE: Framing Error flag
<>	144:ef7eb2e8f9f7	765	* @arg UART_FLAG_PE: Parity Error flag
<>	144:ef7eb2e8f9f7	766	* @retval The new state of __FLAG__ (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	767	*/
<>	144:ef7eb2e8f9f7	768	#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
<>	144:ef7eb2e8f9f7	769
<>	144:ef7eb2e8f9f7	770	/** @brief Enables the specified UART interrupt.
<>	144:ef7eb2e8f9f7	771	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	772	* @param __INTERRUPT__: specifies the UART interrupt source to enable.
<>	144:ef7eb2e8f9f7	773	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	774	* @arg UART_IT_WUF: Wakeup from stop mode interrupt
<>	144:ef7eb2e8f9f7	775	* @arg UART_IT_CM: Character match interrupt
<>	144:ef7eb2e8f9f7	776	* @arg UART_IT_CTS: CTS change interrupt
<>	144:ef7eb2e8f9f7	777	* @arg UART_IT_LBD: LIN Break detection interrupt
<>	144:ef7eb2e8f9f7	778	* @arg UART_IT_TXE: Transmit Data Register empty interrupt
<>	144:ef7eb2e8f9f7	779	* @arg UART_IT_TC: Transmission complete interrupt
<>	144:ef7eb2e8f9f7	780	* @arg UART_IT_RXNE: Receive Data register not empty interrupt
<>	144:ef7eb2e8f9f7	781	* @arg UART_IT_IDLE: Idle line detection interrupt
<>	144:ef7eb2e8f9f7	782	* @arg UART_IT_PE: Parity Error interrupt
<>	144:ef7eb2e8f9f7	783	* @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
<>	144:ef7eb2e8f9f7	784	* @retval None
<>	144:ef7eb2e8f9f7	785	*/
<>	144:ef7eb2e8f9f7	786	#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 \|= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
<>	144:ef7eb2e8f9f7	787	((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 \|= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
<>	144:ef7eb2e8f9f7	788	((__HANDLE__)->Instance->CR3 \|= (1U << ((__INTERRUPT__) & UART_IT_MASK))))
<>	144:ef7eb2e8f9f7	789
<>	144:ef7eb2e8f9f7	790
<>	144:ef7eb2e8f9f7	791	/** @brief Disables the specified UART interrupt.
<>	144:ef7eb2e8f9f7	792	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	793	* @param __INTERRUPT__: specifies the UART interrupt source to disable.
<>	144:ef7eb2e8f9f7	794	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	795	* @arg UART_IT_CM: Character match interrupt
<>	144:ef7eb2e8f9f7	796	* @arg UART_IT_CTS: CTS change interrupt
<>	144:ef7eb2e8f9f7	797	* @arg UART_IT_LBD: LIN Break detection interrupt
<>	144:ef7eb2e8f9f7	798	* @arg UART_IT_TXE: Transmit Data Register empty interrupt
<>	144:ef7eb2e8f9f7	799	* @arg UART_IT_TC: Transmission complete interrupt
<>	144:ef7eb2e8f9f7	800	* @arg UART_IT_RXNE: Receive Data register not empty interrupt
<>	144:ef7eb2e8f9f7	801	* @arg UART_IT_IDLE: Idle line detection interrupt
<>	144:ef7eb2e8f9f7	802	* @arg UART_IT_PE: Parity Error interrupt
<>	144:ef7eb2e8f9f7	803	* @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
<>	144:ef7eb2e8f9f7	804	* @retval None
<>	144:ef7eb2e8f9f7	805	*/
<>	144:ef7eb2e8f9f7	806	#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
<>	144:ef7eb2e8f9f7	807	((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
<>	144:ef7eb2e8f9f7	808	((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))
<>	144:ef7eb2e8f9f7	809
<>	144:ef7eb2e8f9f7	810	/** @brief Checks whether the specified UART interrupt has occurred or not.
<>	144:ef7eb2e8f9f7	811	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	812	* @param __IT__: specifies the UART interrupt to check.
<>	144:ef7eb2e8f9f7	813	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	814	* @arg UART_IT_CM: Character match interrupt
<>	144:ef7eb2e8f9f7	815	* @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
<>	144:ef7eb2e8f9f7	816	* @arg UART_IT_LBD: LIN Break detection interrupt
<>	144:ef7eb2e8f9f7	817	* @arg UART_IT_TXE: Transmit Data Register empty interrupt
<>	144:ef7eb2e8f9f7	818	* @arg UART_IT_TC: Transmission complete interrupt
<>	144:ef7eb2e8f9f7	819	* @arg UART_IT_RXNE: Receive Data register not empty interrupt
<>	144:ef7eb2e8f9f7	820	* @arg UART_IT_IDLE: Idle line detection interrupt
<>	144:ef7eb2e8f9f7	821	* @arg UART_IT_ORE: OverRun Error interrupt
<>	144:ef7eb2e8f9f7	822	* @arg UART_IT_NE: Noise Error interrupt
<>	144:ef7eb2e8f9f7	823	* @arg UART_IT_FE: Framing Error interrupt
<>	144:ef7eb2e8f9f7	824	* @arg UART_IT_PE: Parity Error interrupt
<>	144:ef7eb2e8f9f7	825	* @retval The new state of __IT__ (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	826	*/
<>	144:ef7eb2e8f9f7	827	#define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
<>	144:ef7eb2e8f9f7	828
<>	144:ef7eb2e8f9f7	829	/** @brief Checks whether the specified UART interrupt source is enabled.
<>	144:ef7eb2e8f9f7	830	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	831	* @param __IT__: specifies the UART interrupt source to check.
<>	144:ef7eb2e8f9f7	832	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	833	* @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
<>	144:ef7eb2e8f9f7	834	* @arg UART_IT_LBD: LIN Break detection interrupt
<>	144:ef7eb2e8f9f7	835	* @arg UART_IT_TXE: Transmit Data Register empty interrupt
<>	144:ef7eb2e8f9f7	836	* @arg UART_IT_TC: Transmission complete interrupt
<>	144:ef7eb2e8f9f7	837	* @arg UART_IT_RXNE: Receive Data register not empty interrupt
<>	144:ef7eb2e8f9f7	838	* @arg UART_IT_IDLE: Idle line detection interrupt
<>	144:ef7eb2e8f9f7	839	* @arg UART_IT_ORE: OverRun Error interrupt
<>	144:ef7eb2e8f9f7	840	* @arg UART_IT_NE: Noise Error interrupt
<>	144:ef7eb2e8f9f7	841	* @arg UART_IT_FE: Framing Error interrupt
<>	144:ef7eb2e8f9f7	842	* @arg UART_IT_PE: Parity Error interrupt
<>	144:ef7eb2e8f9f7	843	* @retval The new state of __IT__ (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	844	*/
<>	144:ef7eb2e8f9f7	845	#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \
<>	144:ef7eb2e8f9f7	846	(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & UART_IT_MASK)))
<>	144:ef7eb2e8f9f7	847
<>	144:ef7eb2e8f9f7	848	/** @brief Set a specific UART request flag.
<>	144:ef7eb2e8f9f7	849	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	850	* @param __REQ__: specifies the request flag to set
<>	144:ef7eb2e8f9f7	851	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	852	* @arg UART_AUTOBAUD_REQUEST: Auto-Baud Rate Request
<>	144:ef7eb2e8f9f7	853	* @arg UART_SENDBREAK_REQUEST: Send Break Request
<>	144:ef7eb2e8f9f7	854	* @arg UART_MUTE_MODE_REQUEST: Mute Mode Request
<>	144:ef7eb2e8f9f7	855	* @arg UART_RXDATA_FLUSH_REQUEST: Receive Data flush Request
<>	144:ef7eb2e8f9f7	856	* @arg UART_TXDATA_FLUSH_REQUEST: Transmit data flush Request
<>	144:ef7eb2e8f9f7	857	* @retval None
<>	144:ef7eb2e8f9f7	858	*/
<>	144:ef7eb2e8f9f7	859	#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR \|= (uint32_t)(__REQ__))
<>	144:ef7eb2e8f9f7	860
<>	144:ef7eb2e8f9f7	861	/** @brief Enables the UART one bit sample method
<>	144:ef7eb2e8f9f7	862	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	863	* @retval None
<>	144:ef7eb2e8f9f7	864	*/
<>	144:ef7eb2e8f9f7	865	#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\|= USART_CR3_ONEBIT)
<>	144:ef7eb2e8f9f7	866
<>	144:ef7eb2e8f9f7	867	/** @brief Disables the UART one bit sample method
<>	144:ef7eb2e8f9f7	868	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	869	* @retval None
<>	144:ef7eb2e8f9f7	870	*/
<>	144:ef7eb2e8f9f7	871	#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
<>	144:ef7eb2e8f9f7	872
<>	144:ef7eb2e8f9f7	873	/** @brief Enable UART
<>	144:ef7eb2e8f9f7	874	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	875	* @retval None
<>	144:ef7eb2e8f9f7	876	*/
<>	144:ef7eb2e8f9f7	877	#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 \|= USART_CR1_UE)
<>	144:ef7eb2e8f9f7	878
<>	144:ef7eb2e8f9f7	879	/** @brief Disable UART
<>	144:ef7eb2e8f9f7	880	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	881	* @retval None
<>	144:ef7eb2e8f9f7	882	*/
<>	144:ef7eb2e8f9f7	883	#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
<>	144:ef7eb2e8f9f7	884
<>	144:ef7eb2e8f9f7	885	/** @brief Enable CTS flow control
<>	144:ef7eb2e8f9f7	886	* This macro allows to enable CTS hardware flow control for a given UART instance,
<>	144:ef7eb2e8f9f7	887	* without need to call HAL_UART_Init() function.
<>	144:ef7eb2e8f9f7	888	* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
<>	144:ef7eb2e8f9f7	889	* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
<>	144:ef7eb2e8f9f7	890	* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
<>	144:ef7eb2e8f9f7	891	* - UART instance should have already been initialised (through call of HAL_UART_Init() )
<>	144:ef7eb2e8f9f7	892	* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
<>	144:ef7eb2e8f9f7	893	* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
<>	144:ef7eb2e8f9f7	894	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	895	* The Handle Instance can be USART1, USART2 or LPUART.
<>	144:ef7eb2e8f9f7	896	* @retval None
<>	144:ef7eb2e8f9f7	897	*/
<>	144:ef7eb2e8f9f7	898	#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	899	do{ \
<>	144:ef7eb2e8f9f7	900	SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
<>	144:ef7eb2e8f9f7	901	(__HANDLE__)->Init.HwFlowCtl \|= USART_CR3_CTSE; \
<>	144:ef7eb2e8f9f7	902	} while(0)
<>	144:ef7eb2e8f9f7	903
<>	144:ef7eb2e8f9f7	904	/** @brief Disable CTS flow control
<>	144:ef7eb2e8f9f7	905	* This macro allows to disable CTS hardware flow control for a given UART instance,
<>	144:ef7eb2e8f9f7	906	* without need to call HAL_UART_Init() function.
<>	144:ef7eb2e8f9f7	907	* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
<>	144:ef7eb2e8f9f7	908	* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
<>	144:ef7eb2e8f9f7	909	* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
<>	144:ef7eb2e8f9f7	910	* - UART instance should have already been initialised (through call of HAL_UART_Init() )
<>	144:ef7eb2e8f9f7	911	* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
<>	144:ef7eb2e8f9f7	912	* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
<>	144:ef7eb2e8f9f7	913	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	914	* The Handle Instance can be USART1, USART2 or LPUART.
<>	144:ef7eb2e8f9f7	915	* @retval None
<>	144:ef7eb2e8f9f7	916	*/
<>	144:ef7eb2e8f9f7	917	#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	918	do{ \
<>	144:ef7eb2e8f9f7	919	CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
<>	144:ef7eb2e8f9f7	920	(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
<>	144:ef7eb2e8f9f7	921	} while(0)
<>	144:ef7eb2e8f9f7	922
<>	144:ef7eb2e8f9f7	923	/** @brief Enable RTS flow control
<>	144:ef7eb2e8f9f7	924	* This macro allows to enable RTS hardware flow control for a given UART instance,
<>	144:ef7eb2e8f9f7	925	* without need to call HAL_UART_Init() function.
<>	144:ef7eb2e8f9f7	926	* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
<>	144:ef7eb2e8f9f7	927	* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
<>	144:ef7eb2e8f9f7	928	* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
<>	144:ef7eb2e8f9f7	929	* - UART instance should have already been initialised (through call of HAL_UART_Init() )
<>	144:ef7eb2e8f9f7	930	* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
<>	144:ef7eb2e8f9f7	931	* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
<>	144:ef7eb2e8f9f7	932	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	933	* The Handle Instance can be USART1, USART2 or LPUART.
<>	144:ef7eb2e8f9f7	934	* @retval None
<>	144:ef7eb2e8f9f7	935	*/
<>	144:ef7eb2e8f9f7	936	#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	937	do{ \
<>	144:ef7eb2e8f9f7	938	SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
<>	144:ef7eb2e8f9f7	939	(__HANDLE__)->Init.HwFlowCtl \|= USART_CR3_RTSE; \
<>	144:ef7eb2e8f9f7	940	} while(0)
<>	144:ef7eb2e8f9f7	941
<>	144:ef7eb2e8f9f7	942	/** @brief Disable RTS flow control
<>	144:ef7eb2e8f9f7	943	* This macro allows to disable RTS hardware flow control for a given UART instance,
<>	144:ef7eb2e8f9f7	944	* without need to call HAL_UART_Init() function.
<>	144:ef7eb2e8f9f7	945	* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
<>	144:ef7eb2e8f9f7	946	* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
<>	144:ef7eb2e8f9f7	947	* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
<>	144:ef7eb2e8f9f7	948	* - UART instance should have already been initialised (through call of HAL_UART_Init() )
<>	144:ef7eb2e8f9f7	949	* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
<>	144:ef7eb2e8f9f7	950	* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
<>	144:ef7eb2e8f9f7	951	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	952	* The Handle Instance can be USART1, USART2 or LPUART.
<>	144:ef7eb2e8f9f7	953	* @retval None
<>	144:ef7eb2e8f9f7	954	*/
<>	144:ef7eb2e8f9f7	955	#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	956	do{ \
<>	144:ef7eb2e8f9f7	957	CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
<>	144:ef7eb2e8f9f7	958	(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
<>	144:ef7eb2e8f9f7	959	} while(0)
<>	144:ef7eb2e8f9f7	960
<>	144:ef7eb2e8f9f7	961	/**
<>	144:ef7eb2e8f9f7	962	* @}
<>	144:ef7eb2e8f9f7	963	*/
<>	144:ef7eb2e8f9f7	964
<>	144:ef7eb2e8f9f7	965	/* Private macros --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	966	/** @defgroup UART_Private_Macros UART Private Macros
<>	144:ef7eb2e8f9f7	967	* @{
<>	144:ef7eb2e8f9f7	968	*/
<>	144:ef7eb2e8f9f7	969	/** @brief BRR division operation to set BRR register with LPUART
<>	144:ef7eb2e8f9f7	970	* @param _PCLK_: LPUART clock
<>	144:ef7eb2e8f9f7	971	* @param _BAUD_: Baud rate set by the user
<>	144:ef7eb2e8f9f7	972	* @retval Division result
<>	144:ef7eb2e8f9f7	973	*/
<>	144:ef7eb2e8f9f7	974	#define UART_DIV_LPUART(_PCLK_, _BAUD_) ((((_PCLK_)*256)+((_BAUD_)/2))/((_BAUD_)))
<>	144:ef7eb2e8f9f7	975
<>	144:ef7eb2e8f9f7	976	/** @brief BRR division operation to set BRR register in 8-bit oversampling mode
<>	144:ef7eb2e8f9f7	977	* @param _PCLK_: UART clock
<>	144:ef7eb2e8f9f7	978	* @param _BAUD_: Baud rate set by the user
<>	144:ef7eb2e8f9f7	979	* @retval Division result
<>	144:ef7eb2e8f9f7	980	*/
<>	144:ef7eb2e8f9f7	981	#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) ((((_PCLK_)*2)+((_BAUD_)/2))/((_BAUD_)))
<>	144:ef7eb2e8f9f7	982
<>	144:ef7eb2e8f9f7	983	/** @brief BRR division operation to set BRR register in 16-bit oversampling mode
<>	144:ef7eb2e8f9f7	984	* @param _PCLK_: UART clock
<>	144:ef7eb2e8f9f7	985	* @param _BAUD_: Baud rate set by the user
<>	144:ef7eb2e8f9f7	986	* @retval Division result
<>	144:ef7eb2e8f9f7	987	*/
<>	144:ef7eb2e8f9f7	988	#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) ((((_PCLK_))+((_BAUD_)/2))/((_BAUD_)))
<>	144:ef7eb2e8f9f7	989
<>	144:ef7eb2e8f9f7	990	/** @brief Check UART Baud rate
<>	144:ef7eb2e8f9f7	991	* @param BAUDRATE: Baudrate specified by the user
<>	144:ef7eb2e8f9f7	992	* The maximum Baud Rate is derived from the maximum clock on F7 (i.e. 216 MHz)
<>	144:ef7eb2e8f9f7	993	* divided by the smallest oversampling used on the USART (i.e. 8)
<>	144:ef7eb2e8f9f7	994	* @retval Test result (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	995	*/
<>	144:ef7eb2e8f9f7	996	#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 9000001)
<>	144:ef7eb2e8f9f7	997
<>	144:ef7eb2e8f9f7	998	/** @brief Check UART assertion time
<>	144:ef7eb2e8f9f7	999	* @param TIME: 5-bit value assertion time
<>	144:ef7eb2e8f9f7	1000	* @retval Test result (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	1001	*/
<>	144:ef7eb2e8f9f7	1002	#define IS_UART_ASSERTIONTIME(TIME) ((TIME) <= 0x1F)
<>	144:ef7eb2e8f9f7	1003
<>	144:ef7eb2e8f9f7	1004	/** @brief Check UART deassertion time
<>	144:ef7eb2e8f9f7	1005	* @param TIME: 5-bit value deassertion time
<>	144:ef7eb2e8f9f7	1006	* @retval Test result (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	1007	*/
<>	144:ef7eb2e8f9f7	1008	#define IS_UART_DEASSERTIONTIME(TIME) ((TIME) <= 0x1F)
<>	144:ef7eb2e8f9f7	1009
<>	144:ef7eb2e8f9f7	1010	#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) \|\| \
<>	144:ef7eb2e8f9f7	1011	((STOPBITS) == UART_STOPBITS_2))
<>	144:ef7eb2e8f9f7	1012
<>	144:ef7eb2e8f9f7	1013	#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) \|\| \
<>	144:ef7eb2e8f9f7	1014	((PARITY) == UART_PARITY_EVEN) \|\| \
<>	144:ef7eb2e8f9f7	1015	((PARITY) == UART_PARITY_ODD))
<>	144:ef7eb2e8f9f7	1016
<>	144:ef7eb2e8f9f7	1017	#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
<>	144:ef7eb2e8f9f7	1018	(((CONTROL) == UART_HWCONTROL_NONE) \|\| \
<>	144:ef7eb2e8f9f7	1019	((CONTROL) == UART_HWCONTROL_RTS) \|\| \
<>	144:ef7eb2e8f9f7	1020	((CONTROL) == UART_HWCONTROL_CTS) \|\| \
<>	144:ef7eb2e8f9f7	1021	((CONTROL) == UART_HWCONTROL_RTS_CTS))
<>	144:ef7eb2e8f9f7	1022
<>	144:ef7eb2e8f9f7	1023	#define IS_UART_MODE(MODE) ((((MODE) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((MODE) != (uint32_t)0x00))
<>	144:ef7eb2e8f9f7	1024
<>	144:ef7eb2e8f9f7	1025	#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1026	((STATE) == UART_STATE_ENABLE))
<>	144:ef7eb2e8f9f7	1027
<>	144:ef7eb2e8f9f7	1028	#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) \|\| \
<>	144:ef7eb2e8f9f7	1029	((SAMPLING) == UART_OVERSAMPLING_8))
<>	144:ef7eb2e8f9f7	1030
<>	144:ef7eb2e8f9f7	1031	#define IS_UART_ONE_BIT_SAMPLE(ONEBIT) (((ONEBIT) == UART_ONE_BIT_SAMPLE_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1032	((ONEBIT) == UART_ONE_BIT_SAMPLE_ENABLE))
<>	144:ef7eb2e8f9f7	1033
<>	144:ef7eb2e8f9f7	1034	#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(MODE) (((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) \|\| \
<>	144:ef7eb2e8f9f7	1035	((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) \|\| \
<>	144:ef7eb2e8f9f7	1036	((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) \|\| \
<>	144:ef7eb2e8f9f7	1037	((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
<>	144:ef7eb2e8f9f7	1038
<>	144:ef7eb2e8f9f7	1039	#define IS_UART_RECEIVER_TIMEOUT(TIMEOUT) (((TIMEOUT) == UART_RECEIVER_TIMEOUT_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1040	((TIMEOUT) == UART_RECEIVER_TIMEOUT_ENABLE))
<>	144:ef7eb2e8f9f7	1041
<>	144:ef7eb2e8f9f7	1042	#define IS_UART_LIN(LIN) (((LIN) == UART_LIN_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1043	((LIN) == UART_LIN_ENABLE))
<>	144:ef7eb2e8f9f7	1044
<>	144:ef7eb2e8f9f7	1045	#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) \|\| \
<>	144:ef7eb2e8f9f7	1046	((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))
<>	144:ef7eb2e8f9f7	1047
<>	144:ef7eb2e8f9f7	1048	#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) \|\| \
<>	144:ef7eb2e8f9f7	1049	((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
<>	144:ef7eb2e8f9f7	1050
<>	144:ef7eb2e8f9f7	1051	#define IS_UART_DMA_TX(DMATX) (((DMATX) == UART_DMA_TX_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1052	((DMATX) == UART_DMA_TX_ENABLE))
<>	144:ef7eb2e8f9f7	1053
<>	144:ef7eb2e8f9f7	1054	#define IS_UART_DMA_RX(DMARX) (((DMARX) == UART_DMA_RX_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1055	((DMARX) == UART_DMA_RX_ENABLE))
<>	144:ef7eb2e8f9f7	1056
<>	144:ef7eb2e8f9f7	1057	#define IS_UART_HALF_DUPLEX(HDSEL) (((HDSEL) == UART_HALF_DUPLEX_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1058	((HDSEL) == UART_HALF_DUPLEX_ENABLE))
<>	144:ef7eb2e8f9f7	1059
<>	144:ef7eb2e8f9f7	1060	#define IS_UART_REQUEST_PARAMETER(PARAM) (((PARAM) == UART_AUTOBAUD_REQUEST) \|\| \
<>	144:ef7eb2e8f9f7	1061	((PARAM) == UART_SENDBREAK_REQUEST) \|\| \
<>	144:ef7eb2e8f9f7	1062	((PARAM) == UART_MUTE_MODE_REQUEST) \|\| \
<>	144:ef7eb2e8f9f7	1063	((PARAM) == UART_RXDATA_FLUSH_REQUEST) \|\| \
<>	144:ef7eb2e8f9f7	1064	((PARAM) == UART_TXDATA_FLUSH_REQUEST))
<>	144:ef7eb2e8f9f7	1065
<>	144:ef7eb2e8f9f7	1066	#define IS_UART_ADVFEATURE_INIT(INIT) ((INIT) <= (UART_ADVFEATURE_NO_INIT \| \
<>	144:ef7eb2e8f9f7	1067	UART_ADVFEATURE_TXINVERT_INIT \| \
<>	144:ef7eb2e8f9f7	1068	UART_ADVFEATURE_RXINVERT_INIT \| \
<>	144:ef7eb2e8f9f7	1069	UART_ADVFEATURE_DATAINVERT_INIT \| \
<>	144:ef7eb2e8f9f7	1070	UART_ADVFEATURE_SWAP_INIT \| \
<>	144:ef7eb2e8f9f7	1071	UART_ADVFEATURE_RXOVERRUNDISABLE_INIT \| \
<>	144:ef7eb2e8f9f7	1072	UART_ADVFEATURE_DMADISABLEONERROR_INIT \| \
<>	144:ef7eb2e8f9f7	1073	UART_ADVFEATURE_AUTOBAUDRATE_INIT \| \
<>	144:ef7eb2e8f9f7	1074	UART_ADVFEATURE_MSBFIRST_INIT))
<>	144:ef7eb2e8f9f7	1075
<>	144:ef7eb2e8f9f7	1076	#define IS_UART_ADVFEATURE_TXINV(TXINV) (((TXINV) == UART_ADVFEATURE_TXINV_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1077	((TXINV) == UART_ADVFEATURE_TXINV_ENABLE))
<>	144:ef7eb2e8f9f7	1078
<>	144:ef7eb2e8f9f7	1079	#define IS_UART_ADVFEATURE_RXINV(RXINV) (((RXINV) == UART_ADVFEATURE_RXINV_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1080	((RXINV) == UART_ADVFEATURE_RXINV_ENABLE))
<>	144:ef7eb2e8f9f7	1081
<>	144:ef7eb2e8f9f7	1082	#define IS_UART_ADVFEATURE_DATAINV(DATAINV) (((DATAINV) == UART_ADVFEATURE_DATAINV_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1083	((DATAINV) == UART_ADVFEATURE_DATAINV_ENABLE))
<>	144:ef7eb2e8f9f7	1084
<>	144:ef7eb2e8f9f7	1085	#define IS_UART_ADVFEATURE_SWAP(SWAP) (((SWAP) == UART_ADVFEATURE_SWAP_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1086	((SWAP) == UART_ADVFEATURE_SWAP_ENABLE))
<>	144:ef7eb2e8f9f7	1087
<>	144:ef7eb2e8f9f7	1088	#define IS_UART_OVERRUN(OVERRUN) (((OVERRUN) == UART_ADVFEATURE_OVERRUN_ENABLE) \|\| \
<>	144:ef7eb2e8f9f7	1089	((OVERRUN) == UART_ADVFEATURE_OVERRUN_DISABLE))
<>	144:ef7eb2e8f9f7	1090
<>	144:ef7eb2e8f9f7	1091	#define IS_UART_ADVFEATURE_AUTOBAUDRATE(AUTOBAUDRATE) (((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1092	((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
<>	144:ef7eb2e8f9f7	1093
<>	144:ef7eb2e8f9f7	1094	#define IS_UART_ADVFEATURE_DMAONRXERROR(DMA) (((DMA) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) \|\| \
<>	144:ef7eb2e8f9f7	1095	((DMA) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
<>	144:ef7eb2e8f9f7	1096
<>	144:ef7eb2e8f9f7	1097	#define IS_UART_ADVFEATURE_MSBFIRST(MSBFIRST) (((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1098	((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_ENABLE))
<>	144:ef7eb2e8f9f7	1099
<>	144:ef7eb2e8f9f7	1100	#define IS_UART_MUTE_MODE(MUTE) (((MUTE) == UART_ADVFEATURE_MUTEMODE_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1101	((MUTE) == UART_ADVFEATURE_MUTEMODE_ENABLE))
<>	144:ef7eb2e8f9f7	1102
<>	144:ef7eb2e8f9f7	1103	#define IS_UART_DE_POLARITY(POLARITY) (((POLARITY) == UART_DE_POLARITY_HIGH) \|\| \
<>	144:ef7eb2e8f9f7	1104	((POLARITY) == UART_DE_POLARITY_LOW))
<>	144:ef7eb2e8f9f7	1105
<>	144:ef7eb2e8f9f7	1106	/**
<>	144:ef7eb2e8f9f7	1107	* @}
<>	144:ef7eb2e8f9f7	1108	*/
<>	144:ef7eb2e8f9f7	1109	/* Include UART HAL Extension module */
<>	144:ef7eb2e8f9f7	1110	#include "stm32f7xx_hal_uart_ex.h"
<>	144:ef7eb2e8f9f7	1111	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1112	/** @addtogroup UART_Exported_Functions UART Exported Functions
<>	144:ef7eb2e8f9f7	1113	* @{
<>	144:ef7eb2e8f9f7	1114	*/
<>	144:ef7eb2e8f9f7	1115
<>	144:ef7eb2e8f9f7	1116	/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	1117	* @{
<>	144:ef7eb2e8f9f7	1118	*/
<>	144:ef7eb2e8f9f7	1119
<>	144:ef7eb2e8f9f7	1120	/* Initialization and de-initialization functions ****************************/
<>	144:ef7eb2e8f9f7	1121	HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1122	HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1123	HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
<>	144:ef7eb2e8f9f7	1124	HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
<>	144:ef7eb2e8f9f7	1125	HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime);
<>	144:ef7eb2e8f9f7	1126	HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1127	void HAL_UART_MspInit(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1128	void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1129
<>	144:ef7eb2e8f9f7	1130	/**
<>	144:ef7eb2e8f9f7	1131	* @}
<>	144:ef7eb2e8f9f7	1132	*/
<>	144:ef7eb2e8f9f7	1133
<>	144:ef7eb2e8f9f7	1134	/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
<>	144:ef7eb2e8f9f7	1135	* @{
<>	144:ef7eb2e8f9f7	1136	*/
<>	144:ef7eb2e8f9f7	1137
<>	144:ef7eb2e8f9f7	1138	/* IO operation functions *****************************************************/
<>	144:ef7eb2e8f9f7	1139	HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size, uint32_t Timeout);
<>	144:ef7eb2e8f9f7	1140	HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size, uint32_t Timeout);
<>	144:ef7eb2e8f9f7	1141	HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size);
<>	144:ef7eb2e8f9f7	1142	HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size);
<>	144:ef7eb2e8f9f7	1143	HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size);
<>	144:ef7eb2e8f9f7	1144	HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size);
<>	144:ef7eb2e8f9f7	1145	HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1146	HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1147	HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1148
<>	144:ef7eb2e8f9f7	1149	void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1150	void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1151	void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1152	void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1153	void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1154	void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1155
<>	144:ef7eb2e8f9f7	1156	/**
<>	144:ef7eb2e8f9f7	1157	* @}
<>	144:ef7eb2e8f9f7	1158	*/
<>	144:ef7eb2e8f9f7	1159
<>	144:ef7eb2e8f9f7	1160	/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
<>	144:ef7eb2e8f9f7	1161	* @{
<>	144:ef7eb2e8f9f7	1162	*/
<>	144:ef7eb2e8f9f7	1163
<>	144:ef7eb2e8f9f7	1164	/* Peripheral Control functions ************************************************/
<>	144:ef7eb2e8f9f7	1165	HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1166	HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
<>	144:ef7eb2e8f9f7	1167	HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1168	HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1169	void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1170	HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1171	HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1172
<>	144:ef7eb2e8f9f7	1173	/**
<>	144:ef7eb2e8f9f7	1174	* @}
<>	144:ef7eb2e8f9f7	1175	*/
<>	144:ef7eb2e8f9f7	1176
<>	144:ef7eb2e8f9f7	1177	/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions
<>	144:ef7eb2e8f9f7	1178	* @{
<>	144:ef7eb2e8f9f7	1179	*/
<>	144:ef7eb2e8f9f7	1180
<>	144:ef7eb2e8f9f7	1181	/* Peripheral State and Errors functions **************************************************/
<>	144:ef7eb2e8f9f7	1182	HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1183	uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1184
<>	144:ef7eb2e8f9f7	1185	/**
<>	144:ef7eb2e8f9f7	1186	* @}
<>	144:ef7eb2e8f9f7	1187	*/
<>	144:ef7eb2e8f9f7	1188
<>	144:ef7eb2e8f9f7	1189	/**
<>	144:ef7eb2e8f9f7	1190	* @}
<>	144:ef7eb2e8f9f7	1191	*/
<>	144:ef7eb2e8f9f7	1192
<>	144:ef7eb2e8f9f7	1193	/* Private functions -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1194	/** @addtogroup UART_Private_Functions UART Private Functions
<>	144:ef7eb2e8f9f7	1195	* @{
<>	144:ef7eb2e8f9f7	1196	*/
<>	144:ef7eb2e8f9f7	1197
<>	144:ef7eb2e8f9f7	1198	HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1199	HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1200	HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
<>	144:ef7eb2e8f9f7	1201	void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1202
<>	144:ef7eb2e8f9f7	1203	/**
<>	144:ef7eb2e8f9f7	1204	* @}
<>	144:ef7eb2e8f9f7	1205	*/
<>	144:ef7eb2e8f9f7	1206
<>	144:ef7eb2e8f9f7	1207	/**
<>	144:ef7eb2e8f9f7	1208	* @}
<>	144:ef7eb2e8f9f7	1209	*/
<>	144:ef7eb2e8f9f7	1210
<>	144:ef7eb2e8f9f7	1211	/**
<>	144:ef7eb2e8f9f7	1212	* @}
<>	144:ef7eb2e8f9f7	1213	*/
<>	144:ef7eb2e8f9f7	1214
<>	144:ef7eb2e8f9f7	1215	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	1216	}
<>	144:ef7eb2e8f9f7	1217	#endif
<>	144:ef7eb2e8f9f7	1218
<>	144:ef7eb2e8f9f7	1219	#endif /* __STM32F7xx_HAL_UART_H */
<>	144:ef7eb2e8f9f7	1220
<>	144:ef7eb2e8f9f7	1221	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Repository toolbox

Repository details

Type:	Library
Created:	02 May 2018
Imports:	22
Forks:	0
Commits:	180
Dependents:	11
Dependencies:	0
Followers:	9

This repository is Public (Unlisted).

Important changes to repositories hosted on mbed.com

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_uart.h@179:97f825502e2a, 2018-05-02 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Important changes to repositories hosted on mbed.com

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_uart.h@179:97f825502e2a, 2018-05-02 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Access Warning