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targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_uart.h@179:97f825502e2a, 2018-05-02 (annotated)

Committer:: benkatz
Date:: Wed May 02 18:08:16 2018 +0000
Revision:: 179:97f825502e2a
Parent:: 157:ff67d9f36b67

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f3xx_hal_uart.h
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	157:ff67d9f36b67	5	* @version V1.4.0
<>	157:ff67d9f36b67	6	* @date 16-December-2016
<>	144:ef7eb2e8f9f7	7	* @brief Header file of UART HAL module.
<>	144:ef7eb2e8f9f7	8	******************************************************************************
<>	144:ef7eb2e8f9f7	9	* @attention
<>	144:ef7eb2e8f9f7	10	*
<>	144:ef7eb2e8f9f7	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	12	*
<>	144:ef7eb2e8f9f7	13	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	14	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	16	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	18	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	19	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	21	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	22	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	23	*
<>	144:ef7eb2e8f9f7	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	34	*
<>	157:ff67d9f36b67	35	******************************************************************************
<>	144:ef7eb2e8f9f7	36	*/
<>	144:ef7eb2e8f9f7	37
<>	144:ef7eb2e8f9f7	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	144:ef7eb2e8f9f7	39	#ifndef __STM32F3xx_HAL_UART_H
<>	144:ef7eb2e8f9f7	40	#define __STM32F3xx_HAL_UART_H
<>	144:ef7eb2e8f9f7	41
<>	144:ef7eb2e8f9f7	42	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	43	extern "C" {
<>	144:ef7eb2e8f9f7	44	#endif
<>	144:ef7eb2e8f9f7	45
<>	144:ef7eb2e8f9f7	46	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	47	#include "stm32f3xx_hal_def.h"
<>	144:ef7eb2e8f9f7	48
<>	144:ef7eb2e8f9f7	49	/** @addtogroup STM32F3xx_HAL_Driver
<>	144:ef7eb2e8f9f7	50	* @{
<>	144:ef7eb2e8f9f7	51	*/
<>	144:ef7eb2e8f9f7	52
<>	144:ef7eb2e8f9f7	53	/** @addtogroup UART
<>	144:ef7eb2e8f9f7	54	* @{
<>	144:ef7eb2e8f9f7	55	*/
<>	144:ef7eb2e8f9f7	56
<>	144:ef7eb2e8f9f7	57	/* Exported types ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	58	/** @defgroup UART_Exported_Types UART Exported Types
<>	144:ef7eb2e8f9f7	59	* @{
<>	144:ef7eb2e8f9f7	60	*/
<>	144:ef7eb2e8f9f7	61
<>	144:ef7eb2e8f9f7	62	/**
<>	144:ef7eb2e8f9f7	63	* @brief UART Init Structure definition
<>	144:ef7eb2e8f9f7	64	*/
<>	144:ef7eb2e8f9f7	65	typedef struct
<>	144:ef7eb2e8f9f7	66	{
<>	144:ef7eb2e8f9f7	67	uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
<>	144:ef7eb2e8f9f7	68	The baud rate register is computed using the following formula:
<>	144:ef7eb2e8f9f7	69	- If oversampling is 16 or in LIN mode,
<>	144:ef7eb2e8f9f7	70	Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate)))
<>	157:ff67d9f36b67	71	- If oversampling is 8U,
<>	157:ff67d9f36b67	72	Baud Rate Register[15:4] = ((2U * PCLKx) / ((huart->Init.BaudRate)))[15:4]
<>	144:ef7eb2e8f9f7	73	Baud Rate Register[3] = 0
<>	157:ff67d9f36b67	74	Baud Rate Register[2:0] = (((2U * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1 */
<>	144:ef7eb2e8f9f7	75
<>	144:ef7eb2e8f9f7	76	uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
<>	157:ff67d9f36b67	77	This parameter can be a value of @ref UARTEx_Word_Length. */
<>	144:ef7eb2e8f9f7	78
<>	144:ef7eb2e8f9f7	79	uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
<>	157:ff67d9f36b67	80	This parameter can be a value of @ref UART_Stop_Bits. */
<>	144:ef7eb2e8f9f7	81
<>	144:ef7eb2e8f9f7	82	uint32_t Parity; /*!< Specifies the parity mode.
<>	144:ef7eb2e8f9f7	83	This parameter can be a value of @ref UART_Parity
<>	144:ef7eb2e8f9f7	84	@note When parity is enabled, the computed parity is inserted
<>	144:ef7eb2e8f9f7	85	at the MSB position of the transmitted data (9th bit when
<>	144:ef7eb2e8f9f7	86	the word length is set to 9 data bits; 8th bit when the
<>	144:ef7eb2e8f9f7	87	word length is set to 8 data bits). */
<>	144:ef7eb2e8f9f7	88
<>	144:ef7eb2e8f9f7	89	uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
<>	157:ff67d9f36b67	90	This parameter can be a value of @ref UART_Mode. */
<>	144:ef7eb2e8f9f7	91
<>	144:ef7eb2e8f9f7	92	uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled
<>	144:ef7eb2e8f9f7	93	or disabled.
<>	157:ff67d9f36b67	94	This parameter can be a value of @ref UART_Hardware_Flow_Control. */
<>	144:ef7eb2e8f9f7	95
<>	157:ff67d9f36b67	96	uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8U).
<>	157:ff67d9f36b67	97	This parameter can be a value of @ref UART_Over_Sampling. */
<>	144:ef7eb2e8f9f7	98
<>	144:ef7eb2e8f9f7	99	uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
<>	144:ef7eb2e8f9f7	100	Selecting the single sample method increases the receiver tolerance to clock
<>	144:ef7eb2e8f9f7	101	deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
<>	144:ef7eb2e8f9f7	102	}UART_InitTypeDef;
<>	144:ef7eb2e8f9f7	103
<>	144:ef7eb2e8f9f7	104	/**
<>	144:ef7eb2e8f9f7	105	* @brief UART Advanced Features initalization structure definition
<>	144:ef7eb2e8f9f7	106	*/
<>	144:ef7eb2e8f9f7	107	typedef struct
<>	144:ef7eb2e8f9f7	108	{
<>	144:ef7eb2e8f9f7	109	uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several
<>	144:ef7eb2e8f9f7	110	Advanced Features may be initialized at the same time .
<>	157:ff67d9f36b67	111	This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */
<>	144:ef7eb2e8f9f7	112
<>	144:ef7eb2e8f9f7	113	uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
<>	157:ff67d9f36b67	114	This parameter can be a value of @ref UART_Tx_Inv. */
<>	144:ef7eb2e8f9f7	115
<>	144:ef7eb2e8f9f7	116	uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted.
<>	157:ff67d9f36b67	117	This parameter can be a value of @ref UART_Rx_Inv. */
<>	144:ef7eb2e8f9f7	118
<>	144:ef7eb2e8f9f7	119	uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic
<>	144:ef7eb2e8f9f7	120	vs negative/inverted logic).
<>	157:ff67d9f36b67	121	This parameter can be a value of @ref UART_Data_Inv. */
<>	144:ef7eb2e8f9f7	122
<>	144:ef7eb2e8f9f7	123	uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.
<>	157:ff67d9f36b67	124	This parameter can be a value of @ref UART_Rx_Tx_Swap. */
<>	144:ef7eb2e8f9f7	125
<>	144:ef7eb2e8f9f7	126	uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.
<>	157:ff67d9f36b67	127	This parameter can be a value of @ref UART_Overrun_Disable. */
<>	144:ef7eb2e8f9f7	128
<>	144:ef7eb2e8f9f7	129	uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.
<>	157:ff67d9f36b67	130	This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */
<>	144:ef7eb2e8f9f7	131
<>	144:ef7eb2e8f9f7	132	uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled.
<>	144:ef7eb2e8f9f7	133	This parameter can be a value of @ref UART_AutoBaudRate_Enable */
<>	144:ef7eb2e8f9f7	134
<>	144:ef7eb2e8f9f7	135	uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate
<>	144:ef7eb2e8f9f7	136	detection is carried out.
<>	157:ff67d9f36b67	137	This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */
<>	144:ef7eb2e8f9f7	138
<>	144:ef7eb2e8f9f7	139	uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
<>	157:ff67d9f36b67	140	This parameter can be a value of @ref UART_MSB_First. */
<>	144:ef7eb2e8f9f7	141	} UART_AdvFeatureInitTypeDef;
<>	144:ef7eb2e8f9f7	142
<>	144:ef7eb2e8f9f7	143	/**
<>	144:ef7eb2e8f9f7	144	* @brief UART wake up from stop mode parameters
<>	144:ef7eb2e8f9f7	145	*/
<>	144:ef7eb2e8f9f7	146	typedef struct
<>	144:ef7eb2e8f9f7	147	{
<>	144:ef7eb2e8f9f7	148	uint32_t WakeUpEvent; /*!< Specifies which event will activat the Wakeup from Stop mode flag (WUF).
<>	144:ef7eb2e8f9f7	149	This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
<>	144:ef7eb2e8f9f7	150	If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
<>	144:ef7eb2e8f9f7	151	be filled up. */
<>	144:ef7eb2e8f9f7	152
<>	144:ef7eb2e8f9f7	153	uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long.
<>	157:ff67d9f36b67	154	This parameter can be a value of @ref UART_WakeUp_Address_Length. */
<>	144:ef7eb2e8f9f7	155
<>	157:ff67d9f36b67	156	uint8_t Address; /!< UART/USART node address (7-bit long max). /
<>	144:ef7eb2e8f9f7	157	} UART_WakeUpTypeDef;
<>	144:ef7eb2e8f9f7	158
<>	144:ef7eb2e8f9f7	159	/**
<>	144:ef7eb2e8f9f7	160	* @brief HAL UART State structures definition
<>	144:ef7eb2e8f9f7	161	* @note HAL UART State value is a combination of 2 different substates: gState and RxState.
<>	144:ef7eb2e8f9f7	162	* - gState contains UART state information related to global Handle management
<>	144:ef7eb2e8f9f7	163	* and also information related to Tx operations.
<>	144:ef7eb2e8f9f7	164	* gState value coding follow below described bitmap :
<>	144:ef7eb2e8f9f7	165	* b7-b6 Error information
<>	144:ef7eb2e8f9f7	166	* 00 : No Error
<>	144:ef7eb2e8f9f7	167	* 01 : (Not Used)
<>	144:ef7eb2e8f9f7	168	* 10 : Timeout
<>	144:ef7eb2e8f9f7	169	* 11 : Error
<>	144:ef7eb2e8f9f7	170	* b5 IP initilisation status
<>	144:ef7eb2e8f9f7	171	* 0 : Reset (IP not initialized)
<>	144:ef7eb2e8f9f7	172	* 1 : Init done (IP not initialized. HAL UART Init function already called)
<>	144:ef7eb2e8f9f7	173	* b4-b3 (not used)
<>	144:ef7eb2e8f9f7	174	* xx : Should be set to 00
<>	144:ef7eb2e8f9f7	175	* b2 Intrinsic process state
<>	144:ef7eb2e8f9f7	176	* 0 : Ready
<>	144:ef7eb2e8f9f7	177	* 1 : Busy (IP busy with some configuration or internal operations)
<>	144:ef7eb2e8f9f7	178	* b1 (not used)
<>	144:ef7eb2e8f9f7	179	* x : Should be set to 0
<>	144:ef7eb2e8f9f7	180	* b0 Tx state
<>	144:ef7eb2e8f9f7	181	* 0 : Ready (no Tx operation ongoing)
<>	144:ef7eb2e8f9f7	182	* 1 : Busy (Tx operation ongoing)
<>	144:ef7eb2e8f9f7	183	* - RxState contains information related to Rx operations.
<>	144:ef7eb2e8f9f7	184	* RxState value coding follow below described bitmap :
<>	144:ef7eb2e8f9f7	185	* b7-b6 (not used)
<>	144:ef7eb2e8f9f7	186	* xx : Should be set to 00
<>	144:ef7eb2e8f9f7	187	* b5 IP initilisation status
<>	144:ef7eb2e8f9f7	188	* 0 : Reset (IP not initialized)
<>	144:ef7eb2e8f9f7	189	* 1 : Init done (IP not initialized)
<>	144:ef7eb2e8f9f7	190	* b4-b2 (not used)
<>	144:ef7eb2e8f9f7	191	* xxx : Should be set to 000
<>	144:ef7eb2e8f9f7	192	* b1 Rx state
<>	144:ef7eb2e8f9f7	193	* 0 : Ready (no Rx operation ongoing)
<>	144:ef7eb2e8f9f7	194	* 1 : Busy (Rx operation ongoing)
<>	144:ef7eb2e8f9f7	195	* b0 (not used)
<>	144:ef7eb2e8f9f7	196	* x : Should be set to 0.
<>	144:ef7eb2e8f9f7	197	*/
<>	144:ef7eb2e8f9f7	198	typedef enum
<>	144:ef7eb2e8f9f7	199	{
<>	144:ef7eb2e8f9f7	200	HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized
<>	144:ef7eb2e8f9f7	201	Value is allowed for gState and RxState */
<>	144:ef7eb2e8f9f7	202	HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
<>	144:ef7eb2e8f9f7	203	Value is allowed for gState and RxState */
<>	144:ef7eb2e8f9f7	204	HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
<>	144:ef7eb2e8f9f7	205	Value is allowed for gState only */
<>	144:ef7eb2e8f9f7	206	HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
<>	144:ef7eb2e8f9f7	207	Value is allowed for gState only */
<>	144:ef7eb2e8f9f7	208	HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
<>	144:ef7eb2e8f9f7	209	Value is allowed for RxState only */
<>	144:ef7eb2e8f9f7	210	HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
<>	144:ef7eb2e8f9f7	211	Not to be used for neither gState nor RxState.
<>	144:ef7eb2e8f9f7	212	Value is result of combination (Or) between gState and RxState values */
<>	144:ef7eb2e8f9f7	213	HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
<>	144:ef7eb2e8f9f7	214	Value is allowed for gState only */
<>	144:ef7eb2e8f9f7	215	HAL_UART_STATE_ERROR = 0xE0U /*!< Error
<>	144:ef7eb2e8f9f7	216	Value is allowed for gState only */
<>	144:ef7eb2e8f9f7	217	}HAL_UART_StateTypeDef;
<>	144:ef7eb2e8f9f7	218
<>	144:ef7eb2e8f9f7	219	/**
<>	144:ef7eb2e8f9f7	220	* @brief UART clock sources definition
<>	144:ef7eb2e8f9f7	221	*/
<>	144:ef7eb2e8f9f7	222	typedef enum
<>	144:ef7eb2e8f9f7	223	{
<>	157:ff67d9f36b67	224	UART_CLOCKSOURCE_PCLK1 = 0x00U, /!< PCLK1 clock source /
<>	157:ff67d9f36b67	225	UART_CLOCKSOURCE_PCLK2 = 0x01U, /!< PCLK2 clock source /
<>	157:ff67d9f36b67	226	UART_CLOCKSOURCE_HSI = 0x02U, /!< HSI clock source /
<>	157:ff67d9f36b67	227	UART_CLOCKSOURCE_SYSCLK = 0x04U, /!< SYSCLK clock source /
<>	157:ff67d9f36b67	228	UART_CLOCKSOURCE_LSE = 0x08U, /!< LSE clock source /
<>	157:ff67d9f36b67	229	UART_CLOCKSOURCE_UNDEFINED = 0x10U /!< Undefined clock source /
<>	144:ef7eb2e8f9f7	230	}UART_ClockSourceTypeDef;
<>	144:ef7eb2e8f9f7	231
<>	144:ef7eb2e8f9f7	232	/**
<>	144:ef7eb2e8f9f7	233	* @brief UART handle Structure definition
<>	144:ef7eb2e8f9f7	234	*/
<>	144:ef7eb2e8f9f7	235	typedef struct
<>	144:ef7eb2e8f9f7	236	{
<>	144:ef7eb2e8f9f7	237	USART_TypeDef Instance; /!< UART registers base address */
<>	144:ef7eb2e8f9f7	238
<>	144:ef7eb2e8f9f7	239	UART_InitTypeDef Init; /!< UART communication parameters /
<>	144:ef7eb2e8f9f7	240
<>	144:ef7eb2e8f9f7	241	UART_AdvFeatureInitTypeDef AdvancedInit; /!< UART Advanced Features initialization parameters /
<>	144:ef7eb2e8f9f7	242
<>	144:ef7eb2e8f9f7	243	uint8_t pTxBuffPtr; /!< Pointer to UART Tx transfer Buffer */
<>	144:ef7eb2e8f9f7	244
<>	144:ef7eb2e8f9f7	245	uint16_t TxXferSize; /!< UART Tx Transfer size /
<>	144:ef7eb2e8f9f7	246
<>	157:ff67d9f36b67	247	__IO uint16_t TxXferCount; /!< UART Tx Transfer Counter /
<>	144:ef7eb2e8f9f7	248
<>	144:ef7eb2e8f9f7	249	uint8_t pRxBuffPtr; /!< Pointer to UART Rx transfer Buffer */
<>	144:ef7eb2e8f9f7	250
<>	144:ef7eb2e8f9f7	251	uint16_t RxXferSize; /!< UART Rx Transfer size /
<>	144:ef7eb2e8f9f7	252
<>	157:ff67d9f36b67	253	__IO uint16_t RxXferCount; /!< UART Rx Transfer Counter /
<>	144:ef7eb2e8f9f7	254
<>	144:ef7eb2e8f9f7	255	uint16_t Mask; /!< UART Rx RDR register mask /
<>	144:ef7eb2e8f9f7	256
<>	144:ef7eb2e8f9f7	257	DMA_HandleTypeDef hdmatx; /!< UART Tx DMA Handle parameters */
<>	144:ef7eb2e8f9f7	258
<>	144:ef7eb2e8f9f7	259	DMA_HandleTypeDef hdmarx; /!< UART Rx DMA Handle parameters */
<>	144:ef7eb2e8f9f7	260
<>	157:ff67d9f36b67	261	HAL_LockTypeDef Lock; /!< Locking object /
<>	144:ef7eb2e8f9f7	262
<>	144:ef7eb2e8f9f7	263	__IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management
<>	144:ef7eb2e8f9f7	264	and also related to Tx operations.
<>	144:ef7eb2e8f9f7	265	This parameter can be a value of @ref HAL_UART_StateTypeDef */
<>	144:ef7eb2e8f9f7	266
<>	144:ef7eb2e8f9f7	267	__IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations.
<>	144:ef7eb2e8f9f7	268	This parameter can be a value of @ref HAL_UART_StateTypeDef */
<>	144:ef7eb2e8f9f7	269
<>	144:ef7eb2e8f9f7	270	__IO uint32_t ErrorCode; /!< UART Error code /
<>	144:ef7eb2e8f9f7	271
<>	144:ef7eb2e8f9f7	272	}UART_HandleTypeDef;
<>	144:ef7eb2e8f9f7	273
<>	144:ef7eb2e8f9f7	274	/**
<>	144:ef7eb2e8f9f7	275	* @}
<>	144:ef7eb2e8f9f7	276	*/
<>	144:ef7eb2e8f9f7	277
<>	144:ef7eb2e8f9f7	278	/* Exported constants --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	279	/** @defgroup UART_Exported_Constants UART Exported Constants
<>	144:ef7eb2e8f9f7	280	* @{
<>	144:ef7eb2e8f9f7	281	*/
<>	144:ef7eb2e8f9f7	282
<>	144:ef7eb2e8f9f7	283	/** @defgroup UART_Error UART Error
<>	144:ef7eb2e8f9f7	284	* @{
<>	144:ef7eb2e8f9f7	285	*/
<>	157:ff67d9f36b67	286	#define HAL_UART_ERROR_NONE (0x00000000U) /!< No error /
<>	157:ff67d9f36b67	287	#define HAL_UART_ERROR_PE (0x00000001U) /!< Parity error /
<>	157:ff67d9f36b67	288	#define HAL_UART_ERROR_NE (0x00000002U) /!< Noise error /
<>	157:ff67d9f36b67	289	#define HAL_UART_ERROR_FE (0x00000004U) /!< frame error /
<>	157:ff67d9f36b67	290	#define HAL_UART_ERROR_ORE (0x00000008U) /!< Overrun error /
<>	157:ff67d9f36b67	291	#define HAL_UART_ERROR_DMA (0x00000010U) /!< DMA transfer error /
<>	157:ff67d9f36b67	292	#define HAL_UART_ERROR_BUSY (0x00000020U) /!< Busy Error /
<>	144:ef7eb2e8f9f7	293	/**
<>	144:ef7eb2e8f9f7	294	* @}
<>	144:ef7eb2e8f9f7	295	*/
<>	144:ef7eb2e8f9f7	296
<>	144:ef7eb2e8f9f7	297	/** @defgroup UART_Stop_Bits UART Number of Stop Bits
<>	144:ef7eb2e8f9f7	298	* @{
<>	144:ef7eb2e8f9f7	299	*/
<>	144:ef7eb2e8f9f7	300	#define UART_STOPBITS_0_5 USART_CR2_STOP_0 /!< UART frame with 0.5 stop bit /
<>	157:ff67d9f36b67	301	#define UART_STOPBITS_1 (0x00000000U) /!< UART frame with 1 stop bit /
<>	144:ef7eb2e8f9f7	302	#define UART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 \| USART_CR2_STOP_1)) /!< UART frame with 1.5 stop bits /
<>	144:ef7eb2e8f9f7	303	#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) /!< UART frame with 2 stop bits /
<>	144:ef7eb2e8f9f7	304	/**
<>	144:ef7eb2e8f9f7	305	* @}
<>	144:ef7eb2e8f9f7	306	*/
<>	144:ef7eb2e8f9f7	307
<>	144:ef7eb2e8f9f7	308	/** @defgroup UART_Parity UART Parity
<>	144:ef7eb2e8f9f7	309	* @{
<>	144:ef7eb2e8f9f7	310	*/
<>	157:ff67d9f36b67	311	#define UART_PARITY_NONE (0x00000000U) /!< No parity /
<>	144:ef7eb2e8f9f7	312	#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /!< Even parity /
<>	144:ef7eb2e8f9f7	313	#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE \| USART_CR1_PS)) /!< Odd parity /
<>	144:ef7eb2e8f9f7	314	/**
<>	144:ef7eb2e8f9f7	315	* @}
<>	144:ef7eb2e8f9f7	316	*/
<>	144:ef7eb2e8f9f7	317
<>	144:ef7eb2e8f9f7	318	/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
<>	144:ef7eb2e8f9f7	319	* @{
<>	144:ef7eb2e8f9f7	320	*/
<>	157:ff67d9f36b67	321	#define UART_HWCONTROL_NONE (0x00000000U) /!< No hardware control /
<>	144:ef7eb2e8f9f7	322	#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) /!< Request To Send /
<>	144:ef7eb2e8f9f7	323	#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) /!< Clear To Send /
<>	144:ef7eb2e8f9f7	324	#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE \| USART_CR3_CTSE)) /!< Request and Clear To Send /
<>	144:ef7eb2e8f9f7	325	/**
<>	144:ef7eb2e8f9f7	326	* @}
<>	144:ef7eb2e8f9f7	327	*/
<>	144:ef7eb2e8f9f7	328
<>	144:ef7eb2e8f9f7	329	/** @defgroup UART_Mode UART Transfer Mode
<>	144:ef7eb2e8f9f7	330	* @{
<>	144:ef7eb2e8f9f7	331	*/
<>	144:ef7eb2e8f9f7	332	#define UART_MODE_RX ((uint32_t)USART_CR1_RE) /!< RX mode /
<>	144:ef7eb2e8f9f7	333	#define UART_MODE_TX ((uint32_t)USART_CR1_TE) /!< TX mode /
<>	144:ef7eb2e8f9f7	334	#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE \|USART_CR1_RE)) /!< RX and TX mode /
<>	144:ef7eb2e8f9f7	335	/**
<>	144:ef7eb2e8f9f7	336	* @}
<>	144:ef7eb2e8f9f7	337	*/
<>	144:ef7eb2e8f9f7	338
<>	144:ef7eb2e8f9f7	339	/** @defgroup UART_State UART State
<>	144:ef7eb2e8f9f7	340	* @{
<>	144:ef7eb2e8f9f7	341	*/
<>	157:ff67d9f36b67	342	#define UART_STATE_DISABLE (0x00000000U) /!< UART disabled /
<>	144:ef7eb2e8f9f7	343	#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) /!< UART enabled /
<>	144:ef7eb2e8f9f7	344	/**
<>	144:ef7eb2e8f9f7	345	* @}
<>	144:ef7eb2e8f9f7	346	*/
<>	144:ef7eb2e8f9f7	347
<>	144:ef7eb2e8f9f7	348	/** @defgroup UART_Over_Sampling UART Over Sampling
<>	144:ef7eb2e8f9f7	349	* @{
<>	144:ef7eb2e8f9f7	350	*/
<>	157:ff67d9f36b67	351	#define UART_OVERSAMPLING_16 (0x00000000U) /!< Oversampling by 16U /
<>	144:ef7eb2e8f9f7	352	#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) /!< Oversampling by 8 /
<>	144:ef7eb2e8f9f7	353	/**
<>	144:ef7eb2e8f9f7	354	* @}
<>	144:ef7eb2e8f9f7	355	*/
<>	144:ef7eb2e8f9f7	356
<>	144:ef7eb2e8f9f7	357	/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
<>	144:ef7eb2e8f9f7	358	* @{
<>	144:ef7eb2e8f9f7	359	*/
<>	157:ff67d9f36b67	360	#define UART_ONE_BIT_SAMPLE_DISABLE (0x00000000U) /!< One-bit sampling disable /
<>	144:ef7eb2e8f9f7	361	#define UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /!< One-bit sampling enable /
<>	144:ef7eb2e8f9f7	362	/**
<>	144:ef7eb2e8f9f7	363	* @}
<>	144:ef7eb2e8f9f7	364	*/
<>	144:ef7eb2e8f9f7	365
<>	144:ef7eb2e8f9f7	366	/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode
<>	144:ef7eb2e8f9f7	367	* @{
<>	144:ef7eb2e8f9f7	368	*/
<>	157:ff67d9f36b67	369	#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT (0x00000000U) /!< Auto Baud rate detection on start bit /
<>	144:ef7eb2e8f9f7	370	#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0) /!< Auto Baud rate detection on falling edge /
<>	144:ef7eb2e8f9f7	371	#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1) /!< Auto Baud rate detection on 0x7F frame detection /
<>	144:ef7eb2e8f9f7	372	#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE) /!< Auto Baud rate detection on 0x55 frame detection /
<>	144:ef7eb2e8f9f7	373	/**
<>	144:ef7eb2e8f9f7	374	* @}
<>	144:ef7eb2e8f9f7	375	*/
<>	144:ef7eb2e8f9f7	376
<>	144:ef7eb2e8f9f7	377	/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut
<>	144:ef7eb2e8f9f7	378	* @{
<>	144:ef7eb2e8f9f7	379	*/
<>	157:ff67d9f36b67	380	#define UART_RECEIVER_TIMEOUT_DISABLE (0x00000000U) /!< UART receiver timeout disable /
<>	144:ef7eb2e8f9f7	381	#define UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) /!< UART receiver timeout enable /
<>	144:ef7eb2e8f9f7	382	/**
<>	144:ef7eb2e8f9f7	383	* @}
<>	144:ef7eb2e8f9f7	384	*/
<>	144:ef7eb2e8f9f7	385
<>	144:ef7eb2e8f9f7	386	/** @defgroup UART_LIN UART Local Interconnection Network mode
<>	144:ef7eb2e8f9f7	387	* @{
<>	144:ef7eb2e8f9f7	388	*/
<>	157:ff67d9f36b67	389	#define UART_LIN_DISABLE (0x00000000U) /!< Local Interconnect Network disable /
<>	144:ef7eb2e8f9f7	390	#define UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN) /!< Local Interconnect Network enable /
<>	144:ef7eb2e8f9f7	391	/**
<>	144:ef7eb2e8f9f7	392	* @}
<>	144:ef7eb2e8f9f7	393	*/
<>	144:ef7eb2e8f9f7	394
<>	144:ef7eb2e8f9f7	395	/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection
<>	144:ef7eb2e8f9f7	396	* @{
<>	144:ef7eb2e8f9f7	397	*/
<>	157:ff67d9f36b67	398	#define UART_LINBREAKDETECTLENGTH_10B (0x00000000U) /!< LIN 10-bit break detection length /
<>	144:ef7eb2e8f9f7	399	#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) /!< LIN 11-bit break detection length /
<>	144:ef7eb2e8f9f7	400	/**
<>	144:ef7eb2e8f9f7	401	* @}
<>	144:ef7eb2e8f9f7	402	*/
<>	144:ef7eb2e8f9f7	403
<>	144:ef7eb2e8f9f7	404	/** @defgroup UART_DMA_Tx UART DMA Tx
<>	144:ef7eb2e8f9f7	405	* @{
<>	144:ef7eb2e8f9f7	406	*/
<>	157:ff67d9f36b67	407	#define UART_DMA_TX_DISABLE (0x00000000U) /!< UART DMA TX disabled /
<>	144:ef7eb2e8f9f7	408	#define UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) /!< UART DMA TX enabled /
<>	144:ef7eb2e8f9f7	409	/**
<>	144:ef7eb2e8f9f7	410	* @}
<>	144:ef7eb2e8f9f7	411	*/
<>	144:ef7eb2e8f9f7	412
<>	144:ef7eb2e8f9f7	413	/** @defgroup UART_DMA_Rx UART DMA Rx
<>	144:ef7eb2e8f9f7	414	* @{
<>	144:ef7eb2e8f9f7	415	*/
<>	157:ff67d9f36b67	416	#define UART_DMA_RX_DISABLE (0x00000000U) /!< UART DMA RX disabled /
<>	144:ef7eb2e8f9f7	417	#define UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) /!< UART DMA RX enabled /
<>	144:ef7eb2e8f9f7	418	/**
<>	144:ef7eb2e8f9f7	419	* @}
<>	144:ef7eb2e8f9f7	420	*/
<>	144:ef7eb2e8f9f7	421
<>	144:ef7eb2e8f9f7	422	/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection
<>	144:ef7eb2e8f9f7	423	* @{
<>	144:ef7eb2e8f9f7	424	*/
<>	157:ff67d9f36b67	425	#define UART_HALF_DUPLEX_DISABLE (0x00000000U) /!< UART half-duplex disabled /
<>	144:ef7eb2e8f9f7	426	#define UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL) /!< UART half-duplex enabled /
<>	144:ef7eb2e8f9f7	427	/**
<>	144:ef7eb2e8f9f7	428	* @}
<>	144:ef7eb2e8f9f7	429	*/
<>	144:ef7eb2e8f9f7	430
<>	144:ef7eb2e8f9f7	431	/** @defgroup UART_WakeUp_Address_Length UART WakeUp Address Length
<>	144:ef7eb2e8f9f7	432	* @{
<>	144:ef7eb2e8f9f7	433	*/
<>	157:ff67d9f36b67	434	#define UART_ADDRESS_DETECT_4B (0x00000000U) /!< 4-bit long wake-up address /
<>	144:ef7eb2e8f9f7	435	#define UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7) /!< 7-bit long wake-up address /
<>	144:ef7eb2e8f9f7	436	/**
<>	144:ef7eb2e8f9f7	437	* @}
<>	144:ef7eb2e8f9f7	438	*/
<>	144:ef7eb2e8f9f7	439
<>	144:ef7eb2e8f9f7	440	/** @defgroup UART_WakeUp_Methods UART WakeUp Methods
<>	144:ef7eb2e8f9f7	441	* @{
<>	144:ef7eb2e8f9f7	442	*/
<>	157:ff67d9f36b67	443	#define UART_WAKEUPMETHOD_IDLELINE (0x00000000U) /!< UART wake-up on idle line /
<>	144:ef7eb2e8f9f7	444	#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE) /!< UART wake-up on address mark /
<>	144:ef7eb2e8f9f7	445	/**
<>	144:ef7eb2e8f9f7	446	* @}
<>	144:ef7eb2e8f9f7	447	*/
<>	144:ef7eb2e8f9f7	448
<>	144:ef7eb2e8f9f7	449	/** @defgroup UART_Flags UART Status Flags
<>	144:ef7eb2e8f9f7	450	* Elements values convention: 0xXXXX
<>	144:ef7eb2e8f9f7	451	* - 0xXXXX : Flag mask in the ISR register
<>	144:ef7eb2e8f9f7	452	* @{
<>	144:ef7eb2e8f9f7	453	*/
<>	157:ff67d9f36b67	454	#define UART_FLAG_REACK (0x00400000U) /!< UART receive enable acknowledge flag /
<>	157:ff67d9f36b67	455	#define UART_FLAG_TEACK (0x00200000U) /!< UART transmit enable acknowledge flag /
<>	157:ff67d9f36b67	456	#define UART_FLAG_WUF (0x00100000U) /!< UART wake-up from stop mode flag /
<>	157:ff67d9f36b67	457	#define UART_FLAG_RWU (0x00080000U) /!< UART receiver wake-up from mute mode flag /
<>	157:ff67d9f36b67	458	#define UART_FLAG_SBKF (0x00040000U) /!< UART send break flag /
<>	157:ff67d9f36b67	459	#define UART_FLAG_CMF (0x00020000U) /!< UART character match flag /
<>	157:ff67d9f36b67	460	#define UART_FLAG_BUSY (0x00010000U) /!< UART busy flag /
<>	157:ff67d9f36b67	461	#define UART_FLAG_ABRF (0x00008000U) /!< UART auto Baud rate flag /
<>	157:ff67d9f36b67	462	#define UART_FLAG_ABRE (0x00004000U) /!< UART auto Baud rate error /
<>	157:ff67d9f36b67	463	#define UART_FLAG_EOBF (0x00001000U) /!< UART end of block flag /
<>	157:ff67d9f36b67	464	#define UART_FLAG_RTOF (0x00000800U) /!< UART receiver timeout flag /
<>	157:ff67d9f36b67	465	#define UART_FLAG_CTS (0x00000400U) /!< UART clear to send flag /
<>	157:ff67d9f36b67	466	#define UART_FLAG_CTSIF (0x00000200U) /!< UART clear to send interrupt flag /
<>	157:ff67d9f36b67	467	#define UART_FLAG_LBDF (0x00000100U) /!< UART LIN break detection flag /
<>	157:ff67d9f36b67	468	#define UART_FLAG_TXE (0x00000080U) /!< UART transmit data register empty /
<>	157:ff67d9f36b67	469	#define UART_FLAG_TC (0x00000040U) /!< UART transmission complete /
<>	157:ff67d9f36b67	470	#define UART_FLAG_RXNE (0x00000020U) /!< UART read data register not empty /
<>	157:ff67d9f36b67	471	#define UART_FLAG_IDLE (0x00000010U) /!< UART idle flag /
<>	157:ff67d9f36b67	472	#define UART_FLAG_ORE (0x00000008U) /!< UART overrun error /
<>	157:ff67d9f36b67	473	#define UART_FLAG_NE (0x00000004U) /!< UART noise error /
<>	157:ff67d9f36b67	474	#define UART_FLAG_FE (0x00000002U) /!< UART frame error /
<>	157:ff67d9f36b67	475	#define UART_FLAG_PE (0x00000001U) /!< UART parity error /
<>	144:ef7eb2e8f9f7	476	/**
<>	144:ef7eb2e8f9f7	477	* @}
<>	144:ef7eb2e8f9f7	478	*/
<>	144:ef7eb2e8f9f7	479
<>	144:ef7eb2e8f9f7	480	/** @defgroup UART_Interrupt_definition UART Interrupts Definition
<>	144:ef7eb2e8f9f7	481	* Elements values convention: 000ZZZZZ0XXYYYYYb
<>	144:ef7eb2e8f9f7	482	* - YYYYY : Interrupt source position in the XX register (5bits)
<>	144:ef7eb2e8f9f7	483	* - XX : Interrupt source register (2bits)
<>	144:ef7eb2e8f9f7	484	* - 01: CR1 register
<>	144:ef7eb2e8f9f7	485	* - 10: CR2 register
<>	144:ef7eb2e8f9f7	486	* - 11: CR3 register
<>	144:ef7eb2e8f9f7	487	* - ZZZZZ : Flag position in the ISR register(5bits)
<>	144:ef7eb2e8f9f7	488	* @{
<>	144:ef7eb2e8f9f7	489	*/
<>	157:ff67d9f36b67	490	#define UART_IT_PE (0x0028U) /!< UART parity error interruption /
<>	157:ff67d9f36b67	491	#define UART_IT_TXE (0x0727U) /!< UART transmit data register empty interruption /
<>	157:ff67d9f36b67	492	#define UART_IT_TC (0x0626U) /!< UART transmission complete interruption /
<>	157:ff67d9f36b67	493	#define UART_IT_RXNE (0x0525U) /!< UART read data register not empty interruption /
<>	157:ff67d9f36b67	494	#define UART_IT_IDLE (0x0424U) /!< UART idle interruption /
<>	157:ff67d9f36b67	495	#define UART_IT_LBD (0x0846U) /!< UART LIN break detection interruption /
<>	157:ff67d9f36b67	496	#define UART_IT_CTS (0x096AU) /!< UART CTS interruption /
<>	157:ff67d9f36b67	497	#define UART_IT_CM (0x112EU) /!< UART character match interruption /
<>	157:ff67d9f36b67	498	#define UART_IT_WUF (0x1476U) /!< UART wake-up from stop mode interruption /
<>	157:ff67d9f36b67	499	#define UART_IT_ERR (0x0060U) /!< UART error interruption /
<>	157:ff67d9f36b67	500	#define UART_IT_ORE (0x0300U) /!< UART overrun error interruption /
<>	157:ff67d9f36b67	501	#define UART_IT_NE (0x0200U) /!< UART noise error interruption /
<>	157:ff67d9f36b67	502	#define UART_IT_FE (0x0100U) /!< UART frame error interruption /
<>	144:ef7eb2e8f9f7	503	/**
<>	144:ef7eb2e8f9f7	504	* @}
<>	144:ef7eb2e8f9f7	505	*/
<>	144:ef7eb2e8f9f7	506
<>	144:ef7eb2e8f9f7	507	/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags
<>	144:ef7eb2e8f9f7	508	* @{
<>	144:ef7eb2e8f9f7	509	*/
<>	157:ff67d9f36b67	510	#define UART_CLEAR_PEF USART_ICR_PECF /!< Parity Error Clear Flag /
<>	157:ff67d9f36b67	511	#define UART_CLEAR_FEF USART_ICR_FECF /!< Framing Error Clear Flag /
<>	157:ff67d9f36b67	512	#define UART_CLEAR_NEF USART_ICR_NCF /!< Noise detected Clear Flag /
<>	157:ff67d9f36b67	513	#define UART_CLEAR_OREF USART_ICR_ORECF /!< Overrun Error Clear Flag /
<>	157:ff67d9f36b67	514	#define UART_CLEAR_IDLEF USART_ICR_IDLECF /!< IDLE line detected Clear Flag /
<>	157:ff67d9f36b67	515	#define UART_CLEAR_TCF USART_ICR_TCCF /!< Transmission Complete Clear Flag /
<>	157:ff67d9f36b67	516	#define UART_CLEAR_LBDF USART_ICR_LBDCF /!< LIN Break Detection Clear Flag /
<>	157:ff67d9f36b67	517	#define UART_CLEAR_CTSF USART_ICR_CTSCF /!< CTS Interrupt Clear Flag /
<>	157:ff67d9f36b67	518	#define UART_CLEAR_RTOF USART_ICR_RTOCF /!< Receiver Time Out Clear Flag /
<>	157:ff67d9f36b67	519	#define UART_CLEAR_EOBF USART_ICR_EOBCF /!< End Of Block Clear Flag /
<>	157:ff67d9f36b67	520	#define UART_CLEAR_CMF USART_ICR_CMCF /!< Character Match Clear Flag /
<>	144:ef7eb2e8f9f7	521	#define UART_CLEAR_WUF USART_ICR_WUCF /!< Wake Up from stop mode Clear Flag /
<>	144:ef7eb2e8f9f7	522	/**
<>	144:ef7eb2e8f9f7	523	* @}
<>	144:ef7eb2e8f9f7	524	*/
<>	144:ef7eb2e8f9f7	525
<>	144:ef7eb2e8f9f7	526	/** @defgroup UART_Request_Parameters UART Request Parameters
<>	144:ef7eb2e8f9f7	527	* @{
<>	144:ef7eb2e8f9f7	528	*/
<>	157:ff67d9f36b67	529	#define UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /!< Auto-Baud Rate Request /
<>	157:ff67d9f36b67	530	#define UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ) /!< Send Break Request /
<>	157:ff67d9f36b67	531	#define UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ) /!< Mute Mode Request /
<>	157:ff67d9f36b67	532	#define UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /!< Receive Data flush Request /
<>	157:ff67d9f36b67	533	#define UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /!< Transmit data flush Request /
<>	144:ef7eb2e8f9f7	534	/**
<>	144:ef7eb2e8f9f7	535	* @}
<>	144:ef7eb2e8f9f7	536	*/
<>	144:ef7eb2e8f9f7	537
<>	144:ef7eb2e8f9f7	538	/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type
<>	144:ef7eb2e8f9f7	539	* @{
<>	144:ef7eb2e8f9f7	540	*/
<>	157:ff67d9f36b67	541	#define UART_ADVFEATURE_NO_INIT (0x00000000U) /!< No advanced feature initialization /
<>	157:ff67d9f36b67	542	#define UART_ADVFEATURE_TXINVERT_INIT (0x00000001U) /!< TX pin active level inversion /
<>	157:ff67d9f36b67	543	#define UART_ADVFEATURE_RXINVERT_INIT (0x00000002U) /!< RX pin active level inversion /
<>	157:ff67d9f36b67	544	#define UART_ADVFEATURE_DATAINVERT_INIT (0x00000004U) /!< Binary data inversion /
<>	157:ff67d9f36b67	545	#define UART_ADVFEATURE_SWAP_INIT (0x00000008U) /!< TX/RX pins swap /
<>	157:ff67d9f36b67	546	#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT (0x00000010U) /!< RX overrun disable /
<>	157:ff67d9f36b67	547	#define UART_ADVFEATURE_DMADISABLEONERROR_INIT (0x00000020U) /!< DMA disable on Reception Error /
<>	157:ff67d9f36b67	548	#define UART_ADVFEATURE_AUTOBAUDRATE_INIT (0x00000040U) /!< Auto Baud rate detection initialization /
<>	157:ff67d9f36b67	549	#define UART_ADVFEATURE_MSBFIRST_INIT (0x00000080U) /!< Most significant bit sent/received first /
<>	144:ef7eb2e8f9f7	550	/**
<>	144:ef7eb2e8f9f7	551	* @}
<>	144:ef7eb2e8f9f7	552	*/
<>	144:ef7eb2e8f9f7	553
<>	144:ef7eb2e8f9f7	554	/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
<>	144:ef7eb2e8f9f7	555	* @{
<>	144:ef7eb2e8f9f7	556	*/
<>	157:ff67d9f36b67	557	#define UART_ADVFEATURE_TXINV_DISABLE (0x00000000U) /!< TX pin active level inversion disable /
<>	144:ef7eb2e8f9f7	558	#define UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) /!< TX pin active level inversion enable /
<>	144:ef7eb2e8f9f7	559	/**
<>	144:ef7eb2e8f9f7	560	* @}
<>	144:ef7eb2e8f9f7	561	*/
<>	144:ef7eb2e8f9f7	562
<>	144:ef7eb2e8f9f7	563	/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
<>	144:ef7eb2e8f9f7	564	* @{
<>	144:ef7eb2e8f9f7	565	*/
<>	157:ff67d9f36b67	566	#define UART_ADVFEATURE_RXINV_DISABLE (0x00000000U) /!< RX pin active level inversion disable /
<>	144:ef7eb2e8f9f7	567	#define UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) /!< RX pin active level inversion enable /
<>	144:ef7eb2e8f9f7	568	/**
<>	144:ef7eb2e8f9f7	569	* @}
<>	144:ef7eb2e8f9f7	570	*/
<>	144:ef7eb2e8f9f7	571
<>	144:ef7eb2e8f9f7	572	/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion
<>	144:ef7eb2e8f9f7	573	* @{
<>	144:ef7eb2e8f9f7	574	*/
<>	157:ff67d9f36b67	575	#define UART_ADVFEATURE_DATAINV_DISABLE (0x00000000U) /!< Binary data inversion disable /
<>	144:ef7eb2e8f9f7	576	#define UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) /!< Binary data inversion enable /
<>	144:ef7eb2e8f9f7	577	/**
<>	144:ef7eb2e8f9f7	578	* @}
<>	144:ef7eb2e8f9f7	579	*/
<>	144:ef7eb2e8f9f7	580
<>	144:ef7eb2e8f9f7	581	/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
<>	144:ef7eb2e8f9f7	582	* @{
<>	144:ef7eb2e8f9f7	583	*/
<>	157:ff67d9f36b67	584	#define UART_ADVFEATURE_SWAP_DISABLE (0x00000000U) /!< TX/RX pins swap disable /
<>	144:ef7eb2e8f9f7	585	#define UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) /!< TX/RX pins swap enable /
<>	144:ef7eb2e8f9f7	586	/**
<>	144:ef7eb2e8f9f7	587	* @}
<>	144:ef7eb2e8f9f7	588	*/
<>	144:ef7eb2e8f9f7	589
<>	144:ef7eb2e8f9f7	590	/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable
<>	144:ef7eb2e8f9f7	591	* @{
<>	144:ef7eb2e8f9f7	592	*/
<>	157:ff67d9f36b67	593	#define UART_ADVFEATURE_OVERRUN_ENABLE (0x00000000U) /!< RX overrun enable /
<>	144:ef7eb2e8f9f7	594	#define UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) /!< RX overrun disable /
<>	144:ef7eb2e8f9f7	595	/**
<>	144:ef7eb2e8f9f7	596	* @}
<>	144:ef7eb2e8f9f7	597	*/
<>	144:ef7eb2e8f9f7	598
<>	144:ef7eb2e8f9f7	599	/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable
<>	144:ef7eb2e8f9f7	600	* @{
<>	144:ef7eb2e8f9f7	601	*/
<>	157:ff67d9f36b67	602	#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE (0x00000000U) /!< RX Auto Baud rate detection enable /
<>	144:ef7eb2e8f9f7	603	#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN) /!< RX Auto Baud rate detection disable /
<>	144:ef7eb2e8f9f7	604	/**
<>	144:ef7eb2e8f9f7	605	* @}
<>	144:ef7eb2e8f9f7	606	*/
<>	144:ef7eb2e8f9f7	607
<>	144:ef7eb2e8f9f7	608	/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error
<>	144:ef7eb2e8f9f7	609	* @{
<>	144:ef7eb2e8f9f7	610	*/
<>	157:ff67d9f36b67	611	#define UART_ADVFEATURE_DMA_ENABLEONRXERROR (0x00000000U) /!< DMA enable on Reception Error /
<>	144:ef7eb2e8f9f7	612	#define UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) /!< DMA disable on Reception Error /
<>	144:ef7eb2e8f9f7	613	/**
<>	144:ef7eb2e8f9f7	614	* @}
<>	144:ef7eb2e8f9f7	615	*/
<>	144:ef7eb2e8f9f7	616
<>	144:ef7eb2e8f9f7	617	/** @defgroup UART_MSB_First UART Advanced Feature MSB First
<>	144:ef7eb2e8f9f7	618	* @{
<>	144:ef7eb2e8f9f7	619	*/
<>	157:ff67d9f36b67	620	#define UART_ADVFEATURE_MSBFIRST_DISABLE (0x00000000U) /!< Most significant bit sent/received first disable /
<>	144:ef7eb2e8f9f7	621	#define UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) /!< Most significant bit sent/received first enable /
<>	144:ef7eb2e8f9f7	622	/**
<>	144:ef7eb2e8f9f7	623	* @}
<>	144:ef7eb2e8f9f7	624	*/
<>	144:ef7eb2e8f9f7	625
<>	144:ef7eb2e8f9f7	626	/** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable
<>	144:ef7eb2e8f9f7	627	* @{
<>	144:ef7eb2e8f9f7	628	*/
<>	157:ff67d9f36b67	629	#define UART_ADVFEATURE_STOPMODE_DISABLE (0x00000000U) /!< UART stop mode disable /
<>	144:ef7eb2e8f9f7	630	#define UART_ADVFEATURE_STOPMODE_ENABLE ((uint32_t)USART_CR1_UESM) /!< UART stop mode enable /
<>	144:ef7eb2e8f9f7	631	/**
<>	144:ef7eb2e8f9f7	632	* @}
<>	144:ef7eb2e8f9f7	633	*/
<>	144:ef7eb2e8f9f7	634
<>	144:ef7eb2e8f9f7	635	/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable
<>	144:ef7eb2e8f9f7	636	* @{
<>	144:ef7eb2e8f9f7	637	*/
<>	157:ff67d9f36b67	638	#define UART_ADVFEATURE_MUTEMODE_DISABLE (0x00000000U) /!< UART mute mode disable /
<>	144:ef7eb2e8f9f7	639	#define UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME) /!< UART mute mode enable /
<>	144:ef7eb2e8f9f7	640	/**
<>	144:ef7eb2e8f9f7	641	* @}
<>	144:ef7eb2e8f9f7	642	*/
<>	144:ef7eb2e8f9f7	643
<>	144:ef7eb2e8f9f7	644	/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register
<>	144:ef7eb2e8f9f7	645	* @{
<>	144:ef7eb2e8f9f7	646	*/
<>	157:ff67d9f36b67	647	#define UART_CR2_ADDRESS_LSB_POS ( 24U) /!< UART address-matching LSB position in CR2 register /
<>	144:ef7eb2e8f9f7	648	/**
<>	144:ef7eb2e8f9f7	649	* @}
<>	144:ef7eb2e8f9f7	650	*/
<>	144:ef7eb2e8f9f7	651
<>	144:ef7eb2e8f9f7	652	/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection
<>	144:ef7eb2e8f9f7	653	* @{
<>	144:ef7eb2e8f9f7	654	*/
<>	157:ff67d9f36b67	655	#define UART_WAKEUP_ON_ADDRESS (0x00000000U) /!< UART wake-up on address /
<>	157:ff67d9f36b67	656	#define UART_WAKEUP_ON_STARTBIT ((uint32_t)USART_CR3_WUS_1) /!< UART wake-up on start bit /
<>	157:ff67d9f36b67	657	#define UART_WAKEUP_ON_READDATA_NONEMPTY ((uint32_t)USART_CR3_WUS) /!< UART wake-up on receive data register not empty /
<>	144:ef7eb2e8f9f7	658	/**
<>	144:ef7eb2e8f9f7	659	* @}
<>	144:ef7eb2e8f9f7	660	*/
<>	144:ef7eb2e8f9f7	661
<>	144:ef7eb2e8f9f7	662	/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity
<>	144:ef7eb2e8f9f7	663	* @{
<>	144:ef7eb2e8f9f7	664	*/
<>	157:ff67d9f36b67	665	#define UART_DE_POLARITY_HIGH (0x00000000U) /!< Driver enable signal is active high /
<>	144:ef7eb2e8f9f7	666	#define UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP) /!< Driver enable signal is active low /
<>	144:ef7eb2e8f9f7	667	/**
<>	144:ef7eb2e8f9f7	668	* @}
<>	144:ef7eb2e8f9f7	669	*/
<>	144:ef7eb2e8f9f7	670
<>	144:ef7eb2e8f9f7	671	/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register
<>	144:ef7eb2e8f9f7	672	* @{
<>	144:ef7eb2e8f9f7	673	*/
<>	157:ff67d9f36b67	674	#define UART_CR1_DEAT_ADDRESS_LSB_POS ( 21U) /!< UART Driver Enable assertion time LSB position in CR1 register /
<>	144:ef7eb2e8f9f7	675	/**
<>	144:ef7eb2e8f9f7	676	* @}
<>	144:ef7eb2e8f9f7	677	*/
<>	144:ef7eb2e8f9f7	678
<>	144:ef7eb2e8f9f7	679	/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register
<>	144:ef7eb2e8f9f7	680	* @{
<>	144:ef7eb2e8f9f7	681	*/
<>	157:ff67d9f36b67	682	#define UART_CR1_DEDT_ADDRESS_LSB_POS ( 16U) /!< UART Driver Enable de-assertion time LSB position in CR1 register /
<>	144:ef7eb2e8f9f7	683	/**
<>	144:ef7eb2e8f9f7	684	* @}
<>	144:ef7eb2e8f9f7	685	*/
<>	144:ef7eb2e8f9f7	686
<>	144:ef7eb2e8f9f7	687	/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask
<>	144:ef7eb2e8f9f7	688	* @{
<>	144:ef7eb2e8f9f7	689	*/
<>	157:ff67d9f36b67	690	#define UART_IT_MASK (0x001FU) /!< UART interruptions flags mask /
<>	144:ef7eb2e8f9f7	691	/**
<>	144:ef7eb2e8f9f7	692	* @}
<>	144:ef7eb2e8f9f7	693	*/
<>	144:ef7eb2e8f9f7	694
<>	144:ef7eb2e8f9f7	695	/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value
<>	144:ef7eb2e8f9f7	696	* @{
<>	144:ef7eb2e8f9f7	697	*/
<>	144:ef7eb2e8f9f7	698	#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFF /!< UART polling-based communications time-out value /
<>	144:ef7eb2e8f9f7	699	/**
<>	144:ef7eb2e8f9f7	700	* @}
<>	144:ef7eb2e8f9f7	701	*/
<>	144:ef7eb2e8f9f7	702
<>	144:ef7eb2e8f9f7	703	/**
<>	144:ef7eb2e8f9f7	704	* @}
<>	144:ef7eb2e8f9f7	705	*/
<>	144:ef7eb2e8f9f7	706
<>	144:ef7eb2e8f9f7	707	/* Exported macros -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	708	/** @defgroup UART_Exported_Macros UART Exported Macros
<>	144:ef7eb2e8f9f7	709	* @{
<>	144:ef7eb2e8f9f7	710	*/
<>	144:ef7eb2e8f9f7	711
<>	144:ef7eb2e8f9f7	712	/** @brief Reset UART handle states.
<>	144:ef7eb2e8f9f7	713	* @param __HANDLE__: UART handle.
<>	144:ef7eb2e8f9f7	714	* @retval None
<>	144:ef7eb2e8f9f7	715	*/
<>	144:ef7eb2e8f9f7	716	#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
<>	144:ef7eb2e8f9f7	717	(__HANDLE__)->gState = HAL_UART_STATE_RESET; \
<>	144:ef7eb2e8f9f7	718	(__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
<>	157:ff67d9f36b67	719	} while(0U)
<>	144:ef7eb2e8f9f7	720	/** @brief Flush the UART Data registers.
<>	157:ff67d9f36b67	721	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	722	* @retval None
<>	144:ef7eb2e8f9f7	723	*/
<>	144:ef7eb2e8f9f7	724	#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \
<>	144:ef7eb2e8f9f7	725	do{ \
<>	144:ef7eb2e8f9f7	726	SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
<>	144:ef7eb2e8f9f7	727	SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
<>	157:ff67d9f36b67	728	} while(0U)
<>	144:ef7eb2e8f9f7	729
<>	144:ef7eb2e8f9f7	730	/** @brief Clear the specified UART pending flag.
<>	144:ef7eb2e8f9f7	731	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	732	* @param __FLAG__: specifies the flag to check.
<>	144:ef7eb2e8f9f7	733	* This parameter can be any combination of the following values:
<>	157:ff67d9f36b67	734	* @arg @ref UART_CLEAR_PEF Parity Error Clear Flag
<>	157:ff67d9f36b67	735	* @arg @ref UART_CLEAR_FEF Framing Error Clear Flag
<>	157:ff67d9f36b67	736	* @arg @ref UART_CLEAR_NEF Noise detected Clear Flag
<>	157:ff67d9f36b67	737	* @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
<>	157:ff67d9f36b67	738	* @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
<>	157:ff67d9f36b67	739	* @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
<>	157:ff67d9f36b67	740	* @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag (not available on all devices)
<>	157:ff67d9f36b67	741	* @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
<>	157:ff67d9f36b67	742	* @arg @ref UART_CLEAR_RTOF Receiver Time Out Clear Flag
<>	157:ff67d9f36b67	743	* @arg @ref UART_CLEAR_EOBF End Of Block Clear Flag (not available on all devices)
<>	157:ff67d9f36b67	744	* @arg @ref UART_CLEAR_CMF Character Match Clear Flag
<>	157:ff67d9f36b67	745	* @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag (not available on all devices)
<>	144:ef7eb2e8f9f7	746	* @retval None
<>	144:ef7eb2e8f9f7	747	*/
<>	144:ef7eb2e8f9f7	748	#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
<>	144:ef7eb2e8f9f7	749
<>	144:ef7eb2e8f9f7	750	/** @brief Clear the UART PE pending flag.
<>	144:ef7eb2e8f9f7	751	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	752	* @retval None
<>	144:ef7eb2e8f9f7	753	*/
<>	144:ef7eb2e8f9f7	754	#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
<>	144:ef7eb2e8f9f7	755
<>	144:ef7eb2e8f9f7	756	/** @brief Clear the UART FE pending flag.
<>	144:ef7eb2e8f9f7	757	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	758	* @retval None
<>	144:ef7eb2e8f9f7	759	*/
<>	144:ef7eb2e8f9f7	760	#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
<>	144:ef7eb2e8f9f7	761
<>	144:ef7eb2e8f9f7	762	/** @brief Clear the UART NE pending flag.
<>	144:ef7eb2e8f9f7	763	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	764	* @retval None
<>	144:ef7eb2e8f9f7	765	*/
<>	144:ef7eb2e8f9f7	766	#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
<>	144:ef7eb2e8f9f7	767
<>	144:ef7eb2e8f9f7	768	/** @brief Clear the UART ORE pending flag.
<>	144:ef7eb2e8f9f7	769	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	770	* @retval None
<>	144:ef7eb2e8f9f7	771	*/
<>	144:ef7eb2e8f9f7	772	#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
<>	144:ef7eb2e8f9f7	773
<>	144:ef7eb2e8f9f7	774	/** @brief Clear the UART IDLE pending flag.
<>	144:ef7eb2e8f9f7	775	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	776	* @retval None
<>	144:ef7eb2e8f9f7	777	*/
<>	144:ef7eb2e8f9f7	778	#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
<>	144:ef7eb2e8f9f7	779
<>	144:ef7eb2e8f9f7	780	/** @brief Check whether the specified UART flag is set or not.
<>	144:ef7eb2e8f9f7	781	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	782	* @param __FLAG__: specifies the flag to check.
<>	144:ef7eb2e8f9f7	783	* This parameter can be one of the following values:
<>	157:ff67d9f36b67	784	* @arg @ref UART_FLAG_REACK Receive enable acknowledge flag
<>	157:ff67d9f36b67	785	* @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag
<>	157:ff67d9f36b67	786	* @arg @ref UART_FLAG_WUF Wake up from stop mode flag
<>	157:ff67d9f36b67	787	* @arg @ref UART_FLAG_RWU Receiver wake up flag
<>	157:ff67d9f36b67	788	* @arg @ref UART_FLAG_SBKF Send Break flag
<>	157:ff67d9f36b67	789	* @arg @ref UART_FLAG_CMF Character match flag
<>	157:ff67d9f36b67	790	* @arg @ref UART_FLAG_BUSY Busy flag
<>	157:ff67d9f36b67	791	* @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag
<>	157:ff67d9f36b67	792	* @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag
<>	157:ff67d9f36b67	793	* @arg @ref UART_FLAG_EOBF End of block flag
<>	157:ff67d9f36b67	794	* @arg @ref UART_FLAG_RTOF Receiver timeout flag
<>	157:ff67d9f36b67	795	* @arg @ref UART_FLAG_CTS CTS Change flag (not available for UART4 and UART5)
<>	157:ff67d9f36b67	796	* @arg @ref UART_FLAG_LBDF LIN Break detection flag
<>	157:ff67d9f36b67	797	* @arg @ref UART_FLAG_TXE Transmit data register empty flag
<>	157:ff67d9f36b67	798	* @arg @ref UART_FLAG_TC Transmission Complete flag
<>	157:ff67d9f36b67	799	* @arg @ref UART_FLAG_RXNE Receive data register not empty flag
<>	157:ff67d9f36b67	800	* @arg @ref UART_FLAG_IDLE Idle Line detection flag
<>	157:ff67d9f36b67	801	* @arg @ref UART_FLAG_ORE Overrun Error flag
<>	157:ff67d9f36b67	802	* @arg @ref UART_FLAG_NE Noise Error flag
<>	157:ff67d9f36b67	803	* @arg @ref UART_FLAG_FE Framing Error flag
<>	157:ff67d9f36b67	804	* @arg @ref UART_FLAG_PE Parity Error flag
<>	144:ef7eb2e8f9f7	805	* @retval The new state of __FLAG__ (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	806	*/
<>	144:ef7eb2e8f9f7	807	#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
<>	144:ef7eb2e8f9f7	808
<>	144:ef7eb2e8f9f7	809	/** @brief Enable the specified UART interrupt.
<>	144:ef7eb2e8f9f7	810	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	811	* @param __INTERRUPT__: specifies the UART interrupt source to enable.
<>	144:ef7eb2e8f9f7	812	* This parameter can be one of the following values:
<>	157:ff67d9f36b67	813	* @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
<>	157:ff67d9f36b67	814	* @arg @ref UART_IT_CM Character match interrupt
<>	157:ff67d9f36b67	815	* @arg @ref UART_IT_CTS CTS change interrupt
<>	157:ff67d9f36b67	816	* @arg @ref UART_IT_LBD LIN Break detection interrupt
<>	157:ff67d9f36b67	817	* @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
<>	157:ff67d9f36b67	818	* @arg @ref UART_IT_TC Transmission complete interrupt
<>	157:ff67d9f36b67	819	* @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
<>	157:ff67d9f36b67	820	* @arg @ref UART_IT_IDLE Idle line detection interrupt
<>	157:ff67d9f36b67	821	* @arg @ref UART_IT_PE Parity Error interrupt
<>	157:ff67d9f36b67	822	* @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
<>	144:ef7eb2e8f9f7	823	* @retval None
<>	144:ef7eb2e8f9f7	824	*/
<>	157:ff67d9f36b67	825	#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 \|= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
<>	157:ff67d9f36b67	826	((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 \|= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
<>	144:ef7eb2e8f9f7	827	((__HANDLE__)->Instance->CR3 \|= (1U << ((__INTERRUPT__) & UART_IT_MASK))))
<>	144:ef7eb2e8f9f7	828
<>	144:ef7eb2e8f9f7	829
<>	144:ef7eb2e8f9f7	830	/** @brief Disable the specified UART interrupt.
<>	144:ef7eb2e8f9f7	831	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	832	* @param __INTERRUPT__: specifies the UART interrupt source to disable.
<>	144:ef7eb2e8f9f7	833	* This parameter can be one of the following values:
<>	157:ff67d9f36b67	834	* @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
<>	157:ff67d9f36b67	835	* @arg @ref UART_IT_CM Character match interrupt
<>	157:ff67d9f36b67	836	* @arg @ref UART_IT_CTS CTS change interrupt
<>	157:ff67d9f36b67	837	* @arg @ref UART_IT_LBD LIN Break detection interrupt
<>	157:ff67d9f36b67	838	* @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
<>	157:ff67d9f36b67	839	* @arg @ref UART_IT_TC Transmission complete interrupt
<>	157:ff67d9f36b67	840	* @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
<>	157:ff67d9f36b67	841	* @arg @ref UART_IT_IDLE Idle line detection interrupt
<>	157:ff67d9f36b67	842	* @arg @ref UART_IT_PE Parity Error interrupt
<>	157:ff67d9f36b67	843	* @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
<>	144:ef7eb2e8f9f7	844	* @retval None
<>	144:ef7eb2e8f9f7	845	*/
<>	157:ff67d9f36b67	846	#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
<>	157:ff67d9f36b67	847	((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
<>	144:ef7eb2e8f9f7	848	((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))
<>	144:ef7eb2e8f9f7	849
<>	144:ef7eb2e8f9f7	850	/** @brief Check whether the specified UART interrupt has occurred or not.
<>	144:ef7eb2e8f9f7	851	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	852	* @param __IT__: specifies the UART interrupt to check.
<>	144:ef7eb2e8f9f7	853	* This parameter can be one of the following values:
<>	157:ff67d9f36b67	854	* @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
<>	157:ff67d9f36b67	855	* @arg @ref UART_IT_CM Character match interrupt
<>	157:ff67d9f36b67	856	* @arg @ref UART_IT_CTS CTS change interrupt (not available for UART4 and UART5)
<>	157:ff67d9f36b67	857	* @arg @ref UART_IT_LBD LIN Break detection interrupt
<>	157:ff67d9f36b67	858	* @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
<>	157:ff67d9f36b67	859	* @arg @ref UART_IT_TC Transmission complete interrupt
<>	157:ff67d9f36b67	860	* @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
<>	157:ff67d9f36b67	861	* @arg @ref UART_IT_IDLE Idle line detection interrupt
<>	157:ff67d9f36b67	862	* @arg @ref UART_IT_ORE Overrun Error interrupt
<>	157:ff67d9f36b67	863	* @arg @ref UART_IT_NE Noise Error interrupt
<>	157:ff67d9f36b67	864	* @arg @ref UART_IT_FE Framing Error interrupt
<>	157:ff67d9f36b67	865	* @arg @ref UART_IT_PE Parity Error interrupt
<>	144:ef7eb2e8f9f7	866	* @retval The new state of __IT__ (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	867	*/
<>	157:ff67d9f36b67	868	#define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
<>	144:ef7eb2e8f9f7	869
<>	144:ef7eb2e8f9f7	870	/** @brief Check whether the specified UART interrupt source is enabled or not.
<>	144:ef7eb2e8f9f7	871	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	872	* @param __IT__: specifies the UART interrupt source to check.
<>	144:ef7eb2e8f9f7	873	* This parameter can be one of the following values:
<>	157:ff67d9f36b67	874	* @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
<>	157:ff67d9f36b67	875	* @arg @ref UART_IT_CM Character match interrupt
<>	157:ff67d9f36b67	876	* @arg @ref UART_IT_CTS CTS change interrupt (not available for UART4 and UART5)
<>	157:ff67d9f36b67	877	* @arg @ref UART_IT_LBD LIN Break detection interrupt
<>	157:ff67d9f36b67	878	* @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
<>	157:ff67d9f36b67	879	* @arg @ref UART_IT_TC Transmission complete interrupt
<>	157:ff67d9f36b67	880	* @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
<>	157:ff67d9f36b67	881	* @arg @ref UART_IT_IDLE Idle line detection interrupt
<>	157:ff67d9f36b67	882	* @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
<>	157:ff67d9f36b67	883	* @arg @ref UART_IT_PE Parity Error interrupt
<>	144:ef7eb2e8f9f7	884	* @retval The new state of __IT__ (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	885	*/
<>	157:ff67d9f36b67	886	#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \
<>	157:ff67d9f36b67	887	(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__IT__)) & UART_IT_MASK)))
<>	144:ef7eb2e8f9f7	888
<>	144:ef7eb2e8f9f7	889	/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag.
<>	144:ef7eb2e8f9f7	890	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	891	* @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
<>	144:ef7eb2e8f9f7	892	* to clear the corresponding interrupt
<>	144:ef7eb2e8f9f7	893	* This parameter can be one of the following values:
<>	157:ff67d9f36b67	894	* @arg @ref UART_CLEAR_PEF Parity Error Clear Flag
<>	157:ff67d9f36b67	895	* @arg @ref UART_CLEAR_FEF Framing Error Clear Flag
<>	157:ff67d9f36b67	896	* @arg @ref UART_CLEAR_NEF Noise detected Clear Flag
<>	157:ff67d9f36b67	897	* @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
<>	157:ff67d9f36b67	898	* @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
<>	157:ff67d9f36b67	899	* @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
<>	157:ff67d9f36b67	900	* @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag
<>	157:ff67d9f36b67	901	* @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
<>	157:ff67d9f36b67	902	* @arg @ref UART_CLEAR_RTOF Receiver Time Out Clear Flag
<>	157:ff67d9f36b67	903	* @arg @ref UART_CLEAR_EOBF End Of Block Clear Flag
<>	157:ff67d9f36b67	904	* @arg @ref UART_CLEAR_CMF Character Match Clear Flag
<>	157:ff67d9f36b67	905	* @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag
<>	144:ef7eb2e8f9f7	906	* @retval None
<>	144:ef7eb2e8f9f7	907	*/
<>	144:ef7eb2e8f9f7	908	#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
<>	144:ef7eb2e8f9f7	909
<>	144:ef7eb2e8f9f7	910	/** @brief Set a specific UART request flag.
<>	144:ef7eb2e8f9f7	911	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	912	* @param __REQ__: specifies the request flag to set
<>	144:ef7eb2e8f9f7	913	* This parameter can be one of the following values:
<>	157:ff67d9f36b67	914	* @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request
<>	157:ff67d9f36b67	915	* @arg @ref UART_SENDBREAK_REQUEST Send Break Request
<>	157:ff67d9f36b67	916	* @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request
<>	157:ff67d9f36b67	917	* @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request
<>	157:ff67d9f36b67	918	* @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request
<>	144:ef7eb2e8f9f7	919	* @retval None
<>	144:ef7eb2e8f9f7	920	*/
<>	157:ff67d9f36b67	921	#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR \|= (uint32_t)(__REQ__))
<>	144:ef7eb2e8f9f7	922
<>	144:ef7eb2e8f9f7	923	/** @brief Enable the UART one bit sample method.
<>	144:ef7eb2e8f9f7	924	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	925	* @retval None
<>	144:ef7eb2e8f9f7	926	*/
<>	144:ef7eb2e8f9f7	927	#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\|= USART_CR3_ONEBIT)
<>	144:ef7eb2e8f9f7	928
<>	144:ef7eb2e8f9f7	929	/** @brief Disable the UART one bit sample method.
<>	144:ef7eb2e8f9f7	930	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	931	* @retval None
<>	144:ef7eb2e8f9f7	932	*/
<>	144:ef7eb2e8f9f7	933	#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
<>	144:ef7eb2e8f9f7	934
<>	144:ef7eb2e8f9f7	935	/** @brief Enable UART.
<>	144:ef7eb2e8f9f7	936	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	937	* @retval None
<>	144:ef7eb2e8f9f7	938	*/
<>	144:ef7eb2e8f9f7	939	#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 \|= USART_CR1_UE)
<>	144:ef7eb2e8f9f7	940
<>	157:ff67d9f36b67	941	/** @brief Disable UART.
<>	144:ef7eb2e8f9f7	942	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	943	* @retval None
<>	144:ef7eb2e8f9f7	944	*/
<>	144:ef7eb2e8f9f7	945	#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
<>	144:ef7eb2e8f9f7	946
<>	144:ef7eb2e8f9f7	947	/** @brief Enable CTS flow control.
<>	144:ef7eb2e8f9f7	948	* @note This macro allows to enable CTS hardware flow control for a given UART instance,
<>	144:ef7eb2e8f9f7	949	* without need to call HAL_UART_Init() function.
<>	144:ef7eb2e8f9f7	950	* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
<>	144:ef7eb2e8f9f7	951	* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
<>	144:ef7eb2e8f9f7	952	* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
<>	144:ef7eb2e8f9f7	953	* - UART instance should have already been initialised (through call of HAL_UART_Init() )
<>	144:ef7eb2e8f9f7	954	* - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
<>	144:ef7eb2e8f9f7	955	* and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
<>	144:ef7eb2e8f9f7	956	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	957	* @retval None
<>	144:ef7eb2e8f9f7	958	*/
<>	144:ef7eb2e8f9f7	959	#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	960	do{ \
<>	144:ef7eb2e8f9f7	961	SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
<>	144:ef7eb2e8f9f7	962	(__HANDLE__)->Init.HwFlowCtl \|= USART_CR3_CTSE; \
<>	157:ff67d9f36b67	963	} while(0U)
<>	144:ef7eb2e8f9f7	964
<>	144:ef7eb2e8f9f7	965	/** @brief Disable CTS flow control.
<>	144:ef7eb2e8f9f7	966	* @note This macro allows to disable CTS hardware flow control for a given UART instance,
<>	144:ef7eb2e8f9f7	967	* without need to call HAL_UART_Init() function.
<>	144:ef7eb2e8f9f7	968	* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
<>	144:ef7eb2e8f9f7	969	* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
<>	144:ef7eb2e8f9f7	970	* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
<>	144:ef7eb2e8f9f7	971	* - UART instance should have already been initialised (through call of HAL_UART_Init() )
<>	144:ef7eb2e8f9f7	972	* - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
<>	144:ef7eb2e8f9f7	973	* and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
<>	144:ef7eb2e8f9f7	974	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	975	* @retval None
<>	144:ef7eb2e8f9f7	976	*/
<>	144:ef7eb2e8f9f7	977	#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	978	do{ \
<>	144:ef7eb2e8f9f7	979	CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
<>	144:ef7eb2e8f9f7	980	(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
<>	157:ff67d9f36b67	981	} while(0U)
<>	144:ef7eb2e8f9f7	982
<>	144:ef7eb2e8f9f7	983	/** @brief Enable RTS flow control.
<>	144:ef7eb2e8f9f7	984	* @note This macro allows to enable RTS hardware flow control for a given UART instance,
<>	144:ef7eb2e8f9f7	985	* without need to call HAL_UART_Init() function.
<>	144:ef7eb2e8f9f7	986	* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
<>	144:ef7eb2e8f9f7	987	* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
<>	144:ef7eb2e8f9f7	988	* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
<>	144:ef7eb2e8f9f7	989	* - UART instance should have already been initialised (through call of HAL_UART_Init() )
<>	144:ef7eb2e8f9f7	990	* - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
<>	144:ef7eb2e8f9f7	991	* and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
<>	144:ef7eb2e8f9f7	992	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	993	* @retval None
<>	144:ef7eb2e8f9f7	994	*/
<>	144:ef7eb2e8f9f7	995	#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	996	do{ \
<>	144:ef7eb2e8f9f7	997	SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
<>	144:ef7eb2e8f9f7	998	(__HANDLE__)->Init.HwFlowCtl \|= USART_CR3_RTSE; \
<>	157:ff67d9f36b67	999	} while(0U)
<>	144:ef7eb2e8f9f7	1000
<>	144:ef7eb2e8f9f7	1001	/** @brief Disable RTS flow control.
<>	144:ef7eb2e8f9f7	1002	* @note This macro allows to disable RTS hardware flow control for a given UART instance,
<>	144:ef7eb2e8f9f7	1003	* without need to call HAL_UART_Init() function.
<>	144:ef7eb2e8f9f7	1004	* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
<>	144:ef7eb2e8f9f7	1005	* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
<>	144:ef7eb2e8f9f7	1006	* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
<>	144:ef7eb2e8f9f7	1007	* - UART instance should have already been initialised (through call of HAL_UART_Init() )
<>	144:ef7eb2e8f9f7	1008	* - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
<>	144:ef7eb2e8f9f7	1009	* and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
<>	144:ef7eb2e8f9f7	1010	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	1011	* @retval None
<>	144:ef7eb2e8f9f7	1012	*/
<>	144:ef7eb2e8f9f7	1013	#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	1014	do{ \
<>	144:ef7eb2e8f9f7	1015	CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
<>	144:ef7eb2e8f9f7	1016	(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
<>	157:ff67d9f36b67	1017	} while(0U)
<>	144:ef7eb2e8f9f7	1018
<>	144:ef7eb2e8f9f7	1019	/**
<>	144:ef7eb2e8f9f7	1020	* @}
<>	144:ef7eb2e8f9f7	1021	*/
<>	144:ef7eb2e8f9f7	1022
<>	144:ef7eb2e8f9f7	1023	/* Private macros --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1024	/** @defgroup UART_Private_Macros UART Private Macros
<>	144:ef7eb2e8f9f7	1025	* @{
<>	144:ef7eb2e8f9f7	1026	*/
<>	144:ef7eb2e8f9f7	1027	/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
<>	144:ef7eb2e8f9f7	1028	* @param __PCLK__: UART clock.
<>	144:ef7eb2e8f9f7	1029	* @param __BAUD__: Baud rate set by the user.
<>	144:ef7eb2e8f9f7	1030	* @retval Division result
<>	144:ef7eb2e8f9f7	1031	*/
<>	157:ff67d9f36b67	1032	#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__))
<>	144:ef7eb2e8f9f7	1033
<>	144:ef7eb2e8f9f7	1034	/** @brief BRR division operation to set BRR register in 16-bit oversampling mode.
<>	144:ef7eb2e8f9f7	1035	* @param __PCLK__: UART clock.
<>	144:ef7eb2e8f9f7	1036	* @param __BAUD__: Baud rate set by the user.
<>	144:ef7eb2e8f9f7	1037	* @retval Division result
<>	144:ef7eb2e8f9f7	1038	*/
<>	157:ff67d9f36b67	1039	#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__))
<>	144:ef7eb2e8f9f7	1040
<>	157:ff67d9f36b67	1041	/** @brief Check UART Baud rate.
<>	144:ef7eb2e8f9f7	1042	* @param __BAUDRATE__: Baudrate specified by the user.
<>	144:ef7eb2e8f9f7	1043	* The maximum Baud Rate is derived from the maximum clock on F3 (i.e. 72 MHz)
<>	157:ff67d9f36b67	1044	* divided by the smallest oversampling used on the USART (i.e. 8)
<>	144:ef7eb2e8f9f7	1045	* @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
<>	144:ef7eb2e8f9f7	1046	*/
<>	157:ff67d9f36b67	1047	#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001U)
<>	144:ef7eb2e8f9f7	1048
<>	144:ef7eb2e8f9f7	1049	/** @brief Check UART assertion time.
<>	144:ef7eb2e8f9f7	1050	* @param __TIME__: 5-bit value assertion time.
<>	144:ef7eb2e8f9f7	1051	* @retval Test result (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	1052	*/
<>	157:ff67d9f36b67	1053	#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
<>	144:ef7eb2e8f9f7	1054
<>	144:ef7eb2e8f9f7	1055	/** @brief Check UART deassertion time.
<>	144:ef7eb2e8f9f7	1056	* @param __TIME__: 5-bit value deassertion time.
<>	144:ef7eb2e8f9f7	1057	* @retval Test result (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	1058	*/
<>	157:ff67d9f36b67	1059	#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
<>	144:ef7eb2e8f9f7	1060
<>	144:ef7eb2e8f9f7	1061	/**
<>	144:ef7eb2e8f9f7	1062	* @brief Ensure that UART frame number of stop bits is valid.
<>	144:ef7eb2e8f9f7	1063	* @param __STOPBITS__: UART frame number of stop bits.
<>	144:ef7eb2e8f9f7	1064	* @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
<>	144:ef7eb2e8f9f7	1065	*/
<>	144:ef7eb2e8f9f7	1066	#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) \|\| \
<>	144:ef7eb2e8f9f7	1067	((__STOPBITS__) == UART_STOPBITS_1) \|\| \
<>	144:ef7eb2e8f9f7	1068	((__STOPBITS__) == UART_STOPBITS_1_5) \|\| \
<>	144:ef7eb2e8f9f7	1069	((__STOPBITS__) == UART_STOPBITS_2))
<>	144:ef7eb2e8f9f7	1070
<>	144:ef7eb2e8f9f7	1071	/**
<>	144:ef7eb2e8f9f7	1072	* @brief Ensure that UART frame parity is valid.
<>	144:ef7eb2e8f9f7	1073	* @param __PARITY__: UART frame parity.
<>	144:ef7eb2e8f9f7	1074	* @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
<>	144:ef7eb2e8f9f7	1075	*/
<>	144:ef7eb2e8f9f7	1076	#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) \|\| \
<>	144:ef7eb2e8f9f7	1077	((__PARITY__) == UART_PARITY_EVEN) \|\| \
<>	144:ef7eb2e8f9f7	1078	((__PARITY__) == UART_PARITY_ODD))
<>	144:ef7eb2e8f9f7	1079
<>	144:ef7eb2e8f9f7	1080	/**
<>	144:ef7eb2e8f9f7	1081	* @brief Ensure that UART hardware flow control is valid.
<>	144:ef7eb2e8f9f7	1082	* @param __CONTROL__: UART hardware flow control.
<>	144:ef7eb2e8f9f7	1083	* @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
<>	144:ef7eb2e8f9f7	1084	*/
<>	144:ef7eb2e8f9f7	1085	#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
<>	144:ef7eb2e8f9f7	1086	(((__CONTROL__) == UART_HWCONTROL_NONE) \|\| \
<>	144:ef7eb2e8f9f7	1087	((__CONTROL__) == UART_HWCONTROL_RTS) \|\| \
<>	144:ef7eb2e8f9f7	1088	((__CONTROL__) == UART_HWCONTROL_CTS) \|\| \
<>	144:ef7eb2e8f9f7	1089	((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
<>	144:ef7eb2e8f9f7	1090
<>	144:ef7eb2e8f9f7	1091	/**
<>	144:ef7eb2e8f9f7	1092	* @brief Ensure that UART communication mode is valid.
<>	144:ef7eb2e8f9f7	1093	* @param __MODE__: UART communication mode.
<>	144:ef7eb2e8f9f7	1094	* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
<>	144:ef7eb2e8f9f7	1095	*/
<>	157:ff67d9f36b67	1096	#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
<>	144:ef7eb2e8f9f7	1097
<>	144:ef7eb2e8f9f7	1098	/**
<>	144:ef7eb2e8f9f7	1099	* @brief Ensure that UART state is valid.
<>	144:ef7eb2e8f9f7	1100	* @param __STATE__: UART state.
<>	144:ef7eb2e8f9f7	1101	* @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
<>	144:ef7eb2e8f9f7	1102	*/
<>	144:ef7eb2e8f9f7	1103	#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1104	((__STATE__) == UART_STATE_ENABLE))
<>	144:ef7eb2e8f9f7	1105
<>	144:ef7eb2e8f9f7	1106	/**
<>	144:ef7eb2e8f9f7	1107	* @brief Ensure that UART oversampling is valid.
<>	144:ef7eb2e8f9f7	1108	* @param __SAMPLING__: UART oversampling.
<>	144:ef7eb2e8f9f7	1109	* @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
<>	144:ef7eb2e8f9f7	1110	*/
<>	144:ef7eb2e8f9f7	1111	#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) \|\| \
<>	144:ef7eb2e8f9f7	1112	((__SAMPLING__) == UART_OVERSAMPLING_8))
<>	144:ef7eb2e8f9f7	1113
<>	144:ef7eb2e8f9f7	1114	/**
<>	144:ef7eb2e8f9f7	1115	* @brief Ensure that UART frame sampling is valid.
<>	144:ef7eb2e8f9f7	1116	* @param __ONEBIT__: UART frame sampling.
<>	144:ef7eb2e8f9f7	1117	* @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
<>	144:ef7eb2e8f9f7	1118	*/
<>	144:ef7eb2e8f9f7	1119	#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1120	((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))
<>	144:ef7eb2e8f9f7	1121
<>	144:ef7eb2e8f9f7	1122	/**
<>	144:ef7eb2e8f9f7	1123	* @brief Ensure that Address Length detection parameter is valid.
<>	144:ef7eb2e8f9f7	1124	* @param __ADDRESS__: UART Adress length value.
<>	144:ef7eb2e8f9f7	1125	* @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
<>	144:ef7eb2e8f9f7	1126	*/
<>	144:ef7eb2e8f9f7	1127	#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) \|\| \
<>	144:ef7eb2e8f9f7	1128	((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
<>	144:ef7eb2e8f9f7	1129
<>	144:ef7eb2e8f9f7	1130	/**
<>	144:ef7eb2e8f9f7	1131	* @brief Ensure that UART auto Baud rate detection mode is valid.
<>	144:ef7eb2e8f9f7	1132	* @param __MODE__: UART auto Baud rate detection mode.
<>	144:ef7eb2e8f9f7	1133	* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
<>	144:ef7eb2e8f9f7	1134	*/
<>	157:ff67d9f36b67	1135	#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) \|\| \
<>	144:ef7eb2e8f9f7	1136	((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) \|\| \
<>	157:ff67d9f36b67	1137	((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) \|\| \
<>	144:ef7eb2e8f9f7	1138	((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
<>	144:ef7eb2e8f9f7	1139
<>	144:ef7eb2e8f9f7	1140	/**
<>	144:ef7eb2e8f9f7	1141	* @brief Ensure that UART receiver timeout setting is valid.
<>	144:ef7eb2e8f9f7	1142	* @param __TIMEOUT__: UART receiver timeout setting.
<>	144:ef7eb2e8f9f7	1143	* @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
<>	144:ef7eb2e8f9f7	1144	*/
<>	144:ef7eb2e8f9f7	1145	#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1146	((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
<>	144:ef7eb2e8f9f7	1147
<>	144:ef7eb2e8f9f7	1148	/**
<>	144:ef7eb2e8f9f7	1149	* @brief Ensure that UART LIN state is valid.
<>	144:ef7eb2e8f9f7	1150	* @param __LIN__: UART LIN state.
<>	144:ef7eb2e8f9f7	1151	* @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)
<>	144:ef7eb2e8f9f7	1152	*/
<>	144:ef7eb2e8f9f7	1153	#define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1154	((__LIN__) == UART_LIN_ENABLE))
<>	144:ef7eb2e8f9f7	1155
<>	144:ef7eb2e8f9f7	1156	/**
<>	144:ef7eb2e8f9f7	1157	* @brief Ensure that UART LIN break detection length is valid.
<>	144:ef7eb2e8f9f7	1158	* @param __LENGTH__: UART LIN break detection length.
<>	144:ef7eb2e8f9f7	1159	* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
<>	144:ef7eb2e8f9f7	1160	*/
<>	144:ef7eb2e8f9f7	1161	#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) \|\| \
<>	144:ef7eb2e8f9f7	1162	((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))
<>	144:ef7eb2e8f9f7	1163
<>	144:ef7eb2e8f9f7	1164	/**
<>	144:ef7eb2e8f9f7	1165	* @brief Ensure that UART DMA TX state is valid.
<>	144:ef7eb2e8f9f7	1166	* @param __DMATX__: UART DMA TX state.
<>	144:ef7eb2e8f9f7	1167	* @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
<>	144:ef7eb2e8f9f7	1168	*/
<>	144:ef7eb2e8f9f7	1169	#define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1170	((__DMATX__) == UART_DMA_TX_ENABLE))
<>	144:ef7eb2e8f9f7	1171
<>	144:ef7eb2e8f9f7	1172	/**
<>	144:ef7eb2e8f9f7	1173	* @brief Ensure that UART DMA RX state is valid.
<>	144:ef7eb2e8f9f7	1174	* @param __DMARX__: UART DMA RX state.
<>	144:ef7eb2e8f9f7	1175	* @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
<>	144:ef7eb2e8f9f7	1176	*/
<>	144:ef7eb2e8f9f7	1177	#define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1178	((__DMARX__) == UART_DMA_RX_ENABLE))
<>	144:ef7eb2e8f9f7	1179
<>	144:ef7eb2e8f9f7	1180	/**
<>	144:ef7eb2e8f9f7	1181	* @brief Ensure that UART half-duplex state is valid.
<>	144:ef7eb2e8f9f7	1182	* @param __HDSEL__: UART half-duplex state.
<>	144:ef7eb2e8f9f7	1183	* @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)
<>	144:ef7eb2e8f9f7	1184	*/
<>	144:ef7eb2e8f9f7	1185	#define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1186	((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))
<>	144:ef7eb2e8f9f7	1187
<>	144:ef7eb2e8f9f7	1188	/**
<>	144:ef7eb2e8f9f7	1189	* @brief Ensure that UART wake-up method is valid.
<>	144:ef7eb2e8f9f7	1190	* @param __WAKEUP__: UART wake-up method .
<>	144:ef7eb2e8f9f7	1191	* @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)
<>	144:ef7eb2e8f9f7	1192	*/
<>	144:ef7eb2e8f9f7	1193	#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) \|\| \
<>	144:ef7eb2e8f9f7	1194	((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))
<>	144:ef7eb2e8f9f7	1195
<>	144:ef7eb2e8f9f7	1196	/**
<>	144:ef7eb2e8f9f7	1197	* @brief Ensure that UART advanced features initialization is valid.
<>	144:ef7eb2e8f9f7	1198	* @param __INIT__: UART advanced features initialization.
<>	144:ef7eb2e8f9f7	1199	* @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
<>	144:ef7eb2e8f9f7	1200	*/
<>	144:ef7eb2e8f9f7	1201	#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT \| \
<>	144:ef7eb2e8f9f7	1202	UART_ADVFEATURE_TXINVERT_INIT \| \
<>	144:ef7eb2e8f9f7	1203	UART_ADVFEATURE_RXINVERT_INIT \| \
<>	144:ef7eb2e8f9f7	1204	UART_ADVFEATURE_DATAINVERT_INIT \| \
<>	144:ef7eb2e8f9f7	1205	UART_ADVFEATURE_SWAP_INIT \| \
<>	144:ef7eb2e8f9f7	1206	UART_ADVFEATURE_RXOVERRUNDISABLE_INIT \| \
<>	144:ef7eb2e8f9f7	1207	UART_ADVFEATURE_DMADISABLEONERROR_INIT \| \
<>	144:ef7eb2e8f9f7	1208	UART_ADVFEATURE_AUTOBAUDRATE_INIT \| \
<>	144:ef7eb2e8f9f7	1209	UART_ADVFEATURE_MSBFIRST_INIT))
<>	144:ef7eb2e8f9f7	1210
<>	144:ef7eb2e8f9f7	1211	/**
<>	144:ef7eb2e8f9f7	1212	* @brief Ensure that UART frame TX inversion setting is valid.
<>	144:ef7eb2e8f9f7	1213	* @param __TXINV__: UART frame TX inversion setting.
<>	144:ef7eb2e8f9f7	1214	* @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
<>	144:ef7eb2e8f9f7	1215	*/
<>	144:ef7eb2e8f9f7	1216	#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1217	((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))
<>	144:ef7eb2e8f9f7	1218
<>	144:ef7eb2e8f9f7	1219	/**
<>	144:ef7eb2e8f9f7	1220	* @brief Ensure that UART frame RX inversion setting is valid.
<>	144:ef7eb2e8f9f7	1221	* @param __RXINV__: UART frame RX inversion setting.
<>	144:ef7eb2e8f9f7	1222	* @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
<>	144:ef7eb2e8f9f7	1223	*/
<>	144:ef7eb2e8f9f7	1224	#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1225	((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))
<>	144:ef7eb2e8f9f7	1226
<>	144:ef7eb2e8f9f7	1227	/**
<>	144:ef7eb2e8f9f7	1228	* @brief Ensure that UART frame data inversion setting is valid.
<>	144:ef7eb2e8f9f7	1229	* @param __DATAINV__: UART frame data inversion setting.
<>	144:ef7eb2e8f9f7	1230	* @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
<>	144:ef7eb2e8f9f7	1231	*/
<>	144:ef7eb2e8f9f7	1232	#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1233	((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))
<>	144:ef7eb2e8f9f7	1234
<>	144:ef7eb2e8f9f7	1235	/**
<>	144:ef7eb2e8f9f7	1236	* @brief Ensure that UART frame RX/TX pins swap setting is valid.
<>	144:ef7eb2e8f9f7	1237	* @param __SWAP__: UART frame RX/TX pins swap setting.
<>	144:ef7eb2e8f9f7	1238	* @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
<>	144:ef7eb2e8f9f7	1239	*/
<>	144:ef7eb2e8f9f7	1240	#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1241	((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))
<>	144:ef7eb2e8f9f7	1242
<>	144:ef7eb2e8f9f7	1243	/**
<>	144:ef7eb2e8f9f7	1244	* @brief Ensure that UART frame overrun setting is valid.
<>	144:ef7eb2e8f9f7	1245	* @param __OVERRUN__: UART frame overrun setting.
<>	144:ef7eb2e8f9f7	1246	* @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
<>	144:ef7eb2e8f9f7	1247	*/
<>	144:ef7eb2e8f9f7	1248	#define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) \|\| \
<>	144:ef7eb2e8f9f7	1249	((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))
<>	144:ef7eb2e8f9f7	1250
<>	144:ef7eb2e8f9f7	1251	/**
<>	144:ef7eb2e8f9f7	1252	* @brief Ensure that UART auto Baud rate state is valid.
<>	144:ef7eb2e8f9f7	1253	* @param __AUTOBAUDRATE__: UART auto Baud rate state.
<>	144:ef7eb2e8f9f7	1254	* @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
<>	144:ef7eb2e8f9f7	1255	*/
<>	144:ef7eb2e8f9f7	1256	#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1257	((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
<>	144:ef7eb2e8f9f7	1258
<>	144:ef7eb2e8f9f7	1259	/**
<>	144:ef7eb2e8f9f7	1260	* @brief Ensure that UART DMA enabling or disabling on error setting is valid.
<>	144:ef7eb2e8f9f7	1261	* @param __DMA__: UART DMA enabling or disabling on error setting.
<>	144:ef7eb2e8f9f7	1262	* @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
<>	144:ef7eb2e8f9f7	1263	*/
<>	144:ef7eb2e8f9f7	1264	#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) \|\| \
<>	144:ef7eb2e8f9f7	1265	((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
<>	144:ef7eb2e8f9f7	1266
<>	144:ef7eb2e8f9f7	1267	/**
<>	144:ef7eb2e8f9f7	1268	* @brief Ensure that UART frame MSB first setting is valid.
<>	144:ef7eb2e8f9f7	1269	* @param __MSBFIRST__: UART frame MSB first setting.
<>	144:ef7eb2e8f9f7	1270	* @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
<>	144:ef7eb2e8f9f7	1271	*/
<>	144:ef7eb2e8f9f7	1272	#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1273	((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))
<>	144:ef7eb2e8f9f7	1274
<>	144:ef7eb2e8f9f7	1275	/**
<>	144:ef7eb2e8f9f7	1276	* @brief Ensure that UART stop mode state is valid.
<>	144:ef7eb2e8f9f7	1277	* @param __STOPMODE__: UART stop mode state.
<>	144:ef7eb2e8f9f7	1278	* @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
<>	144:ef7eb2e8f9f7	1279	*/
<>	144:ef7eb2e8f9f7	1280	#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1281	((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))
<>	144:ef7eb2e8f9f7	1282
<>	144:ef7eb2e8f9f7	1283	/**
<>	144:ef7eb2e8f9f7	1284	* @brief Ensure that UART mute mode state is valid.
<>	144:ef7eb2e8f9f7	1285	* @param __MUTE__: UART mute mode state.
<>	144:ef7eb2e8f9f7	1286	* @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)
<>	144:ef7eb2e8f9f7	1287	*/
<>	144:ef7eb2e8f9f7	1288	#define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1289	((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))
<>	144:ef7eb2e8f9f7	1290
<>	144:ef7eb2e8f9f7	1291	/**
<>	144:ef7eb2e8f9f7	1292	* @brief Ensure that UART wake-up selection is valid.
<>	144:ef7eb2e8f9f7	1293	* @param __WAKE__: UART wake-up selection.
<>	144:ef7eb2e8f9f7	1294	* @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
<>	144:ef7eb2e8f9f7	1295	*/
<>	144:ef7eb2e8f9f7	1296	#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) \|\| \
<>	144:ef7eb2e8f9f7	1297	((__WAKE__) == UART_WAKEUP_ON_STARTBIT) \|\| \
<>	144:ef7eb2e8f9f7	1298	((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))
<>	144:ef7eb2e8f9f7	1299
<>	144:ef7eb2e8f9f7	1300	/**
<>	144:ef7eb2e8f9f7	1301	* @brief Ensure that UART driver enable polarity is valid.
<>	144:ef7eb2e8f9f7	1302	* @param __POLARITY__: UART driver enable polarity.
<>	144:ef7eb2e8f9f7	1303	* @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
<>	144:ef7eb2e8f9f7	1304	*/
<>	144:ef7eb2e8f9f7	1305	#define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) \|\| \
<>	144:ef7eb2e8f9f7	1306	((__POLARITY__) == UART_DE_POLARITY_LOW))
<>	144:ef7eb2e8f9f7	1307
<>	144:ef7eb2e8f9f7	1308	/**
<>	144:ef7eb2e8f9f7	1309	* @brief Ensure that UART request parameter is valid.
<>	144:ef7eb2e8f9f7	1310	* @param __PARAM__: UART request parameter.
<>	144:ef7eb2e8f9f7	1311	* @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
<>	144:ef7eb2e8f9f7	1312	*/
<>	144:ef7eb2e8f9f7	1313	#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) \|\| \
<>	144:ef7eb2e8f9f7	1314	((__PARAM__) == UART_SENDBREAK_REQUEST) \|\| \
<>	144:ef7eb2e8f9f7	1315	((__PARAM__) == UART_MUTE_MODE_REQUEST) \|\| \
<>	144:ef7eb2e8f9f7	1316	((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) \|\| \
<>	144:ef7eb2e8f9f7	1317	((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))
<>	157:ff67d9f36b67	1318
<>	144:ef7eb2e8f9f7	1319	/**
<>	144:ef7eb2e8f9f7	1320	* @}
<>	144:ef7eb2e8f9f7	1321	*/
<>	144:ef7eb2e8f9f7	1322
<>	157:ff67d9f36b67	1323	/* Include UART HAL Extended module */
<>	144:ef7eb2e8f9f7	1324	#include "stm32f3xx_hal_uart_ex.h"
<>	144:ef7eb2e8f9f7	1325
<>	144:ef7eb2e8f9f7	1326	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1327	/** @addtogroup UART_Exported_Functions UART Exported Functions
<>	144:ef7eb2e8f9f7	1328	* @{
<>	144:ef7eb2e8f9f7	1329	*/
<>	144:ef7eb2e8f9f7	1330
<>	144:ef7eb2e8f9f7	1331	/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	1332	* @{
<>	144:ef7eb2e8f9f7	1333	*/
<>	144:ef7eb2e8f9f7	1334
<>	144:ef7eb2e8f9f7	1335	/* Initialization and de-initialization functions ****************************/
<>	144:ef7eb2e8f9f7	1336	HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1337	HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1338	HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
<>	144:ef7eb2e8f9f7	1339	HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
<>	144:ef7eb2e8f9f7	1340	HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1341	void HAL_UART_MspInit(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1342	void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1343
<>	144:ef7eb2e8f9f7	1344	/**
<>	144:ef7eb2e8f9f7	1345	* @}
<>	144:ef7eb2e8f9f7	1346	*/
<>	144:ef7eb2e8f9f7	1347
<>	144:ef7eb2e8f9f7	1348	/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
<>	144:ef7eb2e8f9f7	1349	* @{
<>	144:ef7eb2e8f9f7	1350	*/
<>	144:ef7eb2e8f9f7	1351
<>	144:ef7eb2e8f9f7	1352	/* IO operation functions *****************************************************/
<>	144:ef7eb2e8f9f7	1353	HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size, uint32_t Timeout);
<>	144:ef7eb2e8f9f7	1354	HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size, uint32_t Timeout);
<>	144:ef7eb2e8f9f7	1355	HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size);
<>	144:ef7eb2e8f9f7	1356	HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size);
<>	144:ef7eb2e8f9f7	1357	HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size);
<>	144:ef7eb2e8f9f7	1358	HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size);
<>	144:ef7eb2e8f9f7	1359	HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1360	HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1361	HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
<>	157:ff67d9f36b67	1362	/* Transfer Abort functions */
<>	157:ff67d9f36b67	1363	HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
<>	157:ff67d9f36b67	1364	HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
<>	157:ff67d9f36b67	1365	HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
<>	157:ff67d9f36b67	1366	HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
<>	157:ff67d9f36b67	1367	HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
<>	157:ff67d9f36b67	1368	HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
<>	157:ff67d9f36b67	1369
<>	144:ef7eb2e8f9f7	1370	void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1371	void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1372	void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1373	void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1374	void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1375	void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
<>	157:ff67d9f36b67	1376	void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart);
<>	157:ff67d9f36b67	1377	void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart);
<>	157:ff67d9f36b67	1378	void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1379
<>	144:ef7eb2e8f9f7	1380	/**
<>	144:ef7eb2e8f9f7	1381	* @}
<>	144:ef7eb2e8f9f7	1382	*/
<>	144:ef7eb2e8f9f7	1383
<>	144:ef7eb2e8f9f7	1384	/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
<>	144:ef7eb2e8f9f7	1385	* @{
<>	144:ef7eb2e8f9f7	1386	*/
<>	144:ef7eb2e8f9f7	1387
<>	144:ef7eb2e8f9f7	1388	/* Peripheral Control functions ************************************************/
<>	144:ef7eb2e8f9f7	1389	HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1390	HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1391	void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1392	HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1393	HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1394	HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1395
<>	144:ef7eb2e8f9f7	1396	/**
<>	144:ef7eb2e8f9f7	1397	* @}
<>	144:ef7eb2e8f9f7	1398	*/
<>	144:ef7eb2e8f9f7	1399
<>	144:ef7eb2e8f9f7	1400	/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions
<>	144:ef7eb2e8f9f7	1401	* @{
<>	144:ef7eb2e8f9f7	1402	*/
<>	144:ef7eb2e8f9f7	1403
<>	144:ef7eb2e8f9f7	1404	/* Peripheral State and Errors functions **************************************************/
<>	144:ef7eb2e8f9f7	1405	HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1406	uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1407
<>	144:ef7eb2e8f9f7	1408	/**
<>	144:ef7eb2e8f9f7	1409	* @}
<>	144:ef7eb2e8f9f7	1410	*/
<>	144:ef7eb2e8f9f7	1411
<>	144:ef7eb2e8f9f7	1412	/**
<>	144:ef7eb2e8f9f7	1413	* @}
<>	144:ef7eb2e8f9f7	1414	*/
<>	144:ef7eb2e8f9f7	1415
<>	144:ef7eb2e8f9f7	1416	/* Private functions -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1417	/** @addtogroup UART_Private_Functions UART Private Functions
<>	144:ef7eb2e8f9f7	1418	* @{
<>	144:ef7eb2e8f9f7	1419	*/
<>	144:ef7eb2e8f9f7	1420	HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1421	void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1422	HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
<>	157:ff67d9f36b67	1423	HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
<>	144:ef7eb2e8f9f7	1424	HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1425	HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1426	HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1427	void UART_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
<>	157:ff67d9f36b67	1428
<>	144:ef7eb2e8f9f7	1429	/**
<>	144:ef7eb2e8f9f7	1430	* @}
<>	144:ef7eb2e8f9f7	1431	*/
<>	144:ef7eb2e8f9f7	1432
<>	144:ef7eb2e8f9f7	1433	/**
<>	144:ef7eb2e8f9f7	1434	* @}
<>	144:ef7eb2e8f9f7	1435	*/
<>	144:ef7eb2e8f9f7	1436
<>	144:ef7eb2e8f9f7	1437	/**
<>	144:ef7eb2e8f9f7	1438	* @}
<>	144:ef7eb2e8f9f7	1439	*/
<>	144:ef7eb2e8f9f7	1440
<>	144:ef7eb2e8f9f7	1441	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	1442	}
<>	144:ef7eb2e8f9f7	1443	#endif
<>	144:ef7eb2e8f9f7	1444
<>	144:ef7eb2e8f9f7	1445	#endif /* __STM32F3xx_HAL_UART_H */
<>	144:ef7eb2e8f9f7	1446
<>	144:ef7eb2e8f9f7	1447	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
<>	144:ef7eb2e8f9f7	1448

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Type:	Library
Created:	02 May 2018
Imports:	22
Forks:	0
Commits:	180
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targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_uart.h@179:97f825502e2a, 2018-05-02 (annotated)

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