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targets/TARGET_RENESAS/TARGET_RZ_A1H/device/system_MBRZA1H.c@179:97f825502e2a, 2018-05-02 (annotated)

Committer:: benkatz
Date:: Wed May 02 18:08:16 2018 +0000
Revision:: 179:97f825502e2a
Parent:: 149:156823d33999

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/************************************************************************//
<>	144:ef7eb2e8f9f7	2	* @file system_MBRZA1H.c
<>	144:ef7eb2e8f9f7	3	* @brief CMSIS Device System Source File for
<>	144:ef7eb2e8f9f7	4	* ARM Cortex-A9 Device Series
<>	144:ef7eb2e8f9f7	5	* @version V1.00
<>	144:ef7eb2e8f9f7	6	* @date 09 January 2015
<>	144:ef7eb2e8f9f7	7	*
<>	144:ef7eb2e8f9f7	8	* @note
<>	144:ef7eb2e8f9f7	9	*
<>	144:ef7eb2e8f9f7	10	******************************************************************************/
<>	144:ef7eb2e8f9f7	11	/* Copyright (c) 2011 - 2015 ARM LIMITED
<>	144:ef7eb2e8f9f7	12
<>	144:ef7eb2e8f9f7	13	All rights reserved.
<>	144:ef7eb2e8f9f7	14	Redistribution and use in source and binary forms, with or without
<>	144:ef7eb2e8f9f7	15	modification, are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	16	- Redistributions of source code must retain the above copyright
<>	144:ef7eb2e8f9f7	17	notice, this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	18	- Redistributions in binary form must reproduce the above copyright
<>	144:ef7eb2e8f9f7	19	notice, this list of conditions and the following disclaimer in the
<>	144:ef7eb2e8f9f7	20	documentation and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	21	- Neither the name of ARM nor the names of its contributors may be used
<>	144:ef7eb2e8f9f7	22	to endorse or promote products derived from this software without
<>	144:ef7eb2e8f9f7	23	specific prior written permission.
<>	144:ef7eb2e8f9f7	24	*
<>	144:ef7eb2e8f9f7	25	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	26	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	27	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<>	144:ef7eb2e8f9f7	28	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<>	144:ef7eb2e8f9f7	29	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<>	144:ef7eb2e8f9f7	30	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<>	144:ef7eb2e8f9f7	31	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<>	144:ef7eb2e8f9f7	32	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<>	144:ef7eb2e8f9f7	33	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<>	144:ef7eb2e8f9f7	34	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<>	144:ef7eb2e8f9f7	35	POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	36	---------------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	37
<>	144:ef7eb2e8f9f7	38
<>	144:ef7eb2e8f9f7	39	#include <stdint.h>
<>	144:ef7eb2e8f9f7	40	#include "MBRZA1H.h"
<>	144:ef7eb2e8f9f7	41	#include "RZ_A1_Init.h"
<>	144:ef7eb2e8f9f7	42
<>	144:ef7eb2e8f9f7	43
<>	144:ef7eb2e8f9f7	44	#if defined(__ARMCC_VERSION)
<>	144:ef7eb2e8f9f7	45	extern void $Super$$main(void);
<>	144:ef7eb2e8f9f7	46	__asm void FPUEnable(void);
<>	144:ef7eb2e8f9f7	47	#else
<>	144:ef7eb2e8f9f7	48	void FPUEnable(void);
<>	144:ef7eb2e8f9f7	49
<>	144:ef7eb2e8f9f7	50	#endif
<>	144:ef7eb2e8f9f7	51
<>	144:ef7eb2e8f9f7	52	#define FRQCR_IFC_MSK (0x0030)
<>	144:ef7eb2e8f9f7	53	#define FRQCR_IFC_SHFT (8)
<>	144:ef7eb2e8f9f7	54	#define FRQCR_IFC_1P1 (0) /* x1/1 */
<>	144:ef7eb2e8f9f7	55	#define FRQCR_IFC_2P3 (1) /* x2/3 */
<>	144:ef7eb2e8f9f7	56	#define FRQCR_IFC_1P3 (3) /* x1/3 */
<>	144:ef7eb2e8f9f7	57
<>	144:ef7eb2e8f9f7	58	uint32_t IRQNestLevel;
<>	144:ef7eb2e8f9f7	59	unsigned char seen_id0_active = 0; // single byte to hold a flag used in the workaround for GIC errata 733075
<>	144:ef7eb2e8f9f7	60	uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK; /!< System Clock Frequency (Core Clock) /
<>	144:ef7eb2e8f9f7	61
<>	144:ef7eb2e8f9f7	62
<>	144:ef7eb2e8f9f7	63	/**
<>	144:ef7eb2e8f9f7	64	* Initialize the cache.
<>	144:ef7eb2e8f9f7	65	*
<>	144:ef7eb2e8f9f7	66	* @param none
<>	144:ef7eb2e8f9f7	67	* @return none
<>	144:ef7eb2e8f9f7	68	*
<>	144:ef7eb2e8f9f7	69	* @brief Initialise caches. Requires PL1, so implemented as an SVC in case threads are USR mode.
<>	144:ef7eb2e8f9f7	70	*/
<>	144:ef7eb2e8f9f7	71	#if defined(__ARMCC_VERSION)
<>	144:ef7eb2e8f9f7	72	#pragma push
<>	144:ef7eb2e8f9f7	73	#pragma arm
<>	144:ef7eb2e8f9f7	74
<>	144:ef7eb2e8f9f7	75	void InitMemorySubsystem(void) {
<>	144:ef7eb2e8f9f7	76
<>	144:ef7eb2e8f9f7	77	/* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before
<>	144:ef7eb2e8f9f7	78	* enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC.
<>	144:ef7eb2e8f9f7	79	* You are not required to invalidate the main TLB, even though it is recommended for safety
<>	144:ef7eb2e8f9f7	80	* reasons. This ensures compatibility with future revisions of the processor. */
<>	144:ef7eb2e8f9f7	81
<>	144:ef7eb2e8f9f7	82	unsigned int l2_id;
<>	144:ef7eb2e8f9f7	83
<>	144:ef7eb2e8f9f7	84	/* Invalidate undefined data */
<>	144:ef7eb2e8f9f7	85	__ca9u_inv_tlb_all();
<>	144:ef7eb2e8f9f7	86	__v7_inv_icache_all();
<>	144:ef7eb2e8f9f7	87	__v7_inv_dcache_all();
<>	144:ef7eb2e8f9f7	88	__v7_inv_btac();
<>	144:ef7eb2e8f9f7	89
<>	144:ef7eb2e8f9f7	90	/* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and
<>	144:ef7eb2e8f9f7	91	* invalidate in order to flush the valid data to the next level cache.
<>	144:ef7eb2e8f9f7	92	*/
<>	144:ef7eb2e8f9f7	93	__enable_mmu();
<>	144:ef7eb2e8f9f7	94
<>	144:ef7eb2e8f9f7	95	/* After MMU is enabled and data has been invalidated, enable caches and BTAC */
<>	144:ef7eb2e8f9f7	96	__enable_caches();
<>	144:ef7eb2e8f9f7	97	__enable_btac();
<>	144:ef7eb2e8f9f7	98
<>	144:ef7eb2e8f9f7	99	/* If present, you may also need to Invalidate and Enable L2 cache here */
<>	144:ef7eb2e8f9f7	100	l2_id = PL310_GetID();
<>	144:ef7eb2e8f9f7	101	if (l2_id)
<>	144:ef7eb2e8f9f7	102	{
<>	144:ef7eb2e8f9f7	103	PL310_InvAllByWay();
<>	144:ef7eb2e8f9f7	104	PL310_Enable();
<>	144:ef7eb2e8f9f7	105	}
<>	144:ef7eb2e8f9f7	106	}
<>	144:ef7eb2e8f9f7	107	#pragma pop
<>	144:ef7eb2e8f9f7	108
<>	144:ef7eb2e8f9f7	109	#elif defined(__GNUC__)
<>	144:ef7eb2e8f9f7	110
<>	144:ef7eb2e8f9f7	111	void InitMemorySubsystem(void) {
<>	144:ef7eb2e8f9f7	112
<>	144:ef7eb2e8f9f7	113	/* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before
<>	144:ef7eb2e8f9f7	114	* enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC.
<>	144:ef7eb2e8f9f7	115	* You are not required to invalidate the main TLB, even though it is recommended for safety
<>	144:ef7eb2e8f9f7	116	* reasons. This ensures compatibility with future revisions of the processor. */
<>	144:ef7eb2e8f9f7	117
<>	144:ef7eb2e8f9f7	118	unsigned int l2_id;
<>	144:ef7eb2e8f9f7	119
<>	144:ef7eb2e8f9f7	120	/* Invalidate undefined data */
<>	144:ef7eb2e8f9f7	121	__ca9u_inv_tlb_all();
<>	144:ef7eb2e8f9f7	122	__v7_inv_icache_all();
<>	144:ef7eb2e8f9f7	123	__v7_inv_dcache_all();
<>	144:ef7eb2e8f9f7	124	__v7_inv_btac();
<>	144:ef7eb2e8f9f7	125
<>	144:ef7eb2e8f9f7	126	/* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and
<>	144:ef7eb2e8f9f7	127	* invalidate in order to flush the valid data to the next level cache.
<>	144:ef7eb2e8f9f7	128	*/
<>	144:ef7eb2e8f9f7	129	__enable_mmu();
<>	144:ef7eb2e8f9f7	130
<>	144:ef7eb2e8f9f7	131	/* After MMU is enabled and data has been invalidated, enable caches and BTAC */
<>	144:ef7eb2e8f9f7	132	__enable_caches();
<>	144:ef7eb2e8f9f7	133	__enable_btac();
<>	144:ef7eb2e8f9f7	134
<>	144:ef7eb2e8f9f7	135	/* If present, you may also need to Invalidate and Enable L2 cache here */
<>	144:ef7eb2e8f9f7	136	l2_id = PL310_GetID();
<>	144:ef7eb2e8f9f7	137	if (l2_id)
<>	144:ef7eb2e8f9f7	138	{
<>	144:ef7eb2e8f9f7	139	PL310_InvAllByWay();
<>	144:ef7eb2e8f9f7	140	PL310_Enable();
<>	144:ef7eb2e8f9f7	141	}
<>	144:ef7eb2e8f9f7	142	}
<>	144:ef7eb2e8f9f7	143	#elif defined ( __ICCARM__ )
<>	144:ef7eb2e8f9f7	144
<>	144:ef7eb2e8f9f7	145	void InitMemorySubsystem(void) {
<>	144:ef7eb2e8f9f7	146
<>	144:ef7eb2e8f9f7	147	/* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before
<>	144:ef7eb2e8f9f7	148	* enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC.
<>	144:ef7eb2e8f9f7	149	* You are not required to invalidate the main TLB, even though it is recommended for safety
<>	144:ef7eb2e8f9f7	150	* reasons. This ensures compatibility with future revisions of the processor. */
<>	144:ef7eb2e8f9f7	151
<>	144:ef7eb2e8f9f7	152	unsigned int l2_id;
<>	144:ef7eb2e8f9f7	153
<>	144:ef7eb2e8f9f7	154	/* Invalidate undefined data */
<>	144:ef7eb2e8f9f7	155	__ca9u_inv_tlb_all();
<>	144:ef7eb2e8f9f7	156	__v7_inv_icache_all();
<>	144:ef7eb2e8f9f7	157	__v7_inv_dcache_all();
<>	144:ef7eb2e8f9f7	158	__v7_inv_btac();
<>	144:ef7eb2e8f9f7	159
<>	144:ef7eb2e8f9f7	160	/* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and
<>	144:ef7eb2e8f9f7	161	* invalidate in order to flush the valid data to the next level cache.
<>	144:ef7eb2e8f9f7	162	*/
<>	144:ef7eb2e8f9f7	163	__enable_mmu();
<>	144:ef7eb2e8f9f7	164
<>	144:ef7eb2e8f9f7	165	/* After MMU is enabled and data has been invalidated, enable caches and BTAC */
<>	144:ef7eb2e8f9f7	166	__enable_caches();
<>	144:ef7eb2e8f9f7	167	__enable_btac();
<>	144:ef7eb2e8f9f7	168
<>	144:ef7eb2e8f9f7	169	/* If present, you may also need to Invalidate and Enable L2 cache here */
<>	144:ef7eb2e8f9f7	170	l2_id = PL310_GetID();
<>	144:ef7eb2e8f9f7	171	if (l2_id)
<>	144:ef7eb2e8f9f7	172	{
<>	144:ef7eb2e8f9f7	173	PL310_InvAllByWay();
<>	144:ef7eb2e8f9f7	174	PL310_Enable();
<>	144:ef7eb2e8f9f7	175	}
<>	144:ef7eb2e8f9f7	176	}
<>	144:ef7eb2e8f9f7	177	#else
<>	144:ef7eb2e8f9f7	178
<>	144:ef7eb2e8f9f7	179	#endif
<>	144:ef7eb2e8f9f7	180
<>	144:ef7eb2e8f9f7	181
<>	144:ef7eb2e8f9f7	182	IRQHandler IRQTable[Renesas_RZ_A1_IRQ_MAX+1];
<>	144:ef7eb2e8f9f7	183
<>	144:ef7eb2e8f9f7	184	uint32_t IRQCount = sizeof IRQTable / 4;
<>	144:ef7eb2e8f9f7	185
<>	144:ef7eb2e8f9f7	186	uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler)
<>	144:ef7eb2e8f9f7	187	{
<>	144:ef7eb2e8f9f7	188	if (irq < IRQCount) {
<>	144:ef7eb2e8f9f7	189	IRQTable[irq] = handler;
<>	144:ef7eb2e8f9f7	190	return 0;
<>	144:ef7eb2e8f9f7	191	}
<>	144:ef7eb2e8f9f7	192	else {
<>	144:ef7eb2e8f9f7	193	return 1;
<>	144:ef7eb2e8f9f7	194	}
<>	144:ef7eb2e8f9f7	195	}
<>	144:ef7eb2e8f9f7	196
<>	144:ef7eb2e8f9f7	197	uint32_t InterruptHandlerUnregister (IRQn_Type irq)
<>	144:ef7eb2e8f9f7	198	{
<>	144:ef7eb2e8f9f7	199	if (irq < IRQCount) {
<>	144:ef7eb2e8f9f7	200	IRQTable[irq] = 0;
<>	144:ef7eb2e8f9f7	201	return 0;
<>	144:ef7eb2e8f9f7	202	}
<>	144:ef7eb2e8f9f7	203	else {
<>	144:ef7eb2e8f9f7	204	return 1;
<>	144:ef7eb2e8f9f7	205	}
<>	144:ef7eb2e8f9f7	206	}
<>	144:ef7eb2e8f9f7	207
<>	144:ef7eb2e8f9f7	208	/**
<>	144:ef7eb2e8f9f7	209	* Update SystemCoreClock variable
<>	144:ef7eb2e8f9f7	210	*
<>	144:ef7eb2e8f9f7	211	* @param none
<>	144:ef7eb2e8f9f7	212	* @return none
<>	144:ef7eb2e8f9f7	213	*
<>	144:ef7eb2e8f9f7	214	* @brief Updates the SystemCoreClock with current core Clock.
<>	144:ef7eb2e8f9f7	215	*/
<>	144:ef7eb2e8f9f7	216	void SystemCoreClockUpdate (void)
<>	144:ef7eb2e8f9f7	217	{
<>	144:ef7eb2e8f9f7	218	uint32_t frqcr_ifc = ((uint32_t)CPG.FRQCR & (uint32_t)FRQCR_IFC_MSK) >> FRQCR_IFC_SHFT;
<>	144:ef7eb2e8f9f7	219
<>	144:ef7eb2e8f9f7	220	switch (frqcr_ifc) {
<>	144:ef7eb2e8f9f7	221	case FRQCR_IFC_1P1:
<>	144:ef7eb2e8f9f7	222	SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK;
<>	144:ef7eb2e8f9f7	223	break;
<>	144:ef7eb2e8f9f7	224	case FRQCR_IFC_2P3:
<>	144:ef7eb2e8f9f7	225	SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK * 2 / 3;
<>	144:ef7eb2e8f9f7	226	break;
<>	144:ef7eb2e8f9f7	227	case FRQCR_IFC_1P3:
<>	144:ef7eb2e8f9f7	228	SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK / 3;
<>	144:ef7eb2e8f9f7	229	break;
<>	144:ef7eb2e8f9f7	230	default:
<>	144:ef7eb2e8f9f7	231	/* do nothing */
<>	144:ef7eb2e8f9f7	232	break;
<>	144:ef7eb2e8f9f7	233	}
<>	144:ef7eb2e8f9f7	234	}
<>	144:ef7eb2e8f9f7	235
<>	144:ef7eb2e8f9f7	236
<>	144:ef7eb2e8f9f7	237	/**
<>	144:ef7eb2e8f9f7	238	* Initialize the system
<>	144:ef7eb2e8f9f7	239	*
<>	144:ef7eb2e8f9f7	240	* @param none
<>	144:ef7eb2e8f9f7	241	* @return none
<>	144:ef7eb2e8f9f7	242	*
<>	144:ef7eb2e8f9f7	243	* @brief Setup the microcontroller system.
<>	144:ef7eb2e8f9f7	244	* Initialize the System.
<>	144:ef7eb2e8f9f7	245	*/
<>	144:ef7eb2e8f9f7	246	void SystemInit (void)
<>	144:ef7eb2e8f9f7	247	{
<>	144:ef7eb2e8f9f7	248	IRQNestLevel = 0;
<>	144:ef7eb2e8f9f7	249	/* do not use global variables because this function is called before
<>	144:ef7eb2e8f9f7	250	reaching pre-main. RW section maybe overwritten afterwards. */
<>	144:ef7eb2e8f9f7	251	RZ_A1_InitClock();
<>	144:ef7eb2e8f9f7	252	RZ_A1_InitBus();
<>	144:ef7eb2e8f9f7	253
<>	144:ef7eb2e8f9f7	254	//Configure GIC ICDICFR GIC_SetICDICFR()
<>	144:ef7eb2e8f9f7	255	GIC_Enable();
<>	144:ef7eb2e8f9f7	256	__enable_irq();
<>	144:ef7eb2e8f9f7	257
<>	144:ef7eb2e8f9f7	258	}
<>	144:ef7eb2e8f9f7	259
<>	144:ef7eb2e8f9f7	260
<>	144:ef7eb2e8f9f7	261	//Fault Status Register (IFSR/DFSR) definitions
<>	144:ef7eb2e8f9f7	262	#define FSR_ALIGNMENT_FAULT 0x01 //DFSR only. Fault on first lookup
<>	144:ef7eb2e8f9f7	263	#define FSR_INSTRUCTION_CACHE_MAINTENANCE 0x04 //DFSR only - async/external
<>	144:ef7eb2e8f9f7	264	#define FSR_SYNC_EXT_TTB_WALK_FIRST 0x0c //sync/external
<>	144:ef7eb2e8f9f7	265	#define FSR_SYNC_EXT_TTB_WALK_SECOND 0x0e //sync/external
<>	144:ef7eb2e8f9f7	266	#define FSR_SYNC_PARITY_TTB_WALK_FIRST 0x1c //sync/external
<>	144:ef7eb2e8f9f7	267	#define FSR_SYNC_PARITY_TTB_WALK_SECOND 0x1e //sync/external
<>	144:ef7eb2e8f9f7	268	#define FSR_TRANSLATION_FAULT_FIRST 0x05 //MMU Fault - internal
<>	144:ef7eb2e8f9f7	269	#define FSR_TRANSLATION_FAULT_SECOND 0x07 //MMU Fault - internal
<>	144:ef7eb2e8f9f7	270	#define FSR_ACCESS_FLAG_FAULT_FIRST 0x03 //MMU Fault - internal
<>	144:ef7eb2e8f9f7	271	#define FSR_ACCESS_FLAG_FAULT_SECOND 0x06 //MMU Fault - internal
<>	144:ef7eb2e8f9f7	272	#define FSR_DOMAIN_FAULT_FIRST 0x09 //MMU Fault - internal
<>	144:ef7eb2e8f9f7	273	#define FSR_DOMAIN_FAULT_SECOND 0x0b //MMU Fault - internal
<>	144:ef7eb2e8f9f7	274	#define FSR_PERMISION_FAULT_FIRST 0x0f //MMU Fault - internal
<>	144:ef7eb2e8f9f7	275	#define FSR_PERMISION_FAULT_SECOND 0x0d //MMU Fault - internal
<>	144:ef7eb2e8f9f7	276	#define FSR_DEBUG_EVENT 0x02 //internal
<>	144:ef7eb2e8f9f7	277	#define FSR_SYNC_EXT_ABORT 0x08 //sync/external
<>	144:ef7eb2e8f9f7	278	#define FSR_TLB_CONFLICT_ABORT 0x10 //sync/external
<>	144:ef7eb2e8f9f7	279	#define FSR_LOCKDOWN 0x14 //internal
<>	144:ef7eb2e8f9f7	280	#define FSR_COPROCESSOR_ABORT 0x1a //internal
<>	144:ef7eb2e8f9f7	281	#define FSR_SYNC_PARITY_ERROR 0x19 //sync/external
<>	144:ef7eb2e8f9f7	282	#define FSR_ASYNC_EXTERNAL_ABORT 0x16 //DFSR only - async/external
<>	144:ef7eb2e8f9f7	283	#define FSR_ASYNC_PARITY_ERROR 0x18 //DFSR only - async/external
<>	144:ef7eb2e8f9f7	284
<>	144:ef7eb2e8f9f7	285	void CDAbtHandler(uint32_t DFSR, uint32_t DFAR, uint32_t LR) {
<>	144:ef7eb2e8f9f7	286	uint32_t FS = (DFSR & (1 << 10)) >> 6 \| (DFSR & 0x0f); //Store Fault Status
<>	144:ef7eb2e8f9f7	287
<>	144:ef7eb2e8f9f7	288	switch(FS) {
<>	144:ef7eb2e8f9f7	289	//Synchronous parity errors - retry
<>	144:ef7eb2e8f9f7	290	case FSR_SYNC_PARITY_ERROR:
<>	144:ef7eb2e8f9f7	291	case FSR_SYNC_PARITY_TTB_WALK_FIRST:
<>	144:ef7eb2e8f9f7	292	case FSR_SYNC_PARITY_TTB_WALK_SECOND:
<>	144:ef7eb2e8f9f7	293	return;
<>	144:ef7eb2e8f9f7	294
<>	144:ef7eb2e8f9f7	295	//Your code here. Value in DFAR is invalid for some fault statuses.
<>	144:ef7eb2e8f9f7	296	case FSR_ALIGNMENT_FAULT:
<>	144:ef7eb2e8f9f7	297	case FSR_INSTRUCTION_CACHE_MAINTENANCE:
<>	144:ef7eb2e8f9f7	298	case FSR_SYNC_EXT_TTB_WALK_FIRST:
<>	144:ef7eb2e8f9f7	299	case FSR_SYNC_EXT_TTB_WALK_SECOND:
<>	144:ef7eb2e8f9f7	300	case FSR_TRANSLATION_FAULT_FIRST:
<>	144:ef7eb2e8f9f7	301	case FSR_TRANSLATION_FAULT_SECOND:
<>	144:ef7eb2e8f9f7	302	case FSR_ACCESS_FLAG_FAULT_FIRST:
<>	144:ef7eb2e8f9f7	303	case FSR_ACCESS_FLAG_FAULT_SECOND:
<>	144:ef7eb2e8f9f7	304	case FSR_DOMAIN_FAULT_FIRST:
<>	144:ef7eb2e8f9f7	305	case FSR_DOMAIN_FAULT_SECOND:
<>	144:ef7eb2e8f9f7	306	case FSR_PERMISION_FAULT_FIRST:
<>	144:ef7eb2e8f9f7	307	case FSR_PERMISION_FAULT_SECOND:
<>	144:ef7eb2e8f9f7	308	case FSR_DEBUG_EVENT:
<>	144:ef7eb2e8f9f7	309	case FSR_SYNC_EXT_ABORT:
<>	144:ef7eb2e8f9f7	310	case FSR_TLB_CONFLICT_ABORT:
<>	144:ef7eb2e8f9f7	311	case FSR_LOCKDOWN:
<>	144:ef7eb2e8f9f7	312	case FSR_COPROCESSOR_ABORT:
<>	144:ef7eb2e8f9f7	313	case FSR_ASYNC_EXTERNAL_ABORT: //DFAR invalid
<>	144:ef7eb2e8f9f7	314	case FSR_ASYNC_PARITY_ERROR: //DFAR invalid
<>	144:ef7eb2e8f9f7	315	default:
<>	144:ef7eb2e8f9f7	316	while(1);
<>	144:ef7eb2e8f9f7	317	}
<>	144:ef7eb2e8f9f7	318	}
<>	144:ef7eb2e8f9f7	319
<>	144:ef7eb2e8f9f7	320	void CPAbtHandler(uint32_t IFSR, uint32_t IFAR, uint32_t LR) {
<>	144:ef7eb2e8f9f7	321	uint32_t FS = (IFSR & (1 << 10)) >> 6 \| (IFSR & 0x0f); //Store Fault Status
<>	144:ef7eb2e8f9f7	322
<>	144:ef7eb2e8f9f7	323	switch(FS) {
<>	144:ef7eb2e8f9f7	324	//Synchronous parity errors - retry
<>	144:ef7eb2e8f9f7	325	case FSR_SYNC_PARITY_ERROR:
<>	144:ef7eb2e8f9f7	326	case FSR_SYNC_PARITY_TTB_WALK_FIRST:
<>	144:ef7eb2e8f9f7	327	case FSR_SYNC_PARITY_TTB_WALK_SECOND:
<>	144:ef7eb2e8f9f7	328	return;
<>	144:ef7eb2e8f9f7	329
<>	144:ef7eb2e8f9f7	330	//Your code here. Value in IFAR is invalid for some fault statuses.
<>	144:ef7eb2e8f9f7	331	case FSR_SYNC_EXT_TTB_WALK_FIRST:
<>	144:ef7eb2e8f9f7	332	case FSR_SYNC_EXT_TTB_WALK_SECOND:
<>	144:ef7eb2e8f9f7	333	case FSR_TRANSLATION_FAULT_FIRST:
<>	144:ef7eb2e8f9f7	334	case FSR_TRANSLATION_FAULT_SECOND:
<>	144:ef7eb2e8f9f7	335	case FSR_ACCESS_FLAG_FAULT_FIRST:
<>	144:ef7eb2e8f9f7	336	case FSR_ACCESS_FLAG_FAULT_SECOND:
<>	144:ef7eb2e8f9f7	337	case FSR_DOMAIN_FAULT_FIRST:
<>	144:ef7eb2e8f9f7	338	case FSR_DOMAIN_FAULT_SECOND:
<>	144:ef7eb2e8f9f7	339	case FSR_PERMISION_FAULT_FIRST:
<>	144:ef7eb2e8f9f7	340	case FSR_PERMISION_FAULT_SECOND:
<>	144:ef7eb2e8f9f7	341	case FSR_DEBUG_EVENT: //IFAR invalid
<>	144:ef7eb2e8f9f7	342	case FSR_SYNC_EXT_ABORT:
<>	144:ef7eb2e8f9f7	343	case FSR_TLB_CONFLICT_ABORT:
<>	144:ef7eb2e8f9f7	344	case FSR_LOCKDOWN:
<>	144:ef7eb2e8f9f7	345	case FSR_COPROCESSOR_ABORT:
<>	144:ef7eb2e8f9f7	346	default:
<>	144:ef7eb2e8f9f7	347	while(1);
<>	144:ef7eb2e8f9f7	348	}
<>	144:ef7eb2e8f9f7	349	}
<>	144:ef7eb2e8f9f7	350
<>	144:ef7eb2e8f9f7	351	//returns amount to decrement lr by
<>	144:ef7eb2e8f9f7	352	//this will be 0 when we have emulated the instruction and want to execute the next instruction
<>	144:ef7eb2e8f9f7	353	//this will be 2 when we have performed some maintenance and want to retry the instruction in Thumb (state == 2)
<>	144:ef7eb2e8f9f7	354	//this will be 4 when we have performed some maintenance and want to retry the instruction in ARM (state == 4)
<>	144:ef7eb2e8f9f7	355	uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) {
<>	144:ef7eb2e8f9f7	356	const unsigned int THUMB = 2;
<>	144:ef7eb2e8f9f7	357	const unsigned int ARM = 4;
<>	144:ef7eb2e8f9f7	358	//Lazy VFP/NEON initialisation and switching
<>	144:ef7eb2e8f9f7	359
<>	144:ef7eb2e8f9f7	360	// (ARM ARM section A7.5) VFP data processing instruction?
<>	144:ef7eb2e8f9f7	361	// (ARM ARM section A7.6) VFP/NEON register load/store instruction?
<>	144:ef7eb2e8f9f7	362	// (ARM ARM section A7.8) VFP/NEON register data transfer instruction?
<>	144:ef7eb2e8f9f7	363	// (ARM ARM section A7.9) VFP/NEON 64-bit register data transfer instruction?
<>	144:ef7eb2e8f9f7	364	if ((state == ARM && ((opcode & 0x0C000000) >> 26 == 0x03)) \|\|
<>	144:ef7eb2e8f9f7	365	(state == THUMB && ((opcode & 0xEC000000) >> 26 == 0x3B))) {
<>	144:ef7eb2e8f9f7	366	if (((opcode & 0x00000E00) >> 9) == 5) {
<>	144:ef7eb2e8f9f7	367	FPUEnable();
<>	144:ef7eb2e8f9f7	368	return state;
<>	144:ef7eb2e8f9f7	369	}
<>	144:ef7eb2e8f9f7	370	}
<>	144:ef7eb2e8f9f7	371
<>	144:ef7eb2e8f9f7	372	// (ARM ARM section A7.4) NEON data processing instruction?
<>	144:ef7eb2e8f9f7	373	if ((state == ARM && ((opcode & 0xFE000000) >> 24 == 0xF2)) \|\|
<>	144:ef7eb2e8f9f7	374	(state == THUMB && ((opcode & 0xEF000000) >> 24 == 0xEF)) \|\|
<>	144:ef7eb2e8f9f7	375	// (ARM ARM section A7.7) NEON load/store instruction?
<>	144:ef7eb2e8f9f7	376	(state == ARM && ((opcode >> 24) == 0xF4)) \|\|
<>	144:ef7eb2e8f9f7	377	(state == THUMB && ((opcode >> 24) == 0xF9))) {
<>	144:ef7eb2e8f9f7	378	FPUEnable();
<>	144:ef7eb2e8f9f7	379	return state;
<>	144:ef7eb2e8f9f7	380	}
<>	144:ef7eb2e8f9f7	381
<>	144:ef7eb2e8f9f7	382	//Add code here for other Undef cases
<>	144:ef7eb2e8f9f7	383	while(1);
<>	144:ef7eb2e8f9f7	384	}
<>	144:ef7eb2e8f9f7	385
<>	144:ef7eb2e8f9f7	386	#if defined(__ARMCC_VERSION)
<>	144:ef7eb2e8f9f7	387	#pragma push
<>	144:ef7eb2e8f9f7	388	#pragma arm
<>	144:ef7eb2e8f9f7	389	//Critical section, called from undef handler, so systick is disabled
<>	144:ef7eb2e8f9f7	390	__asm void FPUEnable(void) {
<>	144:ef7eb2e8f9f7	391	ARM
<>	144:ef7eb2e8f9f7	392
<>	144:ef7eb2e8f9f7	393	//Permit access to VFP/NEON, registers by modifying CPACR
<>	144:ef7eb2e8f9f7	394	MRC p15,0,R1,c1,c0,2
<>	144:ef7eb2e8f9f7	395	ORR R1,R1,#0x00F00000
<>	144:ef7eb2e8f9f7	396	MCR p15,0,R1,c1,c0,2
<>	144:ef7eb2e8f9f7	397
<>	144:ef7eb2e8f9f7	398	//Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
<>	144:ef7eb2e8f9f7	399	ISB
<>	144:ef7eb2e8f9f7	400
<>	144:ef7eb2e8f9f7	401	//Enable VFP/NEON
<>	144:ef7eb2e8f9f7	402	VMRS R1,FPEXC
<>	144:ef7eb2e8f9f7	403	ORR R1,R1,#0x40000000
<>	144:ef7eb2e8f9f7	404	VMSR FPEXC,R1
<>	144:ef7eb2e8f9f7	405
<>	144:ef7eb2e8f9f7	406	//Initialise VFP/NEON registers to 0
<>	144:ef7eb2e8f9f7	407	MOV R2,#0
<>	144:ef7eb2e8f9f7	408	//Initialise D16 registers to 0
<>	144:ef7eb2e8f9f7	409	VMOV D0, R2,R2
<>	144:ef7eb2e8f9f7	410	VMOV D1, R2,R2
<>	144:ef7eb2e8f9f7	411	VMOV D2, R2,R2
<>	144:ef7eb2e8f9f7	412	VMOV D3, R2,R2
<>	144:ef7eb2e8f9f7	413	VMOV D4, R2,R2
<>	144:ef7eb2e8f9f7	414	VMOV D5, R2,R2
<>	144:ef7eb2e8f9f7	415	VMOV D6, R2,R2
<>	144:ef7eb2e8f9f7	416	VMOV D7, R2,R2
<>	144:ef7eb2e8f9f7	417	VMOV D8, R2,R2
<>	144:ef7eb2e8f9f7	418	VMOV D9, R2,R2
<>	144:ef7eb2e8f9f7	419	VMOV D10,R2,R2
<>	144:ef7eb2e8f9f7	420	VMOV D11,R2,R2
<>	144:ef7eb2e8f9f7	421	VMOV D12,R2,R2
<>	144:ef7eb2e8f9f7	422	VMOV D13,R2,R2
<>	144:ef7eb2e8f9f7	423	VMOV D14,R2,R2
<>	144:ef7eb2e8f9f7	424	VMOV D15,R2,R2
<>	144:ef7eb2e8f9f7	425	//Initialise D32 registers to 0
<>	144:ef7eb2e8f9f7	426	VMOV D16,R2,R2
<>	144:ef7eb2e8f9f7	427	VMOV D17,R2,R2
<>	144:ef7eb2e8f9f7	428	VMOV D18,R2,R2
<>	144:ef7eb2e8f9f7	429	VMOV D19,R2,R2
<>	144:ef7eb2e8f9f7	430	VMOV D20,R2,R2
<>	144:ef7eb2e8f9f7	431	VMOV D21,R2,R2
<>	144:ef7eb2e8f9f7	432	VMOV D22,R2,R2
<>	144:ef7eb2e8f9f7	433	VMOV D23,R2,R2
<>	144:ef7eb2e8f9f7	434	VMOV D24,R2,R2
<>	144:ef7eb2e8f9f7	435	VMOV D25,R2,R2
<>	144:ef7eb2e8f9f7	436	VMOV D26,R2,R2
<>	144:ef7eb2e8f9f7	437	VMOV D27,R2,R2
<>	144:ef7eb2e8f9f7	438	VMOV D28,R2,R2
<>	144:ef7eb2e8f9f7	439	VMOV D29,R2,R2
<>	144:ef7eb2e8f9f7	440	VMOV D30,R2,R2
<>	144:ef7eb2e8f9f7	441	VMOV D31,R2,R2
<>	144:ef7eb2e8f9f7	442	//Initialise FPSCR to a known state
<>	144:ef7eb2e8f9f7	443	VMRS R2,FPSCR
<>	144:ef7eb2e8f9f7	444	LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
<>	144:ef7eb2e8f9f7	445	AND R2,R2,R3
<>	144:ef7eb2e8f9f7	446	VMSR FPSCR,R2
<>	144:ef7eb2e8f9f7	447
<>	144:ef7eb2e8f9f7	448	BX LR
<>	144:ef7eb2e8f9f7	449	}
<>	144:ef7eb2e8f9f7	450	#pragma pop
<>	144:ef7eb2e8f9f7	451
<>	144:ef7eb2e8f9f7	452	#elif defined(__GNUC__)
<>	144:ef7eb2e8f9f7	453	void FPUEnable(void) {
<>	144:ef7eb2e8f9f7	454	__asm__ (
<>	144:ef7eb2e8f9f7	455	".ARM;"
<>	144:ef7eb2e8f9f7	456
<>	144:ef7eb2e8f9f7	457	//Permit access to VFP/NEON, registers by modifying CPACR
<>	144:ef7eb2e8f9f7	458	"MRC p15,0,R1,c1,c0,2;"
<>	144:ef7eb2e8f9f7	459	"ORR R1,R1,#0x00F00000;"
<>	144:ef7eb2e8f9f7	460	"MCR p15,0,R1,c1,c0,2;"
<>	144:ef7eb2e8f9f7	461
<>	144:ef7eb2e8f9f7	462	//Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
<>	144:ef7eb2e8f9f7	463	"ISB;"
<>	144:ef7eb2e8f9f7	464
<>	144:ef7eb2e8f9f7	465	//Enable VFP/NEON
<>	144:ef7eb2e8f9f7	466	"VMRS R1,FPEXC;"
<>	144:ef7eb2e8f9f7	467	"ORR R1,R1,#0x40000000;"
<>	144:ef7eb2e8f9f7	468	"VMSR FPEXC,R1;"
<>	144:ef7eb2e8f9f7	469
<>	144:ef7eb2e8f9f7	470	//Initialise VFP/NEON registers to 0
<>	144:ef7eb2e8f9f7	471	"MOV R2,#0;"
<>	144:ef7eb2e8f9f7	472	//Initialise D16 registers to 0
<>	144:ef7eb2e8f9f7	473	"VMOV D0, R2,R2;"
<>	144:ef7eb2e8f9f7	474	"VMOV D1, R2,R2;"
<>	144:ef7eb2e8f9f7	475	"VMOV D2, R2,R2;"
<>	144:ef7eb2e8f9f7	476	"VMOV D3, R2,R2;"
<>	144:ef7eb2e8f9f7	477	"VMOV D4, R2,R2;"
<>	144:ef7eb2e8f9f7	478	"VMOV D5, R2,R2;"
<>	144:ef7eb2e8f9f7	479	"VMOV D6, R2,R2;"
<>	144:ef7eb2e8f9f7	480	"VMOV D7, R2,R2;"
<>	144:ef7eb2e8f9f7	481	"VMOV D8, R2,R2;"
<>	144:ef7eb2e8f9f7	482	"VMOV D9, R2,R2;"
<>	144:ef7eb2e8f9f7	483	"VMOV D10,R2,R2;"
<>	144:ef7eb2e8f9f7	484	"VMOV D11,R2,R2;"
<>	144:ef7eb2e8f9f7	485	"VMOV D12,R2,R2;"
<>	144:ef7eb2e8f9f7	486	"VMOV D13,R2,R2;"
<>	144:ef7eb2e8f9f7	487	"VMOV D14,R2,R2;"
<>	144:ef7eb2e8f9f7	488	"VMOV D15,R2,R2;"
<>	144:ef7eb2e8f9f7	489	//Initialise D32 registers to 0
<>	144:ef7eb2e8f9f7	490	"VMOV D16,R2,R2;"
<>	144:ef7eb2e8f9f7	491	"VMOV D17,R2,R2;"
<>	144:ef7eb2e8f9f7	492	"VMOV D18,R2,R2;"
<>	144:ef7eb2e8f9f7	493	"VMOV D19,R2,R2;"
<>	144:ef7eb2e8f9f7	494	"VMOV D20,R2,R2;"
<>	144:ef7eb2e8f9f7	495	"VMOV D21,R2,R2;"
<>	144:ef7eb2e8f9f7	496	"VMOV D22,R2,R2;"
<>	144:ef7eb2e8f9f7	497	"VMOV D23,R2,R2;"
<>	144:ef7eb2e8f9f7	498	"VMOV D24,R2,R2;"
<>	144:ef7eb2e8f9f7	499	"VMOV D25,R2,R2;"
<>	144:ef7eb2e8f9f7	500	"VMOV D26,R2,R2;"
<>	144:ef7eb2e8f9f7	501	"VMOV D27,R2,R2;"
<>	144:ef7eb2e8f9f7	502	"VMOV D28,R2,R2;"
<>	144:ef7eb2e8f9f7	503	"VMOV D29,R2,R2;"
<>	144:ef7eb2e8f9f7	504	"VMOV D30,R2,R2;"
<>	144:ef7eb2e8f9f7	505	"VMOV D31,R2,R2;"
<>	144:ef7eb2e8f9f7	506
<>	144:ef7eb2e8f9f7	507	//Initialise FPSCR to a known state
<>	144:ef7eb2e8f9f7	508	"VMRS R2,FPSCR;"
<>	144:ef7eb2e8f9f7	509	"LDR R3,=0x00086060;" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
<>	144:ef7eb2e8f9f7	510	"AND R2,R2,R3;"
<>	144:ef7eb2e8f9f7	511	"VMSR FPSCR,R2;"
<>	144:ef7eb2e8f9f7	512
<>	144:ef7eb2e8f9f7	513	//"BX LR;"
<>	144:ef7eb2e8f9f7	514	:
<>	144:ef7eb2e8f9f7	515	:
<>	144:ef7eb2e8f9f7	516	:"r1", "r2", "r3");
<>	144:ef7eb2e8f9f7	517	return;
<>	144:ef7eb2e8f9f7	518	}
<>	144:ef7eb2e8f9f7	519	#else
<>	144:ef7eb2e8f9f7	520	#endif
<>	144:ef7eb2e8f9f7	521

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Type:	Library
Created:	02 May 2018
Imports:	22
Forks:	0
Commits:	180
Dependents:	11
Dependencies:	0
Followers:	9

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targets/TARGET_RENESAS/TARGET_RZ_A1H/device/system_MBRZA1H.c@179:97f825502e2a, 2018-05-02 (annotated)

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