Ben Katz
/
mbed-dev_spine
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Fork of
mbed-dev-f303
by 
Ben Katz
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/drivers/fsl_cmp.c@179:97f825502e2a, 2018-05-02 (annotated)
- Committer:
- benkatz
- Date:
- Wed May 02 18:08:16 2018 +0000
- Revision:
- 179:97f825502e2a
- Parent:
- 154:37f96f9d4de2
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| <> | 154:37f96f9d4de2 | 1 | /* |
| <> | 154:37f96f9d4de2 | 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. |
| <> | 154:37f96f9d4de2 | 3 | * All rights reserved. |
| <> | 154:37f96f9d4de2 | 4 | * |
| <> | 154:37f96f9d4de2 | 5 | * Redistribution and use in source and binary forms, with or without modification, |
| <> | 154:37f96f9d4de2 | 6 | * are permitted provided that the following conditions are met: |
| <> | 154:37f96f9d4de2 | 7 | * |
| <> | 154:37f96f9d4de2 | 8 | * o Redistributions of source code must retain the above copyright notice, this list |
| <> | 154:37f96f9d4de2 | 9 | * of conditions and the following disclaimer. |
| <> | 154:37f96f9d4de2 | 10 | * |
| <> | 154:37f96f9d4de2 | 11 | * o Redistributions in binary form must reproduce the above copyright notice, this |
| <> | 154:37f96f9d4de2 | 12 | * list of conditions and the following disclaimer in the documentation and/or |
| <> | 154:37f96f9d4de2 | 13 | * other materials provided with the distribution. |
| <> | 154:37f96f9d4de2 | 14 | * |
| <> | 154:37f96f9d4de2 | 15 | * o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
| <> | 154:37f96f9d4de2 | 16 | * contributors may be used to endorse or promote products derived from this |
| <> | 154:37f96f9d4de2 | 17 | * software without specific prior written permission. |
| <> | 154:37f96f9d4de2 | 18 | * |
| <> | 154:37f96f9d4de2 | 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| <> | 154:37f96f9d4de2 | 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| <> | 154:37f96f9d4de2 | 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| <> | 154:37f96f9d4de2 | 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
| <> | 154:37f96f9d4de2 | 23 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| <> | 154:37f96f9d4de2 | 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| <> | 154:37f96f9d4de2 | 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| <> | 154:37f96f9d4de2 | 26 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| <> | 154:37f96f9d4de2 | 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| <> | 154:37f96f9d4de2 | 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| <> | 154:37f96f9d4de2 | 29 | */ |
| <> | 154:37f96f9d4de2 | 30 | |
| <> | 154:37f96f9d4de2 | 31 | #include "fsl_cmp.h" |
| <> | 154:37f96f9d4de2 | 32 | |
| <> | 154:37f96f9d4de2 | 33 | /******************************************************************************* |
| <> | 154:37f96f9d4de2 | 34 | * Prototypes |
| <> | 154:37f96f9d4de2 | 35 | ******************************************************************************/ |
| <> | 154:37f96f9d4de2 | 36 | /*! |
| <> | 154:37f96f9d4de2 | 37 | * @brief Get instance number for CMP module. |
| <> | 154:37f96f9d4de2 | 38 | * |
| <> | 154:37f96f9d4de2 | 39 | * @param base CMP peripheral base address |
| <> | 154:37f96f9d4de2 | 40 | */ |
| <> | 154:37f96f9d4de2 | 41 | static uint32_t CMP_GetInstance(CMP_Type *base); |
| <> | 154:37f96f9d4de2 | 42 | |
| <> | 154:37f96f9d4de2 | 43 | /******************************************************************************* |
| <> | 154:37f96f9d4de2 | 44 | * Variables |
| <> | 154:37f96f9d4de2 | 45 | ******************************************************************************/ |
| <> | 154:37f96f9d4de2 | 46 | /*! @brief Pointers to CMP bases for each instance. */ |
| <> | 154:37f96f9d4de2 | 47 | static CMP_Type *const s_cmpBases[] = CMP_BASE_PTRS; |
| <> | 154:37f96f9d4de2 | 48 | /*! @brief Pointers to CMP clocks for each instance. */ |
| <> | 154:37f96f9d4de2 | 49 | const clock_ip_name_t s_cmpClocks[] = CMP_CLOCKS; |
| <> | 154:37f96f9d4de2 | 50 | |
| <> | 154:37f96f9d4de2 | 51 | /******************************************************************************* |
| <> | 154:37f96f9d4de2 | 52 | * Codes |
| <> | 154:37f96f9d4de2 | 53 | ******************************************************************************/ |
| <> | 154:37f96f9d4de2 | 54 | static uint32_t CMP_GetInstance(CMP_Type *base) |
| <> | 154:37f96f9d4de2 | 55 | { |
| <> | 154:37f96f9d4de2 | 56 | uint32_t instance; |
| <> | 154:37f96f9d4de2 | 57 | |
| <> | 154:37f96f9d4de2 | 58 | /* Find the instance index from base address mappings. */ |
| <> | 154:37f96f9d4de2 | 59 | for (instance = 0; instance < FSL_FEATURE_SOC_CMP_COUNT; instance++) |
| <> | 154:37f96f9d4de2 | 60 | { |
| <> | 154:37f96f9d4de2 | 61 | if (s_cmpBases[instance] == base) |
| <> | 154:37f96f9d4de2 | 62 | { |
| <> | 154:37f96f9d4de2 | 63 | break; |
| <> | 154:37f96f9d4de2 | 64 | } |
| <> | 154:37f96f9d4de2 | 65 | } |
| <> | 154:37f96f9d4de2 | 66 | |
| <> | 154:37f96f9d4de2 | 67 | assert(instance < FSL_FEATURE_SOC_CMP_COUNT); |
| <> | 154:37f96f9d4de2 | 68 | |
| <> | 154:37f96f9d4de2 | 69 | return instance; |
| <> | 154:37f96f9d4de2 | 70 | } |
| <> | 154:37f96f9d4de2 | 71 | |
| <> | 154:37f96f9d4de2 | 72 | void CMP_Init(CMP_Type *base, const cmp_config_t *config) |
| <> | 154:37f96f9d4de2 | 73 | { |
| <> | 154:37f96f9d4de2 | 74 | assert(NULL != config); |
| <> | 154:37f96f9d4de2 | 75 | |
| <> | 154:37f96f9d4de2 | 76 | uint8_t tmp8; |
| <> | 154:37f96f9d4de2 | 77 | |
| <> | 154:37f96f9d4de2 | 78 | /* Enable the clock. */ |
| <> | 154:37f96f9d4de2 | 79 | CLOCK_EnableClock(s_cmpClocks[CMP_GetInstance(base)]); |
| <> | 154:37f96f9d4de2 | 80 | |
| <> | 154:37f96f9d4de2 | 81 | /* Configure. */ |
| <> | 154:37f96f9d4de2 | 82 | CMP_Enable(base, false); /* Disable the CMP module during configuring. */ |
| <> | 154:37f96f9d4de2 | 83 | /* CMPx_CR1. */ |
| <> | 154:37f96f9d4de2 | 84 | tmp8 = base->CR1 & ~(CMP_CR1_PMODE_MASK | CMP_CR1_INV_MASK | CMP_CR1_COS_MASK | CMP_CR1_OPE_MASK); |
| <> | 154:37f96f9d4de2 | 85 | if (config->enableHighSpeed) |
| <> | 154:37f96f9d4de2 | 86 | { |
| <> | 154:37f96f9d4de2 | 87 | tmp8 |= CMP_CR1_PMODE_MASK; |
| <> | 154:37f96f9d4de2 | 88 | } |
| <> | 154:37f96f9d4de2 | 89 | if (config->enableInvertOutput) |
| <> | 154:37f96f9d4de2 | 90 | { |
| <> | 154:37f96f9d4de2 | 91 | tmp8 |= CMP_CR1_INV_MASK; |
| <> | 154:37f96f9d4de2 | 92 | } |
| <> | 154:37f96f9d4de2 | 93 | if (config->useUnfilteredOutput) |
| <> | 154:37f96f9d4de2 | 94 | { |
| <> | 154:37f96f9d4de2 | 95 | tmp8 |= CMP_CR1_COS_MASK; |
| <> | 154:37f96f9d4de2 | 96 | } |
| <> | 154:37f96f9d4de2 | 97 | if (config->enablePinOut) |
| <> | 154:37f96f9d4de2 | 98 | { |
| <> | 154:37f96f9d4de2 | 99 | tmp8 |= CMP_CR1_OPE_MASK; |
| <> | 154:37f96f9d4de2 | 100 | } |
| <> | 154:37f96f9d4de2 | 101 | #if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE |
| <> | 154:37f96f9d4de2 | 102 | if (config->enableTriggerMode) |
| <> | 154:37f96f9d4de2 | 103 | { |
| <> | 154:37f96f9d4de2 | 104 | tmp8 |= CMP_CR1_TRIGM_MASK; |
| <> | 154:37f96f9d4de2 | 105 | } |
| <> | 154:37f96f9d4de2 | 106 | else |
| <> | 154:37f96f9d4de2 | 107 | { |
| <> | 154:37f96f9d4de2 | 108 | tmp8 &= ~CMP_CR1_TRIGM_MASK; |
| <> | 154:37f96f9d4de2 | 109 | } |
| <> | 154:37f96f9d4de2 | 110 | #endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */ |
| <> | 154:37f96f9d4de2 | 111 | base->CR1 = tmp8; |
| <> | 154:37f96f9d4de2 | 112 | |
| <> | 154:37f96f9d4de2 | 113 | /* CMPx_CR0. */ |
| <> | 154:37f96f9d4de2 | 114 | tmp8 = base->CR0 & ~CMP_CR0_HYSTCTR_MASK; |
| <> | 154:37f96f9d4de2 | 115 | tmp8 |= CMP_CR0_HYSTCTR(config->hysteresisMode); |
| <> | 154:37f96f9d4de2 | 116 | base->CR0 = tmp8; |
| <> | 154:37f96f9d4de2 | 117 | |
| <> | 154:37f96f9d4de2 | 118 | CMP_Enable(base, config->enableCmp); /* Enable the CMP module after configured or not. */ |
| <> | 154:37f96f9d4de2 | 119 | } |
| <> | 154:37f96f9d4de2 | 120 | |
| <> | 154:37f96f9d4de2 | 121 | void CMP_Deinit(CMP_Type *base) |
| <> | 154:37f96f9d4de2 | 122 | { |
| <> | 154:37f96f9d4de2 | 123 | /* Disable the CMP module. */ |
| <> | 154:37f96f9d4de2 | 124 | CMP_Enable(base, false); |
| <> | 154:37f96f9d4de2 | 125 | |
| <> | 154:37f96f9d4de2 | 126 | /* Disable the clock. */ |
| <> | 154:37f96f9d4de2 | 127 | CLOCK_DisableClock(s_cmpClocks[CMP_GetInstance(base)]); |
| <> | 154:37f96f9d4de2 | 128 | } |
| <> | 154:37f96f9d4de2 | 129 | |
| <> | 154:37f96f9d4de2 | 130 | void CMP_GetDefaultConfig(cmp_config_t *config) |
| <> | 154:37f96f9d4de2 | 131 | { |
| <> | 154:37f96f9d4de2 | 132 | assert(NULL != config); |
| <> | 154:37f96f9d4de2 | 133 | |
| <> | 154:37f96f9d4de2 | 134 | config->enableCmp = true; /* Enable the CMP module after initialization. */ |
| <> | 154:37f96f9d4de2 | 135 | config->hysteresisMode = kCMP_HysteresisLevel0; |
| <> | 154:37f96f9d4de2 | 136 | config->enableHighSpeed = false; |
| <> | 154:37f96f9d4de2 | 137 | config->enableInvertOutput = false; |
| <> | 154:37f96f9d4de2 | 138 | config->useUnfilteredOutput = false; |
| <> | 154:37f96f9d4de2 | 139 | config->enablePinOut = false; |
| <> | 154:37f96f9d4de2 | 140 | #if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE |
| <> | 154:37f96f9d4de2 | 141 | config->enableTriggerMode = false; |
| <> | 154:37f96f9d4de2 | 142 | #endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */ |
| <> | 154:37f96f9d4de2 | 143 | } |
| <> | 154:37f96f9d4de2 | 144 | |
| <> | 154:37f96f9d4de2 | 145 | void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel) |
| <> | 154:37f96f9d4de2 | 146 | { |
| <> | 154:37f96f9d4de2 | 147 | uint8_t tmp8 = base->MUXCR; |
| <> | 154:37f96f9d4de2 | 148 | |
| <> | 154:37f96f9d4de2 | 149 | tmp8 &= ~(CMP_MUXCR_PSEL_MASK | CMP_MUXCR_MSEL_MASK); |
| <> | 154:37f96f9d4de2 | 150 | tmp8 |= CMP_MUXCR_PSEL(positiveChannel) | CMP_MUXCR_MSEL(negativeChannel); |
| <> | 154:37f96f9d4de2 | 151 | base->MUXCR = tmp8; |
| <> | 154:37f96f9d4de2 | 152 | } |
| <> | 154:37f96f9d4de2 | 153 | |
| <> | 154:37f96f9d4de2 | 154 | #if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA |
| <> | 154:37f96f9d4de2 | 155 | void CMP_EnableDMA(CMP_Type *base, bool enable) |
| <> | 154:37f96f9d4de2 | 156 | { |
| <> | 154:37f96f9d4de2 | 157 | uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ |
| <> | 154:37f96f9d4de2 | 158 | |
| <> | 154:37f96f9d4de2 | 159 | if (enable) |
| <> | 154:37f96f9d4de2 | 160 | { |
| <> | 154:37f96f9d4de2 | 161 | tmp8 |= CMP_SCR_DMAEN_MASK; |
| <> | 154:37f96f9d4de2 | 162 | } |
| <> | 154:37f96f9d4de2 | 163 | else |
| <> | 154:37f96f9d4de2 | 164 | { |
| <> | 154:37f96f9d4de2 | 165 | tmp8 &= ~CMP_SCR_DMAEN_MASK; |
| <> | 154:37f96f9d4de2 | 166 | } |
| <> | 154:37f96f9d4de2 | 167 | base->SCR = tmp8; |
| <> | 154:37f96f9d4de2 | 168 | } |
| <> | 154:37f96f9d4de2 | 169 | #endif /* FSL_FEATURE_CMP_HAS_DMA */ |
| <> | 154:37f96f9d4de2 | 170 | |
| <> | 154:37f96f9d4de2 | 171 | void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config) |
| <> | 154:37f96f9d4de2 | 172 | { |
| <> | 154:37f96f9d4de2 | 173 | assert(NULL != config); |
| <> | 154:37f96f9d4de2 | 174 | |
| <> | 154:37f96f9d4de2 | 175 | uint8_t tmp8; |
| <> | 154:37f96f9d4de2 | 176 | |
| <> | 154:37f96f9d4de2 | 177 | #if defined(FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT) && FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT |
| <> | 154:37f96f9d4de2 | 178 | /* Choose the clock source for sampling. */ |
| <> | 154:37f96f9d4de2 | 179 | if (config->enableSample) |
| <> | 154:37f96f9d4de2 | 180 | { |
| <> | 154:37f96f9d4de2 | 181 | base->CR1 |= CMP_CR1_SE_MASK; /* Choose the external SAMPLE clock. */ |
| <> | 154:37f96f9d4de2 | 182 | } |
| <> | 154:37f96f9d4de2 | 183 | else |
| <> | 154:37f96f9d4de2 | 184 | { |
| <> | 154:37f96f9d4de2 | 185 | base->CR1 &= ~CMP_CR1_SE_MASK; /* Choose the internal divided bus clock. */ |
| <> | 154:37f96f9d4de2 | 186 | } |
| <> | 154:37f96f9d4de2 | 187 | #endif /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */ |
| <> | 154:37f96f9d4de2 | 188 | /* Set the filter count. */ |
| <> | 154:37f96f9d4de2 | 189 | tmp8 = base->CR0 & ~CMP_CR0_FILTER_CNT_MASK; |
| <> | 154:37f96f9d4de2 | 190 | tmp8 |= CMP_CR0_FILTER_CNT(config->filterCount); |
| <> | 154:37f96f9d4de2 | 191 | base->CR0 = tmp8; |
| <> | 154:37f96f9d4de2 | 192 | /* Set the filter period. It is used as the divider to bus clock. */ |
| <> | 154:37f96f9d4de2 | 193 | base->FPR = CMP_FPR_FILT_PER(config->filterPeriod); |
| <> | 154:37f96f9d4de2 | 194 | } |
| <> | 154:37f96f9d4de2 | 195 | |
| <> | 154:37f96f9d4de2 | 196 | void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config) |
| <> | 154:37f96f9d4de2 | 197 | { |
| <> | 154:37f96f9d4de2 | 198 | uint8_t tmp8 = 0U; |
| <> | 154:37f96f9d4de2 | 199 | |
| <> | 154:37f96f9d4de2 | 200 | if (NULL == config) |
| <> | 154:37f96f9d4de2 | 201 | { |
| <> | 154:37f96f9d4de2 | 202 | /* Passing "NULL" as input parameter means no available configuration. So the DAC feature is disabled.*/ |
| <> | 154:37f96f9d4de2 | 203 | base->DACCR = 0U; |
| <> | 154:37f96f9d4de2 | 204 | return; |
| <> | 154:37f96f9d4de2 | 205 | } |
| <> | 154:37f96f9d4de2 | 206 | /* CMPx_DACCR. */ |
| <> | 154:37f96f9d4de2 | 207 | tmp8 |= CMP_DACCR_DACEN_MASK; /* Enable the internal DAC. */ |
| <> | 154:37f96f9d4de2 | 208 | if (kCMP_VrefSourceVin2 == config->referenceVoltageSource) |
| <> | 154:37f96f9d4de2 | 209 | { |
| <> | 154:37f96f9d4de2 | 210 | tmp8 |= CMP_DACCR_VRSEL_MASK; |
| <> | 154:37f96f9d4de2 | 211 | } |
| <> | 154:37f96f9d4de2 | 212 | tmp8 |= CMP_DACCR_VOSEL(config->DACValue); |
| <> | 154:37f96f9d4de2 | 213 | |
| <> | 154:37f96f9d4de2 | 214 | base->DACCR = tmp8; |
| <> | 154:37f96f9d4de2 | 215 | } |
| <> | 154:37f96f9d4de2 | 216 | |
| <> | 154:37f96f9d4de2 | 217 | void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask) |
| <> | 154:37f96f9d4de2 | 218 | { |
| <> | 154:37f96f9d4de2 | 219 | uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ |
| <> | 154:37f96f9d4de2 | 220 | |
| <> | 154:37f96f9d4de2 | 221 | if (0U != (kCMP_OutputRisingInterruptEnable & mask)) |
| <> | 154:37f96f9d4de2 | 222 | { |
| <> | 154:37f96f9d4de2 | 223 | tmp8 |= CMP_SCR_IER_MASK; |
| <> | 154:37f96f9d4de2 | 224 | } |
| <> | 154:37f96f9d4de2 | 225 | if (0U != (kCMP_OutputFallingInterruptEnable & mask)) |
| <> | 154:37f96f9d4de2 | 226 | { |
| <> | 154:37f96f9d4de2 | 227 | tmp8 |= CMP_SCR_IEF_MASK; |
| <> | 154:37f96f9d4de2 | 228 | } |
| <> | 154:37f96f9d4de2 | 229 | base->SCR = tmp8; |
| <> | 154:37f96f9d4de2 | 230 | } |
| <> | 154:37f96f9d4de2 | 231 | |
| <> | 154:37f96f9d4de2 | 232 | void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask) |
| <> | 154:37f96f9d4de2 | 233 | { |
| <> | 154:37f96f9d4de2 | 234 | uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ |
| <> | 154:37f96f9d4de2 | 235 | |
| <> | 154:37f96f9d4de2 | 236 | if (0U != (kCMP_OutputRisingInterruptEnable & mask)) |
| <> | 154:37f96f9d4de2 | 237 | { |
| <> | 154:37f96f9d4de2 | 238 | tmp8 &= ~CMP_SCR_IER_MASK; |
| <> | 154:37f96f9d4de2 | 239 | } |
| <> | 154:37f96f9d4de2 | 240 | if (0U != (kCMP_OutputFallingInterruptEnable & mask)) |
| <> | 154:37f96f9d4de2 | 241 | { |
| <> | 154:37f96f9d4de2 | 242 | tmp8 &= ~CMP_SCR_IEF_MASK; |
| <> | 154:37f96f9d4de2 | 243 | } |
| <> | 154:37f96f9d4de2 | 244 | base->SCR = tmp8; |
| <> | 154:37f96f9d4de2 | 245 | } |
| <> | 154:37f96f9d4de2 | 246 | |
| <> | 154:37f96f9d4de2 | 247 | uint32_t CMP_GetStatusFlags(CMP_Type *base) |
| <> | 154:37f96f9d4de2 | 248 | { |
| <> | 154:37f96f9d4de2 | 249 | uint32_t ret32 = 0U; |
| <> | 154:37f96f9d4de2 | 250 | |
| <> | 154:37f96f9d4de2 | 251 | if (0U != (CMP_SCR_CFR_MASK & base->SCR)) |
| <> | 154:37f96f9d4de2 | 252 | { |
| <> | 154:37f96f9d4de2 | 253 | ret32 |= kCMP_OutputRisingEventFlag; |
| <> | 154:37f96f9d4de2 | 254 | } |
| <> | 154:37f96f9d4de2 | 255 | if (0U != (CMP_SCR_CFF_MASK & base->SCR)) |
| <> | 154:37f96f9d4de2 | 256 | { |
| <> | 154:37f96f9d4de2 | 257 | ret32 |= kCMP_OutputFallingEventFlag; |
| <> | 154:37f96f9d4de2 | 258 | } |
| <> | 154:37f96f9d4de2 | 259 | if (0U != (CMP_SCR_COUT_MASK & base->SCR)) |
| <> | 154:37f96f9d4de2 | 260 | { |
| <> | 154:37f96f9d4de2 | 261 | ret32 |= kCMP_OutputAssertEventFlag; |
| <> | 154:37f96f9d4de2 | 262 | } |
| <> | 154:37f96f9d4de2 | 263 | return ret32; |
| <> | 154:37f96f9d4de2 | 264 | } |
| <> | 154:37f96f9d4de2 | 265 | |
| <> | 154:37f96f9d4de2 | 266 | void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask) |
| <> | 154:37f96f9d4de2 | 267 | { |
| <> | 154:37f96f9d4de2 | 268 | uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ |
| <> | 154:37f96f9d4de2 | 269 | |
| <> | 154:37f96f9d4de2 | 270 | if (0U != (kCMP_OutputRisingEventFlag & mask)) |
| <> | 154:37f96f9d4de2 | 271 | { |
| <> | 154:37f96f9d4de2 | 272 | tmp8 |= CMP_SCR_CFR_MASK; |
| <> | 154:37f96f9d4de2 | 273 | } |
| <> | 154:37f96f9d4de2 | 274 | if (0U != (kCMP_OutputFallingEventFlag & mask)) |
| <> | 154:37f96f9d4de2 | 275 | { |
| <> | 154:37f96f9d4de2 | 276 | tmp8 |= CMP_SCR_CFF_MASK; |
| <> | 154:37f96f9d4de2 | 277 | } |
| <> | 154:37f96f9d4de2 | 278 | base->SCR = tmp8; |
| <> | 154:37f96f9d4de2 | 279 | } |