mbed-dev_spine

Users » benkatz » Code » mbed-dev_spine

Dependents: SPIne CH_Communicatuin_Test CH_Communicatuin_Test2 MCP_SPIne ... more

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_tim_ex.h@179:97f825502e2a, 2018-05-02 (annotated)

Committer:: benkatz
Date:: Wed May 02 18:08:16 2018 +0000
Revision:: 179:97f825502e2a
Parent:: 157:ff67d9f36b67

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f3xx_hal_tim_ex.h
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	157:ff67d9f36b67	5	* @version V1.4.0
<>	157:ff67d9f36b67	6	* @date 16-December-2016
<>	144:ef7eb2e8f9f7	7	* @brief Header file of TIM HAL Extended module.
<>	144:ef7eb2e8f9f7	8	******************************************************************************
<>	144:ef7eb2e8f9f7	9	* @attention
<>	144:ef7eb2e8f9f7	10	*
<>	144:ef7eb2e8f9f7	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	12	*
<>	144:ef7eb2e8f9f7	13	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	14	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	16	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	18	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	19	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	21	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	22	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	23	*
<>	144:ef7eb2e8f9f7	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	34	*
<>	144:ef7eb2e8f9f7	35	******************************************************************************
<>	144:ef7eb2e8f9f7	36	*/
<>	144:ef7eb2e8f9f7	37
<>	144:ef7eb2e8f9f7	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	144:ef7eb2e8f9f7	39	#ifndef __STM32F3xx_HAL_TIM_EX_H
<>	144:ef7eb2e8f9f7	40	#define __STM32F3xx_HAL_TIM_EX_H
<>	144:ef7eb2e8f9f7	41
<>	144:ef7eb2e8f9f7	42	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	43	extern "C" {
<>	144:ef7eb2e8f9f7	44	#endif
<>	144:ef7eb2e8f9f7	45
<>	144:ef7eb2e8f9f7	46	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	47	#include "stm32f3xx_hal_def.h"
<>	144:ef7eb2e8f9f7	48
<>	144:ef7eb2e8f9f7	49	/** @addtogroup STM32F3xx_HAL_Driver
<>	144:ef7eb2e8f9f7	50	* @{
<>	144:ef7eb2e8f9f7	51	*/
<>	144:ef7eb2e8f9f7	52
<>	144:ef7eb2e8f9f7	53	/** @addtogroup TIMEx
<>	144:ef7eb2e8f9f7	54	* @{
<>	144:ef7eb2e8f9f7	55	*/
<>	144:ef7eb2e8f9f7	56
<>	144:ef7eb2e8f9f7	57	/* Exported types ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	58	/** @defgroup TIMEx_Exported_Types TIMEx Exported Types
<>	144:ef7eb2e8f9f7	59	* @{
<>	144:ef7eb2e8f9f7	60	*/
<>	144:ef7eb2e8f9f7	61
<>	144:ef7eb2e8f9f7	62	/**
<>	144:ef7eb2e8f9f7	63	* @brief TIM Hall sensor Configuration Structure definition
<>	144:ef7eb2e8f9f7	64	*/
<>	144:ef7eb2e8f9f7	65
<>	144:ef7eb2e8f9f7	66	typedef struct
<>	144:ef7eb2e8f9f7	67	{
<>	144:ef7eb2e8f9f7	68
<>	144:ef7eb2e8f9f7	69	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
<>	144:ef7eb2e8f9f7	70	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
<>	144:ef7eb2e8f9f7	71
<>	144:ef7eb2e8f9f7	72	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
<>	144:ef7eb2e8f9f7	73	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
<>	144:ef7eb2e8f9f7	74
<>	144:ef7eb2e8f9f7	75	uint32_t IC1Filter; /*!< Specifies the input capture filter.
<>	157:ff67d9f36b67	76	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
<>	144:ef7eb2e8f9f7	77	uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
<>	157:ff67d9f36b67	78	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU */
<>	144:ef7eb2e8f9f7	79	} TIM_HallSensor_InitTypeDef;
<>	144:ef7eb2e8f9f7	80
<>	144:ef7eb2e8f9f7	81	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
<>	144:ef7eb2e8f9f7	82	/**
<>	144:ef7eb2e8f9f7	83	* @brief TIM Master configuration Structure definition
<>	144:ef7eb2e8f9f7	84	* @note STM32F373xC and STM32F378xx: timer instances provide a single TRGO
<>	144:ef7eb2e8f9f7	85	* output
<>	144:ef7eb2e8f9f7	86	*/
<>	144:ef7eb2e8f9f7	87	typedef struct {
<>	144:ef7eb2e8f9f7	88	uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
<>	144:ef7eb2e8f9f7	89	This parameter can be a value of @ref TIM_Master_Mode_Selection */
<>	144:ef7eb2e8f9f7	90	uint32_t MasterSlaveMode; /*!< Master/slave mode selection
<>	144:ef7eb2e8f9f7	91	This parameter can be a value of @ref TIM_Master_Slave_Mode */
<>	144:ef7eb2e8f9f7	92	}TIM_MasterConfigTypeDef;
<>	144:ef7eb2e8f9f7	93
<>	144:ef7eb2e8f9f7	94	/**
<>	144:ef7eb2e8f9f7	95	* @brief TIM Break and Dead time configuration Structure definition
<>	144:ef7eb2e8f9f7	96	* @note STM32F373xC and STM32F378xx: single break input with configurable polarity.
<>	144:ef7eb2e8f9f7	97	*/
<>	144:ef7eb2e8f9f7	98	typedef struct
<>	144:ef7eb2e8f9f7	99	{
<>	144:ef7eb2e8f9f7	100	uint32_t OffStateRunMode; /*!< TIM off state in run mode
<>	144:ef7eb2e8f9f7	101	This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
<>	144:ef7eb2e8f9f7	102	uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
<>	144:ef7eb2e8f9f7	103	This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
<>	144:ef7eb2e8f9f7	104	uint32_t LockLevel; /*!< TIM Lock level
<>	144:ef7eb2e8f9f7	105	This parameter can be a value of @ref TIM_Lock_level */
<>	144:ef7eb2e8f9f7	106	uint32_t DeadTime; /*!< TIM dead Time
<>	157:ff67d9f36b67	107	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFFU */
<>	144:ef7eb2e8f9f7	108	uint32_t BreakState; /*!< TIM Break State
<>	144:ef7eb2e8f9f7	109	This parameter can be a value of @ref TIM_Break_Input_enable_disable */
<>	144:ef7eb2e8f9f7	110	uint32_t BreakPolarity; /*!< TIM Break input polarity
<>	144:ef7eb2e8f9f7	111	This parameter can be a value of @ref TIM_Break_Polarity */
<>	144:ef7eb2e8f9f7	112	uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
<>	144:ef7eb2e8f9f7	113	This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
<>	144:ef7eb2e8f9f7	114	} TIM_BreakDeadTimeConfigTypeDef;
<>	144:ef7eb2e8f9f7	115
<>	144:ef7eb2e8f9f7	116	#endif /* STM32F373xC \|\| STM32F378xx */
<>	144:ef7eb2e8f9f7	117
<>	144:ef7eb2e8f9f7	118	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	119	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
<>	144:ef7eb2e8f9f7	120	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
<>	144:ef7eb2e8f9f7	121	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	122	/**
<>	144:ef7eb2e8f9f7	123	* @brief TIM Break input(s) and Dead time configuration Structure definition
<>	144:ef7eb2e8f9f7	124	* @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
<>	144:ef7eb2e8f9f7	125	* filter and polarity.
<>	144:ef7eb2e8f9f7	126	*/
<>	144:ef7eb2e8f9f7	127	typedef struct
<>	144:ef7eb2e8f9f7	128	{
<>	144:ef7eb2e8f9f7	129	uint32_t OffStateRunMode; /*!< TIM off state in run mode
<>	144:ef7eb2e8f9f7	130	This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
<>	144:ef7eb2e8f9f7	131	uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
<>	144:ef7eb2e8f9f7	132	This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
<>	144:ef7eb2e8f9f7	133	uint32_t LockLevel; /*!< TIM Lock level
<>	144:ef7eb2e8f9f7	134	This parameter can be a value of @ref TIM_Lock_level */
<>	144:ef7eb2e8f9f7	135	uint32_t DeadTime; /*!< TIM dead Time
<>	157:ff67d9f36b67	136	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFFU */
<>	144:ef7eb2e8f9f7	137	uint32_t BreakState; /*!< TIM Break State
<>	144:ef7eb2e8f9f7	138	This parameter can be a value of @ref TIM_Break_Input_enable_disable */
<>	144:ef7eb2e8f9f7	139	uint32_t BreakPolarity; /*!< TIM Break input polarity
<>	144:ef7eb2e8f9f7	140	This parameter can be a value of @ref TIM_Break_Polarity */
<>	144:ef7eb2e8f9f7	141	uint32_t BreakFilter; /*!< Specifies the brek input filter.
<>	157:ff67d9f36b67	142	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
<>	144:ef7eb2e8f9f7	143	uint32_t Break2State; /*!< TIM Break2 State
<>	144:ef7eb2e8f9f7	144	This parameter can be a value of @ref TIMEx_Break2_Input_enable_disable */
<>	144:ef7eb2e8f9f7	145	uint32_t Break2Polarity; /*!< TIM Break2 input polarity
<>	144:ef7eb2e8f9f7	146	This parameter can be a value of @ref TIMEx_Break2_Polarity */
<>	144:ef7eb2e8f9f7	147	uint32_t Break2Filter; /*!< TIM break2 input filter.
<>	157:ff67d9f36b67	148	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
<>	144:ef7eb2e8f9f7	149	uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
<>	144:ef7eb2e8f9f7	150	This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
<>	144:ef7eb2e8f9f7	151	} TIM_BreakDeadTimeConfigTypeDef;
<>	144:ef7eb2e8f9f7	152
<>	144:ef7eb2e8f9f7	153	/**
<>	144:ef7eb2e8f9f7	154	* @brief TIM Master configuration Structure definition
<>	144:ef7eb2e8f9f7	155	* @note Advanced timers provide TRGO2 internal line which is redirected
<>	144:ef7eb2e8f9f7	156	* to the ADC
<>	144:ef7eb2e8f9f7	157	*/
<>	144:ef7eb2e8f9f7	158	typedef struct {
<>	144:ef7eb2e8f9f7	159	uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
<>	144:ef7eb2e8f9f7	160	This parameter can be a value of @ref TIM_Master_Mode_Selection */
<>	144:ef7eb2e8f9f7	161	uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
<>	144:ef7eb2e8f9f7	162	This parameter can be a value of @ref TIMEx_Master_Mode_Selection_2 */
<>	144:ef7eb2e8f9f7	163	uint32_t MasterSlaveMode; /*!< Master/slave mode selection
<>	144:ef7eb2e8f9f7	164	This parameter can be a value of @ref TIM_Master_Slave_Mode */
<>	144:ef7eb2e8f9f7	165	}TIM_MasterConfigTypeDef;
<>	144:ef7eb2e8f9f7	166	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	167	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
<>	144:ef7eb2e8f9f7	168	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
<>	144:ef7eb2e8f9f7	169	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	170	/**
<>	144:ef7eb2e8f9f7	171	* @}
<>	144:ef7eb2e8f9f7	172	*/
<>	144:ef7eb2e8f9f7	173
<>	144:ef7eb2e8f9f7	174	/* Exported constants --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	175	/** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants
<>	144:ef7eb2e8f9f7	176	* @{
<>	144:ef7eb2e8f9f7	177	*/
<>	144:ef7eb2e8f9f7	178
<>	144:ef7eb2e8f9f7	179	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
<>	144:ef7eb2e8f9f7	180	/** @defgroup TIMEx_Channel TIMEx Channel
<>	144:ef7eb2e8f9f7	181	* @{
<>	144:ef7eb2e8f9f7	182	*/
<>	157:ff67d9f36b67	183	#define TIM_CHANNEL_1 (0x0000U)
<>	157:ff67d9f36b67	184	#define TIM_CHANNEL_2 (0x0004U)
<>	157:ff67d9f36b67	185	#define TIM_CHANNEL_3 (0x0008U)
<>	157:ff67d9f36b67	186	#define TIM_CHANNEL_4 (0x000CU)
<>	157:ff67d9f36b67	187	#define TIM_CHANNEL_ALL (0x0018U)
<>	144:ef7eb2e8f9f7	188	/**
<>	144:ef7eb2e8f9f7	189	* @}
<>	144:ef7eb2e8f9f7	190	*/
<>	144:ef7eb2e8f9f7	191
<>	144:ef7eb2e8f9f7	192	/** @defgroup TIMEx_Output_Compare_and_PWM_modes TIMEx Output Compare and PWM Modes
<>	144:ef7eb2e8f9f7	193	* @{
<>	144:ef7eb2e8f9f7	194	*/
<>	157:ff67d9f36b67	195	#define TIM_OCMODE_TIMING (0x0000U)
<>	144:ef7eb2e8f9f7	196	#define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
<>	144:ef7eb2e8f9f7	197	#define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
<>	144:ef7eb2e8f9f7	198	#define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_1)
<>	144:ef7eb2e8f9f7	199	#define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
<>	144:ef7eb2e8f9f7	200	#define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M)
<>	144:ef7eb2e8f9f7	201	#define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
<>	144:ef7eb2e8f9f7	202	#define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
<>	144:ef7eb2e8f9f7	203	/**
<>	144:ef7eb2e8f9f7	204	* @}
<>	144:ef7eb2e8f9f7	205	*/
<>	144:ef7eb2e8f9f7	206
<>	144:ef7eb2e8f9f7	207	/** @defgroup TIMEx_ClearInput_Source TIMEx Clear Input Source
<>	144:ef7eb2e8f9f7	208	* @{
<>	144:ef7eb2e8f9f7	209	*/
<>	157:ff67d9f36b67	210	#define TIM_CLEARINPUTSOURCE_ETR (0x0001U)
<>	157:ff67d9f36b67	211	#define TIM_CLEARINPUTSOURCE_NONE (0x0000U)
<>	144:ef7eb2e8f9f7	212	/**
<>	144:ef7eb2e8f9f7	213	* @}
<>	144:ef7eb2e8f9f7	214	*/
<>	144:ef7eb2e8f9f7	215
<>	144:ef7eb2e8f9f7	216	/** @defgroup TIMEx_Slave_Mode TIMEx Slave Mode
<>	144:ef7eb2e8f9f7	217	* @{
<>	144:ef7eb2e8f9f7	218	*/
<>	157:ff67d9f36b67	219	#define TIM_SLAVEMODE_DISABLE (0x0000U)
<>	144:ef7eb2e8f9f7	220	#define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))
<>	144:ef7eb2e8f9f7	221	#define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0))
<>	144:ef7eb2e8f9f7	222	#define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1))
<>	144:ef7eb2e8f9f7	223	#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0))
<>	144:ef7eb2e8f9f7	224	/**
<>	144:ef7eb2e8f9f7	225	* @}
<>	144:ef7eb2e8f9f7	226	*/
<>	144:ef7eb2e8f9f7	227
<>	144:ef7eb2e8f9f7	228	/** @defgroup TIMEx_Event_Source TIMEx Event Source
<>	144:ef7eb2e8f9f7	229	* @{
<>	144:ef7eb2e8f9f7	230	*/
<>	144:ef7eb2e8f9f7	231	#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /!< Reinitialize the counter and generates an update of the registers /
<>	157:ff67d9f36b67	232	#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /!< A capture/compare event is generated on channel 1U /
<>	157:ff67d9f36b67	233	#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /!< A capture/compare event is generated on channel 2U /
<>	157:ff67d9f36b67	234	#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /!< A capture/compare event is generated on channel 3U /
<>	157:ff67d9f36b67	235	#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /!< A capture/compare event is generated on channel 4U /
<>	144:ef7eb2e8f9f7	236	#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /!< A commutation event is generated /
<>	144:ef7eb2e8f9f7	237	#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /!< A trigger event is generated /
<>	144:ef7eb2e8f9f7	238	#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /!< A break event is generated /
<>	144:ef7eb2e8f9f7	239	/**
<>	144:ef7eb2e8f9f7	240	* @}
<>	144:ef7eb2e8f9f7	241	*/
<>	144:ef7eb2e8f9f7	242
<>	144:ef7eb2e8f9f7	243	/** @defgroup TIMEx_DMA_Base_address TIMEx DMA BAse Address
<>	144:ef7eb2e8f9f7	244	* @{
<>	144:ef7eb2e8f9f7	245	*/
<>	157:ff67d9f36b67	246	#define TIM_DMABASE_CR1 (0x00000000U)
<>	157:ff67d9f36b67	247	#define TIM_DMABASE_CR2 (0x00000001U)
<>	157:ff67d9f36b67	248	#define TIM_DMABASE_SMCR (0x00000002U)
<>	157:ff67d9f36b67	249	#define TIM_DMABASE_DIER (0x00000003U)
<>	157:ff67d9f36b67	250	#define TIM_DMABASE_SR (0x00000004U)
<>	157:ff67d9f36b67	251	#define TIM_DMABASE_EGR (0x00000005U)
<>	157:ff67d9f36b67	252	#define TIM_DMABASE_CCMR1 (0x00000006U)
<>	157:ff67d9f36b67	253	#define TIM_DMABASE_CCMR2 (0x00000007U)
<>	157:ff67d9f36b67	254	#define TIM_DMABASE_CCER (0x00000008U)
<>	157:ff67d9f36b67	255	#define TIM_DMABASE_CNT (0x00000009U)
<>	157:ff67d9f36b67	256	#define TIM_DMABASE_PSC (0x0000000AU)
<>	157:ff67d9f36b67	257	#define TIM_DMABASE_ARR (0x0000000BU)
<>	157:ff67d9f36b67	258	#define TIM_DMABASE_RCR (0x0000000CU)
<>	157:ff67d9f36b67	259	#define TIM_DMABASE_CCR1 (0x0000000DU)
<>	157:ff67d9f36b67	260	#define TIM_DMABASE_CCR2 (0x0000000EU)
<>	157:ff67d9f36b67	261	#define TIM_DMABASE_CCR3 (0x0000000FU)
<>	157:ff67d9f36b67	262	#define TIM_DMABASE_CCR4 (0x00000010U)
<>	157:ff67d9f36b67	263	#define TIM_DMABASE_BDTR (0x00000011U)
<>	157:ff67d9f36b67	264	#define TIM_DMABASE_DCR (0x00000012U)
<>	157:ff67d9f36b67	265	#define TIM_DMABASE_OR (0x00000013U)
<>	144:ef7eb2e8f9f7	266	/**
<>	144:ef7eb2e8f9f7	267	* @}
<>	144:ef7eb2e8f9f7	268	*/
<>	144:ef7eb2e8f9f7	269	#endif /* STM32F373xC \|\| STM32F378xx */
<>	144:ef7eb2e8f9f7	270
<>	144:ef7eb2e8f9f7	271	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	272	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
<>	144:ef7eb2e8f9f7	273	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
<>	144:ef7eb2e8f9f7	274	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	275	/** @defgroup TIMEx_Channel TIMEx Channel
<>	144:ef7eb2e8f9f7	276	* @{
<>	144:ef7eb2e8f9f7	277	*/
<>	157:ff67d9f36b67	278	#define TIM_CHANNEL_1 (0x0000U)
<>	157:ff67d9f36b67	279	#define TIM_CHANNEL_2 (0x0004U)
<>	157:ff67d9f36b67	280	#define TIM_CHANNEL_3 (0x0008U)
<>	157:ff67d9f36b67	281	#define TIM_CHANNEL_4 (0x000CU)
<>	157:ff67d9f36b67	282	#define TIM_CHANNEL_5 (0x0010U)
<>	157:ff67d9f36b67	283	#define TIM_CHANNEL_6 (0x0014U)
<>	157:ff67d9f36b67	284	#define TIM_CHANNEL_ALL (0x003CU)
<>	144:ef7eb2e8f9f7	285	/**
<>	144:ef7eb2e8f9f7	286	* @}
<>	144:ef7eb2e8f9f7	287	*/
<>	144:ef7eb2e8f9f7	288
<>	144:ef7eb2e8f9f7	289	/** @defgroup TIMEx_Output_Compare_and_PWM_modes TIMEx Output Compare and PWM Modes
<>	144:ef7eb2e8f9f7	290	* @{
<>	144:ef7eb2e8f9f7	291	*/
<>	157:ff67d9f36b67	292	#define TIM_OCMODE_TIMING (0x0000U)
<>	144:ef7eb2e8f9f7	293	#define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
<>	144:ef7eb2e8f9f7	294	#define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
<>	144:ef7eb2e8f9f7	295	#define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0)
<>	144:ef7eb2e8f9f7	296	#define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1)
<>	144:ef7eb2e8f9f7	297	#define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0)
<>	144:ef7eb2e8f9f7	298	#define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0)
<>	144:ef7eb2e8f9f7	299	#define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
<>	144:ef7eb2e8f9f7	300
<>	144:ef7eb2e8f9f7	301	#define TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3)
<>	144:ef7eb2e8f9f7	302	#define TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_0)
<>	144:ef7eb2e8f9f7	303	#define TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_2)
<>	144:ef7eb2e8f9f7	304	#define TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
<>	144:ef7eb2e8f9f7	305	#define TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
<>	144:ef7eb2e8f9f7	306	#define TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M)
<>	144:ef7eb2e8f9f7	307
<>	144:ef7eb2e8f9f7	308	/**
<>	144:ef7eb2e8f9f7	309	* @}
<>	144:ef7eb2e8f9f7	310	*/
<>	144:ef7eb2e8f9f7	311
<>	144:ef7eb2e8f9f7	312	/** @defgroup TIMEx_ClearInput_Source TIMEx Clear Input Source
<>	144:ef7eb2e8f9f7	313	* @{
<>	144:ef7eb2e8f9f7	314	*/
<>	157:ff67d9f36b67	315	#define TIM_CLEARINPUTSOURCE_ETR (0x0001U)
<>	157:ff67d9f36b67	316	#define TIM_CLEARINPUTSOURCE_OCREFCLR (0x0002U)
<>	157:ff67d9f36b67	317	#define TIM_CLEARINPUTSOURCE_NONE (0x0000U)
<>	144:ef7eb2e8f9f7	318	/**
<>	144:ef7eb2e8f9f7	319	* @}
<>	144:ef7eb2e8f9f7	320	*/
<>	144:ef7eb2e8f9f7	321
<>	144:ef7eb2e8f9f7	322	/** @defgroup TIMEx_Break2_Input_enable_disable TIMEX Break input 2 Enable
<>	144:ef7eb2e8f9f7	323	* @{
<>	144:ef7eb2e8f9f7	324	*/
<>	157:ff67d9f36b67	325	#define TIM_BREAK2_DISABLE (0x00000000U)
<>	144:ef7eb2e8f9f7	326	#define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E)
<>	144:ef7eb2e8f9f7	327	/**
<>	144:ef7eb2e8f9f7	328	* @}
<>	144:ef7eb2e8f9f7	329	*/
<>	144:ef7eb2e8f9f7	330
<>	144:ef7eb2e8f9f7	331	/** @defgroup TIMEx_Break2_Polarity TIMEx Break Input 2 Polarity
<>	144:ef7eb2e8f9f7	332	* @{
<>	144:ef7eb2e8f9f7	333	*/
<>	157:ff67d9f36b67	334	#define TIM_BREAK2POLARITY_LOW (0x00000000U)
<>	144:ef7eb2e8f9f7	335	#define TIM_BREAK2POLARITY_HIGH ((uint32_t)TIM_BDTR_BK2P)
<>	144:ef7eb2e8f9f7	336	/**
<>	144:ef7eb2e8f9f7	337	* @}
<>	144:ef7eb2e8f9f7	338	*/
<>	144:ef7eb2e8f9f7	339
<>	144:ef7eb2e8f9f7	340	/** @defgroup TIMEx_Master_Mode_Selection_2 TIMEx Master Mode Selection 2 (TRGO2)
<>	144:ef7eb2e8f9f7	341	* @{
<>	144:ef7eb2e8f9f7	342	*/
<>	157:ff67d9f36b67	343	#define TIM_TRGO2_RESET (0x00000000U)
<>	144:ef7eb2e8f9f7	344	#define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0))
<>	144:ef7eb2e8f9f7	345	#define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1))
<>	144:ef7eb2e8f9f7	346	#define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0))
<>	144:ef7eb2e8f9f7	347	#define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2))
<>	144:ef7eb2e8f9f7	348	#define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_0))
<>	144:ef7eb2e8f9f7	349	#define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1))
<>	144:ef7eb2e8f9f7	350	#define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0))
<>	144:ef7eb2e8f9f7	351	#define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3))
<>	144:ef7eb2e8f9f7	352	#define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_0))
<>	144:ef7eb2e8f9f7	353	#define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_1))
<>	144:ef7eb2e8f9f7	354	#define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0))
<>	144:ef7eb2e8f9f7	355	#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2))
<>	144:ef7eb2e8f9f7	356	#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_0))
<>	144:ef7eb2e8f9f7	357	#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \|TIM_CR2_MMS2_1))
<>	144:ef7eb2e8f9f7	358	#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0))
<>	144:ef7eb2e8f9f7	359	/**
<>	144:ef7eb2e8f9f7	360	* @}
<>	144:ef7eb2e8f9f7	361	*/
<>	144:ef7eb2e8f9f7	362
<>	144:ef7eb2e8f9f7	363	/** @defgroup TIMEx_Slave_Mode TIMEx Slave mode
<>	144:ef7eb2e8f9f7	364	* @{
<>	144:ef7eb2e8f9f7	365	*/
<>	157:ff67d9f36b67	366	#define TIM_SLAVEMODE_DISABLE (0x0000U)
<>	144:ef7eb2e8f9f7	367	#define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))
<>	144:ef7eb2e8f9f7	368	#define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0))
<>	144:ef7eb2e8f9f7	369	#define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1))
<>	144:ef7eb2e8f9f7	370	#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0))
<>	144:ef7eb2e8f9f7	371	#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3))
<>	144:ef7eb2e8f9f7	372	/**
<>	144:ef7eb2e8f9f7	373	* @}
<>	144:ef7eb2e8f9f7	374	*/
<>	144:ef7eb2e8f9f7	375
<>	144:ef7eb2e8f9f7	376	/** @defgroup TIM_Event_Source TIMEx Event Source
<>	144:ef7eb2e8f9f7	377	* @{
<>	144:ef7eb2e8f9f7	378	*/
<>	144:ef7eb2e8f9f7	379	#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /!< Reinitialize the counter and generates an update of the registers /
<>	157:ff67d9f36b67	380	#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /!< A capture/compare event is generated on channel 1U /
<>	157:ff67d9f36b67	381	#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /!< A capture/compare event is generated on channel 2U /
<>	157:ff67d9f36b67	382	#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /!< A capture/compare event is generated on channel 3U /
<>	157:ff67d9f36b67	383	#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /!< A capture/compare event is generated on channel 4U /
<>	144:ef7eb2e8f9f7	384	#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /!< A commutation event is generated /
<>	144:ef7eb2e8f9f7	385	#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /!< A trigger event is generated /
<>	144:ef7eb2e8f9f7	386	#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /!< A break event is generated /
<>	144:ef7eb2e8f9f7	387	#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /!< A break 2 event is generated /
<>	144:ef7eb2e8f9f7	388	/**
<>	144:ef7eb2e8f9f7	389	* @}
<>	144:ef7eb2e8f9f7	390	*/
<>	144:ef7eb2e8f9f7	391
<>	144:ef7eb2e8f9f7	392	/** @defgroup TIM_DMA_Base_address TIMEx DMA Base Address
<>	144:ef7eb2e8f9f7	393	* @{
<>	144:ef7eb2e8f9f7	394	*/
<>	157:ff67d9f36b67	395	#define TIM_DMABASE_CR1 (0x00000000U)
<>	157:ff67d9f36b67	396	#define TIM_DMABASE_CR2 (0x00000001U)
<>	157:ff67d9f36b67	397	#define TIM_DMABASE_SMCR (0x00000002U)
<>	157:ff67d9f36b67	398	#define TIM_DMABASE_DIER (0x00000003U)
<>	157:ff67d9f36b67	399	#define TIM_DMABASE_SR (0x00000004U)
<>	157:ff67d9f36b67	400	#define TIM_DMABASE_EGR (0x00000005U)
<>	157:ff67d9f36b67	401	#define TIM_DMABASE_CCMR1 (0x00000006U)
<>	157:ff67d9f36b67	402	#define TIM_DMABASE_CCMR2 (0x00000007U)
<>	157:ff67d9f36b67	403	#define TIM_DMABASE_CCER (0x00000008U)
<>	157:ff67d9f36b67	404	#define TIM_DMABASE_CNT (0x00000009U)
<>	157:ff67d9f36b67	405	#define TIM_DMABASE_PSC (0x0000000AU)
<>	157:ff67d9f36b67	406	#define TIM_DMABASE_ARR (0x0000000BU)
<>	157:ff67d9f36b67	407	#define TIM_DMABASE_RCR (0x0000000CU)
<>	157:ff67d9f36b67	408	#define TIM_DMABASE_CCR1 (0x0000000DU)
<>	157:ff67d9f36b67	409	#define TIM_DMABASE_CCR2 (0x0000000EU)
<>	157:ff67d9f36b67	410	#define TIM_DMABASE_CCR3 (0x0000000FU)
<>	157:ff67d9f36b67	411	#define TIM_DMABASE_CCR4 (0x00000010U)
<>	157:ff67d9f36b67	412	#define TIM_DMABASE_BDTR (0x00000011U)
<>	157:ff67d9f36b67	413	#define TIM_DMABASE_DCR (0x00000012U)
<>	157:ff67d9f36b67	414	#define TIM_DMABASE_CCMR3 (0x00000015U)
<>	157:ff67d9f36b67	415	#define TIM_DMABASE_CCR5 (0x00000016U)
<>	157:ff67d9f36b67	416	#define TIM_DMABASE_CCR6 (0x00000017U)
<>	157:ff67d9f36b67	417	#define TIM_DMABASE_OR (0x00000018U)
<>	144:ef7eb2e8f9f7	418	/**
<>	144:ef7eb2e8f9f7	419	* @}
<>	144:ef7eb2e8f9f7	420	*/
<>	144:ef7eb2e8f9f7	421	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	422	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
<>	144:ef7eb2e8f9f7	423	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
<>	144:ef7eb2e8f9f7	424	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	425
<>	144:ef7eb2e8f9f7	426	#if defined(STM32F302xE) \|\| \
<>	144:ef7eb2e8f9f7	427	defined(STM32F302xC) \|\| \
<>	157:ff67d9f36b67	428	defined(STM32F303x8) \|\| defined(STM32F328xx) \|\| \
<>	144:ef7eb2e8f9f7	429	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	430	/** @defgroup TIMEx_Remap TIMEx Remapping
<>	144:ef7eb2e8f9f7	431	* @{
<>	144:ef7eb2e8f9f7	432	*/
<>	157:ff67d9f36b67	433	#define TIM_TIM1_ADC1_NONE (0x00000000U) /!< TIM1_ETR is not connected to any AWD (analog watchdog)/
<>	157:ff67d9f36b67	434	#define TIM_TIM1_ADC1_AWD1 (0x00000001U) /!< TIM1_ETR is connected to ADC1 AWD1 /
<>	157:ff67d9f36b67	435	#define TIM_TIM1_ADC1_AWD2 (0x00000002U) /!< TIM1_ETR is connected to ADC1 AWD2 /
<>	157:ff67d9f36b67	436	#define TIM_TIM1_ADC1_AWD3 (0x00000003U) /!< TIM1_ETR is connected to ADC1 AWD3 /
<>	157:ff67d9f36b67	437	#define TIM_TIM16_GPIO (0x00000000U) /!< TIM16 TI1 is connected to GPIO /
<>	157:ff67d9f36b67	438	#define TIM_TIM16_RTC (0x00000001U) /!< TIM16 TI1 is connected to RTC_clock /
<>	157:ff67d9f36b67	439	#define TIM_TIM16_HSE (0x00000002U) /!< TIM16 TI1 is connected to HSE/32U /
<>	157:ff67d9f36b67	440	#define TIM_TIM16_MCO (0x00000003U) /!< TIM16 TI1 is connected to MCO /
<>	144:ef7eb2e8f9f7	441	/**
<>	144:ef7eb2e8f9f7	442	* @}
<>	144:ef7eb2e8f9f7	443	*/
<>	144:ef7eb2e8f9f7	444	#endif /* STM32F302xE \|\| */
<>	144:ef7eb2e8f9f7	445	/* STM32F302xC \|\| */
<>	157:ff67d9f36b67	446	/* STM32F303x8 \|\| STM32F328xx \|\| */
<>	144:ef7eb2e8f9f7	447	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx \|\| */
<>	144:ef7eb2e8f9f7	448
<>	157:ff67d9f36b67	449
<>	157:ff67d9f36b67	450	#if defined(STM32F334x8)
<>	144:ef7eb2e8f9f7	451	/** @defgroup TIMEx_Remap TIMEx Remapping 1
<>	144:ef7eb2e8f9f7	452	* @{
<>	144:ef7eb2e8f9f7	453	*/
<>	157:ff67d9f36b67	454	#define TIM_TIM1_ADC1_NONE (0x00000000U) /!< TIM1_ETR is not connected to any AWD (analog watchdog)/
<>	157:ff67d9f36b67	455	#define TIM_TIM1_ADC1_AWD1 (0x00000001U) /!< TIM1_ETR is connected to ADC1 AWD1 /
<>	157:ff67d9f36b67	456	#define TIM_TIM1_ADC1_AWD2 (0x00000002U) /!< TIM1_ETR is connected to ADC1 AWD2 /
<>	157:ff67d9f36b67	457	#define TIM_TIM1_ADC1_AWD3 (0x00000003U) /!< TIM1_ETR is connected to ADC1 AWD3 /
<>	157:ff67d9f36b67	458	#define TIM_TIM16_GPIO (0x00000000U) /!< TIM16 TI1 is connected to GPIO /
<>	157:ff67d9f36b67	459	#define TIM_TIM16_RTC (0x00000001U) /!< TIM16 TI1 is connected to RTC_clock /
<>	157:ff67d9f36b67	460	#define TIM_TIM16_HSE (0x00000002U) /!< TIM16 TI1 is connected to HSE/32U /
<>	157:ff67d9f36b67	461	#define TIM_TIM16_MCO (0x00000003U) /!< TIM16 TI1 is connected to MCO /
<>	144:ef7eb2e8f9f7	462	/**
<>	144:ef7eb2e8f9f7	463	* @}
<>	144:ef7eb2e8f9f7	464	*/
<>	144:ef7eb2e8f9f7	465
<>	144:ef7eb2e8f9f7	466	/** @defgroup TIMEx_Remap2 TIMEx Remapping 2
<>	144:ef7eb2e8f9f7	467	* @{
<>	144:ef7eb2e8f9f7	468	*/
<>	157:ff67d9f36b67	469	#define TIM_TIM1_ADC2_NONE (0x00000000U) /!< TIM1_ETR is not connected to any AWD (analog watchdog)/
<>	157:ff67d9f36b67	470	#define TIM_TIM1_ADC2_AWD1 (0x00000004U) /!< TIM1_ETR is connected to ADC2 AWD1 /
<>	157:ff67d9f36b67	471	#define TIM_TIM1_ADC2_AWD2 (0x00000008U) /!< TIM1_ETR is connected to ADC2 AWD2 /
<>	157:ff67d9f36b67	472	#define TIM_TIM1_ADC2_AWD3 (0x0000000CU) /!< TIM1_ETR is connected to ADC2 AWD3 /
<>	157:ff67d9f36b67	473	#define TIM_TIM16_NONE (0x00000000U) /!< Non significant value for TIM16U /
<>	157:ff67d9f36b67	474	/**
<>	157:ff67d9f36b67	475	* @}
<>	157:ff67d9f36b67	476	*/
<>	157:ff67d9f36b67	477	#endif /* STM32F334x8 */
<>	157:ff67d9f36b67	478
<>	157:ff67d9f36b67	479	#if defined(STM32F303xC) \|\| defined(STM32F358xx)
<>	157:ff67d9f36b67	480	/** @defgroup TIMEx_Remap TIMEx Remapping 1
<>	157:ff67d9f36b67	481	* @{
<>	157:ff67d9f36b67	482	*/
<>	157:ff67d9f36b67	483	#define TIM_TIM1_ADC1_NONE (0x00000000U) /!< TIM1_ETR is not connected to any AWD (analog watchdog)/
<>	157:ff67d9f36b67	484	#define TIM_TIM1_ADC1_AWD1 (0x00000001U) /!< TIM1_ETR is connected to ADC1 AWD1 /
<>	157:ff67d9f36b67	485	#define TIM_TIM1_ADC1_AWD2 (0x00000002U) /!< TIM1_ETR is connected to ADC1 AWD2 /
<>	157:ff67d9f36b67	486	#define TIM_TIM1_ADC1_AWD3 (0x00000003U) /!< TIM1_ETR is connected to ADC1 AWD3 /
<>	157:ff67d9f36b67	487	#define TIM_TIM8_ADC2_NONE (0x00000000U) /!< TIM8_ETR is not connected to any AWD (analog watchdog) /
<>	157:ff67d9f36b67	488	#define TIM_TIM8_ADC2_AWD1 (0x00000001U) /!< TIM8_ETR is connected to ADC2 AWD1 /
<>	157:ff67d9f36b67	489	#define TIM_TIM8_ADC2_AWD2 (0x00000002U) /!< TIM8_ETR is connected to ADC2 AWD2 /
<>	157:ff67d9f36b67	490	#define TIM_TIM8_ADC2_AWD3 (0x00000003U) /!< TIM8_ETR is connected to ADC2 AWD3 /
<>	157:ff67d9f36b67	491	#define TIM_TIM16_GPIO (0x00000000U) /!< TIM16 TI1 is connected to GPIO /
<>	157:ff67d9f36b67	492	#define TIM_TIM16_RTC (0x00000001U) /!< TIM16 TI1 is connected to RTC_clock /
<>	157:ff67d9f36b67	493	#define TIM_TIM16_HSE (0x00000002U) /!< TIM16 TI1 is connected to HSE/32U /
<>	157:ff67d9f36b67	494	#define TIM_TIM16_MCO (0x00000003U) /!< TIM16 TI1 is connected to MCO /
<>	157:ff67d9f36b67	495	/**
<>	157:ff67d9f36b67	496	* @}
<>	157:ff67d9f36b67	497	*/
<>	157:ff67d9f36b67	498
<>	157:ff67d9f36b67	499	/** @defgroup TIMEx_Remap2 TIMEx Remapping 2
<>	157:ff67d9f36b67	500	* @{
<>	157:ff67d9f36b67	501	*/
<>	157:ff67d9f36b67	502	#define TIM_TIM1_ADC4_NONE (0x00000000U) /!< TIM1_ETR is not connected to any AWD (analog watchdog)/
<>	157:ff67d9f36b67	503	#define TIM_TIM1_ADC4_AWD1 (0x00000004U) /!< TIM1_ETR is connected to ADC4 AWD1 /
<>	157:ff67d9f36b67	504	#define TIM_TIM1_ADC4_AWD2 (0x00000008U) /!< TIM1_ETR is connected to ADC4 AWD2 /
<>	157:ff67d9f36b67	505	#define TIM_TIM1_ADC4_AWD3 (0x0000000CU) /!< TIM1_ETR is connected to ADC4 AWD3 /
<>	157:ff67d9f36b67	506	#define TIM_TIM8_ADC3_NONE (0x00000000U) /!< TIM8_ETR is not connected to any AWD (analog watchdog) /
<>	157:ff67d9f36b67	507	#define TIM_TIM8_ADC3_AWD1 (0x00000004U) /!< TIM8_ETR is connected to ADC3 AWD1 /
<>	157:ff67d9f36b67	508	#define TIM_TIM8_ADC3_AWD2 (0x00000008U) /!< TIM8_ETR is connected to ADC3 AWD2 /
<>	157:ff67d9f36b67	509	#define TIM_TIM8_ADC3_AWD3 (0x0000000CU) /!< TIM8_ETR is connected to ADC3 AWD3 /
<>	157:ff67d9f36b67	510	#define TIM_TIM16_NONE (0x00000000U) /!< Non significant value for TIM16U /
<>	144:ef7eb2e8f9f7	511	/**
<>	144:ef7eb2e8f9f7	512	* @}
<>	144:ef7eb2e8f9f7	513	*/
<>	144:ef7eb2e8f9f7	514	#endif /* STM32F303xC \|\| STM32F358xx */
<>	144:ef7eb2e8f9f7	515
<>	144:ef7eb2e8f9f7	516	#if defined(STM32F303xE) \|\| defined(STM32F398xx)
<>	144:ef7eb2e8f9f7	517	/** @defgroup TIMEx_Remap TIMEx Remapping 1
<>	144:ef7eb2e8f9f7	518	* @{
<>	144:ef7eb2e8f9f7	519	*/
<>	157:ff67d9f36b67	520	#define TIM_TIM1_ADC1_NONE (0x00000000U) /!< TIM1_ETR is not connected to any AWD (analog watchdog)/
<>	157:ff67d9f36b67	521	#define TIM_TIM1_ADC1_AWD1 (0x00000001U) /!< TIM1_ETR is connected to ADC1 AWD1 /
<>	157:ff67d9f36b67	522	#define TIM_TIM1_ADC1_AWD2 (0x00000002U) /!< TIM1_ETR is connected to ADC1 AWD2 /
<>	157:ff67d9f36b67	523	#define TIM_TIM1_ADC1_AWD3 (0x00000003U) /!< TIM1_ETR is connected to ADC1 AWD3 /
<>	157:ff67d9f36b67	524	#define TIM_TIM8_ADC2_NONE (0x00000000U) /!< TIM8_ETR is not connected to any AWD (analog watchdog) /
<>	157:ff67d9f36b67	525	#define TIM_TIM8_ADC2_AWD1 (0x00000001U) /!< TIM8_ETR is connected to ADC2 AWD1 /
<>	157:ff67d9f36b67	526	#define TIM_TIM8_ADC2_AWD2 (0x00000002U) /!< TIM8_ETR is connected to ADC2 AWD2 /
<>	157:ff67d9f36b67	527	#define TIM_TIM8_ADC2_AWD3 (0x00000003U) /!< TIM8_ETR is connected to ADC2 AWD3 /
<>	157:ff67d9f36b67	528	#define TIM_TIM16_GPIO (0x00000000U) /!< TIM16 TI1 is connected to GPIO /
<>	157:ff67d9f36b67	529	#define TIM_TIM16_RTC (0x00000001U) /!< TIM16 TI1 is connected to RTC_clock /
<>	157:ff67d9f36b67	530	#define TIM_TIM16_HSE (0x00000002U) /!< TIM16 TI1 is connected to HSE/32U /
<>	157:ff67d9f36b67	531	#define TIM_TIM16_MCO (0x00000003U) /!< TIM16 TI1 is connected to MCO /
<>	157:ff67d9f36b67	532	#define TIM_TIM20_ADC3_NONE (0x00000000U) /!< TIM20_ETR is not connected to any AWD (analog watchdog) /
<>	157:ff67d9f36b67	533	#define TIM_TIM20_ADC3_AWD1 (0x00000001U) /!< TIM20_ETR is connected to ADC3 AWD1 /
<>	157:ff67d9f36b67	534	#define TIM_TIM20_ADC3_AWD2 (0x00000002U) /!< TIM20_ETR is connected to ADC3 AWD2 /
<>	157:ff67d9f36b67	535	#define TIM_TIM20_ADC3_AWD3 (0x00000003U) /!< TIM20_ETR is connected to ADC3 AWD3 /
<>	144:ef7eb2e8f9f7	536	/**
<>	144:ef7eb2e8f9f7	537	* @}
<>	144:ef7eb2e8f9f7	538	*/
<>	144:ef7eb2e8f9f7	539
<>	144:ef7eb2e8f9f7	540	/** @defgroup TIMEx_Remap2 TIMEx Remapping 2
<>	144:ef7eb2e8f9f7	541	* @{
<>	144:ef7eb2e8f9f7	542	*/
<>	157:ff67d9f36b67	543	#define TIM_TIM1_ADC4_NONE (0x00000000U) /!< TIM1_ETR is not connected to any AWD (analog watchdog)/
<>	157:ff67d9f36b67	544	#define TIM_TIM1_ADC4_AWD1 (0x00000004U) /!< TIM1_ETR is connected to ADC4 AWD1 /
<>	157:ff67d9f36b67	545	#define TIM_TIM1_ADC4_AWD2 (0x00000008U) /!< TIM1_ETR is connected to ADC4 AWD2 /
<>	157:ff67d9f36b67	546	#define TIM_TIM1_ADC4_AWD3 (0x0000000CU) /!< TIM1_ETR is connected to ADC4 AWD3 /
<>	157:ff67d9f36b67	547	#define TIM_TIM8_ADC3_NONE (0x00000000U) /!< TIM8_ETR is not connected to any AWD (analog watchdog) /
<>	157:ff67d9f36b67	548	#define TIM_TIM8_ADC3_AWD1 (0x00000004U) /!< TIM8_ETR is connected to ADC3 AWD1 /
<>	157:ff67d9f36b67	549	#define TIM_TIM8_ADC3_AWD2 (0x00000008U) /!< TIM8_ETR is connected to ADC3 AWD2 /
<>	157:ff67d9f36b67	550	#define TIM_TIM8_ADC3_AWD3 (0x0000000CU) /!< TIM8_ETR is connected to ADC3 AWD3 /
<>	157:ff67d9f36b67	551	#define TIM_TIM16_NONE (0x00000000U) /!< Non significant value for TIM16U /
<>	157:ff67d9f36b67	552	#define TIM_TIM20_ADC4_NONE (0x00000000U) /!< TIM20_ETR is not connected to any AWD (analog watchdog) /
<>	157:ff67d9f36b67	553	#define TIM_TIM20_ADC4_AWD1 (0x00000004U) /!< TIM20_ETR is connected to ADC4 AWD1 /
<>	157:ff67d9f36b67	554	#define TIM_TIM20_ADC4_AWD2 (0x00000008U) /!< TIM20_ETR is connected to ADC4 AWD2 /
<>	157:ff67d9f36b67	555	#define TIM_TIM20_ADC4_AWD3 (0x0000000CU) /!< TIM20_ETR is connected to ADC4 AWD3 /
<>	144:ef7eb2e8f9f7	556	/**
<>	144:ef7eb2e8f9f7	557	* @}
<>	144:ef7eb2e8f9f7	558	*/
<>	144:ef7eb2e8f9f7	559	#endif /* STM32F303xE \|\| STM32F398xx */
<>	144:ef7eb2e8f9f7	560
<>	144:ef7eb2e8f9f7	561
<>	144:ef7eb2e8f9f7	562	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
<>	144:ef7eb2e8f9f7	563	/** @defgroup TIMEx_Remap TIMEx remapping
<>	144:ef7eb2e8f9f7	564	* @{
<>	144:ef7eb2e8f9f7	565	*/
<>	157:ff67d9f36b67	566	#define TIM_TIM2_TIM8_TRGO (0x00000000U) /!< TIM8 TRGOUT is connected to TIM2_ITR1 /
<>	157:ff67d9f36b67	567	#define TIM_TIM2_ETH_PTP (0x00000400U) /!< PTP trigger output is connected to TIM2_ITR1 /
<>	157:ff67d9f36b67	568	#define TIM_TIM2_USBFS_SOF (0x00000800U) /!< OTG FS SOF is connected to the TIM2_ITR1 input /
<>	157:ff67d9f36b67	569	#define TIM_TIM2_USBHS_SOF (0x00000C00U) /!< OTG HS SOF is connected to the TIM2_ITR1 input /
<>	157:ff67d9f36b67	570	#define TIM_TIM14_GPIO (0x00000000U) /!< TIM14 TI1 is connected to GPIO /
<>	157:ff67d9f36b67	571	#define TIM_TIM14_RTC (0x00000001U) /!< TIM14 TI1 is connected to RTC_clock /
<>	157:ff67d9f36b67	572	#define TIM_TIM14_HSE (0x00000002U) /!< TIM14 TI1 is connected to HSE/32U /
<>	157:ff67d9f36b67	573	#define TIM_TIM14_MCO (0x00000003U) /!< TIM14 TI1 is connected to MCO /
<>	144:ef7eb2e8f9f7	574	/**
<>	144:ef7eb2e8f9f7	575	* @}
<>	144:ef7eb2e8f9f7	576	*/
<>	144:ef7eb2e8f9f7	577	#endif /* STM32F373xC \|\| STM32F378xx */
<>	144:ef7eb2e8f9f7	578
<>	144:ef7eb2e8f9f7	579	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	580	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
<>	144:ef7eb2e8f9f7	581	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
<>	144:ef7eb2e8f9f7	582	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	157:ff67d9f36b67	583	/** @defgroup TIMEx_Group_Channel5 Group Channel 5 and Channel 1U, 2 or 3
<>	144:ef7eb2e8f9f7	584	* @{
<>	144:ef7eb2e8f9f7	585	*/
<>	157:ff67d9f36b67	586	#define TIM_GROUPCH5_NONE 0x00000000 /!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC /
<>	144:ef7eb2e8f9f7	587	#define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /!< OC1REFC is the logical AND of OC1REFC and OC5REF /
<>	144:ef7eb2e8f9f7	588	#define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /!< OC2REFC is the logical AND of OC2REFC and OC5REF /
<>	144:ef7eb2e8f9f7	589	#define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /!< OC3REFC is the logical AND of OC3REFC and OC5REF /
<>	144:ef7eb2e8f9f7	590	/**
<>	144:ef7eb2e8f9f7	591	* @}
<>	144:ef7eb2e8f9f7	592	*/
<>	144:ef7eb2e8f9f7	593	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	594	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
<>	144:ef7eb2e8f9f7	595	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
<>	144:ef7eb2e8f9f7	596	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	597
<>	144:ef7eb2e8f9f7	598	/**
<>	144:ef7eb2e8f9f7	599	* @}
<>	144:ef7eb2e8f9f7	600	*/
<>	144:ef7eb2e8f9f7	601
<>	144:ef7eb2e8f9f7	602
<>	144:ef7eb2e8f9f7	603	/* Private Macros -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	604	/** @defgroup TIM_Private_Macros TIM Private Macros
<>	144:ef7eb2e8f9f7	605	* @{
<>	144:ef7eb2e8f9f7	606	*/
<>	144:ef7eb2e8f9f7	607	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
<>	144:ef7eb2e8f9f7	608
<>	144:ef7eb2e8f9f7	609	#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
<>	144:ef7eb2e8f9f7	610	((CHANNEL) == TIM_CHANNEL_2) \|\| \
<>	144:ef7eb2e8f9f7	611	((CHANNEL) == TIM_CHANNEL_3) \|\| \
<>	144:ef7eb2e8f9f7	612	((CHANNEL) == TIM_CHANNEL_4) \|\| \
<>	144:ef7eb2e8f9f7	613	((CHANNEL) == TIM_CHANNEL_ALL))
<>	144:ef7eb2e8f9f7	614
<>	144:ef7eb2e8f9f7	615	#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
<>	144:ef7eb2e8f9f7	616	((CHANNEL) == TIM_CHANNEL_2))
<>	144:ef7eb2e8f9f7	617
<>	144:ef7eb2e8f9f7	618	#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
<>	144:ef7eb2e8f9f7	619	((CHANNEL) == TIM_CHANNEL_2) \|\| \
<>	144:ef7eb2e8f9f7	620	((CHANNEL) == TIM_CHANNEL_3))
<>	144:ef7eb2e8f9f7	621
<>	144:ef7eb2e8f9f7	622	#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) \|\| \
<>	144:ef7eb2e8f9f7	623	((MODE) == TIM_OCMODE_PWM2))
<>	144:ef7eb2e8f9f7	624
<>	144:ef7eb2e8f9f7	625	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) \|\| \
<>	144:ef7eb2e8f9f7	626	((MODE) == TIM_OCMODE_ACTIVE) \|\| \
<>	144:ef7eb2e8f9f7	627	((MODE) == TIM_OCMODE_INACTIVE) \|\| \
<>	144:ef7eb2e8f9f7	628	((MODE) == TIM_OCMODE_TOGGLE) \|\| \
<>	144:ef7eb2e8f9f7	629	((MODE) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
<>	144:ef7eb2e8f9f7	630	((MODE) == TIM_OCMODE_FORCED_INACTIVE))
<>	144:ef7eb2e8f9f7	631
<>	144:ef7eb2e8f9f7	632	#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) \|\| \
<>	144:ef7eb2e8f9f7	633	((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
<>	144:ef7eb2e8f9f7	634
<>	144:ef7eb2e8f9f7	635	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	636	((MODE) == TIM_SLAVEMODE_RESET) \|\| \
<>	144:ef7eb2e8f9f7	637	((MODE) == TIM_SLAVEMODE_GATED) \|\| \
<>	144:ef7eb2e8f9f7	638	((MODE) == TIM_SLAVEMODE_TRIGGER) \|\| \
<>	144:ef7eb2e8f9f7	639	((MODE) == TIM_SLAVEMODE_EXTERNAL1))
<>	144:ef7eb2e8f9f7	640
<>	157:ff67d9f36b67	641	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
<>	144:ef7eb2e8f9f7	642
<>	144:ef7eb2e8f9f7	643	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) \|\| \
<>	144:ef7eb2e8f9f7	644	((BASE) == TIM_DMABASE_CR2) \|\| \
<>	144:ef7eb2e8f9f7	645	((BASE) == TIM_DMABASE_SMCR) \|\| \
<>	144:ef7eb2e8f9f7	646	((BASE) == TIM_DMABASE_DIER) \|\| \
<>	144:ef7eb2e8f9f7	647	((BASE) == TIM_DMABASE_SR) \|\| \
<>	144:ef7eb2e8f9f7	648	((BASE) == TIM_DMABASE_EGR) \|\| \
<>	144:ef7eb2e8f9f7	649	((BASE) == TIM_DMABASE_CCMR1) \|\| \
<>	144:ef7eb2e8f9f7	650	((BASE) == TIM_DMABASE_CCMR2) \|\| \
<>	144:ef7eb2e8f9f7	651	((BASE) == TIM_DMABASE_CCER) \|\| \
<>	144:ef7eb2e8f9f7	652	((BASE) == TIM_DMABASE_CNT) \|\| \
<>	144:ef7eb2e8f9f7	653	((BASE) == TIM_DMABASE_PSC) \|\| \
<>	144:ef7eb2e8f9f7	654	((BASE) == TIM_DMABASE_ARR) \|\| \
<>	144:ef7eb2e8f9f7	655	((BASE) == TIM_DMABASE_RCR) \|\| \
<>	144:ef7eb2e8f9f7	656	((BASE) == TIM_DMABASE_CCR1) \|\| \
<>	144:ef7eb2e8f9f7	657	((BASE) == TIM_DMABASE_CCR2) \|\| \
<>	144:ef7eb2e8f9f7	658	((BASE) == TIM_DMABASE_CCR3) \|\| \
<>	144:ef7eb2e8f9f7	659	((BASE) == TIM_DMABASE_CCR4) \|\| \
<>	144:ef7eb2e8f9f7	660	((BASE) == TIM_DMABASE_BDTR) \|\| \
<>	144:ef7eb2e8f9f7	661	((BASE) == TIM_DMABASE_DCR) \|\| \
<>	144:ef7eb2e8f9f7	662	((BASE) == TIM_DMABASE_OR))
<>	144:ef7eb2e8f9f7	663
<>	144:ef7eb2e8f9f7	664	#endif /* STM32F373xC \|\| STM32F378xx */
<>	144:ef7eb2e8f9f7	665
<>	144:ef7eb2e8f9f7	666
<>	144:ef7eb2e8f9f7	667
<>	144:ef7eb2e8f9f7	668	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	669	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
<>	144:ef7eb2e8f9f7	670	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
<>	144:ef7eb2e8f9f7	671	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	672
<>	144:ef7eb2e8f9f7	673	#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
<>	144:ef7eb2e8f9f7	674	((CHANNEL) == TIM_CHANNEL_2) \|\| \
<>	144:ef7eb2e8f9f7	675	((CHANNEL) == TIM_CHANNEL_3) \|\| \
<>	144:ef7eb2e8f9f7	676	((CHANNEL) == TIM_CHANNEL_4) \|\| \
<>	144:ef7eb2e8f9f7	677	((CHANNEL) == TIM_CHANNEL_5) \|\| \
<>	144:ef7eb2e8f9f7	678	((CHANNEL) == TIM_CHANNEL_6) \|\| \
<>	144:ef7eb2e8f9f7	679	((CHANNEL) == TIM_CHANNEL_ALL))
<>	144:ef7eb2e8f9f7	680
<>	144:ef7eb2e8f9f7	681	#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
<>	144:ef7eb2e8f9f7	682	((CHANNEL) == TIM_CHANNEL_2))
<>	144:ef7eb2e8f9f7	683
<>	144:ef7eb2e8f9f7	684	#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
<>	144:ef7eb2e8f9f7	685	((CHANNEL) == TIM_CHANNEL_2) \|\| \
<>	144:ef7eb2e8f9f7	686	((CHANNEL) == TIM_CHANNEL_3))
<>	144:ef7eb2e8f9f7	687
<>	144:ef7eb2e8f9f7	688	#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) \|\| \
<>	144:ef7eb2e8f9f7	689	((MODE) == TIM_OCMODE_PWM2) \|\| \
<>	144:ef7eb2e8f9f7	690	((MODE) == TIM_OCMODE_COMBINED_PWM1) \|\| \
<>	144:ef7eb2e8f9f7	691	((MODE) == TIM_OCMODE_COMBINED_PWM2) \|\| \
<>	144:ef7eb2e8f9f7	692	((MODE) == TIM_OCMODE_ASSYMETRIC_PWM1) \|\| \
<>	144:ef7eb2e8f9f7	693	((MODE) == TIM_OCMODE_ASSYMETRIC_PWM2))
<>	144:ef7eb2e8f9f7	694
<>	144:ef7eb2e8f9f7	695	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) \|\| \
<>	144:ef7eb2e8f9f7	696	((MODE) == TIM_OCMODE_ACTIVE) \|\| \
<>	144:ef7eb2e8f9f7	697	((MODE) == TIM_OCMODE_INACTIVE) \|\| \
<>	144:ef7eb2e8f9f7	698	((MODE) == TIM_OCMODE_TOGGLE) \|\| \
<>	144:ef7eb2e8f9f7	699	((MODE) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
<>	144:ef7eb2e8f9f7	700	((MODE) == TIM_OCMODE_FORCED_INACTIVE) \|\| \
<>	144:ef7eb2e8f9f7	701	((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM1) \|\| \
<>	144:ef7eb2e8f9f7	702	((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM2))
<>	144:ef7eb2e8f9f7	703
<>	144:ef7eb2e8f9f7	704	#define IS_TIM_CLEARINPUT_SOURCE(MODE) (((MODE) == TIM_CLEARINPUTSOURCE_ETR) \|\| \
<>	144:ef7eb2e8f9f7	705	((MODE) == TIM_CLEARINPUTSOURCE_OCREFCLR) \|\| \
<>	144:ef7eb2e8f9f7	706	((MODE) == TIM_CLEARINPUTSOURCE_NONE))
<>	144:ef7eb2e8f9f7	707
<>	157:ff67d9f36b67	708	#define IS_TIM_BREAK_FILTER(BRKFILTER) ((BRKFILTER) <= 0xFU)
<>	144:ef7eb2e8f9f7	709
<>	144:ef7eb2e8f9f7	710	#define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_BREAK2_ENABLE) \|\| \
<>	144:ef7eb2e8f9f7	711	((STATE) == TIM_BREAK2_DISABLE))
<>	144:ef7eb2e8f9f7	712
<>	144:ef7eb2e8f9f7	713	#define IS_TIM_BREAK2_POLARITY(POLARITY) (((POLARITY) == TIM_BREAK2POLARITY_LOW) \|\| \
<>	144:ef7eb2e8f9f7	714	((POLARITY) == TIM_BREAK2POLARITY_HIGH))
<>	144:ef7eb2e8f9f7	715
<>	144:ef7eb2e8f9f7	716	#define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2_RESET) \|\| \
<>	144:ef7eb2e8f9f7	717	((SOURCE) == TIM_TRGO2_ENABLE) \|\| \
<>	144:ef7eb2e8f9f7	718	((SOURCE) == TIM_TRGO2_UPDATE) \|\| \
<>	144:ef7eb2e8f9f7	719	((SOURCE) == TIM_TRGO2_OC1) \|\| \
<>	144:ef7eb2e8f9f7	720	((SOURCE) == TIM_TRGO2_OC1REF) \|\| \
<>	144:ef7eb2e8f9f7	721	((SOURCE) == TIM_TRGO2_OC2REF) \|\| \
<>	144:ef7eb2e8f9f7	722	((SOURCE) == TIM_TRGO2_OC3REF) \|\| \
<>	144:ef7eb2e8f9f7	723	((SOURCE) == TIM_TRGO2_OC3REF) \|\| \
<>	144:ef7eb2e8f9f7	724	((SOURCE) == TIM_TRGO2_OC4REF) \|\| \
<>	144:ef7eb2e8f9f7	725	((SOURCE) == TIM_TRGO2_OC5REF) \|\| \
<>	144:ef7eb2e8f9f7	726	((SOURCE) == TIM_TRGO2_OC6REF) \|\| \
<>	144:ef7eb2e8f9f7	727	((SOURCE) == TIM_TRGO2_OC4REF_RISINGFALLING) \|\| \
<>	144:ef7eb2e8f9f7	728	((SOURCE) == TIM_TRGO2_OC6REF_RISINGFALLING) \|\| \
<>	144:ef7eb2e8f9f7	729	((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) \|\| \
<>	144:ef7eb2e8f9f7	730	((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) \|\| \
<>	144:ef7eb2e8f9f7	731	((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) \|\| \
<>	144:ef7eb2e8f9f7	732	((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
<>	144:ef7eb2e8f9f7	733
<>	144:ef7eb2e8f9f7	734	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	735	((MODE) == TIM_SLAVEMODE_RESET) \|\| \
<>	144:ef7eb2e8f9f7	736	((MODE) == TIM_SLAVEMODE_GATED) \|\| \
<>	144:ef7eb2e8f9f7	737	((MODE) == TIM_SLAVEMODE_TRIGGER) \|\| \
<>	144:ef7eb2e8f9f7	738	((MODE) == TIM_SLAVEMODE_EXTERNAL1) \|\| \
<>	144:ef7eb2e8f9f7	739	((MODE) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
<>	144:ef7eb2e8f9f7	740
<>	157:ff67d9f36b67	741	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFE00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
<>	144:ef7eb2e8f9f7	742
<>	144:ef7eb2e8f9f7	743	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) \|\| \
<>	144:ef7eb2e8f9f7	744	((BASE) == TIM_DMABASE_CR2) \|\| \
<>	144:ef7eb2e8f9f7	745	((BASE) == TIM_DMABASE_SMCR) \|\| \
<>	144:ef7eb2e8f9f7	746	((BASE) == TIM_DMABASE_DIER) \|\| \
<>	144:ef7eb2e8f9f7	747	((BASE) == TIM_DMABASE_SR) \|\| \
<>	144:ef7eb2e8f9f7	748	((BASE) == TIM_DMABASE_EGR) \|\| \
<>	144:ef7eb2e8f9f7	749	((BASE) == TIM_DMABASE_CCMR1) \|\| \
<>	144:ef7eb2e8f9f7	750	((BASE) == TIM_DMABASE_CCMR2) \|\| \
<>	144:ef7eb2e8f9f7	751	((BASE) == TIM_DMABASE_CCER) \|\| \
<>	144:ef7eb2e8f9f7	752	((BASE) == TIM_DMABASE_CNT) \|\| \
<>	144:ef7eb2e8f9f7	753	((BASE) == TIM_DMABASE_PSC) \|\| \
<>	144:ef7eb2e8f9f7	754	((BASE) == TIM_DMABASE_ARR) \|\| \
<>	144:ef7eb2e8f9f7	755	((BASE) == TIM_DMABASE_RCR) \|\| \
<>	144:ef7eb2e8f9f7	756	((BASE) == TIM_DMABASE_CCR1) \|\| \
<>	144:ef7eb2e8f9f7	757	((BASE) == TIM_DMABASE_CCR2) \|\| \
<>	144:ef7eb2e8f9f7	758	((BASE) == TIM_DMABASE_CCR3) \|\| \
<>	144:ef7eb2e8f9f7	759	((BASE) == TIM_DMABASE_CCR4) \|\| \
<>	144:ef7eb2e8f9f7	760	((BASE) == TIM_DMABASE_BDTR) \|\| \
<>	144:ef7eb2e8f9f7	761	((BASE) == TIM_DMABASE_CCMR3) \|\| \
<>	144:ef7eb2e8f9f7	762	((BASE) == TIM_DMABASE_CCR5) \|\| \
<>	144:ef7eb2e8f9f7	763	((BASE) == TIM_DMABASE_CCR6) \|\| \
<>	144:ef7eb2e8f9f7	764	((BASE) == TIM_DMABASE_OR))
<>	144:ef7eb2e8f9f7	765
<>	144:ef7eb2e8f9f7	766	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	767	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
<>	144:ef7eb2e8f9f7	768	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
<>	144:ef7eb2e8f9f7	769	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	770
<>	144:ef7eb2e8f9f7	771	#if defined(STM32F302xE) \|\| \
<>	144:ef7eb2e8f9f7	772	defined(STM32F302xC) \|\| \
<>	157:ff67d9f36b67	773	defined(STM32F303x8) \|\| defined(STM32F328xx) \|\| \
<>	144:ef7eb2e8f9f7	774	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	775
<>	144:ef7eb2e8f9f7	776	#define IS_TIM_REMAP(REMAP) (((REMAP) == TIM_TIM1_ADC1_NONE) \|\|\
<>	144:ef7eb2e8f9f7	777	((REMAP) == TIM_TIM1_ADC1_AWD1) \|\|\
<>	144:ef7eb2e8f9f7	778	((REMAP) == TIM_TIM1_ADC1_AWD2) \|\|\
<>	144:ef7eb2e8f9f7	779	((REMAP) == TIM_TIM1_ADC1_AWD3) \|\|\
<>	144:ef7eb2e8f9f7	780	((REMAP) == TIM_TIM16_GPIO) \|\|\
<>	144:ef7eb2e8f9f7	781	((REMAP) == TIM_TIM16_RTC) \|\|\
<>	144:ef7eb2e8f9f7	782	((REMAP) == TIM_TIM16_HSE) \|\|\
<>	144:ef7eb2e8f9f7	783	((REMAP) == TIM_TIM16_MCO))
<>	144:ef7eb2e8f9f7	784
<>	144:ef7eb2e8f9f7	785	#endif /* STM32F302xE \|\| */
<>	144:ef7eb2e8f9f7	786	/* STM32F302xC \|\| */
<>	157:ff67d9f36b67	787	/* STM32F303x8 \|\| STM32F328xx \|\| */
<>	144:ef7eb2e8f9f7	788	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx \|\| */
<>	144:ef7eb2e8f9f7	789
<>	157:ff67d9f36b67	790	#if defined(STM32F334x8)
<>	157:ff67d9f36b67	791	#define IS_TIM_REMAP(REMAP1) (((REMAP1) == TIM_TIM1_ADC1_NONE) \|\|\
<>	157:ff67d9f36b67	792	((REMAP1) == TIM_TIM1_ADC1_AWD1) \|\|\
<>	157:ff67d9f36b67	793	((REMAP1) == TIM_TIM1_ADC1_AWD2) \|\|\
<>	157:ff67d9f36b67	794	((REMAP1) == TIM_TIM1_ADC1_AWD3) \|\|\
<>	157:ff67d9f36b67	795	((REMAP1) == TIM_TIM16_GPIO) \|\|\
<>	157:ff67d9f36b67	796	((REMAP1) == TIM_TIM16_RTC) \|\|\
<>	157:ff67d9f36b67	797	((REMAP1) == TIM_TIM16_HSE) \|\|\
<>	157:ff67d9f36b67	798	((REMAP1) == TIM_TIM16_MCO))
<>	157:ff67d9f36b67	799
<>	157:ff67d9f36b67	800	#define IS_TIM_REMAP2(REMAP2) (((REMAP2) == TIM_TIM1_ADC2_NONE) \|\|\
<>	157:ff67d9f36b67	801	((REMAP2) == TIM_TIM1_ADC2_AWD1) \|\|\
<>	157:ff67d9f36b67	802	((REMAP2) == TIM_TIM1_ADC2_AWD2) \|\|\
<>	157:ff67d9f36b67	803	((REMAP2) == TIM_TIM1_ADC2_AWD3) \|\|\
<>	157:ff67d9f36b67	804	((REMAP2) == TIM_TIM16_NONE))
<>	157:ff67d9f36b67	805
<>	157:ff67d9f36b67	806	#endif /* STM32F334x8 */
<>	157:ff67d9f36b67	807
<>	144:ef7eb2e8f9f7	808	#if defined(STM32F303xC) \|\| defined(STM32F358xx)
<>	144:ef7eb2e8f9f7	809
<>	144:ef7eb2e8f9f7	810	#define IS_TIM_REMAP(REMAP1) (((REMAP1) == TIM_TIM1_ADC1_NONE) \|\|\
<>	144:ef7eb2e8f9f7	811	((REMAP1) == TIM_TIM1_ADC1_AWD1) \|\|\
<>	144:ef7eb2e8f9f7	812	((REMAP1) == TIM_TIM1_ADC1_AWD2) \|\|\
<>	144:ef7eb2e8f9f7	813	((REMAP1) == TIM_TIM1_ADC1_AWD3) \|\|\
<>	144:ef7eb2e8f9f7	814	((REMAP1) == TIM_TIM8_ADC2_NONE) \|\|\
<>	144:ef7eb2e8f9f7	815	((REMAP1) == TIM_TIM8_ADC2_AWD1) \|\|\
<>	144:ef7eb2e8f9f7	816	((REMAP1) == TIM_TIM8_ADC2_AWD2) \|\|\
<>	144:ef7eb2e8f9f7	817	((REMAP1) == TIM_TIM8_ADC2_AWD3) \|\|\
<>	144:ef7eb2e8f9f7	818	((REMAP1) == TIM_TIM16_GPIO) \|\|\
<>	144:ef7eb2e8f9f7	819	((REMAP1) == TIM_TIM16_RTC) \|\|\
<>	144:ef7eb2e8f9f7	820	((REMAP1) == TIM_TIM16_HSE) \|\|\
<>	144:ef7eb2e8f9f7	821	((REMAP1) == TIM_TIM16_MCO))
<>	144:ef7eb2e8f9f7	822
<>	144:ef7eb2e8f9f7	823	#define IS_TIM_REMAP2(REMAP2) (((REMAP2) == TIM_TIM1_ADC4_NONE) \|\|\
<>	144:ef7eb2e8f9f7	824	((REMAP2) == TIM_TIM1_ADC4_AWD1) \|\|\
<>	144:ef7eb2e8f9f7	825	((REMAP2) == TIM_TIM1_ADC4_AWD2) \|\|\
<>	144:ef7eb2e8f9f7	826	((REMAP2) == TIM_TIM1_ADC4_AWD3) \|\|\
<>	144:ef7eb2e8f9f7	827	((REMAP2) == TIM_TIM8_ADC3_NONE) \|\|\
<>	144:ef7eb2e8f9f7	828	((REMAP2) == TIM_TIM8_ADC3_AWD1) \|\|\
<>	144:ef7eb2e8f9f7	829	((REMAP2) == TIM_TIM8_ADC3_AWD2) \|\|\
<>	144:ef7eb2e8f9f7	830	((REMAP2) == TIM_TIM8_ADC3_AWD3) \|\|\
<>	144:ef7eb2e8f9f7	831	((REMAP2) == TIM_TIM16_NONE))
<>	144:ef7eb2e8f9f7	832
<>	144:ef7eb2e8f9f7	833	#endif /* STM32F303xC \|\| STM32F358xx */
<>	144:ef7eb2e8f9f7	834
<>	144:ef7eb2e8f9f7	835	#if defined(STM32F303xE) \|\| defined(STM32F398xx)
<>	144:ef7eb2e8f9f7	836
<>	144:ef7eb2e8f9f7	837	#define IS_TIM_REMAP(REMAP1) (((REMAP1) == TIM_TIM1_ADC1_NONE) \|\|\
<>	144:ef7eb2e8f9f7	838	((REMAP1) == TIM_TIM1_ADC1_AWD1) \|\|\
<>	144:ef7eb2e8f9f7	839	((REMAP1) == TIM_TIM1_ADC1_AWD2) \|\|\
<>	144:ef7eb2e8f9f7	840	((REMAP1) == TIM_TIM1_ADC1_AWD3) \|\|\
<>	144:ef7eb2e8f9f7	841	((REMAP1) == TIM_TIM8_ADC2_NONE) \|\|\
<>	144:ef7eb2e8f9f7	842	((REMAP1) == TIM_TIM8_ADC2_AWD1) \|\|\
<>	144:ef7eb2e8f9f7	843	((REMAP1) == TIM_TIM8_ADC2_AWD2) \|\|\
<>	144:ef7eb2e8f9f7	844	((REMAP1) == TIM_TIM8_ADC2_AWD3) \|\|\
<>	144:ef7eb2e8f9f7	845	((REMAP1) == TIM_TIM16_GPIO) \|\|\
<>	144:ef7eb2e8f9f7	846	((REMAP1) == TIM_TIM16_RTC) \|\|\
<>	144:ef7eb2e8f9f7	847	((REMAP1) == TIM_TIM16_HSE) \|\|\
<>	144:ef7eb2e8f9f7	848	((REMAP1) == TIM_TIM16_MCO) \|\|\
<>	144:ef7eb2e8f9f7	849	((REMAP1) == TIM_TIM20_ADC3_NONE) \|\|\
<>	144:ef7eb2e8f9f7	850	((REMAP1) == TIM_TIM20_ADC3_AWD1) \|\|\
<>	144:ef7eb2e8f9f7	851	((REMAP1) == TIM_TIM20_ADC3_AWD2) \|\|\
<>	144:ef7eb2e8f9f7	852	((REMAP1) == TIM_TIM20_ADC3_AWD3))
<>	144:ef7eb2e8f9f7	853
<>	144:ef7eb2e8f9f7	854	#define IS_TIM_REMAP2(REMAP2) (((REMAP2) == TIM_TIM1_ADC4_NONE) \|\|\
<>	144:ef7eb2e8f9f7	855	((REMAP2) == TIM_TIM1_ADC4_AWD1) \|\|\
<>	144:ef7eb2e8f9f7	856	((REMAP2) == TIM_TIM1_ADC4_AWD2) \|\|\
<>	144:ef7eb2e8f9f7	857	((REMAP2) == TIM_TIM1_ADC4_AWD3) \|\|\
<>	144:ef7eb2e8f9f7	858	((REMAP2) == TIM_TIM8_ADC3_NONE) \|\|\
<>	144:ef7eb2e8f9f7	859	((REMAP2) == TIM_TIM8_ADC3_AWD1) \|\|\
<>	144:ef7eb2e8f9f7	860	((REMAP2) == TIM_TIM8_ADC3_AWD2) \|\|\
<>	144:ef7eb2e8f9f7	861	((REMAP2) == TIM_TIM8_ADC3_AWD3) \|\|\
<>	144:ef7eb2e8f9f7	862	((REMAP2) == TIM_TIM16_NONE) \|\|\
<>	144:ef7eb2e8f9f7	863	((REMAP2) == TIM_TIM20_ADC4_NONE) \|\|\
<>	144:ef7eb2e8f9f7	864	((REMAP2) == TIM_TIM20_ADC4_AWD1) \|\|\
<>	144:ef7eb2e8f9f7	865	((REMAP2) == TIM_TIM20_ADC4_AWD2) \|\|\
<>	144:ef7eb2e8f9f7	866	((REMAP2) == TIM_TIM20_ADC4_AWD3))
<>	144:ef7eb2e8f9f7	867
<>	144:ef7eb2e8f9f7	868	#endif /* STM32F303xE \|\| STM32F398xx */
<>	144:ef7eb2e8f9f7	869
<>	144:ef7eb2e8f9f7	870	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
<>	144:ef7eb2e8f9f7	871
<>	144:ef7eb2e8f9f7	872	#define IS_TIM_REMAP(REMAP) (((REMAP) == TIM_TIM2_TIM8_TRGO) \|\|\
<>	144:ef7eb2e8f9f7	873	((REMAP) == TIM_TIM2_ETH_PTP) \|\|\
<>	144:ef7eb2e8f9f7	874	((REMAP) == TIM_TIM2_USBFS_SOF) \|\|\
<>	144:ef7eb2e8f9f7	875	((REMAP) == TIM_TIM2_USBHS_SOF) \|\|\
<>	144:ef7eb2e8f9f7	876	((REMAP) == TIM_TIM14_GPIO) \|\|\
<>	144:ef7eb2e8f9f7	877	((REMAP) == TIM_TIM14_RTC) \|\|\
<>	144:ef7eb2e8f9f7	878	((REMAP) == TIM_TIM14_HSE) \|\|\
<>	144:ef7eb2e8f9f7	879	((REMAP) == TIM_TIM14_MCO))
<>	144:ef7eb2e8f9f7	880
<>	144:ef7eb2e8f9f7	881	#endif /* STM32F373xC \|\| STM32F378xx */
<>	144:ef7eb2e8f9f7	882
<>	144:ef7eb2e8f9f7	883
<>	144:ef7eb2e8f9f7	884	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	885	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
<>	144:ef7eb2e8f9f7	886	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
<>	144:ef7eb2e8f9f7	887	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	888
<>	157:ff67d9f36b67	889	#define IS_TIM_GROUPCH5(OCREF) ((((OCREF) & 0x1FFFFFFFU) == 0x00000000U))
<>	144:ef7eb2e8f9f7	890
<>	144:ef7eb2e8f9f7	891	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	892	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
<>	144:ef7eb2e8f9f7	893	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
<>	144:ef7eb2e8f9f7	894	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	895
<>	157:ff67d9f36b67	896	#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFFU)
<>	144:ef7eb2e8f9f7	897
<>	144:ef7eb2e8f9f7	898	/**
<>	144:ef7eb2e8f9f7	899	* @}
<>	144:ef7eb2e8f9f7	900	*/
<>	144:ef7eb2e8f9f7	901	/* End of private macros -----------------------------------------------------*/
<>	144:ef7eb2e8f9f7	902
<>	144:ef7eb2e8f9f7	903
<>	144:ef7eb2e8f9f7	904	/* Exported macro ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	905	/** @defgroup TIMEx_Exported_Macros TIMEx Exported Macros
<>	144:ef7eb2e8f9f7	906	* @{
<>	144:ef7eb2e8f9f7	907	*/
<>	144:ef7eb2e8f9f7	908
<>	144:ef7eb2e8f9f7	909	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
<>	144:ef7eb2e8f9f7	910	/**
<>	144:ef7eb2e8f9f7	911	* @brief Sets the TIM Capture Compare Register value on runtime without
<>	144:ef7eb2e8f9f7	912	* calling another time ConfigChannel function.
<>	144:ef7eb2e8f9f7	913	* @param __HANDLE__: TIM handle.
<>	144:ef7eb2e8f9f7	914	* @param __CHANNEL__: TIM Channels to be configured.
<>	144:ef7eb2e8f9f7	915	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	916	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	917	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	918	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	919	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	920	* @param __COMPARE__: specifies the Capture Compare register new value.
<>	144:ef7eb2e8f9f7	921	* @retval None
<>	144:ef7eb2e8f9f7	922	*/
<>	144:ef7eb2e8f9f7	923	#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
<>	157:ff67d9f36b67	924	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
<>	144:ef7eb2e8f9f7	925
<>	144:ef7eb2e8f9f7	926	/**
<>	144:ef7eb2e8f9f7	927	* @brief Gets the TIM Capture Compare Register value on runtime
<>	144:ef7eb2e8f9f7	928	* @param __HANDLE__: TIM handle.
<>	144:ef7eb2e8f9f7	929	* @param __CHANNEL__: TIM Channel associated with the capture compare register
<>	144:ef7eb2e8f9f7	930	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	931	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
<>	144:ef7eb2e8f9f7	932	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
<>	144:ef7eb2e8f9f7	933	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
<>	144:ef7eb2e8f9f7	934	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
<>	144:ef7eb2e8f9f7	935	* @retval None
<>	144:ef7eb2e8f9f7	936	*/
<>	144:ef7eb2e8f9f7	937	#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
<>	157:ff67d9f36b67	938	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
<>	157:ff67d9f36b67	939
<>	157:ff67d9f36b67	940	/**
<>	157:ff67d9f36b67	941	* @brief Sets the TIM Output compare preload.
<>	157:ff67d9f36b67	942	* @param __HANDLE__: TIM handle.
<>	157:ff67d9f36b67	943	* @param __CHANNEL__: TIM Channels to be configured.
<>	157:ff67d9f36b67	944	* This parameter can be one of the following values:
<>	157:ff67d9f36b67	945	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	157:ff67d9f36b67	946	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	157:ff67d9f36b67	947	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	157:ff67d9f36b67	948	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	157:ff67d9f36b67	949	* @retval None
<>	157:ff67d9f36b67	950	*/
<>	157:ff67d9f36b67	951	#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
<>	157:ff67d9f36b67	952	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= TIM_CCMR1_OC1PE) :\
<>	157:ff67d9f36b67	953	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= TIM_CCMR1_OC2PE) :\
<>	157:ff67d9f36b67	954	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= TIM_CCMR2_OC3PE) :\
<>	157:ff67d9f36b67	955	((__HANDLE__)->Instance->CCMR2 \|= TIM_CCMR2_OC4PE))
<>	157:ff67d9f36b67	956
<>	157:ff67d9f36b67	957	/**
<>	157:ff67d9f36b67	958	* @brief Resets the TIM Output compare preload.
<>	157:ff67d9f36b67	959	* @param __HANDLE__: TIM handle.
<>	157:ff67d9f36b67	960	* @param __CHANNEL__: TIM Channels to be configured.
<>	157:ff67d9f36b67	961	* This parameter can be one of the following values:
<>	157:ff67d9f36b67	962	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	157:ff67d9f36b67	963	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	157:ff67d9f36b67	964	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	157:ff67d9f36b67	965	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	157:ff67d9f36b67	966	* @retval None
<>	157:ff67d9f36b67	967	*/
<>	157:ff67d9f36b67	968	#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
<>	157:ff67d9f36b67	969	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
<>	157:ff67d9f36b67	970	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
<>	157:ff67d9f36b67	971	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
<>	157:ff67d9f36b67	972	((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE))
<>	157:ff67d9f36b67	973
<>	144:ef7eb2e8f9f7	974	#endif /* STM32F373xC \|\| STM32F378xx */
<>	144:ef7eb2e8f9f7	975
<>	144:ef7eb2e8f9f7	976	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	977	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
<>	144:ef7eb2e8f9f7	978	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
<>	144:ef7eb2e8f9f7	979	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	980	/**
<>	144:ef7eb2e8f9f7	981	* @brief Sets the TIM Capture Compare Register value on runtime without
<>	144:ef7eb2e8f9f7	982	* calling another time ConfigChannel function.
<>	144:ef7eb2e8f9f7	983	* @param __HANDLE__: TIM handle.
<>	144:ef7eb2e8f9f7	984	* @param __CHANNEL__: TIM Channels to be configured.
<>	144:ef7eb2e8f9f7	985	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	986	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	987	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	988	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	989	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	990	* @arg TIM_CHANNEL_5: TIM Channel 5 selected
<>	144:ef7eb2e8f9f7	991	* @arg TIM_CHANNEL_6: TIM Channel 6 selected
<>	144:ef7eb2e8f9f7	992	* @param __COMPARE__: specifies the Capture Compare register new value.
<>	144:ef7eb2e8f9f7	993	* @retval None
<>	144:ef7eb2e8f9f7	994	*/
<>	144:ef7eb2e8f9f7	995	#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
<>	144:ef7eb2e8f9f7	996	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
<>	144:ef7eb2e8f9f7	997	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
<>	144:ef7eb2e8f9f7	998	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
<>	144:ef7eb2e8f9f7	999	((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
<>	144:ef7eb2e8f9f7	1000	((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
<>	144:ef7eb2e8f9f7	1001	((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
<>	144:ef7eb2e8f9f7	1002
<>	144:ef7eb2e8f9f7	1003	/**
<>	144:ef7eb2e8f9f7	1004	* @brief Gets the TIM Capture Compare Register value on runtime
<>	144:ef7eb2e8f9f7	1005	* @param __HANDLE__: TIM handle.
<>	144:ef7eb2e8f9f7	1006	* @param __CHANNEL__: TIM Channel associated with the capture compare register
<>	144:ef7eb2e8f9f7	1007	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1008	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
<>	144:ef7eb2e8f9f7	1009	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
<>	144:ef7eb2e8f9f7	1010	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
<>	144:ef7eb2e8f9f7	1011	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
<>	144:ef7eb2e8f9f7	1012	* @arg TIM_CHANNEL_5: get capture/compare 5 register value
<>	144:ef7eb2e8f9f7	1013	* @arg TIM_CHANNEL_6: get capture/compare 6 register value
<>	144:ef7eb2e8f9f7	1014	* @retval None
<>	144:ef7eb2e8f9f7	1015	*/
<>	144:ef7eb2e8f9f7	1016	#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
<>	144:ef7eb2e8f9f7	1017	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
<>	144:ef7eb2e8f9f7	1018	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
<>	144:ef7eb2e8f9f7	1019	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
<>	144:ef7eb2e8f9f7	1020	((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
<>	144:ef7eb2e8f9f7	1021	((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
<>	144:ef7eb2e8f9f7	1022	((__HANDLE__)->Instance->CCR6))
<>	157:ff67d9f36b67	1023
<>	157:ff67d9f36b67	1024	/**
<>	157:ff67d9f36b67	1025	* @brief Sets the TIM Output compare preload.
<>	157:ff67d9f36b67	1026	* @param __HANDLE__: TIM handle.
<>	157:ff67d9f36b67	1027	* @param __CHANNEL__: TIM Channels to be configured.
<>	157:ff67d9f36b67	1028	* This parameter can be one of the following values:
<>	157:ff67d9f36b67	1029	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	157:ff67d9f36b67	1030	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	157:ff67d9f36b67	1031	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	157:ff67d9f36b67	1032	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	157:ff67d9f36b67	1033	* @arg TIM_CHANNEL_5: TIM Channel 5 selected
<>	157:ff67d9f36b67	1034	* @arg TIM_CHANNEL_6: TIM Channel 6 selected
<>	157:ff67d9f36b67	1035	* @retval None
<>	157:ff67d9f36b67	1036	*/
<>	157:ff67d9f36b67	1037	#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
<>	157:ff67d9f36b67	1038	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= TIM_CCMR1_OC1PE) :\
<>	157:ff67d9f36b67	1039	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= TIM_CCMR1_OC2PE) :\
<>	157:ff67d9f36b67	1040	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= TIM_CCMR2_OC3PE) :\
<>	157:ff67d9f36b67	1041	((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 \|= TIM_CCMR2_OC4PE) :\
<>	157:ff67d9f36b67	1042	((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 \|= TIM_CCMR3_OC5PE) :\
<>	157:ff67d9f36b67	1043	((__HANDLE__)->Instance->CCMR3 \|= TIM_CCMR3_OC6PE))
<>	157:ff67d9f36b67	1044
<>	157:ff67d9f36b67	1045	/**
<>	157:ff67d9f36b67	1046	* @brief Resets the TIM Output compare preload.
<>	157:ff67d9f36b67	1047	* @param __HANDLE__: TIM handle.
<>	157:ff67d9f36b67	1048	* @param __CHANNEL__: TIM Channels to be configured.
<>	157:ff67d9f36b67	1049	* This parameter can be one of the following values:
<>	157:ff67d9f36b67	1050	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	157:ff67d9f36b67	1051	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	157:ff67d9f36b67	1052	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	157:ff67d9f36b67	1053	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	157:ff67d9f36b67	1054	* @arg TIM_CHANNEL_5: TIM Channel 5 selected
<>	157:ff67d9f36b67	1055	* @arg TIM_CHANNEL_6: TIM Channel 6 selected
<>	157:ff67d9f36b67	1056	* @retval None
<>	157:ff67d9f36b67	1057	*/
<>	157:ff67d9f36b67	1058	#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
<>	157:ff67d9f36b67	1059	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
<>	157:ff67d9f36b67	1060	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
<>	157:ff67d9f36b67	1061	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
<>	157:ff67d9f36b67	1062	((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\
<>	157:ff67d9f36b67	1063	((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\
<>	157:ff67d9f36b67	1064	((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE))
<>	157:ff67d9f36b67	1065
<>	144:ef7eb2e8f9f7	1066	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	1067	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
<>	144:ef7eb2e8f9f7	1068	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
<>	144:ef7eb2e8f9f7	1069	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	1070	/**
<>	144:ef7eb2e8f9f7	1071	* @}
<>	144:ef7eb2e8f9f7	1072	*/
<>	144:ef7eb2e8f9f7	1073
<>	144:ef7eb2e8f9f7	1074	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1075	/** @addtogroup TIMEx_Exported_Functions
<>	144:ef7eb2e8f9f7	1076	* @{
<>	144:ef7eb2e8f9f7	1077	*/
<>	144:ef7eb2e8f9f7	1078
<>	144:ef7eb2e8f9f7	1079	/** @addtogroup TIMEx_Exported_Functions_Group1
<>	144:ef7eb2e8f9f7	1080	* @{
<>	144:ef7eb2e8f9f7	1081	*/
<>	144:ef7eb2e8f9f7	1082	/* Timer Hall Sensor functions **********************************************/
<>	144:ef7eb2e8f9f7	1083	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef htim, TIM_HallSensor_InitTypeDef sConfig);
<>	144:ef7eb2e8f9f7	1084	HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1085
<>	144:ef7eb2e8f9f7	1086	void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1087	void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1088
<>	144:ef7eb2e8f9f7	1089	/* Blocking mode: Polling */
<>	144:ef7eb2e8f9f7	1090	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1091	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1092	/* Non-Blocking mode: Interrupt */
<>	144:ef7eb2e8f9f7	1093	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1094	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1095	/* Non-Blocking mode: DMA */
<>	144:ef7eb2e8f9f7	1096	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
<>	144:ef7eb2e8f9f7	1097	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1098	/**
<>	144:ef7eb2e8f9f7	1099	* @}
<>	144:ef7eb2e8f9f7	1100	*/
<>	144:ef7eb2e8f9f7	1101
<>	144:ef7eb2e8f9f7	1102	/** @addtogroup TIMEx_Exported_Functions_Group2
<>	144:ef7eb2e8f9f7	1103	* @{
<>	144:ef7eb2e8f9f7	1104	*/
<>	144:ef7eb2e8f9f7	1105	/* Timer Complementary Output Compare functions *****************************/
<>	144:ef7eb2e8f9f7	1106	/* Blocking mode: Polling */
<>	144:ef7eb2e8f9f7	1107	HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1108	HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1109
<>	144:ef7eb2e8f9f7	1110	/* Non-Blocking mode: Interrupt */
<>	144:ef7eb2e8f9f7	1111	HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1112	HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1113
<>	144:ef7eb2e8f9f7	1114	/* Non-Blocking mode: DMA */
<>	144:ef7eb2e8f9f7	1115	HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
<>	144:ef7eb2e8f9f7	1116	HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1117	/**
<>	144:ef7eb2e8f9f7	1118	* @}
<>	144:ef7eb2e8f9f7	1119	*/
<>	144:ef7eb2e8f9f7	1120
<>	144:ef7eb2e8f9f7	1121	/** @addtogroup TIMEx_Exported_Functions_Group3
<>	144:ef7eb2e8f9f7	1122	* @{
<>	144:ef7eb2e8f9f7	1123	*/
<>	144:ef7eb2e8f9f7	1124	/* Timer Complementary PWM functions ****************************************/
<>	144:ef7eb2e8f9f7	1125	/* Blocking mode: Polling */
<>	144:ef7eb2e8f9f7	1126	HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1127	HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1128
<>	144:ef7eb2e8f9f7	1129	/* Non-Blocking mode: Interrupt */
<>	144:ef7eb2e8f9f7	1130	HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1131	HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1132	/* Non-Blocking mode: DMA */
<>	144:ef7eb2e8f9f7	1133	HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
<>	144:ef7eb2e8f9f7	1134	HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1135	/**
<>	144:ef7eb2e8f9f7	1136	* @}
<>	144:ef7eb2e8f9f7	1137	*/
<>	144:ef7eb2e8f9f7	1138
<>	144:ef7eb2e8f9f7	1139	/** @addtogroup TIMEx_Exported_Functions_Group4
<>	144:ef7eb2e8f9f7	1140	* @{
<>	144:ef7eb2e8f9f7	1141	*/
<>	144:ef7eb2e8f9f7	1142	/* Timer Complementary One Pulse functions **********************************/
<>	144:ef7eb2e8f9f7	1143	/* Blocking mode: Polling */
<>	144:ef7eb2e8f9f7	1144	HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<>	144:ef7eb2e8f9f7	1145	HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<>	144:ef7eb2e8f9f7	1146
<>	144:ef7eb2e8f9f7	1147	/* Non-Blocking mode: Interrupt */
<>	144:ef7eb2e8f9f7	1148	HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<>	144:ef7eb2e8f9f7	1149	HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<>	144:ef7eb2e8f9f7	1150	/**
<>	144:ef7eb2e8f9f7	1151	* @}
<>	144:ef7eb2e8f9f7	1152	*/
<>	144:ef7eb2e8f9f7	1153
<>	144:ef7eb2e8f9f7	1154	/** @addtogroup TIMEx_Exported_Functions_Group5
<>	144:ef7eb2e8f9f7	1155	* @{
<>	144:ef7eb2e8f9f7	1156	*/
<>	144:ef7eb2e8f9f7	1157	/* Extended Control functions ************************************************/
<>	144:ef7eb2e8f9f7	1158	HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
<>	144:ef7eb2e8f9f7	1159	HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
<>	144:ef7eb2e8f9f7	1160	HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
<>	144:ef7eb2e8f9f7	1161	HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef htim, TIM_MasterConfigTypeDef sMasterConfig);
<>	144:ef7eb2e8f9f7	1162	HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef htim, TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig);
<>	144:ef7eb2e8f9f7	1163
<>	144:ef7eb2e8f9f7	1164	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	157:ff67d9f36b67	1165	defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| defined(STM32F334x8)
<>	144:ef7eb2e8f9f7	1166	HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap1, uint32_t Remap2);
<>	144:ef7eb2e8f9f7	1167	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	1168	/* STM32F303xC \|\| STM32F358xx */
<>	144:ef7eb2e8f9f7	1169
<>	144:ef7eb2e8f9f7	1170	#if defined(STM32F302xE) \|\| \
<>	144:ef7eb2e8f9f7	1171	defined(STM32F302xC) \|\| \
<>	157:ff67d9f36b67	1172	defined(STM32F303x8) \|\| defined(STM32F328xx) \|\| \
<>	144:ef7eb2e8f9f7	1173	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx) \|\| \
<>	144:ef7eb2e8f9f7	1174	defined(STM32F373xC) \|\| defined(STM32F378xx)
<>	144:ef7eb2e8f9f7	1175	HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
<>	144:ef7eb2e8f9f7	1176	#endif /* STM32F302xE \|\| */
<>	144:ef7eb2e8f9f7	1177	/* STM32F302xC \|\| */
<>	144:ef7eb2e8f9f7	1178	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
<>	144:ef7eb2e8f9f7	1179	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx \|\| */
<>	144:ef7eb2e8f9f7	1180	/* STM32F373xC \|\| STM32F378xx */
<>	144:ef7eb2e8f9f7	1181
<>	144:ef7eb2e8f9f7	1182	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	1183	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
<>	144:ef7eb2e8f9f7	1184	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
<>	144:ef7eb2e8f9f7	1185	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	1186	HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
<>	144:ef7eb2e8f9f7	1187	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	1188	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
<>	144:ef7eb2e8f9f7	1189	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
<>	144:ef7eb2e8f9f7	1190	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	1191	/**
<>	144:ef7eb2e8f9f7	1192	* @}
<>	144:ef7eb2e8f9f7	1193	*/
<>	144:ef7eb2e8f9f7	1194
<>	144:ef7eb2e8f9f7	1195	/** @addtogroup TIMEx_Exported_Functions_Group6
<>	144:ef7eb2e8f9f7	1196	* @{
<>	144:ef7eb2e8f9f7	1197	*/
<>	144:ef7eb2e8f9f7	1198	/* Extended Callback *********************************************************/
<>	144:ef7eb2e8f9f7	1199	void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1200	void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1201	/**
<>	144:ef7eb2e8f9f7	1202	* @}
<>	144:ef7eb2e8f9f7	1203	*/
<>	144:ef7eb2e8f9f7	1204
<>	144:ef7eb2e8f9f7	1205	/** @addtogroup TIMEx_Exported_Functions_Group7
<>	144:ef7eb2e8f9f7	1206	* @{
<>	144:ef7eb2e8f9f7	1207	*/
<>	144:ef7eb2e8f9f7	1208	/* Extended Peripheral State functions **************************************/
<>	144:ef7eb2e8f9f7	1209	HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1210	/**
<>	144:ef7eb2e8f9f7	1211	* @}
<>	144:ef7eb2e8f9f7	1212	*/
<>	144:ef7eb2e8f9f7	1213
<>	144:ef7eb2e8f9f7	1214	/**
<>	144:ef7eb2e8f9f7	1215	* @}
<>	144:ef7eb2e8f9f7	1216	*/
<>	144:ef7eb2e8f9f7	1217	/* End of exported functions -------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1218
<>	144:ef7eb2e8f9f7	1219	/* Private functions----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1220	/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
<>	144:ef7eb2e8f9f7	1221	* @{
<>	144:ef7eb2e8f9f7	1222	*/
<>	144:ef7eb2e8f9f7	1223	void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	1224	/**
<>	144:ef7eb2e8f9f7	1225	* @}
<>	144:ef7eb2e8f9f7	1226	*/
<>	144:ef7eb2e8f9f7	1227	/* End of private functions --------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1228
<>	144:ef7eb2e8f9f7	1229	/**
<>	144:ef7eb2e8f9f7	1230	* @}
<>	144:ef7eb2e8f9f7	1231	*/
<>	144:ef7eb2e8f9f7	1232
<>	144:ef7eb2e8f9f7	1233	/**
<>	144:ef7eb2e8f9f7	1234	* @}
<>	144:ef7eb2e8f9f7	1235	*/
<>	144:ef7eb2e8f9f7	1236
<>	144:ef7eb2e8f9f7	1237	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	1238	}
<>	144:ef7eb2e8f9f7	1239	#endif
<>	144:ef7eb2e8f9f7	1240
<>	144:ef7eb2e8f9f7	1241
<>	144:ef7eb2e8f9f7	1242	#endif /* __STM32F3xx_HAL_TIM_EX_H */
<>	144:ef7eb2e8f9f7	1243
<>	144:ef7eb2e8f9f7	1244	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Repository toolbox

Repository details

Type:	Library
Created:	02 May 2018
Imports:	22
Forks:	0
Commits:	180
Dependents:	11
Dependencies:	0
Followers:	9

This repository is Public (Unlisted).

Important changes to repositories hosted on mbed.com

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_tim_ex.h@179:97f825502e2a, 2018-05-02 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Important changes to repositories hosted on mbed.com

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_tim_ex.h@179:97f825502e2a, 2018-05-02 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Access Warning