Ben Katz
/
mbed-dev_spine
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Dependents: SPIne CH_Communicatuin_Test CH_Communicatuin_Test2 MCP_SPIne ... more
Fork of
mbed-dev-f303
by 
Ben Katz
Revision 135:eec55f8ee438, committed 2016-05-23
- Comitter:
- mbed_official
- Date:
- Mon May 23 10:45:11 2016 +0100
- Parent:
- 134:c5ba39804b6b
- Child:
- 136:5728e9819171
- Commit message:
- Synchronized with git revision 275100e9694eca820b966a3fb9abc8b5f3dadff2
Full URL: https://github.com/mbedmicro/mbed/commit/275100e9694eca820b966a3fb9abc8b5f3dadff2/
Changed in this revision
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/stm32f042x6.h Mon May 23 10:00:12 2016 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/stm32f042x6.h Mon May 23 10:45:11 2016 +0100 @@ -672,7 +672,7 @@ #define IWDG ((IWDG_TypeDef *) IWDG_BASE) #define USART2 ((USART_TypeDef *) USART2_BASE) #define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define CAN ((CAN_TypeDef *) CAN_BASE) +#define CAN1 ((CAN_TypeDef *) CAN_BASE) #define CRS ((CRS_TypeDef *) CRS_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) #define CEC ((CEC_TypeDef *) CEC_BASE)
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/stm32f072xb.h Mon May 23 10:00:12 2016 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/stm32f072xb.h Mon May 23 10:45:11 2016 +0100 @@ -732,7 +732,7 @@ #define USART4 ((USART_TypeDef *) USART4_BASE) #define I2C1 ((I2C_TypeDef *) I2C1_BASE) #define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define CAN ((CAN_TypeDef *) CAN_BASE) +#define CAN1 ((CAN_TypeDef *) CAN_BASE) #define CRS ((CRS_TypeDef *) CRS_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) #define DAC ((DAC_TypeDef *) DAC_BASE)
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/stm32f091xc.h Mon May 23 10:00:12 2016 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/stm32f091xc.h Mon May 23 10:45:11 2016 +0100 @@ -708,7 +708,7 @@ #define USART5 ((USART_TypeDef *) USART5_BASE) #define I2C1 ((I2C_TypeDef *) I2C1_BASE) #define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define CAN ((CAN_TypeDef *) CAN_BASE) +#define CAN1 ((CAN_TypeDef *) CAN_BASE) #define CRS ((CRS_TypeDef *) CRS_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) #define DAC ((DAC_TypeDef *) DAC_BASE)
--- a/targets/hal/TARGET_STM/TARGET_STM32F0/PeripheralPins.h Mon May 23 10:00:12 2016 +0100 +++ b/targets/hal/TARGET_STM/TARGET_STM32F0/PeripheralPins.h Mon May 23 10:45:11 2016 +0100 @@ -63,4 +63,9 @@ extern const PinMap PinMap_SPI_SCLK[]; extern const PinMap PinMap_SPI_SSEL[]; +//*** CAN *** + +extern const PinMap PinMap_CAN_RD[]; +extern const PinMap PinMap_CAN_TD[]; + #endif
--- a/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PeripheralNames.h Mon May 23 10:00:12 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PeripheralNames.h Mon May 23 10:45:11 2016 +0100
@@ -68,6 +68,10 @@
PWM_17 = (int)TIM17_BASE
} PWMName;
+typedef enum {
+ CAN_1 = (int)CAN_BASE
+} CANName;
+
#ifdef __cplusplus
}
#endif
--- a/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PeripheralPins.c Mon May 23 10:00:12 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PeripheralPins.c Mon May 23 10:45:11 2016 +0100
@@ -146,3 +146,14 @@
// {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)},
{NC, NC, 0}
};
+
+const PinMap PinMap_CAN_RD[] = {
+// {PB_8 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_CAN)},
+ {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_CAN)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_CAN_TD[] = {
+ {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_CAN)},
+ {NC, NC, 0}
+};
--- a/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device.h Mon May 23 10:00:12 2016 +0100 +++ b/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device.h Mon May 23 10:45:11 2016 +0100 @@ -54,6 +54,8 @@ #define DEVICE_SLEEP 1 +#define DEVICE_CAN 1 + //======================================= #define DEVICE_SEMIHOST 0
--- a/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/objects.h Mon May 23 10:00:12 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/objects.h Mon May 23 10:45:11 2016 +0100
@@ -95,6 +95,11 @@
uint32_t pulse;
};
+struct can_s {
+ CANName can;
+ int index;
+};
+
#include "gpio_object.h"
#ifdef __cplusplus
--- a/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PeripheralNames.h Mon May 23 10:00:12 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PeripheralNames.h Mon May 23 10:45:11 2016 +0100
@@ -75,6 +75,10 @@
PWM_17 = (int)TIM17_BASE
} PWMName;
+typedef enum {
+ CAN_1 = (int)CAN_BASE
+} CANName;
+
#ifdef __cplusplus
}
#endif
--- a/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PeripheralPins.c Mon May 23 10:00:12 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PeripheralPins.c Mon May 23 10:45:11 2016 +0100
@@ -196,3 +196,15 @@
{PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
{NC, NC, 0}
};
+
+const PinMap PinMap_CAN_RD[] = {
+ {PB_8 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_CAN)},
+ {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_CAN)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_CAN_TD[] = {
+ {PB_9 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_CAN)},
+ {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_CAN)},
+ {NC, NC, 0}
+};
--- a/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device.h Mon May 23 10:00:12 2016 +0100 +++ b/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device.h Mon May 23 10:45:11 2016 +0100 @@ -54,6 +54,8 @@ #define DEVICE_SLEEP 1 +#define DEVICE_CAN 1 + //======================================= #define DEVICE_SEMIHOST 0
--- a/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/objects.h Mon May 23 10:00:12 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/objects.h Mon May 23 10:45:11 2016 +0100
@@ -100,6 +100,11 @@
uint32_t pulse;
};
+struct can_s {
+ CANName can;
+ int index;
+};
+
#include "gpio_object.h"
#ifdef __cplusplus
--- a/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PeripheralNames.h Mon May 23 10:00:12 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PeripheralNames.h Mon May 23 10:45:11 2016 +0100
@@ -79,6 +79,10 @@
PWM_17 = (int)TIM17_BASE
} PWMName;
+typedef enum {
+ CAN_1 = (int)CAN_BASE
+} CANName;
+
#ifdef __cplusplus
}
#endif
--- a/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PeripheralPins.c Mon May 23 10:00:12 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PeripheralPins.c Mon May 23 10:45:11 2016 +0100
@@ -218,3 +218,15 @@
{PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
{NC, NC, 0}
};
+
+const PinMap PinMap_CAN_RD[] = {
+ {PB_8 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_CAN)},
+ {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_CAN)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_CAN_TD[] = {
+ {PB_9 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_CAN)},
+ {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_CAN)},
+ {NC, NC, 0}
+};
--- a/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device.h Mon May 23 10:00:12 2016 +0100 +++ b/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device.h Mon May 23 10:45:11 2016 +0100 @@ -54,6 +54,8 @@ #define DEVICE_SLEEP 1 +#define DEVICE_CAN 1 + //======================================= #define DEVICE_SEMIHOST 0
--- a/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/objects.h Mon May 23 10:00:12 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/objects.h Mon May 23 10:45:11 2016 +0100
@@ -100,6 +100,11 @@
uint32_t pulse;
};
+struct can_s {
+ CANName can;
+ int index;
+};
+
#include "gpio_object.h"
#ifdef __cplusplus