Ben Katz
/
mbed-dev_spine
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Dependents: SPIne CH_Communicatuin_Test CH_Communicatuin_Test2 MCP_SPIne ... more
Fork of
mbed-dev-f303
by 
Ben Katz
Revision 173:e131a1973e81, committed 2017-09-15
- Comitter:
- AnnaBridge
- Date:
- Fri Sep 15 14:59:18 2017 +0100
- Parent:
- 172:7d866c31b3c5
- Child:
- 174:b96e65c34a4d
- Commit message:
- This updates the lib to the mbed lib v 151
Changed in this revision
--- a/mbed.h Thu Aug 31 17:27:04 2017 +0100 +++ b/mbed.h Fri Sep 15 14:59:18 2017 +0100 @@ -16,13 +16,13 @@ #ifndef MBED_H #define MBED_H -#define MBED_LIBRARY_VERSION 150 +#define MBED_LIBRARY_VERSION 151 #if MBED_CONF_RTOS_PRESENT // RTOS present, this is valid only for mbed OS 5 #define MBED_MAJOR_VERSION 5 #define MBED_MINOR_VERSION 5 -#define MBED_PATCH_VERSION 6 +#define MBED_PATCH_VERSION 7 #else // mbed 2
--- a/platform/mbed_application.c Thu Aug 31 17:27:04 2017 +0100
+++ b/platform/mbed_application.c Fri Sep 15 14:59:18 2017 +0100
@@ -44,12 +44,12 @@
static void powerdown_nvic()
{
- int isr_count;
+ int isr_groups_32;
int i;
int j;
- isr_count = (SCnSCB->ICTR & SCnSCB_ICTR_INTLINESNUM_Msk) >> SCnSCB_ICTR_INTLINESNUM_Pos;
- for (i = 0; i < isr_count; i++) {
+ isr_groups_32 = ((SCnSCB->ICTR & SCnSCB_ICTR_INTLINESNUM_Msk) >> SCnSCB_ICTR_INTLINESNUM_Pos) + 1;
+ for (i = 0; i < isr_groups_32; i++) {
NVIC->ICER[i] = 0xFFFFFFFF;
NVIC->ICPR[i] = 0xFFFFFFFF;
for (j = 0; j < 8; j++) {
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/cmsis_nvic.h Thu Aug 31 17:27:04 2017 +0100 +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/cmsis_nvic.h Fri Sep 15 14:59:18 2017 +0100 @@ -39,7 +39,7 @@ #endif /* Symbols defined by the linker script */ -#define NVIC_NUM_VECTORS (16 + 240) // CORE + MCU Peripherals +#define NVIC_NUM_VECTORS (16 + 100) // CORE + MCU Peripherals #define NVIC_RAM_VECTOR_ADDRESS (__VECTOR_RAM) // Vectors positioned at start of RAM #endif
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/device/cmsis_nvic.h Thu Aug 31 17:27:04 2017 +0100 +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/device/cmsis_nvic.h Fri Sep 15 14:59:18 2017 +0100 @@ -39,7 +39,7 @@ #endif /* Symbols defined by the linker script */ -#define NVIC_NUM_VECTORS (16 + 240) // CORE + MCU Peripherals +#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals #define NVIC_RAM_VECTOR_ADDRESS (__VECTOR_RAM) // Vectors positioned at start of RAM #endif
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/device/cmsis_nvic.h Thu Aug 31 17:27:04 2017 +0100 +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/device/cmsis_nvic.h Fri Sep 15 14:59:18 2017 +0100 @@ -39,7 +39,7 @@ #endif /* Symbols defined by the linker script */ -#define NVIC_NUM_VECTORS (16 + 240) // CORE + MCU Peripherals +#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals #define NVIC_RAM_VECTOR_ADDRESS (__VECTOR_RAM) // Vectors positioned at start of RAM #endif
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/device/cmsis_nvic.h Thu Aug 31 17:27:04 2017 +0100 +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/device/cmsis_nvic.h Fri Sep 15 14:59:18 2017 +0100 @@ -39,7 +39,7 @@ #endif /* Symbols defined by the linker script */ -#define NVIC_NUM_VECTORS (16 + 240) // CORE + MCU Peripherals +#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals #define NVIC_RAM_VECTOR_ADDRESS (__VECTOR_RAM) // Vectors positioned at start of RAM #endif
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/cmsis_nvic.h Thu Aug 31 17:27:04 2017 +0100 +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/cmsis_nvic.h Fri Sep 15 14:59:18 2017 +0100 @@ -39,7 +39,7 @@ #endif /* Symbols defined by the linker script */ -#define NVIC_NUM_VECTORS (16 + 240) // CORE + MCU Peripherals +#define NVIC_NUM_VECTORS (16 + 65) // CORE + MCU Peripherals #define NVIC_RAM_VECTOR_ADDRESS (__VECTOR_RAM) // Vectors positioned at start of RAM #endif
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/TARGET_MCU_K22F512/device/cmsis_nvic.h Thu Aug 31 17:27:04 2017 +0100 +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/TARGET_MCU_K22F512/device/cmsis_nvic.h Fri Sep 15 14:59:18 2017 +0100 @@ -39,7 +39,7 @@ #endif /* defined(__CC_ARM) */ /* Symbols defined by the linker script */ -#define NVIC_NUM_VECTORS (16 + 240) // CORE + MCU Peripherals +#define NVIC_NUM_VECTORS (16 + 74) // CORE + MCU Peripherals #define NVIC_RAM_VECTOR_ADDRESS (__VECTOR_RAM) // Vectors positioned at start of RAM #endif
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/device/cmsis_nvic.h Thu Aug 31 17:27:04 2017 +0100 +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/device/cmsis_nvic.h Fri Sep 15 14:59:18 2017 +0100 @@ -39,7 +39,7 @@ #endif /* defined(__CC_ARM) */ /* Symbols defined by the linker script */ -#define NVIC_NUM_VECTORS (16 + 240) // CORE + MCU Peripherals +#define NVIC_NUM_VECTORS (16 + 86) // CORE + MCU Peripherals #define NVIC_RAM_VECTOR_ADDRESS (__VECTOR_RAM) // Vectors positioned at start of RAM #endif
--- a/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_hsusbd.c Thu Aug 31 17:27:04 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_hsusbd.c Fri Sep 15 14:59:18 2017 +0100
@@ -294,7 +294,7 @@
if ((gUsbCmd.bmRequestType & 0x80ul) == 0x80ul) { /* request data transfer direction */
/* Device to host */
switch (gUsbCmd.bRequest) {
- case GET_CONFIGURATION: {
+ case USBD_GET_CONFIGURATION: {
/* Return current configuration setting */
HSUSBD_PrepareCtrlIn((uint8_t *)&g_hsusbd_UsbConfig, 1ul);
@@ -302,14 +302,14 @@
HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_INTKIEN_Msk);
break;
}
- case GET_DESCRIPTOR: {
+ case USBD_GET_DESCRIPTOR: {
if (!HSUSBD_GetDescriptor()) {
HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_INTKIF_Msk);
HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_INTKIEN_Msk);
}
break;
}
- case GET_INTERFACE: {
+ case USBD_GET_INTERFACE: {
/* Return current interface setting */
HSUSBD_PrepareCtrlIn((uint8_t *)&g_hsusbd_UsbAltInterface, 1ul);
@@ -317,7 +317,7 @@
HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_INTKIEN_Msk);
break;
}
- case GET_STATUS: {
+ case USBD_GET_STATUS: {
/* Device */
if (gUsbCmd.bmRequestType == 0x80ul) {
if ((g_hsusbd_sInfo->gu8ConfigDesc[7] & 0x40ul) == 0x40ul) {
@@ -350,7 +350,7 @@
} else {
/* Host to device */
switch (gUsbCmd.bRequest) {
- case CLEAR_FEATURE: {
+ case USBD_CLEAR_FEATURE: {
if((gUsbCmd.wValue & 0xfful) == FEATURE_ENDPOINT_HALT) {
uint32_t epNum, i;
@@ -370,7 +370,7 @@
HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk);
break;
}
- case SET_ADDRESS: {
+ case USBD_SET_ADDRESS: {
g_hsusbd_UsbAddr = (uint8_t)gUsbCmd.wValue;
/* Status Stage */
HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk);
@@ -378,7 +378,7 @@
HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk);
break;
}
- case SET_CONFIGURATION: {
+ case USBD_SET_CONFIGURATION: {
g_hsusbd_UsbConfig = (uint8_t)gUsbCmd.wValue;
g_hsusbd_Configured = (uint8_t)1ul;
/* Status stage */
@@ -387,7 +387,7 @@
HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk);
break;
}
- case SET_FEATURE: {
+ case USBD_SET_FEATURE: {
if ((gUsbCmd.wValue & 0x3ul) == 2ul) { /* TEST_MODE */
g_hsusbd_EnableTestMode = (uint8_t)1ul;
g_hsusbd_TestSelector = (uint8_t)(gUsbCmd.wIndex >> 8);
@@ -402,7 +402,7 @@
HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk);
break;
}
- case SET_INTERFACE: {
+ case USBD_SET_INTERFACE: {
g_hsusbd_UsbAltInterface = (uint8_t)gUsbCmd.wValue;
if (g_hsusbd_pfnSetInterface != NULL) {
g_hsusbd_pfnSetInterface((uint32_t)g_hsusbd_UsbAltInterface);
@@ -442,11 +442,11 @@
void HSUSBD_UpdateDeviceState(void)
{
switch (gUsbCmd.bRequest) {
- case SET_ADDRESS: {
+ case USBD_SET_ADDRESS: {
HSUSBD_SET_ADDR(g_hsusbd_UsbAddr);
break;
}
- case SET_CONFIGURATION: {
+ case USBD_SET_CONFIGURATION: {
if (g_hsusbd_UsbConfig == 0ul) {
uint32_t volatile i;
/* Reset PID DATA0 */
@@ -458,7 +458,7 @@
}
break;
}
- case SET_FEATURE: {
+ case USBD_SET_FEATURE: {
if(gUsbCmd.wValue == FEATURE_ENDPOINT_HALT) {
uint32_t idx;
idx = (uint32_t)(gUsbCmd.wIndex & 0xFul);
@@ -479,7 +479,7 @@
}
break;
}
- case CLEAR_FEATURE: {
+ case USBD_CLEAR_FEATURE: {
if(gUsbCmd.wValue == FEATURE_ENDPOINT_HALT) {
uint32_t idx;
idx = (uint32_t)(gUsbCmd.wIndex & 0xFul);
--- a/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_sys.h Thu Aug 31 17:27:04 2017 +0100 +++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_sys.h Fri Sep 15 14:59:18 2017 +0100 @@ -117,7 +117,10 @@ #define SYS_USBPHY_USBROLE_STD_USBH (0x1UL << SYS_USBPHY_USBROLE_Pos) /*!< Standard USB host \hideinitializer */ #define SYS_USBPHY_USBROLE_ID_DEPH (0x2UL << SYS_USBPHY_USBROLE_Pos) /*!< ID dependent device \hideinitializer */ #define SYS_USBPHY_USBROLE_ON_THE_GO (0x3UL << SYS_USBPHY_USBROLE_Pos) /*!< On-The-Go device \hideinitializer */ - +#define SYS_USBPHY_HSUSBROLE_STD_USBD (0x0UL << SYS_USBPHY_HSUSBROLE_Pos) /*!< Standard USB device \hideinitializer */ +#define SYS_USBPHY_HSUSBROLE_STD_USBH (0x1UL << SYS_USBPHY_HSUSBROLE_Pos) /*!< Standard USB host \hideinitializer */ +#define SYS_USBPHY_HSUSBROLE_ID_DEPH (0x2UL << SYS_USBPHY_HSUSBROLE_Pos) /*!< ID dependent device \hideinitializer */ +#define SYS_USBPHY_HSUSBROLE_ON_THE_GO (0x3UL << SYS_USBPHY_HSUSBROLE_Pos) /*!< On-The-Go device \hideinitializer */ /*---------------------------------------------------------------------------------------------------------*/ /* Multi-Function constant definitions. */
--- a/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_usbd.c Thu Aug 31 17:27:04 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_usbd.c Fri Sep 15 14:59:18 2017 +0100
@@ -267,7 +267,7 @@
if((g_usbd_SetupPacket[0] & 0x80ul) == 0x80ul) { /* request data transfer direction */
/* Device to host */
switch(g_usbd_SetupPacket[1]) {
- case GET_CONFIGURATION: {
+ case USBD_GET_CONFIGURATION: {
/* Return current configuration setting */
/* Data stage */
addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
@@ -278,12 +278,12 @@
USBD_PrepareCtrlOut(0, 0ul);
break;
}
- case GET_DESCRIPTOR: {
+ case USBD_GET_DESCRIPTOR: {
USBD_GetDescriptor();
USBD_PrepareCtrlOut(0, 0ul); /* For status stage */
break;
}
- case GET_INTERFACE: {
+ case USBD_GET_INTERFACE: {
/* Return current interface setting */
/* Data stage */
addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
@@ -294,7 +294,7 @@
USBD_PrepareCtrlOut(0, 0ul);
break;
}
- case GET_STATUS: {
+ case USBD_GET_STATUS: {
/* Device */
if(g_usbd_SetupPacket[0] == 0x80ul) {
uint8_t u8Tmp;
@@ -342,7 +342,7 @@
} else {
/* Host to device */
switch(g_usbd_SetupPacket[1]) {
- case CLEAR_FEATURE: {
+ case USBD_CLEAR_FEATURE: {
if(g_usbd_SetupPacket[2] == FEATURE_ENDPOINT_HALT) {
uint32_t epNum, i;
@@ -363,7 +363,7 @@
USBD_SET_PAYLOAD_LEN(EP0, 0ul);
break;
}
- case SET_ADDRESS: {
+ case USBD_SET_ADDRESS: {
g_usbd_UsbAddr = g_usbd_SetupPacket[2];
/* Status Stage */
USBD_SET_DATA1(EP0);
@@ -371,7 +371,7 @@
break;
}
- case SET_CONFIGURATION: {
+ case USBD_SET_CONFIGURATION: {
g_usbd_UsbConfig = g_usbd_SetupPacket[2];
if(g_usbd_pfnSetConfigCallback) {
@@ -383,7 +383,7 @@
USBD_SET_PAYLOAD_LEN(EP0, 0ul);
break;
}
- case SET_FEATURE: {
+ case USBD_SET_FEATURE: {
if( (g_usbd_SetupPacket[0] & 0xFul) == 0ul ) { /* 0: device */
if((g_usbd_SetupPacket[2] == 3ul) && (g_usbd_SetupPacket[3] == 0ul)) { /* 3: HNP enable */
OTG->CTL |= (OTG_CTL_HNPREQEN_Msk | OTG_CTL_BUSREQ_Msk);
@@ -401,7 +401,7 @@
break;
}
- case SET_INTERFACE: {
+ case USBD_SET_INTERFACE: {
g_usbd_UsbAltInterface = g_usbd_SetupPacket[2];
if(g_usbd_pfnSetInterface != NULL) {
g_usbd_pfnSetInterface(g_usbd_UsbAltInterface);
@@ -491,7 +491,7 @@
}
} else {
/* In ACK for Set address */
- if((g_usbd_SetupPacket[0] == REQ_STANDARD) && (g_usbd_SetupPacket[1] == SET_ADDRESS)) {
+ if((g_usbd_SetupPacket[0] == REQ_STANDARD) && (g_usbd_SetupPacket[1] == USBD_SET_ADDRESS)) {
addr = USBD_GET_ADDR();
if((addr != g_usbd_UsbAddr) && (addr == 0ul)) {
USBD_SET_ADDR(g_usbd_UsbAddr);
--- a/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_usbd.h Thu Aug 31 17:27:04 2017 +0100 +++ b/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_usbd.h Fri Sep 15 14:59:18 2017 +0100 @@ -69,17 +69,17 @@ #define REQ_VENDOR 0x40ul /* USB Standard Request */ -#define GET_STATUS 0x00ul -#define CLEAR_FEATURE 0x01ul -#define SET_FEATURE 0x03ul -#define SET_ADDRESS 0x05ul -#define GET_DESCRIPTOR 0x06ul -#define SET_DESCRIPTOR 0x07ul -#define GET_CONFIGURATION 0x08ul -#define SET_CONFIGURATION 0x09ul -#define GET_INTERFACE 0x0Aul -#define SET_INTERFACE 0x0Bul -#define SYNC_FRAME 0x0Cul +#define USBD_GET_STATUS 0x00ul +#define USBD_CLEAR_FEATURE 0x01ul +#define USBD_SET_FEATURE 0x03ul +#define USBD_SET_ADDRESS 0x05ul +#define USBD_GET_DESCRIPTOR 0x06ul +#define USBD_SET_DESCRIPTOR 0x07ul +#define USBD_GET_CONFIGURATION 0x08ul +#define USBD_SET_CONFIGURATION 0x09ul +#define USBD_GET_INTERFACE 0x0Aul +#define USBD_SET_INTERFACE 0x0Bul +#define USBD_SYNC_FRAME 0x0Cul /* USB Descriptor Type */ #define DESC_DEVICE 0x01ul
Binary file targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/lib_peripheral_mbed_arm.ar has changed
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct Thu Aug 31 17:27:04 2017 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct Fri Sep 15 14:59:18 2017 +0100
@@ -1,51 +1,78 @@
-; *************************************************************
-; *** Scatter-Loading Description File for RTL8195A ***
-; *************************************************************
-LR_ROM 0x00000000 0x00030000{
- _ROM_CODE 0x00000000 0x00030000 {
- ;*.o (RESET, +First)
- ;*(InRoot$$Sections)
- }
-}
+; Realtek Semiconductor Corp.
+;
+; RTL8195A ARMCC Scatter File
+;
+; MEMORY
+; {
+; SROM (rx) : ORIGIN = 0x10000000, LENGTH = 0x00007000
+; SRAM (rwx) : ORIGIN = 0x10007000, LENGTH = 0x00070000 - 0x00007000
+; TCM (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000
+; DRAM (rwx) : ORIGIN = 0x30000000, LENGTH = 2M
+; }
-LR_RAM 0x10006000 0x6FFFF {
-;LR_RAM 0x10000000 0x6FFFF {
- ;ROM_BSS 0x10000000 0x0005FFF{
- ;rtl_console.o(.mon.ram.bss*)
- ;}
-
- .image2.table 0x10006000 FIXED {
- rtl8195a_init.o(.image2.ram.data*)
- rtl8195a_init.o(.image2.validate.rodata*)
- }
-
- .text +0 FIXED{
- rtl8195a_init.o(.infra.ram.start)
- ;*.o(.mon.ram.text*)
- ;*.o(.hal.flash.text*)
- ;*.o(.hal.sdrc.text*)
- ;*.o(.hal.gpio.text*)
- ;*.o(.text*)
- ;*.o(.rodata*)
- .ANY (+RO)
+LR_IRAM 0x10007000 (0x70000 - 0x7000) {
+
+ IMAGE2_TABLE 0x10007000 FIXED {
+ *rtl8195a_init.o(.image2.ram.data*, +FIRST)
+ *rtl8195a_init.o(.image2.validate.rodata*)
}
- .data +0 FIXED{
- .ANY (+RW)
+ ER_IRAM +0 FIXED {
+ *rtl8195a_crypto.o (+RO)
+ * (i.mbedtls*)
+ *libc.a (+RO)
+
+ *rtx_*.o (+RO)
+ *Ticker.o (+RO)
+ *Timeout.o (+RO)
+ *rtx_timer.o (+RO)
+ *TimerEvent.o (+RO)
+ *mbed_ticker_api.o (+RO)
+ *mbed_critical.o (+RO)
+ *us_ticker.o (+RO)
+
+ *lib_peripheral_mbed_arm.ar (+RO)
}
RW_IRAM1 +0 UNINIT FIXED {
- .ANY (+ZI)
+ *rtl8195a_crypto.o(+RW)
+ ;*mbedtls*.o(+RW)
+ *libc.a (+RW)
+ *(.sdram.data*)
+ *lib_peripheral_mbed_arm.ar (+RW)
}
- TCM_OVERLAY 0x1FFF0000 0x10000{
- lwip_mem.o(.bss*)
- lwip_memp.o(.bss*)
- *.o(.tcm.heap*)
+ RW_IRAM2 +0 UNINIT FIXED {
+ *rtl8195a_crypto.o(+ZI, COMMON)
+ ;*mbedtls*.o(+ZI, COMMON)
+ *libc.a (+ZI, COMMON)
+ *(.bss.thread_stack_main)
+ *lib_peripheral_mbed_arm.ar (+ZI, COMMON)
+ }
+
+ ARM_LIB_STACK (0x10070000 - 0x1000) EMPTY 0x1000 {
}
}
-LR_DRAM 0x30000000 0x1FFFFF{
- _DRAM_CODE 0x30000000 0x1FFFFF{
- }
-}
\ No newline at end of file
+LR_TCM 0x1FFF0000 0x10000 {
+ TCM_OVERLAY 0x1FFF0000 0x10000 {
+ *lwip_mem.o(.bss*)
+ *lwip_memp.o(.bss*)
+ *.o(.tcm.heap*)
+ }
+}
+
+LR_DRAM 0x30000000 0x200000 {
+
+ ER_DRAM +0 FIXED {
+ .ANY (+RO)
+ }
+
+ RW_DRAM1 +0 UNINIT FIXED {
+ .ANY (+RW)
+ }
+
+ RW_DRAM2 +0 UNINIT FIXED {
+ .ANY (+ZI)
+ }
+}
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/sys.cpp Thu Aug 31 17:27:04 2017 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 15 14:59:18 2017 +0100
@@ -1,46 +1,24 @@
-/******************************************************************************
- * Copyright (c) 2013-2016 Realtek Semiconductor Corp.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- * mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- ******************************************************************************/
-
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
#ifdef __cplusplus
extern "C" {
-#endif
+#endif
#include <rt_misc.h>
#include <stdint.h>
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
+extern char Image$$RW_IRAM2$$ZI$$Limit[];
+
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM2$$ZI$$Limit;
uint32_t sp_limit = __current_sp();
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
- //push down stack pointer to recycle some of the stack space that are not use in future
- __asm volatile
- (
- "MRS IP, MSP \n"
- "ADD IP, #64 \n"
- "BIC IP, IP, #7 \n"
- "MSR MSP, IP \n"
- );
struct __initial_stackheap r;
r.heap_base = zi_limit;
r.heap_limit = sp_limit;
@@ -49,4 +27,4 @@
#ifdef __cplusplus
}
-#endif
+#endif
Binary file targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_peripheral_mbed_gcc.a has changed
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/rlx8195A-symbol-v02-img2.ld Thu Aug 31 17:27:04 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,853 +0,0 @@
-/*
- * Copyright (c) 2013-2016 Realtek Semiconductor Corp.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-
-ENTRY(Reset_Handler)
-
-/*INCLUDE "mbed-os/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/export-rom_v02.txt"*/
-SECTIONS
-{
- __vectors_table = 0x0;
- Reset_Handler = 0x101;
- NMI_Handler = 0x109;
- HardFault_Handler = 0x10d;
- MemManage_Handler = 0x121;
- BusFault_Handler = 0x125;
- UsageFault_Handler = 0x129;
- HalLogUartInit = 0x201;
- HalSerialGetcRtl8195a = 0x309;
- HalSerialGetIsrEnRegRtl8195a = 0x329;
- HalSerialSetIrqEnRegRtl8195a = 0x335;
- HalCpuClkConfig = 0x341;
- HalGetCpuClk = 0x355;
- HalRomInfo = 0x39d;
- HalGetRomInfo = 0x3b5;
- HalResetVsr = 0x3c5;
- HalDelayUs = 0x899;
- HalNMIHandler = 0x8e1;
- HalHardFaultHandler = 0x911;
- HalMemManageHandler = 0xc09;
- HalBusFaultHandler = 0xc39;
- HalUsageFaultHandler = 0xc69;
- HalUart0PinCtrlRtl8195A = 0xcfd;
- HalUart1PinCtrlRtl8195A = 0xdc9;
- HalUart2PinCtrlRtl8195A = 0xe9d;
- HalSPI0PinCtrlRtl8195A = 0xf75;
- HalSPI1PinCtrlRtl8195A = 0x1015;
- HalSPI2PinCtrlRtl8195A = 0x10e5;
- HalSPI0MCSPinCtrlRtl8195A = 0x11b5;
- HalI2C0PinCtrlRtl8195A = 0x1275;
- HalI2C1PinCtrlRtl8195A = 0x1381;
- HalI2C2PinCtrlRtl8195A = 0x1459;
- HalI2C3PinCtrlRtl8195A = 0x1529;
- HalI2S0PinCtrlRtl8195A = 0x1639;
- HalI2S1PinCtrlRtl8195A = 0x176d;
- HalPCM0PinCtrlRtl8195A = 0x1845;
- HalPCM1PinCtrlRtl8195A = 0x1949;
- HalSDIODPinCtrlRtl8195A = 0x1a1d;
- HalSDIOHPinCtrlRtl8195A = 0x1a6d;
- HalMIIPinCtrlRtl8195A = 0x1ab9;
- HalWLLEDPinCtrlRtl8195A = 0x1b51;
- HalWLANT0PinCtrlRtl8195A = 0x1c0d;
- HalWLANT1PinCtrlRtl8195A = 0x1c61;
- HalWLBTCOEXPinCtrlRtl8195A = 0x1cb5;
- HalWLBTCMDPinCtrlRtl8195A = 0x1d05;
- HalNFCPinCtrlRtl8195A = 0x1d59;
- HalPWM0PinCtrlRtl8195A = 0x1da9;
- HalPWM1PinCtrlRtl8195A = 0x1ead;
- HalPWM2PinCtrlRtl8195A = 0x1fb5;
- HalPWM3PinCtrlRtl8195A = 0x20b1;
- HalETE0PinCtrlRtl8195A = 0x21b9;
- HalETE1PinCtrlRtl8195A = 0x22c1;
- HalETE2PinCtrlRtl8195A = 0x23c9;
- HalETE3PinCtrlRtl8195A = 0x24d1;
- HalEGTIMPinCtrlRtl8195A = 0x25d9;
- HalSPIFlashPinCtrlRtl8195A = 0x2679;
- HalSDRPinCtrlRtl8195A = 0x2725;
- HalJTAGPinCtrlRtl8195A = 0x280d;
- HalTRACEPinCtrlRtl8195A = 0x2861;
- HalLOGUartPinCtrlRtl8195A = 0x28b9;
- HalLOGUartIRPinCtrlRtl8195A = 0x291d;
- HalSICPinCtrlRtl8195A = 0x2981;
- HalEEPROMPinCtrlRtl8195A = 0x29d9;
- HalDEBUGPinCtrlRtl8195A = 0x2a31;
- HalPinCtrlRtl8195A = 0x2b39;
- SpicRxCmdRtl8195A = 0x2e5d;
- SpicWaitBusyDoneRtl8195A = 0x2ea5;
- SpicGetFlashStatusRtl8195A = 0x2eb5;
- SpicWaitWipDoneRtl8195A = 0x2f55;
- SpicTxCmdRtl8195A = 0x2f6d;
- SpicSetFlashStatusRtl8195A = 0x2fc1;
- SpicCmpDataForCalibrationRtl8195A = 0x3049;
- SpicLoadInitParaFromClockRtl8195A = 0x3081;
- SpicInitRtl8195A = 0x30e5;
- SpicEraseFlashRtl8195A = 0x31bd;
- SpiFlashApp = 0x3279;
- HalPeripheralIntrHandle = 0x33b5;
- HalSysOnIntrHandle = 0x3439;
- HalWdgIntrHandle = 0x3485;
- HalTimer0IntrHandle = 0x34d5;
- HalTimer1IntrHandle = 0x3525;
- HalI2C3IntrHandle = 0x3575;
- HalTimer2To7IntrHandle = 0x35c5;
- HalSpi0IntrHandle = 0x3615;
- HalGpioIntrHandle = 0x3665;
- HalUart0IntrHandle = 0x36b5;
- HalSpiFlashIntrHandle = 0x3705;
- HalUsbOtgIntrHandle = 0x3755;
- HalSdioHostIntrHandle = 0x37a5;
- HalI2s0OrPcm0IntrHandle = 0x37f5;
- HalI2s1OrPcm1IntrHandle = 0x3845;
- HalWlDmaIntrHandle = 0x3895;
- HalWlProtocolIntrHandle = 0x38e5;
- HalCryptoIntrHandle = 0x3935;
- HalGmacIntrHandle = 0x3985;
- HalGdma0Ch0IntrHandle = 0x39d5;
- HalGdma0Ch1IntrHandle = 0x3a25;
- HalGdma0Ch2IntrHandle = 0x3a75;
- HalGdma0Ch3IntrHandle = 0x3ac5;
- HalGdma0Ch4IntrHandle = 0x3b15;
- HalGdma0Ch5IntrHandle = 0x3b65;
- HalGdma1Ch0IntrHandle = 0x3bb5;
- HalGdma1Ch1IntrHandle = 0x3c05;
- HalGdma1Ch2IntrHandle = 0x3c55;
- HalGdma1Ch3IntrHandle = 0x3ca5;
- HalGdma1Ch4IntrHandle = 0x3cf5;
- HalGdma1Ch5IntrHandle = 0x3d45;
- HalSdioDeviceIntrHandle = 0x3d95;
- VectorTableInitRtl8195A = 0x3de5;
- VectorTableInitForOSRtl8195A = 0x4019;
- VectorIrqRegisterRtl8195A = 0x4029;
- VectorIrqUnRegisterRtl8195A = 0x4091;
- VectorIrqEnRtl8195A = 0x40f1;
- VectorIrqDisRtl8195A = 0x418d;
- _UartRxDmaIrqHandle = 0x422d;
- HalRuartPutCRtl8195a = 0x4281;
- HalRuartGetCRtl8195a = 0x429d;
- HalRuartRTSCtrlRtl8195a = 0x42bd;
- HalRuartGetDebugValueRtl8195a = 0x42e1;
- HalRuartGetIMRRtl8195a = 0x43e1;
- HalRuartSetIMRRtl8195a = 0x442d;
- _UartIrqHandle = 0x4465;
- HalRuartDmaInitRtl8195a = 0x4681;
- HalRuartIntDisableRtl8195a = 0x4845;
- HalRuartDeInitRtl8195a = 0x4855;
- HalRuartIntEnableRtl8195a = 0x4985;
- _UartTxDmaIrqHandle = 0x4995;
- HalRuartRegIrqRtl8195a = 0x49d1;
- HalRuartAdapterLoadDefRtl8195a = 0x4a4d;
- HalRuartTxGdmaLoadDefRtl8195a = 0x4add;
- HalRuartRxGdmaLoadDefRtl8195a = 0x4bc9;
- RuartLock = 0x4cc9;
- RuartUnLock = 0x4ced;
- HalRuartIntSendRtl8195a = 0x4d09;
- HalRuartDmaSendRtl8195a = 0x4e35;
- HalRuartStopSendRtl8195a = 0x4f89;
- HalRuartIntRecvRtl8195a = 0x504d;
- HalRuartDmaRecvRtl8195a = 0x51ad;
- HalRuartStopRecvRtl8195a = 0x52cd;
- RuartIsTimeout = 0x5385;
- HalRuartSendRtl8195a = 0x53b1;
- HalRuartRecvRtl8195a = 0x5599;
- RuartResetRxFifoRtl8195a = 0x5751;
- HalRuartResetRxFifoRtl8195a = 0x5775;
- HalRuartInitRtl8195a = 0x5829;
- HalGdmaOnOffRtl8195a = 0x5df1;
- HalGdmaChIsrEnAndDisRtl8195a = 0x5e0d;
- HalGdmaChEnRtl8195a = 0x5e51;
- HalGdmaChDisRtl8195a = 0x5e6d;
- HalGdamChInitRtl8195a = 0x5e91;
- HalGdmaChSetingRtl8195a = 0x5ebd;
- HalGdmaChBlockSetingRtl8195a = 0x000060dd;
- HalGdmaChIsrCleanRtl8195a = 0x6419;
- HalGdmaChCleanAutoSrcRtl8195a = 0x64a1;
- HalGdmaChCleanAutoDstRtl8195a = 0x6501;
- HalEFUSEPowerSwitch8195AROM = 0x6561;
- HALEFUSEOneByteReadROM = 0x65f9;
- HALEFUSEOneByteWriteROM = 0x6699;
- __rtl_memcmpb_v1_00 = 0x681d;
- __rtl_random_v1_00 = 0x6861;
- __rtl_align_to_be32_v1_00 = 0x6881;
- __rtl_memsetw_v1_00 = 0x6899;
- __rtl_memsetb_v1_00 = 0x68ad;
- __rtl_memcpyw_v1_00 = 0x68bd;
- __rtl_memcpyb_v1_00 = 0x68dd;
- __rtl_memDump_v1_00 = 0x68f5;
- __rtl_AES_set_encrypt_key = 0x6901;
- __rtl_cryptoEngine_AES_set_decrypt_key = 0x6c11;
- __rtl_cryptoEngine_set_security_mode_v1_00 = 0x6c95;
- __rtl_cryptoEngine_init_v1_00 = 0x6ea9;
- __rtl_cryptoEngine_exit_v1_00 = 0x7055;
- __rtl_cryptoEngine_reset_v1_00 = 0x70b1;
- __rtl_cryptoEngine_v1_00 = 0x70ed;
- __rtl_crypto_cipher_init_v1_00 = 0x7c69;
- __rtl_crypto_cipher_encrypt_v1_00 = 0x7c89;
- __rtl_crypto_cipher_decrypt_v1_00 = 0x7cad;
- HalSsiPinmuxEnableRtl8195a = 0x7cd5;
- HalSsiEnableRtl8195a = 0x7e45;
- HalSsiDisableRtl8195a = 0x7ef9;
- HalSsiLoadSettingRtl8195a = 0x7fad;
- HalSsiSetInterruptMaskRtl8195a = 0x8521;
- HalSsiGetInterruptMaskRtl8195a = 0x85c9;
- HalSsiSetSclkPolarityRtl8195a = 0x863d;
- HalSsiSetSclkPhaseRtl8195a = 0x8715;
- HalSsiWriteRtl8195a = 0x87e9;
- HalSsiSetDeviceRoleRtl8195a = 0x8861;
- HalSsiSetRxFifoThresholdLevelRtl8195a = 0x88c9;
- HalSsiSetTxFifoThresholdLevelRtl8195a = 0x8941;
- HalSsiReadRtl8195a = 0x89b9;
- HalSsiGetRxFifoLevelRtl8195a = 0x8a2d;
- HalSsiGetTxFifoLevelRtl8195a = 0x8aa5;
- HalSsiGetStatusRtl8195a = 0x8b1d;
- HalSsiWriteableRtl8195a = 0x8b91;
- HalSsiReadableRtl8195a = 0x8c09;
- HalSsiBusyRtl8195a = 0x8c81;
- HalSsiReadInterruptRtl8195a = 0x8cf9;
- HalSsiWriteInterruptRtl8195a = 0x8efd;
- HalSsiSetSlaveEnableRegisterRtl8195a = 0x9009;
- HalSsiGetInterruptStatusRtl8195a = 0x90d9;
- HalSsiInterruptEnableRtl8195a = 0x914d;
- HalSsiInterruptDisableRtl8195a = 0x9299;
- HalSsiGetRawInterruptStatusRtl8195a = 0x93e9;
- HalSsiGetSlaveEnableRegisterRtl8195a = 0x945d;
- HalSsiInitRtl8195a = 0x94d1;
- _SsiReadInterrupt = 0x9ba5;
- _SsiWriteInterrupt = 0x9db1;
- _SsiIrqHandle = 0x9eb1;
- HalI2CWrite32 = 0xa061;
- HalI2CRead32 = 0xa09d;
- HalI2CDeInit8195a = 0xa0dd;
- HalI2CSendRtl8195a = 0xa1f1;
- HalI2CReceiveRtl8195a = 0xa25d;
- HalI2CEnableRtl8195a = 0xa271;
- HalI2CIntrCtrl8195a = 0xa389;
- HalI2CReadRegRtl8195a = 0xa3a1;
- HalI2CWriteRegRtl8195a = 0xa3b1;
- HalI2CSetCLKRtl8195a = 0xa3c5;
- HalI2CMassSendRtl8195a = 0xa6e9;
- HalI2CClrIntrRtl8195a = 0xa749;
- HalI2CClrAllIntrRtl8195a = 0xa761;
- HalI2CInit8195a = 0xa775;
- HalI2CDMACtrl8195a = 0xaa31;
- RtkI2CIoCtrl = 0xaa61;
- RtkI2CPowerCtrl = 0xaa65;
- HalI2COpInit = 0xaa69;
- I2CIsTimeout = 0xac65;
- I2CTXGDMAISRHandle = 0xb435;
- I2CRXGDMAISRHandle = 0xb4c1;
- RtkI2CIrqInit = 0xb54d;
- RtkI2CIrqDeInit = 0xb611;
- RtkI2CPinMuxInit = 0xb675;
- RtkI2CPinMuxDeInit = 0xb7c9;
- RtkI2CDMAInit = 0xb955;
- RtkI2CInit = 0xbc95;
- RtkI2CDMADeInit = 0xbdad;
- RtkI2CDeInit = 0xbe4d;
- RtkI2CSendUserAddr = 0xbee5;
- RtkI2CSend = 0xc07d;
- RtkI2CLoadDefault = 0xce51;
- RtkSalI2COpInit = 0xcf21;
- HalI2SWrite32 = 0xcf65;
- HalI2SRead32 = 0xcf85;
- HalI2SDeInitRtl8195a = 0xcfa9;
- HalI2STxRtl8195a = 0xcfc9;
- HalI2SRxRtl8195a = 0xd011;
- HalI2SEnableRtl8195a = 0xd05d;
- HalI2SIntrCtrlRtl8195a = 0xd0b1;
- HalI2SReadRegRtl8195a = 0xd0d1;
- HalI2SClrIntrRtl8195a = 0xd0dd;
- HalI2SClrAllIntrRtl8195a = 0xd0fd;
- HalI2SInitRtl8195a = 0xd11d;
- GPIO_GetIPPinName_8195a = 0xd2e5;
- GPIO_GetChipPinName_8195a = 0xd331;
- GPIO_PullCtrl_8195a = 0xd39d;
- GPIO_FuncOn_8195a = 0xd421;
- GPIO_FuncOff_8195a = 0xd481;
- GPIO_Int_Mask_8195a = 0xd4e9;
- GPIO_Int_SetType_8195a = 0xd511;
- HAL_GPIO_IrqHandler_8195a = 0xd5fd;
- HAL_GPIO_MbedIrqHandler_8195a = 0xd645;
- HAL_GPIO_UserIrqHandler_8195a = 0xd6a1;
- HAL_GPIO_IntCtrl_8195a = 0xd6cd;
- HAL_GPIO_Init_8195a = 0xd805;
- HAL_GPIO_DeInit_8195a = 0xdac1;
- HAL_GPIO_ReadPin_8195a = 0xdbd1;
- HAL_GPIO_WritePin_8195a = 0xdc91;
- HAL_GPIO_RegIrq_8195a = 0xddad;
- HAL_GPIO_UnRegIrq_8195a = 0xddf5;
- HAL_GPIO_UserRegIrq_8195a = 0xde15;
- HAL_GPIO_UserUnRegIrq_8195a = 0xdef9;
- HAL_GPIO_MaskIrq_8195a = 0xdfc1;
- HAL_GPIO_UnMaskIrq_8195a = 0xe061;
- HAL_GPIO_IntDebounce_8195a = 0xe101;
- HAL_GPIO_GetIPPinName_8195a = 0xe1c1;
- HAL_GPIO_PullCtrl_8195a = 0xe1c9;
- DumpForOneBytes = 0xe259;
- CmdRomHelp = 0xe419;
- CmdWriteWord = 0xe491;
- CmdDumpHelfWord = 0xe505;
- CmdDumpWord = 0xe5f1;
- CmdDumpByte = 0xe6f5;
- CmdSpiFlashTool = 0xe751;
- GetRomCmdNum = 0xe7a9;
- CmdWriteByte = 0xe7ad;
- Isspace = 0xe7ed;
- Strtoul = 0xe801;
- ArrayInitialize = 0xe8b1;
- GetArgc = 0xe8c9;
- GetArgv = 0xe8f9;
- UartLogCmdExecute = 0xe95d;
- UartLogShowBackSpace = 0xe9fd;
- UartLogRecallOldCmd = 0xea39;
- UartLogHistoryCmd = 0xea71;
- UartLogCmdChk = 0xeadd;
- UartLogIrqHandle = 0xebf5;
- RtlConsolInit = 0xecc5;
- RtlConsolTaskRom = 0xed49;
- RtlExitConsol = 0xed79;
- RtlConsolRom = 0xedcd;
- HalTimerOpInit = 0xee0d;
- HalTimerIrq2To7Handle = 0xee59;
- HalGetTimerIdRtl8195a = 0xef09;
- HalTimerInitRtl8195a = 0xef3d;
- HalTimerDisRtl8195a = 0xf069;
- HalTimerEnRtl8195a = 0xf089;
- HalTimerReadCountRtl8195a = 0xf0a9;
- HalTimerIrqClearRtl8195a = 0xf0bd;
- HalTimerDumpRegRtl8195a = 0xf0d1;
- VSprintf = 0xf129;
- DiagPrintf = 0xf39d;
- DiagSPrintf = 0xf3b9;
- DiagSnPrintf = 0xf3d1;
- prvDiagPrintf = 0xf3ed;
- prvDiagSPrintf = 0xf40d;
- _memcmp = 0xf429;
- _memcpy = 0xf465;
- _memset = 0xf511;
- Rand = 0xf585;
- _strncpy = 0xf60d;
- _strcpy = 0xf629;
- prvStrCpy = 0xf639;
- _strlen = 0xf651;
- _strnlen = 0xf669;
- prvStrLen = 0xf699;
- _strcmp = 0xf6b1;
- _strncmp = 0xf6d1;
- prvStrCmp = 0xf719;
- StrUpr = 0xf749;
- prvAtoi = 0xf769;
- prvStrStr = 0xf7bd;
- _strsep = 0xf7d5;
- skip_spaces = 0xf815;
- skip_atoi = 0xf831;
- _parse_integer_fixup_radix = 0xf869;
- _parse_integer = 0xf8bd;
- simple_strtoull = 0xf915;
- simple_strtoll = 0xf945;
- simple_strtoul = 0xf965;
- simple_strtol = 0xf96d;
- _vsscanf = 0xf985;
- _sscanf = 0xff71;
- div_u64 = 0xff91;
- div_s64 = 0xff99;
- div_u64_rem = 0xffa1;
- div_s64_rem = 0xffb1;
- _strpbrk = 0xffc1;
- _strchr = 0xffed;
- aes_set_key = 0x10005;
- aes_encrypt = 0x103d1;
- aes_decrypt = 0x114a5;
- AES_WRAP = 0x125c9;
- AES_UnWRAP = 0x12701;
- crc32_get = 0x12861;
- arc4_byte = 0x12895;
- rt_arc4_init = 0x128bd;
- rt_arc4_crypt = 0x12901;
- rt_md5_init = 0x131c1;
- rt_md5_append = 0x131f5;
- rt_md5_final = 0x1327d;
- rt_md5_hmac = 0x132d5;
- rtw_get_bit_value_from_ieee_value = 0x13449;
- rtw_is_cckrates_included = 0x13475;
- rtw_is_cckratesonly_included = 0x134b5;
- rtw_check_network_type = 0x134dd;
- rtw_set_fixed_ie = 0x1350d;
- rtw_set_ie = 0x1352d;
- rtw_get_ie = 0x1355d;
- rtw_set_supported_rate = 0x13591;
- rtw_get_rateset_len = 0x13611;
- rtw_get_wpa_ie = 0x1362d;
- rtw_get_wpa2_ie = 0x136c9;
- rtw_get_wpa_cipher_suite = 0x13701;
- rtw_get_wpa2_cipher_suite = 0x13769;
- rtw_parse_wpa_ie = 0x137d1;
- rtw_parse_wpa2_ie = 0x138ad;
- rtw_get_sec_ie = 0x13965;
- rtw_get_wps_ie = 0x13a15;
- rtw_get_wps_attr = 0x13a99;
- rtw_get_wps_attr_content = 0x13b49;
- rtw_ieee802_11_parse_elems = 0x13b91;
- str_2char2num = 0x13d9d;
- key_2char2num = 0x13db9;
- convert_ip_addr = 0x13dd1;
- rom_psk_PasswordHash = 0x13e9d;
- rom_psk_CalcGTK = 0x13ed5;
- rom_psk_CalcPTK = 0x13f69;
- wep_80211_encrypt = 0x14295;
- wep_80211_decrypt = 0x142f5;
- tkip_micappendbyte = 0x14389;
- rtw_secmicsetkey = 0x143d9;
- rtw_secmicappend = 0x14419;
- rtw_secgetmic = 0x14435;
- rtw_seccalctkipmic = 0x1449d;
- tkip_phase1 = 0x145a5;
- tkip_phase2 = 0x14725;
- tkip_80211_encrypt = 0x14941;
- tkip_80211_decrypt = 0x149d5;
- aes1_encrypt = 0x14a8d;
- aesccmp_construct_mic_iv = 0x14c65;
- aesccmp_construct_mic_header1 = 0x14ccd;
- aesccmp_construct_mic_header2 = 0x14d21;
- aesccmp_construct_ctr_preload = 0x14db5;
- aes_80211_encrypt = 0x14e29;
- aes_80211_decrypt = 0x151ad;
- _sha1_process_message_block = 0x155b9;
- _sha1_pad_message = 0x15749;
- rt_sha1_init = 0x157e5;
- rt_sha1_update = 0x15831;
- rt_sha1_finish = 0x158a9;
- rt_hmac_sha1 = 0x15909;
- rom_aes_128_cbc_encrypt = 0x15a65;
- rom_aes_128_cbc_decrypt = 0x15ae1;
- rom_rijndaelKeySetupEnc = 0x15b5d;
- rom_aes_decrypt_init = 0x15c39;
- rom_aes_internal_decrypt = 0x15d15;
- rom_aes_decrypt_deinit = 0x16071;
- rom_aes_encrypt_init = 0x16085;
- rom_aes_internal_encrypt = 0x1609d;
- rom_aes_encrypt_deinit = 0x16451;
- bignum_init = 0x17b35;
- bignum_deinit = 0x17b61;
- bignum_get_unsigned_bin_len = 0x17b81;
- bignum_get_unsigned_bin = 0x17b85;
- bignum_set_unsigned_bin = 0x17c21;
- bignum_cmp = 0x17cd1;
- bignum_cmp_d = 0x17cd5;
- bignum_add = 0x17cfd;
- bignum_sub = 0x17d0d;
- bignum_mul = 0x17d1d;
- bignum_exptmod = 0x17d2d;
- WPS_realloc = 0x17d51;
- os_zalloc = 0x17d99;
- rom_hmac_sha256_vector = 0x17dc1;
- rom_hmac_sha256 = 0x17ebd;
- rom_sha256_vector = 0x18009;
- phy_CalculateBitShift = 0x18221;
- PHY_SetBBReg_8195A = 0x18239;
- PHY_QueryBBReg_8195A = 0x18279;
- ROM_odm_QueryRxPwrPercentage = 0x1829d;
- ROM_odm_EVMdbToPercentage = 0x182bd;
- ROM_odm_SignalScaleMapping_8195A = 0x182e5;
- ROM_odm_FalseAlarmCounterStatistics = 0x183cd;
- ROM_odm_SetEDCCAThreshold = 0x18721;
- ROM_odm_SetTRxMux = 0x18749;
- ROM_odm_SetCrystalCap = 0x18771;
- ROM_odm_GetDefaultCrytaltalCap = 0x187d5;
- ROM_ODM_CfoTrackingReset = 0x187e9;
- ROM_odm_CfoTrackingFlow = 0x18811;
- curve25519_donna = 0x1965d;
- aes_test_alignment_detection = 0x1a391;
- aes_mode_reset = 0x1a3ed;
- aes_ecb_encrypt = 0x1a3f9;
- aes_ecb_decrypt = 0x1a431;
- aes_cbc_encrypt = 0x1a469;
- aes_cbc_decrypt = 0x1a579;
- aes_cfb_encrypt = 0x1a701;
- aes_cfb_decrypt = 0x1a9e5;
- aes_ofb_crypt = 0x1acc9;
- aes_ctr_crypt = 0x1af7d;
- aes_encrypt_key128 = 0x1b289;
- aes_encrypt_key192 = 0x1b2a5;
- aes_encrypt_key256 = 0x1b2c1;
- aes_encrypt_key = 0x1b2e1;
- aes_decrypt_key128 = 0x1b351;
- aes_decrypt_key192 = 0x1b36d;
- aes_decrypt_key256 = 0x1b389;
- aes_decrypt_key = 0x1b3a9;
- aes_init = 0x1b419;
- CRYPTO_chacha_20 = 0x1b41d;
- CRYPTO_poly1305_init = 0x1bc25;
- CRYPTO_poly1305_update = 0x1bd09;
- CRYPTO_poly1305_finish = 0x1bd8d;
- rom_sha512_starts = 0x1ceb5;
- rom_sha512_update = 0x1d009;
- rom_sha512_finish = 0x1d011;
- rom_sha512 = 0x1d261;
- rom_sha512_hmac_starts = 0x1d299;
- rom_sha512_hmac_update = 0x1d35d;
- rom_sha512_hmac_finish = 0x1d365;
- rom_sha512_hmac_reset = 0x1d3b5;
- rom_sha512_hmac = 0x1d3d1;
- rom_sha512_hkdf = 0x1d40d;
- rom_ed25519_gen_keypair = 0x1d501;
- rom_ed25519_gen_signature = 0x1d505;
- rom_ed25519_verify_signature = 0x1d51d;
- rom_ed25519_crypto_sign_seed_keypair = 0x1d521;
- rom_ed25519_crypto_sign_detached = 0x1d579;
- rom_ed25519_crypto_sign_verify_detached = 0x1d655;
- rom_ed25519_ge_double_scalarmult_vartime = 0x1f86d;
- rom_ed25519_ge_frombytes_negate_vartime = 0x1fc35;
- rom_ed25519_ge_p3_tobytes = 0x207d5;
- rom_ed25519_ge_scalarmult_base = 0x20821;
- rom_ed25519_ge_tobytes = 0x209e1;
- rom_ed25519_sc_muladd = 0x20a2d;
- rom_ed25519_sc_reduce = 0x2603d;
- __rtl_memchr_v1_00 = 0x28a4d;
- __rtl_memcmp_v1_00 = 0x28ae1;
- __rtl_memcpy_v1_00 = 0x28b49;
- __rtl_memmove_v1_00 = 0x28bed;
- __rtl_memset_v1_00 = 0x28cb5;
- __rtl_strcat_v1_00 = 0x28d49;
- __rtl_strchr_v1_00 = 0x28d91;
- __rtl_strcmp_v1_00 = 0x28e55;
- __rtl_strcpy_v1_00 = 0x28ec9;
- __rtl_strlen_v1_00 = 0x28f15;
- __rtl_strncat_v1_00 = 0x28f69;
- __rtl_strncmp_v1_00 = 0x28fc5;
- __rtl_strncpy_v1_00 = 0x2907d;
- __rtl_strstr_v1_00 = 0x293cd;
- __rtl_strsep_v1_00 = 0x2960d;
- __rtl_strtok_v1_00 = 0x29619;
- __rtl__strtok_r_v1_00 = 0x2962d;
- __rtl_strtok_r_v1_00 = 0x29691;
- __rtl_close_v1_00 = 0x29699;
- __rtl_fstat_v1_00 = 0x296ad;
- __rtl_isatty_v1_00 = 0x296c1;
- __rtl_lseek_v1_00 = 0x296d5;
- __rtl_open_v1_00 = 0x296e9;
- __rtl_read_v1_00 = 0x296fd;
- __rtl_write_v1_00 = 0x29711;
- __rtl_sbrk_v1_00 = 0x29725;
- __rtl_ltoa_v1_00 = 0x297bd;
- __rtl_ultoa_v1_00 = 0x29855;
- __rtl_dtoi_v1_00 = 0x298c5;
- __rtl_dtoi64_v1_00 = 0x29945;
- __rtl_dtoui_v1_00 = 0x299dd;
- __rtl_ftol_v1_00 = 0x299e5;
- __rtl_itof_v1_00 = 0x29a51;
- __rtl_itod_v1_00 = 0x29ae9;
- __rtl_i64tod_v1_00 = 0x29b79;
- __rtl_uitod_v1_00 = 0x29c55;
- __rtl_ftod_v1_00 = 0x29d2d;
- __rtl_dtof_v1_00 = 0x29de9;
- __rtl_uitof_v1_00 = 0x29e89;
- __rtl_fadd_v1_00 = 0x29f65;
- __rtl_fsub_v1_00 = 0x2a261;
- __rtl_fmul_v1_00 = 0x2a559;
- __rtl_fdiv_v1_00 = 0x2a695;
- __rtl_dadd_v1_00 = 0x2a825;
- __rtl_dsub_v1_00 = 0x2aed9;
- __rtl_dmul_v1_00 = 0x2b555;
- __rtl_ddiv_v1_00 = 0x2b8ad;
- __rtl_dcmpeq_v1_00 = 0x2be4d;
- __rtl_dcmplt_v1_00 = 0x2bebd;
- __rtl_dcmpgt_v1_00 = 0x2bf51;
- __rtl_dcmple_v1_00 = 0x2c049;
- __rtl_fcmplt_v1_00 = 0x2c139;
- __rtl_fcmpgt_v1_00 = 0x2c195;
- __rtl_cos_f32_v1_00 = 0x2c229;
- __rtl_sin_f32_v1_00 = 0x2c435;
- __rtl_fabs_v1_00 = 0x2c639;
- __rtl_fabsf_v1_00 = 0x2c641;
- __rtl_dtoa_r_v1_00 = 0x2c77d;
- __rom_mallocr_init_v1_00 = 0x2d7d1;
- __rtl_free_r_v1_00 = 0x2d841;
- __rtl_malloc_r_v1_00 = 0x2da31;
- __rtl_realloc_r_v1_00 = 0x2df55;
- __rtl_memalign_r_v1_00 = 0x2e331;
- __rtl_valloc_r_v1_00 = 0x2e421;
- __rtl_pvalloc_r_v1_00 = 0x2e42d;
- __rtl_calloc_r_v1_00 = 0x2e441;
- __rtl_cfree_r_v1_00 = 0x2e4a9;
- __rtl_Balloc_v1_00 = 0x2e515;
- __rtl_Bfree_v1_00 = 0x2e571;
- __rtl_i2b_v1_00 = 0x2e585;
- __rtl_multadd_v1_00 = 0x2e599;
- __rtl_mult_v1_00 = 0x2e629;
- __rtl_pow5mult_v1_00 = 0x2e769;
- __rtl_hi0bits_v1_00 = 0x2e809;
- __rtl_d2b_v1_00 = 0x2e845;
- __rtl_lshift_v1_00 = 0x2e901;
- __rtl_cmp_v1_00 = 0x2e9bd;
- __rtl_diff_v1_00 = 0x2ea01;
- __rtl_sread_v1_00 = 0x2eae9;
- __rtl_seofread_v1_00 = 0x2eb39;
- __rtl_swrite_v1_00 = 0x2eb3d;
- __rtl_sseek_v1_00 = 0x2ebc1;
- __rtl_sclose_v1_00 = 0x2ec11;
- __rtl_sbrk_r_v1_00 = 0x2ec41;
- __rtl_fflush_r_v1_00 = 0x2ef8d;
- __rtl_vfprintf_r_v1_00 = 0x2f661;
- __rtl_fpclassifyd = 0x30c15;
- CpkClkTbl = 0x30c68;
- ROM_IMG1_VALID_PATTEN = 0x30c80;
- SpicCalibrationPattern = 0x30c88;
- SpicInitCPUCLK = 0x30c98;
- BAUDRATE = 0x30ca8;
- OVSR = 0x30d1c;
- DIV = 0x30d90;
- OVSR_ADJ = 0x30e04;
- __AES_rcon = 0x30e78;
- __AES_Te4 = 0x30ea0;
- I2CDmaChNo = 0x312a0;
- UartLogRomCmdTable = 0x316a0;
- _HalRuartOp = 0x31700;
- _HalGdmaOp = 0x31760;
- RTW_WPA_OUI_TYPE = 0x3540c;
- WPA_CIPHER_SUITE_NONE = 0x35410;
- WPA_CIPHER_SUITE_WEP40 = 0x35414;
- WPA_CIPHER_SUITE_TKIP = 0x35418;
- WPA_CIPHER_SUITE_CCMP = 0x3541c;
- WPA_CIPHER_SUITE_WEP104 = 0x35420;
- RSN_CIPHER_SUITE_NONE = 0x35424;
- RSN_CIPHER_SUITE_WEP40 = 0x35428;
- RSN_CIPHER_SUITE_TKIP = 0x3542c;
- RSN_CIPHER_SUITE_CCMP = 0x35430;
- RSN_CIPHER_SUITE_WEP104 = 0x35434;
- RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X = 0x35444;
- RSN_AUTH_KEY_MGMT_UNSPEC_802_1X = 0x35448;
- RSN_VERSION_BSD = 0x3544c;
- rom_wps_Te0 = 0x35988;
- rom_wps_rcons = 0x35d88;
- rom_wps_Td4s = 0x35d94;
- rom_wps_Td0 = 0x35e94;
- NewVectorTable = 0x10000000;
- UserIrqFunTable = 0x10000100;
- UserIrqDataTable = 0x10000200;
- __rom_bss_start__ = 0x10000300;
- CfgSysDebugWarn = 0x10000300;
- CfgSysDebugInfo = 0x10000304;
- CfgSysDebugErr = 0x10000308;
- ConfigDebugWarn = 0x1000030c;
- ConfigDebugInfo = 0x10000310;
- ConfigDebugErr = 0x10000314;
- HalTimerOp = 0x10000318;
- GPIOState = 0x10000334;
- gTimerRecord = 0x1000034c;
- SSI_DBG_CONFIG = 0x10000350;
- _pHAL_Gpio_Adapter = 0x10000354;
- Timer2To7VectorTable = 0x10000358;
- pUartLogCtl = 0x10000384;
- UartLogBuf = 0x10000388;
- UartLogCtl = 0x10000408;
- UartLogHistoryBuf = 0x10000430;
- ArgvArray = 0x100006ac;
- rom_wlan_ram_map = 0x100006d4;
- FalseAlmCnt = 0x100006e0;
- ROMInfo = 0x10000720;
- DM_CfoTrack = 0x10000738;
- rom_libgloss_ram_map = 0x10000760;
- __rtl_errno = 0x10000bc4;
- _rtl_impure_ptr = 0x10001c60;
-}
-
-/* DATA_RAM: We cannot put Code(.text) in DATA_RAM, this region is reserved for Image1(boot loader).
- But we can put .data/.bss of Image2 in this region */
-MEMORY
-{
- TCM (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000
- ROM_USED_RAM (rwx) : ORIGIN = 0x10000bc8, LENGTH = 0x10006000-0x10000bc8
- DATA_RAM (rwx) : ORIGIN = 0x10002100, LENGTH = 0x10006000 - 0x10002100
- BD_RAM (rwx) : ORIGIN = 0x10006000, LENGTH = 0x10070000 - 0x10006000
- SD_RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 2M
-}
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- * _reset_init : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- * __exidx_start
- * __exidx_end
- * __etext
- * __data_start__
- * __preinit_array_start
- * __preinit_array_end
- * __init_array_start
- * __init_array_end
- * __fini_array_start
- * __fini_array_end
- * __data_end__
- * __bss_start__
- * __bss_end__
- * __end__
- * end
- * __HeapLimit
- * __StackLimit
- * __StackTop
- * __stack
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
- __rom_bss_start__ = 0x10000300;
- __rom_bss_end__ = 0x10000bc8;
- __ram_table_start__ = 0x10000bc8;
-/*
- .ram.start.table :
- {
-
- } > ROM_USED_RAM
-*/
- .image2.table :
- {
- __image2_start__ = .;
- __image2_entry_func__ = .;
- KEEP(*(SORT(.image2.ram.data*)))
- __image2_validate_code__ = .;
- KEEP(*(.image2.validate.rodata*))
- } > BD_RAM
-
- .text :
- {
- . = ALIGN(4);
- *(.infra.ram.start*)
- *(.mon.ram.text*)
- *(.hal.flash.text*)
- *(.hal.sdrc.text*)
- *(.hal.gpio.text*)
- *(.text*)
-
- KEEP(*(.init))
- KEEP(*(.fini))
-
- /* .ctors */
- *crtbegin.o(.ctors)
- *crtbegin?.o(.ctors)
- *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
- *(SORT(.ctors.*))
- *(.ctors)
-
- /* .dtors */
- *crtbegin.o(.dtors)
- *crtbegin?.o(.dtors)
- *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
- *(SORT(.dtors.*))
- *(.dtors)
- *(.rodata*)
- KEEP(*(.eh_frame*))
- } > BD_RAM
- __etext = .;
-
-
- __data_start__ = .;
- .data :
- {
- *(vtable)
- *(.data*)
-
- . = ALIGN(4);
- /* preinit data */
- PROVIDE (__preinit_array_start = .);
- KEEP(*(.preinit_array))
- PROVIDE (__preinit_array_end = .);
-
- . = ALIGN(4);
- /* init data */
- PROVIDE (__init_array_start = .);
- KEEP(*(SORT(.init_array.*)))
- KEEP(*(.init_array))
- PROVIDE (__init_array_end = .);
-
- . = ALIGN(4);
- /* finit data */
- PROVIDE (__fini_array_start = .);
- KEEP(*(SORT(.fini_array.*)))
- KEEP(*(.fini_array))
- PROVIDE (__fini_array_end = .);
-
- . = ALIGN(4);
-
- /* All data end */
- } > BD_RAM
- __data_end__ = .;
- __image2_end__ = .;
-
- .ARM.extab :
- {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > BD_RAM
-
- __exidx_start = .;
- .ARM.exidx :
- {
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- } > BD_RAM
- __exidx_end = .;
-
- .bss :
- {
- __bss_start__ = .;
- *(.bss*)
- *(.bdsram.data*)
- *(COMMON)
- __bss_end__ = .;
- } > BD_RAM
-
-
- .bf_data :
- {
- __buffer_data_start__ = .;
- *(.bfsram.data*)
- __buffer_data_end__ = .;
- } > BD_RAM
-
- .heap :
- {
- __end__ = .;
- end = __end__;
- *(.heap*)
- __HeapLimit = .;
- } > BD_RAM
-
- .TCM_overlay :
- {
- *lwip_mem.o (.bss*)
- *lwip_memp.o (.bss*)
- *(.tcm.heap*)
- } > TCM
-
- /* .stack_dummy section doesn't contains any symbols. It is only
- * used for linker to calculate size of stack sections, and assign
- * values to stack symbols later */
- .stack_dummy :
- {
- *(.stack)
- } > BD_RAM
-
- /* Set stack top to end of RAM, and stack limit move down by
- * size of stack_dummy section */
- __StackTop = ORIGIN(BD_RAM) + LENGTH(BD_RAM);
- __StackLimit = __StackTop - SIZEOF(.stack_dummy);
- PROVIDE(__stack = __StackTop);
-
- /* Check if data + heap + stack exceeds RAM limit */
- ASSERT(__StackLimit >= __HeapLimit, "region RAM exceeds ram limit")
-
-}
-
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a.ld Fri Sep 15 14:59:18 2017 +0100
@@ -0,0 +1,237 @@
+/*
+ * Copyright (c) 2013-2016 Realtek Semiconductor Corp.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+INCLUDE "rtl8195a_rom.h"
+/* DATA_RAM: We cannot put Code(.text) in DATA_RAM, this region is reserved for Image1(boot loader).
+ But we can put .data/.bss of Image2 in this region */
+MEMORY
+{
+ TCM (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000
+ DATA_RAM (rwx) : ORIGIN = 0x10002100, LENGTH = 0x10007000 - 0x10002100
+ SRAM1 (rwx) : ORIGIN = 0x10007000, LENGTH = 0x10070000 - 0x10007000
+ SRAM2 (rwx) : ORIGIN = 0x30000000, LENGTH = 2M
+}
+
+/* Stack sizes: */
+StackSize = 0x1000;
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * _reset_init : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .image2.table :
+ {
+ KEEP(*(SORT(.image2.ram.data*)))
+ KEEP(*(.image2.validate.rodata*))
+ } > SRAM2
+
+ .text.sram1 :
+ {
+ . = ALIGN(4);
+ *rtl8195a_crypto.o (.text* .rodata*)
+ *mbedtls*.o (.text* .rodata*)
+ *libc.a: (.text* .rodata*)
+ *Ticker.o (.text*)
+ *Timeout.o (.text*)
+ *TimerEvent.o (.text*)
+ *mbed_ticker_api.o (.text*)
+ *mbed_critical.o (.text*)
+ *us_ticker.o (.text*)
+
+ *lib_peripheral_mbed_gcc.a: (.text*)
+
+ } > SRAM1
+
+ .text.sram2 :
+ {
+ . = ALIGN(4);
+ *(.mon.ram.text*)
+ *(.hal.flash.text*)
+ *(.hal.sdrc.text*)
+ *(.hal.gpio.text*)
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > SRAM2
+ __etext = .;
+
+ __data_start__ = .;
+
+ .data.sram1 :
+ {
+ . = ALIGN(4);
+ __sram_data_start__ = .;
+ *rtl8195a_crypto*.o (.data*)
+ *mbedtls*.o (.data*)
+ __sram_data_end__ = .;
+ } > SRAM1
+
+ .data.sram2 :
+ {
+ __sdram_data_start__ = .;
+ *(vtable)
+ *(.data*)
+ *(.sdram.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE (__fini_array_end = .);
+
+ . = ALIGN(4);
+
+ __sdram_data_end__ = .;
+ /* All data end */
+ } > SRAM2
+ __data_end__ = .;
+ __image2_end__ = .;
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > SRAM2
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > SRAM2
+ __exidx_end = .;
+
+ .bss.sram1 (NOLOAD) :
+ {
+ __bss_sram_start__ = .;
+ *rtl8195a_crypto.o (.bss* COMMON)
+ *mbedtls*.o (.bss* COMMON)
+ *(.bss.thread_stack_main)
+ __bss_sram_end__ = .;
+ } > SRAM1
+
+ .bss.sram2 (NOLOAD) :
+ {
+ __bss_start__ = .;
+ __bss_dram_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ *(.bdsram.data*)
+ __bss_dram_end__ = .;
+ __bss_end__ = .;
+ } > SRAM2
+
+ .bf_data :
+ {
+ __buffer_data_start__ = .;
+ *(.bfsram.data*)
+ __buffer_data_end__ = .;
+ } > SRAM2
+
+ .heap (NOLOAD):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ . = ORIGIN(SRAM1) + LENGTH(SRAM1) - StackSize;
+ __HeapLimit = .;
+ } > SRAM1
+
+ .TCM_overlay :
+ {
+ __bss_dtcm_start__ = .;
+ *lwip_mem.o (.bss*)
+ *lwip_memp.o (.bss*)
+ *(.tcm.heap*)
+ __bss_dtcm_end__ = .;
+ } > TCM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (NOLOAD):
+ {
+ __StackLimit = .;
+ *(.stack)
+ . += StackSize - (. - __StackLimit);
+ } > SRAM1
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(SRAM1) + LENGTH(SRAM1);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM exceeds ram limit")
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a_rom.h Fri Sep 15 14:59:18 2017 +0100
@@ -0,0 +1,759 @@
+/*
+ * Copyright (c) 2013-2016 Realtek Semiconductor Corp.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+SECTIONS
+{
+ __vectors_table = 0x0;
+ Reset_Handler = 0x101;
+ NMI_Handler = 0x109;
+ HardFault_Handler = 0x10d;
+ MemManage_Handler = 0x121;
+ BusFault_Handler = 0x125;
+ UsageFault_Handler = 0x129;
+ HalLogUartInit = 0x201;
+ HalSerialPutcRtl8195a = 0x2d9;
+ HalSerialGetcRtl8195a = 0x309;
+ HalSerialGetIsrEnRegRtl8195a = 0x329;
+ HalSerialSetIrqEnRegRtl8195a = 0x335;
+ HalCpuClkConfig = 0x341;
+ HalGetCpuClk = 0x355;
+ HalRomInfo = 0x39d;
+ HalGetRomInfo = 0x3b5;
+ HalResetVsr = 0x3c5;
+ HalDelayUs = 0x899;
+ HalNMIHandler = 0x8e1;
+ HalHardFaultHandler = 0x911;
+ HalMemManageHandler = 0xc09;
+ HalBusFaultHandler = 0xc39;
+ HalUsageFaultHandler = 0xc69;
+ HalUart0PinCtrlRtl8195A = 0xcfd;
+ HalUart1PinCtrlRtl8195A = 0xdc9;
+ HalUart2PinCtrlRtl8195A = 0xe9d;
+ HalSPI0PinCtrlRtl8195A = 0xf75;
+ HalSPI1PinCtrlRtl8195A = 0x1015;
+ HalSPI2PinCtrlRtl8195A = 0x10e5;
+ HalSPI0MCSPinCtrlRtl8195A = 0x11b5;
+ HalI2C0PinCtrlRtl8195A = 0x1275;
+ HalI2C1PinCtrlRtl8195A = 0x1381;
+ HalI2C2PinCtrlRtl8195A = 0x1459;
+ HalI2C3PinCtrlRtl8195A = 0x1529;
+ HalI2S0PinCtrlRtl8195A = 0x1639;
+ HalI2S1PinCtrlRtl8195A = 0x176d;
+ HalPCM0PinCtrlRtl8195A = 0x1845;
+ HalPCM1PinCtrlRtl8195A = 0x1949;
+ HalSDIODPinCtrlRtl8195A = 0x1a1d;
+ HalSDIOHPinCtrlRtl8195A = 0x1a6d;
+ HalMIIPinCtrlRtl8195A = 0x1ab9;
+ HalWLLEDPinCtrlRtl8195A = 0x1b51;
+ HalWLANT0PinCtrlRtl8195A = 0x1c0d;
+ HalWLANT1PinCtrlRtl8195A = 0x1c61;
+ HalWLBTCOEXPinCtrlRtl8195A = 0x1cb5;
+ HalWLBTCMDPinCtrlRtl8195A = 0x1d05;
+ HalNFCPinCtrlRtl8195A = 0x1d59;
+ HalPWM0PinCtrlRtl8195A = 0x1da9;
+ HalPWM1PinCtrlRtl8195A = 0x1ead;
+ HalPWM2PinCtrlRtl8195A = 0x1fb5;
+ HalPWM3PinCtrlRtl8195A = 0x20b1;
+ HalETE0PinCtrlRtl8195A = 0x21b9;
+ HalETE1PinCtrlRtl8195A = 0x22c1;
+ HalETE2PinCtrlRtl8195A = 0x23c9;
+ HalETE3PinCtrlRtl8195A = 0x24d1;
+ HalEGTIMPinCtrlRtl8195A = 0x25d9;
+ HalSPIFlashPinCtrlRtl8195A = 0x2679;
+ HalSDRPinCtrlRtl8195A = 0x2725;
+ HalJTAGPinCtrlRtl8195A = 0x280d;
+ HalTRACEPinCtrlRtl8195A = 0x2861;
+ HalLOGUartPinCtrlRtl8195A = 0x28b9;
+ HalLOGUartIRPinCtrlRtl8195A = 0x291d;
+ HalSICPinCtrlRtl8195A = 0x2981;
+ HalEEPROMPinCtrlRtl8195A = 0x29d9;
+ HalDEBUGPinCtrlRtl8195A = 0x2a31;
+ HalPinCtrlRtl8195A = 0x2b39;
+ SpicRxCmdRtl8195A = 0x2e5d;
+ SpicWaitBusyDoneRtl8195A = 0x2ea5;
+ SpicGetFlashStatusRtl8195A = 0x2eb5;
+ SpicWaitWipDoneRtl8195A = 0x2f55;
+ SpicTxCmdRtl8195A = 0x2f6d;
+ SpicSetFlashStatusRtl8195A = 0x2fc1;
+ SpicCmpDataForCalibrationRtl8195A = 0x3049;
+ SpicLoadInitParaFromClockRtl8195A = 0x3081;
+ SpicInitRtl8195A = 0x30e5;
+ SpicEraseFlashRtl8195A = 0x31bd;
+ SpiFlashApp = 0x3279;
+ HalPeripheralIntrHandle = 0x33b5;
+ HalSysOnIntrHandle = 0x3439;
+ HalWdgIntrHandle = 0x3485;
+ HalTimer0IntrHandle = 0x34d5;
+ HalTimer1IntrHandle = 0x3525;
+ HalI2C3IntrHandle = 0x3575;
+ HalTimer2To7IntrHandle = 0x35c5;
+ HalSpi0IntrHandle = 0x3615;
+ HalGpioIntrHandle = 0x3665;
+ HalUart0IntrHandle = 0x36b5;
+ HalSpiFlashIntrHandle = 0x3705;
+ HalUsbOtgIntrHandle = 0x3755;
+ HalSdioHostIntrHandle = 0x37a5;
+ HalI2s0OrPcm0IntrHandle = 0x37f5;
+ HalI2s1OrPcm1IntrHandle = 0x3845;
+ HalWlDmaIntrHandle = 0x3895;
+ HalWlProtocolIntrHandle = 0x38e5;
+ HalCryptoIntrHandle = 0x3935;
+ HalGmacIntrHandle = 0x3985;
+ HalGdma0Ch0IntrHandle = 0x39d5;
+ HalGdma0Ch1IntrHandle = 0x3a25;
+ HalGdma0Ch2IntrHandle = 0x3a75;
+ HalGdma0Ch3IntrHandle = 0x3ac5;
+ HalGdma0Ch4IntrHandle = 0x3b15;
+ HalGdma0Ch5IntrHandle = 0x3b65;
+ HalGdma1Ch0IntrHandle = 0x3bb5;
+ HalGdma1Ch1IntrHandle = 0x3c05;
+ HalGdma1Ch2IntrHandle = 0x3c55;
+ HalGdma1Ch3IntrHandle = 0x3ca5;
+ HalGdma1Ch4IntrHandle = 0x3cf5;
+ HalGdma1Ch5IntrHandle = 0x3d45;
+ HalSdioDeviceIntrHandle = 0x3d95;
+ VectorTableInitRtl8195A = 0x3de5;
+ VectorTableInitForOSRtl8195A = 0x4019;
+ VectorIrqRegisterRtl8195A = 0x4029;
+ VectorIrqUnRegisterRtl8195A = 0x4091;
+ VectorIrqEnRtl8195A = 0x40f1;
+ VectorIrqDisRtl8195A = 0x418d;
+ _UartRxDmaIrqHandle = 0x422d;
+ HalRuartPutCRtl8195a = 0x4281;
+ HalRuartGetCRtl8195a = 0x429d;
+ HalRuartRTSCtrlRtl8195a = 0x42bd;
+ HalRuartGetDebugValueRtl8195a = 0x42e1;
+ HalRuartGetIMRRtl8195a = 0x43e1;
+ HalRuartSetIMRRtl8195a = 0x442d;
+ _UartIrqHandle = 0x4465;
+ HalRuartDmaInitRtl8195a = 0x4681;
+ HalRuartIntDisableRtl8195a = 0x4845;
+ HalRuartDeInitRtl8195a = 0x4855;
+ HalRuartIntEnableRtl8195a = 0x4985;
+ _UartTxDmaIrqHandle = 0x4995;
+ HalRuartRegIrqRtl8195a = 0x49d1;
+ HalRuartAdapterLoadDefRtl8195a = 0x4a4d;
+ HalRuartTxGdmaLoadDefRtl8195a = 0x4add;
+ HalRuartRxGdmaLoadDefRtl8195a = 0x4bc9;
+ RuartLock = 0x4cc9;
+ RuartUnLock = 0x4ced;
+ HalRuartIntSendRtl8195a = 0x4d09;
+ HalRuartDmaSendRtl8195a = 0x4e35;
+ HalRuartStopSendRtl8195a = 0x4f89;
+ HalRuartIntRecvRtl8195a = 0x504d;
+ HalRuartDmaRecvRtl8195a = 0x51ad;
+ HalRuartStopRecvRtl8195a = 0x52cd;
+ RuartIsTimeout = 0x5385;
+ HalRuartSendRtl8195a = 0x53b1;
+ HalRuartRecvRtl8195a = 0x5599;
+ RuartResetRxFifoRtl8195a = 0x5751;
+ HalRuartResetRxFifoRtl8195a = 0x5775;
+ HalRuartInitRtl8195a = 0x5829;
+ HalGdmaOnOffRtl8195a = 0x5df1;
+ HalGdmaChIsrEnAndDisRtl8195a = 0x5e0d;
+ HalGdmaChEnRtl8195a = 0x5e51;
+ HalGdmaChDisRtl8195a = 0x5e6d;
+ HalGdamChInitRtl8195a = 0x5e91;
+ HalGdmaChSetingRtl8195a = 0x5ebd;
+ HalGdmaChBlockSetingRtl8195a = 0x60dd;
+ HalGdmaChIsrCleanRtl8195a = 0x6419;
+ HalGdmaChCleanAutoSrcRtl8195a = 0x64a1;
+ HalGdmaChCleanAutoDstRtl8195a = 0x6501;
+ HalEFUSEPowerSwitch8195AROM = 0x6561;
+ HALEFUSEOneByteReadROM = 0x65f9;
+ HALEFUSEOneByteWriteROM = 0x6699;
+ __rtl_memcmpb_v1_00 = 0x681d;
+ __rtl_random_v1_00 = 0x6861;
+ __rtl_align_to_be32_v1_00 = 0x6881;
+ __rtl_memsetw_v1_00 = 0x6899;
+ __rtl_memsetb_v1_00 = 0x68ad;
+ __rtl_memcpyw_v1_00 = 0x68bd;
+ __rtl_memcpyb_v1_00 = 0x68dd;
+ __rtl_memDump_v1_00 = 0x68f5;
+ __rtl_AES_set_encrypt_key = 0x6901;
+ __rtl_cryptoEngine_AES_set_decrypt_key = 0x6c11;
+ __rtl_cryptoEngine_set_security_mode_v1_00 = 0x6c95;
+ __rtl_cryptoEngine_init_v1_00 = 0x6ea9;
+ __rtl_cryptoEngine_exit_v1_00 = 0x7055;
+ __rtl_cryptoEngine_reset_v1_00 = 0x70b1;
+ __rtl_cryptoEngine_v1_00 = 0x70ed;
+ __rtl_crypto_cipher_init_v1_00 = 0x7c69;
+ __rtl_crypto_cipher_encrypt_v1_00 = 0x7c89;
+ __rtl_crypto_cipher_decrypt_v1_00 = 0x7cad;
+ HalSsiPinmuxEnableRtl8195a = 0x7cd5;
+ HalSsiEnableRtl8195a = 0x7e45;
+ HalSsiDisableRtl8195a = 0x7ef9;
+ HalSsiLoadSettingRtl8195a = 0x7fad;
+ HalSsiSetInterruptMaskRtl8195a = 0x8521;
+ HalSsiGetInterruptMaskRtl8195a = 0x85c9;
+ HalSsiSetSclkPolarityRtl8195a = 0x863d;
+ HalSsiSetSclkPhaseRtl8195a = 0x8715;
+ HalSsiWriteRtl8195a = 0x87e9;
+ HalSsiSetDeviceRoleRtl8195a = 0x8861;
+ HalSsiSetRxFifoThresholdLevelRtl8195a = 0x88c9;
+ HalSsiSetTxFifoThresholdLevelRtl8195a = 0x8941;
+ HalSsiReadRtl8195a = 0x89b9;
+ HalSsiGetRxFifoLevelRtl8195a = 0x8a2d;
+ HalSsiGetTxFifoLevelRtl8195a = 0x8aa5;
+ HalSsiGetStatusRtl8195a = 0x8b1d;
+ HalSsiWriteableRtl8195a = 0x8b91;
+ HalSsiReadableRtl8195a = 0x8c09;
+ HalSsiBusyRtl8195a = 0x8c81;
+ HalSsiReadInterruptRtl8195a = 0x8cf9;
+ HalSsiWriteInterruptRtl8195a = 0x8efd;
+ HalSsiSetSlaveEnableRegisterRtl8195a = 0x9009;
+ HalSsiGetInterruptStatusRtl8195a = 0x90d9;
+ HalSsiInterruptEnableRtl8195a = 0x914d;
+ HalSsiInterruptDisableRtl8195a = 0x9299;
+ HalSsiGetRawInterruptStatusRtl8195a = 0x93e9;
+ HalSsiGetSlaveEnableRegisterRtl8195a = 0x945d;
+ HalSsiInitRtl8195a = 0x94d1;
+ _SsiReadInterrupt = 0x9ba5;
+ _SsiWriteInterrupt = 0x9db1;
+ _SsiIrqHandle = 0x9eb1;
+ HalI2CWrite32 = 0xa061;
+ HalI2CRead32 = 0xa09d;
+ HalI2CDeInit8195a = 0xa0dd;
+ HalI2CSendRtl8195a = 0xa1f1;
+ HalI2CReceiveRtl8195a = 0xa25d;
+ HalI2CEnableRtl8195a = 0xa271;
+ HalI2CIntrCtrl8195a = 0xa389;
+ HalI2CReadRegRtl8195a = 0xa3a1;
+ HalI2CWriteRegRtl8195a = 0xa3b1;
+ HalI2CSetCLKRtl8195a = 0xa3c5;
+ HalI2CMassSendRtl8195a = 0xa6e9;
+ HalI2CClrIntrRtl8195a = 0xa749;
+ HalI2CClrAllIntrRtl8195a = 0xa761;
+ HalI2CInit8195a = 0xa775;
+ HalI2CDMACtrl8195a = 0xaa31;
+ RtkI2CIoCtrl = 0xaa61;
+ RtkI2CPowerCtrl = 0xaa65;
+ HalI2COpInit = 0xaa69;
+ I2CIsTimeout = 0xac65;
+ I2CTXGDMAISRHandle = 0xb435;
+ I2CRXGDMAISRHandle = 0xb4c1;
+ RtkI2CIrqInit = 0xb54d;
+ RtkI2CIrqDeInit = 0xb611;
+ RtkI2CPinMuxInit = 0xb675;
+ RtkI2CPinMuxDeInit = 0xb7c9;
+ RtkI2CDMAInit = 0xb955;
+ RtkI2CInit = 0xbc95;
+ RtkI2CDMADeInit = 0xbdad;
+ RtkI2CDeInit = 0xbe4d;
+ RtkI2CSendUserAddr = 0xbee5;
+ RtkI2CSend = 0xc07d;
+ RtkI2CLoadDefault = 0xce51;
+ RtkSalI2COpInit = 0xcf21;
+ HalI2SWrite32 = 0xcf65;
+ HalI2SRead32 = 0xcf85;
+ HalI2SDeInitRtl8195a = 0xcfa9;
+ HalI2STxRtl8195a = 0xcfc9;
+ HalI2SRxRtl8195a = 0xd011;
+ HalI2SEnableRtl8195a = 0xd05d;
+ HalI2SIntrCtrlRtl8195a = 0xd0b1;
+ HalI2SReadRegRtl8195a = 0xd0d1;
+ HalI2SClrIntrRtl8195a = 0xd0dd;
+ HalI2SClrAllIntrRtl8195a = 0xd0fd;
+ HalI2SInitRtl8195a = 0xd11d;
+ GPIO_GetIPPinName_8195a = 0xd2e5;
+ GPIO_GetChipPinName_8195a = 0xd331;
+ GPIO_PullCtrl_8195a = 0xd39d;
+ GPIO_FuncOn_8195a = 0xd421;
+ GPIO_FuncOff_8195a = 0xd481;
+ GPIO_Int_Mask_8195a = 0xd4e9;
+ GPIO_Int_SetType_8195a = 0xd511;
+ HAL_GPIO_IrqHandler_8195a = 0xd5fd;
+ HAL_GPIO_MbedIrqHandler_8195a = 0xd645;
+ HAL_GPIO_UserIrqHandler_8195a = 0xd6a1;
+ HAL_GPIO_IntCtrl_8195a = 0xd6cd;
+ HAL_GPIO_Init_8195a = 0xd805;
+ HAL_GPIO_DeInit_8195a = 0xdac1;
+ HAL_GPIO_ReadPin_8195a = 0xdbd1;
+ HAL_GPIO_WritePin_8195a = 0xdc91;
+ HAL_GPIO_RegIrq_8195a = 0xddad;
+ HAL_GPIO_UnRegIrq_8195a = 0xddf5;
+ HAL_GPIO_UserRegIrq_8195a = 0xde15;
+ HAL_GPIO_UserUnRegIrq_8195a = 0xdef9;
+ HAL_GPIO_MaskIrq_8195a = 0xdfc1;
+ HAL_GPIO_UnMaskIrq_8195a = 0xe061;
+ HAL_GPIO_IntDebounce_8195a = 0xe101;
+ HAL_GPIO_GetIPPinName_8195a = 0xe1c1;
+ HAL_GPIO_PullCtrl_8195a = 0xe1c9;
+ DumpForOneBytes = 0xe259;
+ CmdRomHelp = 0xe419;
+ CmdWriteWord = 0xe491;
+ CmdDumpHelfWord = 0xe505;
+ CmdDumpWord = 0xe5f1;
+ CmdDumpByte = 0xe6f5;
+ CmdSpiFlashTool = 0xe751;
+ GetRomCmdNum = 0xe7a9;
+ CmdWriteByte = 0xe7ad;
+ Isspace = 0xe7ed;
+ Strtoul = 0xe801;
+ ArrayInitialize = 0xe8b1;
+ GetArgc = 0xe8c9;
+ GetArgv = 0xe8f9;
+ UartLogCmdExecute = 0xe95d;
+ UartLogShowBackSpace = 0xe9fd;
+ UartLogRecallOldCmd = 0xea39;
+ UartLogHistoryCmd = 0xea71;
+ UartLogCmdChk = 0xeadd;
+ UartLogIrqHandle = 0xebf5;
+ RtlConsolInit = 0xecc5;
+ RtlConsolTaskRom = 0xed49;
+ RtlExitConsol = 0xed79;
+ RtlConsolRom = 0xedcd;
+ HalTimerOpInit = 0xee0d;
+ HalTimerIrq2To7Handle = 0xee59;
+ HalGetTimerIdRtl8195a = 0xef09;
+ HalTimerInitRtl8195a = 0xef3d;
+ HalTimerDisRtl8195a = 0xf069;
+ HalTimerEnRtl8195a = 0xf089;
+ HalTimerReadCountRtl8195a = 0xf0a9;
+ HalTimerIrqClearRtl8195a = 0xf0bd;
+ HalTimerDumpRegRtl8195a = 0xf0d1;
+ VSprintf = 0xf129;
+ DiagPrintf = 0xf39d;
+ DiagSPrintf = 0xf3b9;
+ DiagSnPrintf = 0xf3d1;
+ prvDiagPrintf = 0xf3ed;
+ prvDiagSPrintf = 0xf40d;
+ _memcmp = 0xf429;
+ _memcpy = 0xf465;
+ _memset = 0xf511;
+ __memcmp = 0xf429;
+ __memcpy = 0xf465;
+ __memset = 0xf511;
+ Rand = 0xf585;
+ _strncpy = 0xf60d;
+ _strcpy = 0xf629;
+ __strncpy = 0xf60d;
+ __strcpy = 0xf629;
+ prvStrCpy = 0xf639;
+ _strlen = 0xf651;
+ _strnlen = 0xf669;
+ __strlen = 0xf651;
+ __strnlen = 0xf669;
+ prvStrLen = 0xf699;
+ _strcmp = 0xf6b1;
+ _strncmp = 0xf6d1;
+ __strcmp = 0xf6b1;
+ __strncmp = 0xf6d1;
+ prvStrCmp = 0xf719;
+ StrUpr = 0xf749;
+ prvAtoi = 0xf769;
+ prvStrStr = 0xf7bd;
+ _strsep = 0xf7d5;
+ __strsep = 0xf7d5;
+ skip_spaces = 0xf815;
+ skip_atoi = 0xf831;
+ _parse_integer_fixup_radix = 0xf869;
+ _parse_integer = 0xf8bd;
+ simple_strtoull = 0xf915;
+ simple_strtoll = 0xf945;
+ simple_strtoul = 0xf965;
+ simple_strtol = 0xf96d;
+ _vsscanf = 0xf985;
+ _sscanf = 0xff71;
+ div_u64 = 0xff91;
+ div_s64 = 0xff99;
+ div_u64_rem = 0xffa1;
+ div_s64_rem = 0xffb1;
+ __strpbrk = 0xffc1;
+ __strchr = 0xffed;
+ aes_set_key = 0x10005;
+ aes_encrypt = 0x103d1;
+ aes_decrypt = 0x114a5;
+ AES_WRAP = 0x125c9;
+ AES_UnWRAP = 0x12701;
+ crc32_get = 0x12861;
+ arc4_byte = 0x12895;
+ rt_arc4_init = 0x128bd;
+ rt_arc4_crypt = 0x12901;
+ rt_md5_init = 0x131c1;
+ rt_md5_append = 0x131f5;
+ rt_md5_final = 0x1327d;
+ rt_md5_hmac = 0x132d5;
+ rtw_get_bit_value_from_ieee_value = 0x13449;
+ rtw_is_cckrates_included = 0x13475;
+ rtw_is_cckratesonly_included = 0x134b5;
+ rtw_check_network_type = 0x134dd;
+ rtw_set_fixed_ie = 0x1350d;
+ rtw_set_ie = 0x1352d;
+ rtw_get_ie = 0x1355d;
+ rtw_set_supported_rate = 0x13591;
+ rtw_get_rateset_len = 0x13611;
+ rtw_get_wpa_ie = 0x1362d;
+ rtw_get_wpa2_ie = 0x136c9;
+ rtw_get_wpa_cipher_suite = 0x13701;
+ rtw_get_wpa2_cipher_suite = 0x13769;
+ rtw_parse_wpa_ie = 0x137d1;
+ rtw_parse_wpa2_ie = 0x138ad;
+ rtw_get_sec_ie = 0x13965;
+ rtw_get_wps_ie = 0x13a15;
+ rtw_get_wps_attr = 0x13a99;
+ rtw_get_wps_attr_content = 0x13b49;
+ rtw_ieee802_11_parse_elems = 0x13b91;
+ str_2char2num = 0x13d9d;
+ key_2char2num = 0x13db9;
+ convert_ip_addr = 0x13dd1;
+ rom_psk_PasswordHash = 0x13e9d;
+ rom_psk_CalcGTK = 0x13ed5;
+ rom_psk_CalcPTK = 0x13f69;
+ wep_80211_encrypt = 0x14295;
+ wep_80211_decrypt = 0x142f5;
+ tkip_micappendbyte = 0x14389;
+ rtw_secmicsetkey = 0x143d9;
+ rtw_secmicappend = 0x14419;
+ rtw_secgetmic = 0x14435;
+ rtw_seccalctkipmic = 0x1449d;
+ tkip_phase1 = 0x145a5;
+ tkip_phase2 = 0x14725;
+ tkip_80211_encrypt = 0x14941;
+ tkip_80211_decrypt = 0x149d5;
+ aes1_encrypt = 0x14a8d;
+ aesccmp_construct_mic_iv = 0x14c65;
+ aesccmp_construct_mic_header1 = 0x14ccd;
+ aesccmp_construct_mic_header2 = 0x14d21;
+ aesccmp_construct_ctr_preload = 0x14db5;
+ aes_80211_encrypt = 0x14e29;
+ aes_80211_decrypt = 0x151ad;
+ _sha1_process_message_block = 0x155b9;
+ _sha1_pad_message = 0x15749;
+ rt_sha1_init = 0x157e5;
+ rt_sha1_update = 0x15831;
+ rt_sha1_finish = 0x158a9;
+ rt_hmac_sha1 = 0x15909;
+ rom_aes_128_cbc_encrypt = 0x15a65;
+ rom_aes_128_cbc_decrypt = 0x15ae1;
+ rom_rijndaelKeySetupEnc = 0x15b5d;
+ rom_aes_decrypt_init = 0x15c39;
+ rom_aes_internal_decrypt = 0x15d15;
+ rom_aes_decrypt_deinit = 0x16071;
+ rom_aes_encrypt_init = 0x16085;
+ rom_aes_internal_encrypt = 0x1609d;
+ rom_aes_encrypt_deinit = 0x16451;
+ bignum_init = 0x17b35;
+ bignum_deinit = 0x17b61;
+ bignum_get_unsigned_bin_len = 0x17b81;
+ bignum_get_unsigned_bin = 0x17b85;
+ bignum_set_unsigned_bin = 0x17c21;
+ bignum_cmp = 0x17cd1;
+ bignum_cmp_d = 0x17cd5;
+ bignum_add = 0x17cfd;
+ bignum_sub = 0x17d0d;
+ bignum_mul = 0x17d1d;
+ bignum_exptmod = 0x17d2d;
+ WPS_realloc = 0x17d51;
+ os_zalloc = 0x17d99;
+ rom_hmac_sha256_vector = 0x17dc1;
+ rom_hmac_sha256 = 0x17ebd;
+ rom_sha256_vector = 0x18009;
+ phy_CalculateBitShift = 0x18221;
+ PHY_SetBBReg_8195A = 0x18239;
+ PHY_QueryBBReg_8195A = 0x18279;
+ ROM_odm_QueryRxPwrPercentage = 0x1829d;
+ ROM_odm_EVMdbToPercentage = 0x182bd;
+ ROM_odm_SignalScaleMapping_8195A = 0x182e5;
+ ROM_odm_FalseAlarmCounterStatistics = 0x183cd;
+ ROM_odm_SetEDCCAThreshold = 0x18721;
+ ROM_odm_SetTRxMux = 0x18749;
+ ROM_odm_SetCrystalCap = 0x18771;
+ ROM_odm_GetDefaultCrytaltalCap = 0x187d5;
+ ROM_ODM_CfoTrackingReset = 0x187e9;
+ ROM_odm_CfoTrackingFlow = 0x18811;
+ curve25519_donna = 0x1965d;
+ aes_test_alignment_detection = 0x1a391;
+ aes_mode_reset = 0x1a3ed;
+ aes_ecb_encrypt = 0x1a3f9;
+ aes_ecb_decrypt = 0x1a431;
+ aes_cbc_encrypt = 0x1a469;
+ aes_cbc_decrypt = 0x1a579;
+ aes_cfb_encrypt = 0x1a701;
+ aes_cfb_decrypt = 0x1a9e5;
+ aes_ofb_crypt = 0x1acc9;
+ aes_ctr_crypt = 0x1af7d;
+ aes_encrypt_key128 = 0x1b289;
+ aes_encrypt_key192 = 0x1b2a5;
+ aes_encrypt_key256 = 0x1b2c1;
+ aes_encrypt_key = 0x1b2e1;
+ aes_decrypt_key128 = 0x1b351;
+ aes_decrypt_key192 = 0x1b36d;
+ aes_decrypt_key256 = 0x1b389;
+ aes_decrypt_key = 0x1b3a9;
+ aes_init = 0x1b419;
+ CRYPTO_chacha_20 = 0x1b41d;
+ CRYPTO_poly1305_init = 0x1bc25;
+ CRYPTO_poly1305_update = 0x1bd09;
+ CRYPTO_poly1305_finish = 0x1bd8d;
+ rom_sha512_starts = 0x1ceb5;
+ rom_sha512_update = 0x1d009;
+ rom_sha512_finish = 0x1d011;
+ rom_sha512 = 0x1d261;
+ rom_sha512_hmac_starts = 0x1d299;
+ rom_sha512_hmac_update = 0x1d35d;
+ rom_sha512_hmac_finish = 0x1d365;
+ rom_sha512_hmac_reset = 0x1d3b5;
+ rom_sha512_hmac = 0x1d3d1;
+ rom_sha512_hkdf = 0x1d40d;
+ rom_ed25519_gen_keypair = 0x1d501;
+ rom_ed25519_gen_signature = 0x1d505;
+ rom_ed25519_verify_signature = 0x1d51d;
+ rom_ed25519_crypto_sign_seed_keypair = 0x1d521;
+ rom_ed25519_crypto_sign_detached = 0x1d579;
+ rom_ed25519_crypto_sign_verify_detached = 0x1d655;
+ rom_ed25519_ge_double_scalarmult_vartime = 0x1f86d;
+ rom_ed25519_ge_frombytes_negate_vartime = 0x1fc35;
+ rom_ed25519_ge_p3_tobytes = 0x207d5;
+ rom_ed25519_ge_scalarmult_base = 0x20821;
+ rom_ed25519_ge_tobytes = 0x209e1;
+ rom_ed25519_sc_muladd = 0x20a2d;
+ rom_ed25519_sc_reduce = 0x2603d;
+ __rtl_memchr_v1_00 = 0x28a4d;
+ __rtl_memcmp_v1_00 = 0x28ae1;
+ __rtl_memcpy_v1_00 = 0x28b49;
+ __rtl_memmove_v1_00 = 0x28bed;
+ __rtl_memset_v1_00 = 0x28cb5;
+ __rtl_strcat_v1_00 = 0x28d49;
+ __rtl_strchr_v1_00 = 0x28d91;
+ __rtl_strcmp_v1_00 = 0x28e55;
+ __rtl_strcpy_v1_00 = 0x28ec9;
+ __rtl_strlen_v1_00 = 0x28f15;
+ __rtl_strncat_v1_00 = 0x28f69;
+ __rtl_strncmp_v1_00 = 0x28fc5;
+ __rtl_strncpy_v1_00 = 0x2907d;
+ __rtl_strstr_v1_00 = 0x293cd;
+ __rtl_strsep_v1_00 = 0x2960d;
+ __rtl_strtok_v1_00 = 0x29619;
+ __rtl__strtok_r_v1_00 = 0x2962d;
+ __rtl_strtok_r_v1_00 = 0x29691;
+ __rtl_close_v1_00 = 0x29699;
+ __rtl_fstat_v1_00 = 0x296ad;
+ __rtl_isatty_v1_00 = 0x296c1;
+ __rtl_lseek_v1_00 = 0x296d5;
+ __rtl_open_v1_00 = 0x296e9;
+ __rtl_read_v1_00 = 0x296fd;
+ __rtl_write_v1_00 = 0x29711;
+ __rtl_sbrk_v1_00 = 0x29725;
+ __rtl_ltoa_v1_00 = 0x297bd;
+ __rtl_ultoa_v1_00 = 0x29855;
+ __rtl_dtoi_v1_00 = 0x298c5;
+ __rtl_dtoi64_v1_00 = 0x29945;
+ __rtl_dtoui_v1_00 = 0x299dd;
+ __rtl_ftol_v1_00 = 0x299e5;
+ __rtl_itof_v1_00 = 0x29a51;
+ __rtl_itod_v1_00 = 0x29ae9;
+ __rtl_i64tod_v1_00 = 0x29b79;
+ __rtl_uitod_v1_00 = 0x29c55;
+ __rtl_ftod_v1_00 = 0x29d2d;
+ __rtl_dtof_v1_00 = 0x29de9;
+ __rtl_uitof_v1_00 = 0x29e89;
+ __rtl_fadd_v1_00 = 0x29f65;
+ __rtl_fsub_v1_00 = 0x2a261;
+ __rtl_fmul_v1_00 = 0x2a559;
+ __rtl_fdiv_v1_00 = 0x2a695;
+ __rtl_dadd_v1_00 = 0x2a825;
+ __rtl_dsub_v1_00 = 0x2aed9;
+ __rtl_dmul_v1_00 = 0x2b555;
+ __rtl_ddiv_v1_00 = 0x2b8ad;
+ __rtl_dcmpeq_v1_00 = 0x2be4d;
+ __rtl_dcmplt_v1_00 = 0x2bebd;
+ __rtl_dcmpgt_v1_00 = 0x2bf51;
+ __rtl_dcmple_v1_00 = 0x2c049;
+ __rtl_fcmplt_v1_00 = 0x2c139;
+ __rtl_fcmpgt_v1_00 = 0x2c195;
+ __rtl_cos_f32_v1_00 = 0x2c229;
+ __rtl_sin_f32_v1_00 = 0x2c435;
+ __rtl_fabs_v1_00 = 0x2c639;
+ __rtl_fabsf_v1_00 = 0x2c641;
+ __rtl_dtoa_r_v1_00 = 0x2c77d;
+ __rom_mallocr_init_v1_00 = 0x2d7d1;
+ __rtl_free_r_v1_00 = 0x2d841;
+ __rtl_malloc_r_v1_00 = 0x2da31;
+ __rtl_realloc_r_v1_00 = 0x2df55;
+ __rtl_memalign_r_v1_00 = 0x2e331;
+ __rtl_valloc_r_v1_00 = 0x2e421;
+ __rtl_pvalloc_r_v1_00 = 0x2e42d;
+ __rtl_calloc_r_v1_00 = 0x2e441;
+ __rtl_cfree_r_v1_00 = 0x2e4a9;
+ __rtl_Balloc_v1_00 = 0x2e515;
+ __rtl_Bfree_v1_00 = 0x2e571;
+ __rtl_i2b_v1_00 = 0x2e585;
+ __rtl_multadd_v1_00 = 0x2e599;
+ __rtl_mult_v1_00 = 0x2e629;
+ __rtl_pow5mult_v1_00 = 0x2e769;
+ __rtl_hi0bits_v1_00 = 0x2e809;
+ __rtl_d2b_v1_00 = 0x2e845;
+ __rtl_lshift_v1_00 = 0x2e901;
+ __rtl_cmp_v1_00 = 0x2e9bd;
+ __rtl_diff_v1_00 = 0x2ea01;
+ __rtl_sread_v1_00 = 0x2eae9;
+ __rtl_seofread_v1_00 = 0x2eb39;
+ __rtl_swrite_v1_00 = 0x2eb3d;
+ __rtl_sseek_v1_00 = 0x2ebc1;
+ __rtl_sclose_v1_00 = 0x2ec11;
+ __rtl_sbrk_r_v1_00 = 0x2ec41;
+ __rtl_fflush_r_v1_00 = 0x2ef8d;
+ __rtl_vfprintf_r_v1_00 = 0x2f661;
+ __rtl_fpclassifyd = 0x30c15;
+ CpkClkTbl = 0x30c68;
+ ROM_IMG1_VALID_PATTEN = 0x30c80;
+ SpicCalibrationPattern = 0x30c88;
+ SpicInitCPUCLK = 0x30c98;
+ BAUDRATE = 0x30ca8;
+ OVSR = 0x30d1c;
+ DIV = 0x30d90;
+ OVSR_ADJ = 0x30e04;
+ __AES_rcon = 0x30e78;
+ __AES_Te4 = 0x30ea0;
+ I2CDmaChNo = 0x312a0;
+ _GPIO_PinMap_Chip2IP_8195a = 0x312b4;
+ _GPIO_PinMap_PullCtrl_8195a = 0x3136c;
+ _GPIO_SWPORT_DDR_TBL = 0x31594;
+ _GPIO_EXT_PORT_TBL = 0x31598;
+ _GPIO_SWPORT_DR_TBL = 0x3159c;
+ UartLogRomCmdTable = 0x316a0;
+ _HalRuartOp = 0x31700;
+ _HalGdmaOp = 0x31760;
+ RTW_WPA_OUI_TYPE = 0x3540c;
+ WPA_CIPHER_SUITE_NONE = 0x35410;
+ WPA_CIPHER_SUITE_WEP40 = 0x35414;
+ WPA_CIPHER_SUITE_TKIP = 0x35418;
+ WPA_CIPHER_SUITE_CCMP = 0x3541c;
+ WPA_CIPHER_SUITE_WEP104 = 0x35420;
+ RSN_CIPHER_SUITE_NONE = 0x35424;
+ RSN_CIPHER_SUITE_WEP40 = 0x35428;
+ RSN_CIPHER_SUITE_TKIP = 0x3542c;
+ RSN_CIPHER_SUITE_CCMP = 0x35430;
+ RSN_CIPHER_SUITE_WEP104 = 0x35434;
+ RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X = 0x35444;
+ RSN_AUTH_KEY_MGMT_UNSPEC_802_1X = 0x35448;
+ RSN_VERSION_BSD = 0x3544c;
+ rom_wps_Te0 = 0x35988;
+ rom_wps_rcons = 0x35d88;
+ rom_wps_Td4s = 0x35d94;
+ rom_wps_Td0 = 0x35e94;
+ __rom_b_cut_end__ = 0x4467c;
+ __rom_c_cut_text_start__ = 0x4467c;
+ HalInitPlatformLogUartV02 = 0x4467d;
+ HalReInitPlatformLogUartV02 = 0x4471d;
+ HalInitPlatformTimerV02 = 0x44755;
+ HalShowBuildInfoV02 = 0x447cd;
+ SpicReleaseDeepPowerDownFlashRtl8195A = 0x44831;
+ HalSpiInitV02 = 0x4488d;
+ HalBootFlowV02 = 0x44a29;
+ HalInitialROMCodeGlobalVarV02 = 0x44ae5;
+ HalResetVsrV02 = 0x44b41;
+ HalI2CSendRtl8195aV02 = 0x44ce1;
+ HalI2CSetCLKRtl8195aV02 = 0x44d59;
+ RtkI2CSendV02 = 0x4508d;
+ RtkI2CReceiveV02 = 0x459a1;
+ HalI2COpInitV02 = 0x461ed;
+ I2CISRHandleV02 = 0x463e9;
+ RtkSalI2COpInitV02 = 0x46be1;
+ SpicLoadInitParaFromClockRtl8195AV02 = 0x46c25;
+ SpiFlashAppV02 = 0x46c85;
+ SpicInitRtl8195AV02 = 0x46dc5;
+ SpicEraseFlashRtl8195AV02 = 0x46ea1;
+ HalTimerIrq2To7HandleV02 = 0x46f5d;
+ HalTimerIrqRegisterRtl8195aV02 = 0x46fe1;
+ HalTimerInitRtl8195aV02 = 0x4706d;
+ HalTimerReadCountRtl8195aV02 = 0x471b5;
+ HalTimerReLoadRtl8195aV02 = 0x471d1;
+ HalTimerIrqUnRegisterRtl8195aV02 = 0x4722d;
+ HalTimerDeInitRtl8195aV02 = 0x472c1;
+ HalTimerOpInitV02 = 0x472f9;
+ GPIO_LockV02 = 0x47345;
+ GPIO_UnLockV02 = 0x47379;
+ GPIO_Int_Clear_8195aV02 = 0x473a5;
+ HAL_GPIO_IntCtrl_8195aV02 = 0x473b5;
+ FindElementIndexV02 = 0x47541;
+ HalRuartInitRtl8195aV02 = 0x4756d;
+ DramInit_rom = 0x47619;
+ ChangeRandSeed_rom = 0x47979;
+ Sdr_Rand2_rom = 0x47985;
+ MemTest_rom = 0x479dd;
+ SdrCalibration_rom = 0x47a45;
+ SdrControllerInit_rom = 0x47d99;
+ SDIO_EnterCritical = 0x47e39;
+ SDIO_ExitCritical = 0x47e85;
+ SDIO_IRQ_Handler_Rom = 0x47ec5;
+ SDIO_Interrupt_Init_Rom = 0x47f31;
+ SDIO_Device_Init_Rom = 0x47f81;
+ SDIO_Interrupt_DeInit_Rom = 0x48215;
+ SDIO_Device_DeInit_Rom = 0x48255;
+ SDIO_Enable_Interrupt_Rom = 0x48281;
+ SDIO_Disable_Interrupt_Rom = 0x482a1;
+ SDIO_Clear_ISR_Rom = 0x482c1;
+ SDIO_Alloc_Rx_Pkt_Rom = 0x482d9;
+ SDIO_Free_Rx_Pkt_Rom = 0x48331;
+ SDIO_Recycle_Rx_BD_Rom = 0x48355;
+ SDIO_RX_IRQ_Handler_BH_Rom = 0x484f1;
+ SDIO_RxTask_Rom = 0x4851d;
+ SDIO_Process_H2C_IOMsg_Rom = 0x4856d;
+ SDIO_Send_C2H_IOMsg_Rom = 0x4859d;
+ SDIO_Process_RPWM_Rom = 0x485b5;
+ SDIO_Reset_Cmd_Rom = 0x485e9;
+ SDIO_Rx_Data_Transaction_Rom = 0x48611;
+ SDIO_Send_C2H_PktMsg_Rom = 0x48829;
+ SDIO_Register_Tx_Callback_Rom = 0x488f5;
+ SDIO_ReadMem_Rom = 0x488fd;
+ SDIO_WriteMem_Rom = 0x489a9;
+ SDIO_SetMem_Rom = 0x48a69;
+ SDIO_TX_Pkt_Handle_Rom = 0x48b29;
+ SDIO_TX_FIFO_DataReady_Rom = 0x48c69;
+ SDIO_IRQ_Handler_BH_Rom = 0x48d95;
+ SDIO_TxTask_Rom = 0x48e9d;
+ SDIO_TaskUp_Rom = 0x48eed;
+ SDIO_Boot_Up = 0x48f55;
+ __rom_c_cut_text_end__ = 0x49070;
+ __rom_c_cut_rodata_start__ = 0x49070;
+ BAUDRATE_v02 = 0x49070;
+ OVSR_v02 = 0x490fc;
+ DIV_v02 = 0x49188;
+ OVSR_ADJ_v02 = 0x49214;
+ SdrDramInfo_rom = 0x492a0;
+ SdrDramTiming_rom = 0x492b4;
+ SdrDramModeReg_rom = 0x492e8;
+ SdrDramDev_rom = 0x49304;
+ __rom_c_cut_rodata_end__ = 0x49314;
+ NewVectorTable = 0x10000000;
+ UserIrqFunTable = 0x10000100;
+ UserIrqDataTable = 0x10000200;
+ __rom_bss_start__ = 0x10000300;
+ CfgSysDebugWarn = 0x10000300;
+ CfgSysDebugInfo = 0x10000304;
+ CfgSysDebugErr = 0x10000308;
+ ConfigDebugWarn = 0x1000030c;
+ ConfigDebugInfo = 0x10000310;
+ ConfigDebugErr = 0x10000314;
+ HalTimerOp = 0x10000318;
+ GPIOState = 0x10000334;
+ gTimerRecord = 0x1000034c;
+ SSI_DBG_CONFIG = 0x10000350;
+ _pHAL_Gpio_Adapter = 0x10000354;
+ Timer2To7VectorTable = 0x10000358;
+ pUartLogCtl = 0x10000384;
+ UartLogBuf = 0x10000388;
+ UartLogCtl = 0x10000408;
+ UartLogHistoryBuf = 0x10000430;
+ ArgvArray = 0x100006ac;
+ rom_wlan_ram_map = 0x100006d4;
+ FalseAlmCnt = 0x100006e0;
+ ROMInfo = 0x10000720;
+ DM_CfoTrack = 0x10000738;
+ rom_libgloss_ram_map = 0x10000760;
+ __rtl_errno = 0x10000bc4;
+}
Binary file targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/lib_peripheral_mbed_iar.a has changed
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/rtl8195a.icf Thu Aug 31 17:27:04 2017 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/rtl8195a.icf Fri Sep 15 14:59:18 2017 +0100
@@ -16,7 +16,7 @@
//define symbol __ICFEDIT_region_RECY_RAM_start__ = 0x10002090;
//define symbol __ICFEDIT_region_RECY_RAM_end__ = 0x100037FF;
if( !isdefinedsymbol( __ICFEDIT_region_BD_RAM_start__ ) ) {
- define symbol __ICFEDIT_region_BD_RAM_start__ = 0x10006000;
+ define symbol __ICFEDIT_region_BD_RAM_start__ = 0x10007000;
}
if( !isdefinedsymbol( __ICFEDIT_region_BD_RAM_end__ ) ) {
define symbol __ICFEDIT_region_BD_RAM_end__ = 0x1006FFFF;
@@ -31,12 +31,12 @@
define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region TCM_region = mem:[from __ICFEDIT_region_TCM_start__ to __ICFEDIT_region_TCM_end__];
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region TCM_region = mem:[from __ICFEDIT_region_TCM_start__ to __ICFEDIT_region_TCM_end__];
define region ROM_USED_RAM_region = mem:[from __ICFEDIT_region_ROM_USED_RAM_start__ to __ICFEDIT_region_ROM_USED_RAM_end__];
-//define region RECY_RAM_region = mem:[from __ICFEDIT_region_RECY_RAM_start__ to __ICFEDIT_region_RECY_RAM_end__];
-define region BD_RAM_region = mem:[from __ICFEDIT_region_BD_RAM_start__ to __ICFEDIT_region_BD_RAM_end__];
-define region SDRAM_RAM_region = mem:[from __ICFEDIT_region_SDRAM_RAM_start__ to __ICFEDIT_region_SDRAM_RAM_end__];
+//define region RECY_RAM_region = mem:[from __ICFEDIT_region_RECY_RAM_start__ to __ICFEDIT_region_RECY_RAM_end__];
+define region BD_RAM_region = mem:[from __ICFEDIT_region_BD_RAM_start__ to __ICFEDIT_region_BD_RAM_end__];
+define region SDRAM_RAM_region = mem:[from __ICFEDIT_region_SDRAM_RAM_start__ to __ICFEDIT_region_SDRAM_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
@@ -95,11 +95,11 @@
section .infra.ram.data*,
section .timer.ram.data*,
section .cutb.ram.data*,
- section .hal.ram.data* object rom.o, // for standard libaray __impure_data_ptr
+ section .hal.ram.data* object rom.o, // for standard libaray __impure_data_ptr
section .cutc.ram.data*,
section .hal.ram.data*
};
-define block .ram_image1.bss with fixed order{ //section .hal.flash.data*,
+define block .ram_image1.bss with fixed order{ //section .hal.flash.data*,
section .hal.sdrc.data*
};
@@ -113,13 +113,14 @@
define block IMAGE1_DBG with fixed order { block .ram.start.table, block .ram_image1.data, block .ram_image1.bss, block .ram_image1.text };
place at start of ROM_USED_RAM_region {
- block .vector_table,
- block .user_vector_table,
- block .user_data_table,
- block .rom.bss,
- block IMAGE1
- };
+ block .vector_table,
+ block .user_vector_table,
+ block .user_data_table,
+ block .rom.bss,
+ block IMAGE1
+ };
+
keep { section .image2.ram.data* };
define block .image2.start.table1 with fixed order{ section .image2.ram.data* };
@@ -133,97 +134,197 @@
block SHT$$INIT_ARRAY
};
define block FPB_REMAP with alignment = 256,fixed order {
- section .fpb.remap*
- };
-define block .ram_image2.text with fixed order{ section .infra.ram.start*,
- section .rodata*,
- block CPP_INIT,
+ section .fpb.remap*
+ };
+
+define block MBEDTLS_TEXT with alignment = 8, fixed order{
+ section .text* object aes.o,
+ section .text* object aesni.o,
+ section .text* object arc4.o,
+ section .text* object asn1parse.o,
+ section .text* object asn1write.o,
+ section .text* object base64.o,
+ section .text* object bignum.o,
+ section .text* object blowfish.o,
+ section .text* object camellia.o,
+ section .text* object ccm.o,
+ section .text* object certs.o,
+ section .text* object cipher.o,
+ section .text* object cipher_wrap.o,
+ section .text* object cmac.o,
+ section .text* object ctr_drbg.o,
+ section .text* object debug.o,
+ section .text* object des.o,
+ section .text* object dhm.o,
+ section .text* object ecdh.o,
+ section .text* object ecdsa.o,
+ section .text* object ecjpake.o,
+ section .text* object ecp.o,
+ section .text* object ecp_curves.o,
+ section .text* object entropy.o,
+ section .text* object entropy_poll.o,
+ section .text* object error.o,
+ section .text* object gcm.o,
+ section .text* object havege.o,
+ section .text* object hmac_drbg.o,
+ section .text* object md.o,
+ section .text* object md2.o,
+ section .text* object md4.o,
+ section .text* object md5.o,
+ section .text* object md_wrap.o,
+ section .text* object memory_buffer_alloc.o,
+ section .text* object net_sockets.o,
+ section .text* object oid.o,
+ section .text* object padlock.o,
+ section .text* object pem.o,
+ section .text* object pk.o,
+ section .text* object pk_wrap.o,
+ section .text* object pkcs11.o,
+ section .text* object pkcs12.o,
+ section .text* object pkcs5.o,
+ section .text* object pkparse.o,
+ section .text* object pkwrite.o,
+ section .text* object platform.o,
+ section .text* object ripemd160.o,
+ section .text* object rsa.o,
+ section .text* object sha1.o,
+ section .text* object sha256.o,
+ section .text* object sha512.o,
+ section .text* object ssl_cache.o,
+ section .text* object ssl_ciphersuites.o,
+ section .text* object ssl_cli.o,
+ section .text* object ssl_cookie.o,
+ section .text* object ssl_srv.o,
+ section .text* object ssl_ticket.o,
+ section .text* object ssl_tls.o,
+ section .text* object threading.o,
+ section .text* object timing.o,
+ section .text* object version.o,
+ section .text* object version_features.o,
+ section .text* object x509.o,
+ section .text* object x509_create.o,
+ section .text* object x509_crl.o,
+ section .text* object x509_crt.o,
+ section .text* object x509_csr.o,
+ section .text* object x509write_crt.o,
+ section .text* object x509write_csr.o,
+ section .text* object xtea.o,
+ };
+
+define block .sram1.text with fixed order {
+ block MBEDTLS_TEXT,
+ section .text* object Ticker.o,
+ section .text* object Timeout.o,
+ section .text* object TimerEvent.o,
+ section .text* object mbed_ticker_api.o,
+ section .text* object mbed_critical.o,
+ section .text* object us_ticker.o,
+
+ section .text* object lib_peripheral_mbed_iar.a,
+ };
+
+define block .sram2.text with fixed order {
+ block .image2.start.table1,
+ block .image2.start.table2,
section .mon.ram.text*,
section .hal.flash.text*,
+ section .hal.sdrc.text*,
section .hal.gpio.text*,
- section .text* object main.o,
section .text*,
- section .wlan.text,
- section .wps.text,
+ section .infra.ram.start*,
+ section .rodata*,
+ };
+
+define block .sram2.data with fixed order {
+ //section .infra.ram.start*,
+ //section .rodata*,
+ //section .wlan.text,
+ //section .wps.text,
section CODE,
- section .otg.rom.text,
+ //section .otg.rom.text,
section Veneer object startup.o,
section __DLIB_PERTHREAD,
section .iar.dynexit*,
+ block CPP_INIT,
//section .mdns.text
- };
+ };
+define block .ram.data with fixed order {
+ readwrite, readonly,
+ section .data*,
+ section .wlan.data,
+ section .wps.data,
+ section DATA,
+ section .ram.otg.data.a,
+ section .iar.init_table,
+ //section .mdns.data,
+ //section .data* object lib_peripheral_mbed_iar.a,
+ };
-define block .ram.data with fixed order{ readwrite, readonly,
- section .data*,
- section .wlan.data,
- section .wps.data,
- section DATA,
- section .ram.otg.data.a,
- section .iar.init_table,
- //section .mdns.data
- };
+define block .ram.bss with fixed order {
+ section .bss*,
+ section COMMON,
+ section .bdsram.data*,
+ };
-define block IMAGE2 with fixed order { block .image2.start.table1, block .image2.start.table2, block .ram_image2.text, block .ram.data };
+define block IMAGE2 with fixed order {
+ block .sram1.text,
+ block .ram.data,
+ block .ram.bss
+ };
-define block .ram.bss with fixed order{ section .bss*,
- section .ssl_ram_map,
- section .hal.flash.data*,
- section .hal.gpio.data*,
- section COMMON,
- section .bdsram.data*,
- section .bss* object heap_4.o
- };
define block .bf_data with fixed order{ section .bfsram.data* };
define block .heap with fixed order{ section .heap* };
define block .stack_dummy with fixed order { section .stack };
-place at start of BD_RAM_region {
+place at start of BD_RAM_region {
block IMAGE2,
//block IMAGE1_DBG,
- block .ram.bss,
+ //block .ram.bss,
//block .bf_data,
- };
+ };
-//place at address mem:0x10052b00 { readwrite,
place at end of BD_RAM_region {
block .bf_data,
block HEAP,
- };
-
-define block SDRAM with fixed order{ section .sdram.text*,
- section .sdram.data*,
- section .mdns.text*,
- section .mdns.data*,
- block FPB_REMAP
- };
+ };
+
+define block SDRAM with fixed order {
+ block .sram2.text,
+ block .sram2.data,
+ section .sdram.text*,
+ section .sdram.data*,
+ section .mdns.text*,
+ section .mdns.data*,
+ block FPB_REMAP
+ };
define block SDRBSS with fixed order{
- section .sdram.bss*
- };
+ section .sdram.bss*
+ };
-place at start of SDRAM_RAM_region {
- block SDRAM,
- block SDRBSS,
- //block IMAGE1_DBG
+place at start of SDRAM_RAM_region {
+ block SDRAM,
+ block SDRBSS,
+ //block IMAGE1_DBG
};
/* TCM placement */
define overlay TCM_overlay {
- section .tcm.heap,
- section .bss object lwip_mem.o,
- section .bss object lwip_memp.o,
- block .heap,
- block .stack_dummy
- };
+ section .tcm.heap,
+ section .bss object lwip_mem.o,
+ section .bss object lwip_memp.o,
+ block .heap,
+ block .stack_dummy
+ };
/* dummy code placement */
define overlay TCM_overlay { block IMAGE1_DBG };
-place at start of TCM_region { overlay TCM_overlay };
-place at end of TCM_region { block CSTACK};
+place at start of TCM_region { overlay TCM_overlay };
+place at end of TCM_region { block CSTACK};
-define exported symbol __rom_bss_start__ = 0x10000300; // use in rom
-define exported symbol __rom_bss_end__ = 0x10000bc8; // use in rom
-define exported symbol __ram_start_table_start__= 0x10000bc8; // use in rom
-define exported symbol __image1_validate_code__= 0x10000bdc; // needed by ram code
-define exported symbol _rtl_impure_ptr = 0x10001c60; // for standard library
+define exported symbol __rom_bss_start__ = 0x10000300; // use in rom
+define exported symbol __rom_bss_end__ = 0x10000bc8; // use in rom
+define exported symbol __ram_start_table_start__= 0x10000bc8; // use in rom
+define exported symbol __image1_validate_code__= 0x10000bdc; // needed by ram code
+define exported symbol _rtl_impure_ptr = 0x10001c60; // for standard library
define exported symbol __sdio_rom_bss_start__ = 0x1006D000;
define exported symbol __sdio_rom_bss_end__ = 0x1006fa10;
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/platform_autoconf.h Thu Aug 31 17:27:04 2017 +0100 +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/platform_autoconf.h Fri Sep 15 14:59:18 2017 +0100 @@ -186,7 +186,7 @@ #define CONFIG_UART_LOG_HISTORY 1 #undef CONFIG_CONSOLE_NORMALL_MODE #define CONFIG_CONSOLE_VERIFY_MODE 1 -#define CONFIG_DEBUG_LOG 1 +#undef CONFIG_DEBUG_LOG #define CONFIG_DEBUG_ERR_MSG 1 #undef CONFIG_DEBUG_WARN_MSG #undef CONFIG_DEBUG_INFO_MSG
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c Thu Aug 31 17:27:04 2017 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c Fri Sep 15 14:59:18 2017 +0100
@@ -14,26 +14,39 @@
* limitations under the License.
*/
#include "rtl8195a.h"
-#include "system_8195a.h"
-#if defined ( __CC_ARM ) /* ARM Compiler 4/5 */
-extern uint8_t Image$$RW_IRAM1$$ZI$$Base[];
-#define __bss_start__ Image$$RW_IRAM1$$ZI$$Base
-extern uint8_t Image$$RW_IRAM1$$ZI$$Limit[];
-#define __bss_end__ Image$$RW_IRAM1$$ZI$$Limit
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler 6 */
-extern uint8_t Image$$RW_IRAM1$$ZI$$Base[];
-#define __bss_start__ Image$$RW_IRAM1$$ZI$$Base
-extern uint8_t Image$$RW_IRAM1$$ZI$$Limit[];
-#define __bss_end__ Image$$RW_IRAM1$$ZI$$Limit
+
+#if defined(__CC_ARM)
+#include "cmsis_armcc.h"
+#elif defined(__GNUC__)
+#include "cmsis_gcc.h"
+#else
+#include <cmsis_iar.h>
+#endif
+
+
+#if defined(__CC_ARM) || \
+ (defined (__ARMCC_VERSION) && __ARMCC_VERSION >= 6010050)
-#elif defined ( __ICCARM__ )
+extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
+extern uint8_t Image$$RW_IRAM2$$ZI$$Base[];
+extern uint8_t Image$$RW_IRAM2$$ZI$$Limit[];
+extern uint8_t Image$$TCM_OVERLAY$$ZI$$Base[];
+extern uint8_t Image$$TCM_OVERLAY$$ZI$$Limit[];
+extern uint8_t Image$$RW_DRAM2$$ZI$$Base[];
+extern uint8_t Image$$RW_DRAM2$$ZI$$Limit[];
+#define __bss_sram_start__ Image$$RW_IRAM2$$ZI$$Base
+#define __bss_sram_end__ Image$$RW_IRAM2$$ZI$$Limit
+#define __bss_dtcm_start__ Image$$TCM_OVERLAY$$ZI$$Base
+#define __bss_dtcm_end__ Image$$TCM_OVERLAY$$ZI$$Limit
+#define __bss_dram_start__ Image$$RW_DRAM2$$ZI$$Base
+#define __bss_dram_end__ Image$$RW_DRAM2$$ZI$$Limit
+#define __stackp Image$$ARM_LIB_STACK$$ZI$$Limit
+
+#elif defined (__ICCARM__)
+
#pragma section=".ram.bss"
-#pragma section=".rom.bss"
-#pragma section=".ram.start.table"
-#pragma section=".ram_image1.bss"
-#pragma section=".image2.start.table1"
-#pragma section=".image2.start.table2"
+extern uint32_t CSTACK$$Limit;
uint8_t *__bss_start__;
uint8_t *__bss_end__;
@@ -42,30 +55,34 @@
__bss_start__ = (uint8_t *)__section_begin(".ram.bss");
__bss_end__ = (uint8_t *)__section_end(".ram.bss");
}
+#define __stackp CSTACK$$Limit
+
#else
-extern uint8_t __bss_start__[];
-extern uint8_t __bss_end__[];
-extern uint8_t __image1_bss_start__[];
-extern uint8_t __image1_bss_end__[];
-extern uint8_t __image2_entry_func__[];
-extern uint8_t __image2_validate_code__[];
+
+extern uint32_t __StackTop;
+extern uint32_t __StackLimit;
+extern uint8_t __bss_sram_start__[];
+extern uint8_t __bss_sram_end__[];
+extern uint8_t __bss_dtcm_start__[];
+extern uint8_t __bss_dtcm_end__[];
+extern uint8_t __bss_dram_start__[];
+extern uint8_t __bss_dram_end__[];
+
+#define __stackp __StackTop
#endif
extern VECTOR_Func NewVectorTable[];
extern void SystemCoreClockUpdate(void);
extern void PLAT_Start(void);
extern void PLAT_Main(void);
-extern HAL_TIMER_OP HalTimerOp;
-
-IMAGE2_START_RAM_FUN_SECTION const RAM_START_FUNCTION gImage2EntryFun0 = {
+
+IMAGE2_START_RAM_FUN_SECTION
+const RAM_START_FUNCTION gImage2EntryFun0 = {
PLAT_Start
};
-IMAGE1_VALID_PATTEN_SECTION const uint8_t RAM_IMG1_VALID_PATTEN[] = {
- 0x23, 0x79, 0x16, 0x88, 0xff, 0xff, 0xff, 0xff
-};
-
-IMAGE2_VALID_PATTEN_SECTION const uint8_t RAM_IMG2_VALID_PATTEN[20] = {
+IMAGE2_VALID_PATTEN_SECTION
+const uint8_t IMAGE2_SIGNATURE[20] = {
'R', 'T', 'K', 'W', 'i', 'n', 0x0, 0xff,
(FW_VERSION&0xff), ((FW_VERSION >> 8)&0xff),
(FW_SUBVERSION&0xff), ((FW_SUBVERSION >> 8)&0xff),
@@ -93,7 +110,7 @@
#endif
}
-#if defined ( __ICCARM__ )
+#if defined (__ICCARM__)
void __TRAP_HardFaultHandler_Patch(uint32_t addr)
{
uint32_t cfsr;
@@ -118,9 +135,9 @@
* Otherwise it will keep hitting MemMange Fault on the same assembly code.
*
* To step to next command, we need parse the assembly code to check if
- * it is 16-bit or 32-bit command.
+ * it is 16-bit or 32-bit command.
* Ref: ARM Architecture Reference Manual (ARMv7-A and ARMv7-R edition),
- * Chapter A6 - Thumb Instruction Set Encoding
+ * Chapter A6 - Thumb Instruction Set Encoding
*
* However, the fault assembly code (Ex. LDR or ADR) is not actually executed,
* So the register value is un-predictable.
@@ -154,96 +171,63 @@
}
#endif
-// Override original Interrupt Vector Table
-INFRA_START_SECTION void TRAP_OverrideTable(uint32_t stackp)
-{
- // Override NMI Handler
- NewVectorTable[2] = (VECTOR_Func) TRAP_NMIHandler;
-
- #if defined ( __ICCARM__ )
- NewVectorTable[3] = (VECTOR_Func) TRAP_HardFaultHandler_Patch;
- #endif
-}
-
-INFRA_START_SECTION void PLAT_Init(void)
+extern _LONG_CALL_ void * __rtl_memset_v1_00(void * m , int c , size_t n);
+// Image2 Entry Function
+void PLAT_Start(void)
{
uint32_t val;
- //Set SPS lower voltage
+#if defined (__ICCARM__)
+ __iar_data_init_app();
+#endif
+
+ // Clear RAM BSS
+#if defined (__ICCARM__)
+ __rtl_memset_v1_00((void *)__bss_start__, 0, __bss_end__ - __bss_start__);
+#else
+ __rtl_memset_v1_00((void *)__bss_sram_start__, 0, __bss_sram_end__ - __bss_sram_start__);
+ __rtl_memset_v1_00((void *)__bss_dtcm_start__, 0, __bss_dtcm_end__ - __bss_dtcm_start__);
+ __rtl_memset_v1_00((void *)__bss_dram_start__, 0, __bss_dram_end__ - __bss_dram_start__);
+#endif
+
+ // Set MSP
+ __set_MSP((uint32_t)&__stackp - 0x100);
+ // Overwrite vector table
+ NewVectorTable[2] = (VECTOR_Func) TRAP_NMIHandler;
+#if defined ( __ICCARM__ )
+ NewVectorTable[3] = (VECTOR_Func) TRAP_HardFaultHandler_Patch;
+#endif
+
+ extern HAL_TIMER_OP_EXT HalTimerOpExt;
+ __rtl_memset_v1_00((void *)&HalTimerOpExt, 0, sizeof(HalTimerOpExt));
+ __rtl_memset_v1_00((void *)&HalTimerOp, 0, sizeof(HalTimerOp));
+
+ HalTimerOpInit_Patch(&HalTimerOp);
+ SystemCoreClockUpdate();
+
+ // Set SPS lower voltage
val = __RTK_CTRL_READ32(REG_SYS_EFUSE_SYSCFG0);
val &= 0xf0ffffff;
val |= 0x6000000;
__RTK_CTRL_WRITE32(REG_SYS_EFUSE_SYSCFG0, val);
-
- //xtal buffer driving current
+
+ // xtal buffer driving current
val = __RTK_CTRL_READ32(REG_SYS_XTAL_CTRL1);
val &= ~(BIT_MASK_SYS_XTAL_DRV_RF1 << BIT_SHIFT_SYS_XTAL_DRV_RF1);
val |= BIT_SYS_XTAL_DRV_RF1(1);
__RTK_CTRL_WRITE32(REG_SYS_XTAL_CTRL1, val);
-}
-//3 Image 2
-extern _LONG_CALL_ void * __rtl_memset_v1_00(void * m , int c , size_t n);
-
-//extern uint32_t mbed_stack_isr_start;
-//extern uint32_t mbed_stack_isr_size;
-INFRA_START_SECTION void PLAT_Start(void)
-{
- u8 isFlashEn;
-#if defined ( __ICCARM__ )
- __iar_data_init_app();
-#endif
- // Clear RAM BSS
- __rtl_memset_v1_00((void *)__bss_start__, 0, __bss_end__ - __bss_start__);
-
- TRAP_OverrideTable(0x1FFFFFFC);
-/* add by Ian --for mbed isr stack address setting */
- __set_MSP(0x1fffffbc);
-
-
-#ifdef CONFIG_SPIC_MODULE
- if ((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT_SOC_FLASH_EN) != 0) {
- isFlashEn = 1;
- } else {
- isFlashEn = 0;
- }
-#endif
+ // Initialize SPIC, then disable it for power saving.
+ if ((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT_SOC_FLASH_EN) != 0) {
+ SpicNVMCalLoadAll();
+ SpicReadIDRtl8195A();
+ SpicDisableRtl8195A();
+ }
#ifdef CONFIG_TIMER_MODULE
- HalTimerOpInit_Patch(&HalTimerOp);
+ Calibration32k();
#endif
- //DBG_8195A("===== Enter Image 2 ====\n");
-
-
- SystemCoreClockUpdate();
-
- if (isFlashEn) {
-#if CONFIG_SPIC_EN && SPIC_CALIBRATION_IN_NVM
- SpicNVMCalLoadAll();
-#endif
- SpicReadIDRtl8195A();
- // turn off SPIC for power saving
- SpicDisableRtl8195A();
- }
-
-
- PLAT_Init();
-#ifdef CONFIG_TIMER_MODULE
- Calibration32k();
-
-#ifdef CONFIG_WDG
-#ifdef CONFIG_WDG_TEST
- WDGInit();
-#endif //CONFIG_WDG_TEST
-#endif //CONFIG_WDG
-#endif //CONFIG_TIMER_MODULE
-
-#ifdef CONFIG_SOC_PS_MODULE
- //InitSoCPM();
-#endif
- /* GPIOA_7 does not pull high at power on. It causes SDIO Device
- * hardware to enable automatically and occupy GPIOA[7:0] */
#ifndef CONFIG_SDIO_DEVICE_EN
SDIO_DEV_Disable();
#endif
@@ -256,37 +240,41 @@
extern void PendSV_Handler(void);
extern void SysTick_Handler(void);
+// The Main App entry point
#if defined (__CC_ARM)
__asm void ARM_PLAT_Main(void)
{
- IMPORT SystemInit
- IMPORT __main
- BL SystemInit
- BL __main
+ IMPORT SystemInit
+ IMPORT __main
+ BL SystemInit
+ BL __main
+}
+#elif defined (__ICCARM__)
+extern void __iar_program_start(void);
+
+void IAR_PLAT_Main(void)
+{
+ SystemInit();
+ __iar_program_start();
}
#endif
-extern void __iar_program_start( void );
-// The Main App entry point
void PLAT_Main(void)
{
TRAP_Init((void *)SVC_Handler, (void *)PendSV_Handler, (void *)SysTick_Handler);
-#if defined (__ICCARM__)
- //IAR_PLAT_Main();
- SystemInit();
- __iar_program_start();
-#elif defined (__CC_ARM)
- ARM_PLAT_Main();
-
-#elif defined (__GNUC__)
- __asm (
- "ldr r0, =SystemInit \n"
+#if defined (__CC_ARM)
+ ARM_PLAT_Main();
+#elif defined (__ICCARM__)
+ IAR_PLAT_Main();
+#else
+ __asm ("ldr r0, =SystemInit \n"
"blx r0 \n"
"ldr r0, =_start \n"
"bx r0 \n"
);
#endif
+
// Never reached
- for(;;);
+ for (;;);
}
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_timer.h Thu Aug 31 17:27:04 2017 +0100 +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_timer.h Fri Sep 15 14:59:18 2017 +0100 @@ -15,7 +15,7 @@ #define _RTL8195A_TIMER_H_ -#define TIMER_TICK_US 31 +#define TIMER_TICK_US 32 #define TIMER_LOAD_COUNT_OFF 0x00 #define TIMER_CURRENT_VAL_OFF 0x04
--- a/targets/TARGET_Realtek/TARGET_AMEBA/analogin_api.c Thu Aug 31 17:27:04 2017 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/analogin_api.c Fri Sep 15 14:59:18 2017 +0100
@@ -113,12 +113,10 @@
/* Load user setting */
if ((pHalADCInitDataTmp->ADCEndian == ADC_DATA_ENDIAN_LITTLE) || (pHalADCInitDataTmp->ADCEndian == ADC_DATA_ENDIAN_BIG)) {
- DBG_8195A("K\n");
pSalADCHND->pInitDat->ADCEndian = pHalADCInitDataTmp->ADCEndian;
}
if ((pHalADCInitDataTmp->ADCAudioEn != ADC_FEATURE_DISABLED) && (pHalADCInitDataTmp->ADCAudioEn < 2)) {
- DBG_8195A("O\n");
pSalADCHND->pInitDat->ADCAudioEn = pHalADCInitDataTmp->ADCAudioEn;
}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.c Fri Sep 15 14:59:18 2017 +0100
@@ -0,0 +1,154 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2013-2017 Realtek Semiconductor Corp.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdio.h>
+#include <string.h>
+
+#include "mbed_wait_api.h"
+
+#include "rtl8195a.h"
+#include "flash_ext.h"
+
+#define FLASH_TOP 0x200000
+#define FLASH_SECTOR_SIZE 0x1000
+#define FLASH_SECTOR_MASK ~(FLASH_SECTOR_SIZE - 1)
+#define OTA_REGION1 0x0b000
+#define OTA_REGION2 0xc0000
+#define TAG_OFS 0xc
+#define VER_OFS 0x10
+
+#define TAG_DOWNLOAD 0x81950001
+#define TAG_VERIFIED 0x81950003
+
+static flash_t flash_obj;
+
+typedef struct imginfo_s {
+ uint32_t base;
+ uint32_t tag;
+ uint64_t ver;
+} imginfo_t;
+
+
+void OTA_GetImageInfo(imginfo_t *info)
+{
+ uint32_t ver_hi, ver_lo;
+
+ flash_ext_read_word(&flash_obj, info->base + TAG_OFS, &info->tag);
+ flash_ext_read_word(&flash_obj, info->base + VER_OFS, &ver_lo);
+ flash_ext_read_word(&flash_obj, info->base + VER_OFS + 4, &ver_hi);
+
+ if (info->tag == TAG_DOWNLOAD) {
+ info->ver = ((uint64_t)ver_hi << 32) | (uint64_t) ver_lo;
+ } else {
+ info->ver = 0;
+ }
+}
+
+uint32_t OTA_GetBase(void)
+{
+ static uint32_t ota_base = 0;
+ imginfo_t region1, region2;
+
+ if (ota_base == OTA_REGION1 || ota_base == OTA_REGION2) {
+ return ota_base;
+ }
+
+ region1.base = OTA_REGION1;
+ region2.base = OTA_REGION2;
+
+ OTA_GetImageInfo(®ion1);
+ OTA_GetImageInfo(®ion2);
+
+ if (region1.ver >= region2.ver) {
+ ota_base = region2.base;
+ } else {
+ ota_base = region1.base;
+ }
+ return ota_base;
+}
+
+uint32_t OTA_MarkUpdateDone(void)
+{
+ uint32_t addr = OTA_GetBase() + TAG_OFS;
+
+ return flash_ext_write_word(&flash_obj, addr, TAG_DOWNLOAD);
+}
+
+uint32_t OTA_UpdateImage(uint32_t offset, uint32_t len, uint8_t *data)
+{
+ uint32_t addr, start, end, count, shift;
+ uint8_t *pdata = data;
+ uint8_t buf[FLASH_SECTOR_SIZE];
+
+ start = OTA_GetBase() + offset;
+ end = start + len;
+
+ if (data == NULL || start > FLASH_TOP || end > FLASH_TOP) {
+ return 0;
+ }
+
+ addr = start & FLASH_SECTOR_MASK;
+ if (addr != start) {
+ shift = start - addr;
+ count = MIN(FLASH_SECTOR_SIZE - shift, len);
+ flash_ext_stream_read(&flash_obj, addr, shift, buf);
+ memcpy((void *)(buf + shift), (void *)pdata, count);
+
+ flash_ext_erase_sector(&flash_obj, addr);
+ flash_ext_stream_write(&flash_obj, addr, FLASH_SECTOR_SIZE, buf);
+ addr += FLASH_SECTOR_SIZE;
+ pdata += count;
+ }
+
+ while (addr < end) {
+ printf("OTA: update addr=0x%lx, len=%ld\r\n", addr, len);
+ count = MIN(FLASH_SECTOR_SIZE, end - addr);
+ flash_ext_erase_sector(&flash_obj, addr);
+ flash_ext_stream_write(&flash_obj, addr, count, pdata);
+ addr += FLASH_SECTOR_SIZE;
+ pdata += count;
+ }
+ return len;
+}
+
+uint32_t OTA_ReadImage(uint32_t offset, uint32_t len, uint8_t *data)
+{
+ uint32_t addr, endaddr;
+
+ addr = OTA_GetBase() + offset;
+ endaddr = addr + len;
+
+ if (data == NULL || addr > FLASH_TOP || endaddr > FLASH_TOP) {
+ return 0;
+ }
+
+ printf("OTA: read addr=0x%lx\r\n", addr);
+ return flash_ext_stream_read(&flash_obj, addr, len, data);
+}
+
+void OTA_ResetTarget(void)
+{
+ __RTK_CTRL_WRITE32(0x14, 0x00000021);
+ wait(1);
+
+ // write SCB->AIRCR
+ HAL_WRITE32(0xE000ED00, 0x0C,
+ (0x5FA << 16) | // VECTKEY
+ (HAL_READ32(0xE000ED00, 0x0C) & (7 << 8)) | // PRIGROUP
+ (1 << 2)); // SYSRESETREQ
+
+ // not reached
+ while (1);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.h Fri Sep 15 14:59:18 2017 +0100
@@ -0,0 +1,18 @@
+#ifndef MBED_OTA_API_H
+#define MBED_OTA_API_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+extern uint32_t OTA_UpdateImage(uint32_t offset, uint32_t len, uint8_t *data);
+extern uint32_t OTA_ReadImage(uint32_t offset, uint32_t len, uint8_t *data);
+extern uint32_t OTA_MarkUpdateDone(void);
+extern void OTA_ResetTarget(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MBED_OTA_API_H */
+
--- a/targets/TARGET_Realtek/TARGET_AMEBA/us_ticker.c Thu Aug 31 17:27:04 2017 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/us_ticker.c Fri Sep 15 14:59:18 2017 +0100
@@ -77,21 +77,22 @@
void us_ticker_set_interrupt(timestamp_t timestamp)
{
uint32_t cur_time_us;
- uint32_t time_def;
+ uint32_t time_dif;
-
+ HalTimerOp.HalTimerDis((u32)TimerAdapter.TimerId);
cur_time_us = us_ticker_read();
- if ((uint32_t)timestamp >= cur_time_us) {
- time_def = (uint32_t)timestamp - cur_time_us;
+ if ((uint32_t)timestamp > cur_time_us) {
+ time_dif = (uint32_t)timestamp - cur_time_us;
} else {
- time_def = 0xffffffff - cur_time_us + (uint32_t)timestamp;
+ HalTimerOpExt.HalTimerReLoad((u32)TimerAdapter.TimerId, 0xffffffff);
+ HalTimerOpExt.HalTimerIrqEn((u32)TimerAdapter.TimerId);
+ HalTimerOp.HalTimerEn((u32)TimerAdapter.TimerId);
+ NVIC_SetPendingIRQ(TIMER2_7_IRQ);
+ return;
}
- if (time_def < TIMER_TICK_US) {
- time_def = TIMER_TICK_US; // at least 1 tick
- }
- HalTimerOp.HalTimerDis((u32)TimerAdapter.TimerId);
- HalTimerOpExt.HalTimerReLoad((u32)TimerAdapter.TimerId, time_def);
+ TimerAdapter.TimerLoadValueUs = time_dif;
+ HalTimerOpExt.HalTimerReLoad((u32)TimerAdapter.TimerId, time_dif / TIMER_TICK_US);
HalTimerOpExt.HalTimerIrqEn((u32)TimerAdapter.TimerId);
HalTimerOp.HalTimerEn((u32)TimerAdapter.TimerId);
--- a/targets/TARGET_Realtek/mbed_rtx.h Thu Aug 31 17:27:04 2017 +0100
+++ b/targets/TARGET_Realtek/mbed_rtx.h Fri Sep 15 14:59:18 2017 +0100
@@ -21,16 +21,14 @@
#include "rtl8195a.h"
#if defined(__CC_ARM)
-#ifdef CONFIG_RTL8195A
- #define INITIAL_SP 0x10070000
- #define ISR_STACK_START 0x1FFFEFFC
-#else
- #ERROR "NOT SUPPORT NOW"
-#endif
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Length[];
+ #define ISR_STACK_START (unsigned char *)(Image$$ARM_LIB_STACK$$ZI$$Base)
+ #define ISR_STACK_SIZE (uint32_t)(Image$$ARM_LIB_STACK$$ZI$$Length)
+ #define INITIAL_SP (uint32_t)(Image$$ARM_LIB_STACK$$ZI$$Base)
#elif defined(__GNUC__)
extern uint32_t __StackTop[];
extern uint32_t __StackLimit[];
-// extern uint32_t __end__[];
extern uint32_t __HeapLimit[];
#define INITIAL_SP (__StackTop)
#endif
@@ -54,4 +52,3 @@
#endif
#endif
-
--- a/targets/TARGET_STM/TARGET_STM32F1/pin_device.h Thu Aug 31 17:27:04 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F1/pin_device.h Fri Sep 15 14:59:18 2017 +0100
@@ -37,6 +37,9 @@
static inline void stm_pin_DisconnectDebug(PinName pin)
{
+ // Enable AFIO clock
+ __HAL_RCC_AFIO_CLK_ENABLE();
+
// Disconnect JTAG-DP + SW-DP signals.
// Warning: Need to reconnect under reset
if ((pin == PA_13) || (pin == PA_14)) {
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/system_clock.c Thu Aug 31 17:27:04 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/system_clock.c Fri Sep 15 14:59:18 2017 +0100
@@ -240,6 +240,8 @@
/******************************************************************************/
void HardFault_Handler(void)
{
+#if !defined(NDEBUG) || NDEBUG == 0
printf("Hard Fault\n");
+#endif
NVIC_SystemReset();
}
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/system_clock.c Thu Aug 31 17:27:04 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/system_clock.c Fri Sep 15 14:59:18 2017 +0100
@@ -243,6 +243,8 @@
/******************************************************************************/
void HardFault_Handler(void)
{
+#if !defined(NDEBUG) || NDEBUG == 0
printf("Hard Fault\n");
+#endif
NVIC_SystemReset();
}
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/hal_tick.h Thu Aug 31 17:27:04 2017 +0100 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/hal_tick.h Fri Sep 15 14:59:18 2017 +0100 @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h Thu Aug 31 17:27:04 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h Fri Sep 15 14:59:18 2017 +0100
@@ -95,7 +95,7 @@
P_A17 = PD_12, // GPIO-3
P_A18 = PA_3, // UART-DSR
// B
- // C
+ // C
P_C5 = PG_4, // SPI-IRQ
P_C6 = PE_13, // SPI-MISO
P_C8 = PE_12, // Res
@@ -153,9 +153,18 @@
LED1 = PE_0, // Red / Mode
LED2 = PB_6, // Green / Switch-1
LED3 = PB_8, // Blue
- LED4 = D10,
+ LED4 = D10,
SW0 = PF_2, // Switch-0
SW1 = PB_6, // Green / Switch-1
+
+ LED_RED = LED1,
+ LED_GREEN = LED2,
+ LED_BLUE = LED3,
+
+ // Standardized button names
+ BUTTON1 = SW0,
+ BUTTON2 = SW1,
+
// ST-Link
USBRX = PA_10,
USBTX = PA_9,
--- a/targets/TARGET_STM/TARGET_STM32F4/analogin_api.c Thu Aug 31 17:27:04 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/analogin_api.c Fri Sep 15 14:59:18 2017 +0100
@@ -180,11 +180,12 @@
break;
case 17:
sConfig.Channel = ADC_CHANNEL_VREFINT;
+ /* From experiment, measurement needs max sampling time to be valid */
+ sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES;
break;
case 18:
sConfig.Channel = ADC_CHANNEL_VBAT;
- /* From experiment, VBAT measurement needs max
- * sampling time to be avlid */
+ /* From experiment, measurement needs max sampling time to be valid */
sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES;
break;
default:
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/system_clock.c Thu Aug 31 17:27:04 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/system_clock.c Fri Sep 15 14:59:18 2017 +0100
@@ -41,7 +41,7 @@
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
+#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
@@ -253,7 +253,9 @@
/******************************************************************************/
void HardFault_Handler(void)
{
+#if !defined(NDEBUG) || NDEBUG == 0
printf("Hard Fault\n");
+#endif
NVIC_SystemReset();
}
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/xdot_low_power.c Thu Aug 31 17:27:04 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/xdot_low_power.c Fri Sep 15 14:59:18 2017 +0100
@@ -31,6 +31,12 @@
#include "xdot_low_power.h"
#include "stdio.h"
+#if defined(NDEBUG) && NDEBUG == 1
+#define xdot_lp_debug(...) do {} while(0)
+#else
+#define xdot_lp_debug(...) printf(__VA_ARGS__)
+#endif
+
static uint32_t portA[6];
static uint32_t portB[6];
static uint32_t portC[6];
@@ -230,7 +236,7 @@
HSERCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4;
HSERCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV3;
if (HAL_RCC_OscConfig(&HSERCC_OscInitStruct) != HAL_OK) {
- printf("OSC initialization failed - initiating soft reset\r\n");
+ xdot_lp_debug("OSC initialization failed - initiating soft reset\r\n");
NVIC_SystemReset();
}
@@ -241,7 +247,7 @@
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
- printf("PLL initialization failed - initiating soft reset\r\n");
+ xdot_lp_debug("PLL initialization failed - initiating soft reset\r\n");
NVIC_SystemReset();
}
@@ -254,7 +260,7 @@
HSIRCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
HAL_StatusTypeDef ret = HAL_RCC_OscConfig(&HSIRCC_OscInitStruct);
if ( ret != HAL_OK ) {
- printf("HSI initialization failed - ADC will not function properly\r\n");
+ xdot_lp_debug("HSI initialization failed - ADC will not function properly\r\n");
}
}
--- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.c Thu Aug 31 17:27:04 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.c Fri Sep 15 14:59:18 2017 +0100
@@ -655,6 +655,10 @@
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
}
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) {
+ __HAL_SPI_DISABLE(hspi);
+ }
+
/* Clear overrun flag in 2 Lines communication mode because received is not read */
if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
--- a/targets/TARGET_STM/hal_tick_16b.c Thu Aug 31 17:27:04 2017 +0100
+++ b/targets/TARGET_STM/hal_tick_16b.c Fri Sep 15 14:59:18 2017 +0100
@@ -148,6 +148,13 @@
// Enable timer
HAL_TIM_Base_Start(&TimMasterHandle);
+#ifndef NDEBUG
+#ifdef TIM_MST_DBGMCU_FREEZE
+ // Freeze timer on stop/breakpoint
+ TIM_MST_DBGMCU_FREEZE;
+#endif
+#endif
+
#if DEBUG_TICK > 0
__HAL_RCC_GPIOB_CLK_ENABLE();
GPIO_InitTypeDef GPIO_InitStruct;
--- a/targets/TARGET_STM/hal_tick_32b.c Thu Aug 31 17:27:04 2017 +0100
+++ b/targets/TARGET_STM/hal_tick_32b.c Fri Sep 15 14:59:18 2017 +0100
@@ -118,6 +118,13 @@
__HAL_TIM_SET_COMPARE(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY);
__HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
+#ifndef NDEBUG
+#ifdef TIM_MST_DBGMCU_FREEZE
+ // Freeze timer on stop/breakpoint
+ TIM_MST_DBGMCU_FREEZE;
+#endif
+#endif
+
#if DEBUG_TICK > 0
__HAL_RCC_GPIOB_CLK_ENABLE();
GPIO_InitTypeDef GPIO_InitStruct;
--- a/targets/TARGET_STM/stm_spi_api.c Thu Aug 31 17:27:04 2017 +0100
+++ b/targets/TARGET_STM/stm_spi_api.c Fri Sep 15 14:59:18 2017 +0100
@@ -63,6 +63,9 @@
# define DEBUG_PRINTF(...) {}
#endif
+/* Consider 10ms as the default timeout for sending/receving 1 byte */
+#define TIMEOUT_1_BYTE 10
+
void init_spi(spi_t *obj)
{
struct spi_s *spiobj = SPI_S(obj);
@@ -75,7 +78,14 @@
error("Cannot initialize SPI");
}
- __HAL_SPI_ENABLE(handle);
+ /* In case of standard 4 wires SPI,PI can be kept enabled all time
+ * and SCK will only be generated during the write operations. But in case
+ * of 3 wires, it should be only enabled during rd/wr unitary operations,
+ * which is handled inside STM32 HAL layer.
+ */
+ if (handle->Init.Direction == SPI_DIRECTION_2LINES) {
+ __HAL_SPI_ENABLE(handle);
+ }
}
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
@@ -156,7 +166,13 @@
handle->Instance = SPI_INST(obj);
handle->Init.Mode = SPI_MODE_MASTER;
handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256;
- handle->Init.Direction = SPI_DIRECTION_2LINES;
+
+ if (miso != NC) {
+ handle->Init.Direction = SPI_DIRECTION_2LINES;
+ } else {
+ handle->Init.Direction = SPI_DIRECTION_1LINE;
+ }
+
handle->Init.CLKPhase = SPI_PHASE_1EDGE;
handle->Init.CLKPolarity = SPI_POLARITY_LOW;
handle->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
@@ -353,6 +369,10 @@
struct spi_s *spiobj = SPI_S(obj);
SPI_HandleTypeDef *handle = &(spiobj->handle);
+ if (handle->Init.Direction == SPI_DIRECTION_1LINE) {
+ return HAL_SPI_Transmit(handle, (uint8_t*)&value, 1, TIMEOUT_1_BYTE);
+ }
+
#if defined(LL_SPI_RX_FIFO_TH_HALF)
/* Configure the default data size */
if (handle->Init.DataSize == SPI_DATASIZE_16BIT) {
@@ -390,13 +410,31 @@
int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
char *rx_buffer, int rx_length, char write_fill)
{
+ struct spi_s *spiobj = SPI_S(obj);
+ SPI_HandleTypeDef *handle = &(spiobj->handle);
int total = (tx_length > rx_length) ? tx_length : rx_length;
-
- for (int i = 0; i < total; i++) {
- char out = (i < tx_length) ? tx_buffer[i] : write_fill;
- char in = spi_master_write(obj, out);
- if (i < rx_length) {
- rx_buffer[i] = in;
+ int i = 0;
+ if (handle->Init.Direction == SPI_DIRECTION_2LINES) {
+ for (i = 0; i < total; i++) {
+ char out = (i < tx_length) ? tx_buffer[i] : write_fill;
+ char in = spi_master_write(obj, out);
+ if (i < rx_length) {
+ rx_buffer[i] = in;
+ }
+ }
+ } else {
+ /* In case of 1 WIRE only, first handle TX, then Rx */
+ if (tx_length != 0) {
+ if (HAL_OK != HAL_SPI_Transmit(handle, (uint8_t*)tx_buffer, tx_length, tx_length*TIMEOUT_1_BYTE)) {
+ /* report an error */
+ total = 0;
+ }
+ }
+ if (rx_length != 0) {
+ if (HAL_OK != HAL_SPI_Receive(handle, (uint8_t*)rx_buffer, rx_length, rx_length*TIMEOUT_1_BYTE)) {
+ /* report an error */
+ total = 0;
+ }
}
}
@@ -410,17 +448,13 @@
int spi_slave_read(spi_t *obj)
{
- SPI_TypeDef *spi = SPI_INST(obj);
struct spi_s *spiobj = SPI_S(obj);
SPI_HandleTypeDef *handle = &(spiobj->handle);
while (!ssp_readable(obj));
- if (handle->Init.DataSize == SPI_DATASIZE_8BIT) {
- // Force 8-bit access to the data register
- uint8_t *p_spi_dr = 0;
- p_spi_dr = (uint8_t *) & (spi->DR);
- return (int)(*p_spi_dr);
+ if (handle->Init.DataSize == SPI_DATASIZE_16BIT) {
+ return LL_SPI_ReceiveData16(SPI_INST(obj));
} else {
- return (int)spi->DR;
+ return LL_SPI_ReceiveData8(SPI_INST(obj));
}
}
--- a/targets/targets.json Thu Aug 31 17:27:04 2017 +0100
+++ b/targets/targets.json Fri Sep 15 14:59:18 2017 +0100
@@ -1594,7 +1594,8 @@
"macros_add": ["USBHOST_OTHER"],
"device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "TRNG", "FLASH"],
"release_versions": ["2", "5"],
- "device_name": "STM32L476VG"
+ "device_name": "STM32L476VG",
+ "bootloader_supported": true
},
"MTS_MDOT_F405RG": {
"inherits": ["FAMILY_STM32"],