Revision 163:74e0ce7f98e8, committed 2017-04-28

Comitter:

Anna Bridge

Date:

Fri Apr 28 14:04:18 2017 +0100

Parent:

162:e13f6fdb2ac4

Child:

164:289d4deac6e4

Commit message:

This updates the lib to the mbed lib v141

Changed in this revision

--- a/drivers/CAN.cpp	Wed Apr 12 16:21:43 2017 +0100
+++ b/drivers/CAN.cpp	Fri Apr 28 14:04:18 2017 +0100
@@ -27,7 +27,7 @@
     // No lock needed in constructor
 
     for (int i = 0; i < sizeof _irq / sizeof _irq[0]; i++) {
-        _irq[i].attach(donothing);
+        _irq[i] = callback(donothing);
     }
 
     can_init(&_can, rd, td);
@@ -104,10 +104,10 @@
 void CAN::attach(Callback<void()> func, IrqType type) {
     lock();
     if (func) {
-        _irq[(CanIrqType)type].attach(func);
+        _irq[(CanIrqType)type] = func;
         can_irq_set(&_can, (CanIrqType)type, 1);
     } else {
-        _irq[(CanIrqType)type].attach(donothing);
+        _irq[(CanIrqType)type] = callback(donothing);
         can_irq_set(&_can, (CanIrqType)type, 0);
     }
     unlock();

--- a/mbed.h	Wed Apr 12 16:21:43 2017 +0100
+++ b/mbed.h	Fri Apr 28 14:04:18 2017 +0100
@@ -16,13 +16,13 @@
 #ifndef MBED_H
 #define MBED_H
 
-#define MBED_LIBRARY_VERSION 140
+#define MBED_LIBRARY_VERSION 141
 
 #if MBED_CONF_RTOS_PRESENT
 // RTOS present, this is valid only for mbed OS 5
 #define MBED_MAJOR_VERSION 5
 #define MBED_MINOR_VERSION 4
-#define MBED_PATCH_VERSION 3
+#define MBED_PATCH_VERSION 4
 
 #else
 // mbed 2

--- a/platform/mbed_board.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/platform/mbed_board.c	Fri Apr 28 14:04:18 2017 +0100
@@ -75,20 +75,17 @@
 
 void mbed_error_vfprintf(const char * format, va_list arg) {
 #if DEVICE_SERIAL
-
-#if MBED_CONF_PLATFORM_STDIO_CONVERT_NEWLINES
-    char stdio_out_prev;
-#endif
-
+#define ERROR_BUF_SIZE      (128)
     core_util_critical_section_enter();
-    char buffer[128];
-    int size = vsprintf(buffer, format, arg);
+    char buffer[ERROR_BUF_SIZE];
+    int size = vsnprintf(buffer, ERROR_BUF_SIZE, format, arg);
     if (size > 0) {
         if (!stdio_uart_inited) {
             serial_init(&stdio_uart, STDIO_UART_TX, STDIO_UART_RX);
         }
 #if MBED_CONF_PLATFORM_STDIO_CONVERT_NEWLINES
-        for (unsigned int i = 0; i < size; i++) {
+        char stdio_out_prev = '\0';
+        for (int i = 0; i < size; i++) {
             if (buffer[i] == '\n' && stdio_out_prev != '\r') {
                  serial_putc(&stdio_uart, '\r');
             }
@@ -96,7 +93,7 @@
             stdio_out_prev = buffer[i];
         }
 #else
-        for (unsigned int i = 0; i < size; i++) {
+        for (int i = 0; i < size; i++) {
             serial_putc(&stdio_uart, buffer[i]);
         }
 #endif

--- a/platform/mbed_retarget.cpp	Wed Apr 12 16:21:43 2017 +0100
+++ b/platform/mbed_retarget.cpp	Fri Apr 28 14:04:18 2017 +0100
@@ -120,6 +120,7 @@
 #endif
 }
 
+#if MBED_CONF_FILESYSTEM_PRESENT
 static inline int openmode_to_posix(int openmode) {
     int posix = openmode;
 #ifdef __ARMCC_VERSION
@@ -154,6 +155,7 @@
 #endif
     return posix;
 }
+#endif
 
 extern "C" WEAK void mbed_sdk_init(void);
 extern "C" WEAK void mbed_sdk_init(void) {

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_ARM_STD/MK66FN2M0xxx18.sct	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_ARM_STD/MK66FN2M0xxx18.sct	Fri Apr 28 14:04:18 2017 +0100
@@ -47,10 +47,6 @@
 */
 #define __ram_vector_table__            1
 
-/* Heap 1/4 of ram and stack 1/8 */
-#define __stack_size__       0x8000
-#define __heap_size__        0x10000
-
 #if (defined(__ram_vector_table__))
   #define __ram_vector_table_size__    0x00000400
 #else

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/device/TOOLCHAIN_ARM_STD/MK82FN256xxx15.sct	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/device/TOOLCHAIN_ARM_STD/MK82FN256xxx15.sct	Fri Apr 28 14:04:18 2017 +0100
@@ -49,10 +49,6 @@
 */
 
 #define __ram_vector_table__            1
-  		  
-/* Heap 1/4 of ram and stack 1/8 */
-#define __stack_size__       0x8000
-#define __heap_size__        0x10000
 
 #if (defined(__ram_vector_table__))
   #define __ram_vector_table_size__    0x000003C0

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/device/TOOLCHAIN_ARM_STD/MKL27Z64xxx4.sct	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/device/TOOLCHAIN_ARM_STD/MKL27Z64xxx4.sct	Fri Apr 28 14:04:18 2017 +0100
@@ -50,10 +50,6 @@
 */
 #define __ram_vector_table__            1
 
-/* Heap 1/4 of ram and stack 1/8 */
-#define __stack_size__       0x800
-#define __heap_size__        0x1000
-
 #if (defined(__ram_vector_table__))
   #define __ram_vector_table_size__    0x00000200
 #else

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/device/TOOLCHAIN_ARM_STD/MKL43Z256xxx4.sct	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/device/TOOLCHAIN_ARM_STD/MKL43Z256xxx4.sct	Fri Apr 28 14:04:18 2017 +0100
@@ -47,10 +47,6 @@
 */
 #define __ram_vector_table__            1
 
-/* Heap 1/4 of ram and stack 1/8 */
-#define __stack_size__       0x1000
-#define __heap_size__        0x2800
-
 #if (defined(__ram_vector_table__))
   #define __ram_vector_table_size__    0x00000200
 #else

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/device/TOOLCHAIN_ARM_STD/MKL82Z128xxx7.sct	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/device/TOOLCHAIN_ARM_STD/MKL82Z128xxx7.sct	Fri Apr 28 14:04:18 2017 +0100
@@ -50,10 +50,6 @@
 */
 #define __ram_vector_table__            1
 
-/* Heap 1/4 of ram and stack 1/8 */
-#define __stack_size__       0x3000
-#define __heap_size__        0x6000
-
 #if (defined(__ram_vector_table__))
   #define __ram_vector_table_size__    0x00000140
 #else

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_ARM_STD/MKW24D512xxx5.sct	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_ARM_STD/MKW24D512xxx5.sct	Fri Apr 28 14:04:18 2017 +0100
@@ -45,10 +45,6 @@
 */
 #define __ram_vector_table__            1
 
-/* Heap 1/4 of ram and stack 1/8 */
-#define __stack_size__       0x2000
-#define __heap_size__        0x4000
-
 #if (defined(__ram_vector_table__))
   #define __ram_vector_table_size__    0x00000400
 #else

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/device/TOOLCHAIN_ARM_STD/MKW41Z512xxx4.sct	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/device/TOOLCHAIN_ARM_STD/MKW41Z512xxx4.sct	Fri Apr 28 14:04:18 2017 +0100
@@ -45,10 +45,6 @@
 */
 #define __ram_vector_table__            1
 
-/* Heap 1/4 of ram and stack 1/8 */
-#define __stack_size__       0x4000
-#define __heap_size__        0x8000
-
 #if (defined(__ram_vector_table__))
   #define __ram_vector_table_size__    0x00000200
 #else

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/TARGET_MCU_K22F512/device/TOOLCHAIN_ARM_STD/MK22FN512xxx12.sct	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/TARGET_MCU_K22F512/device/TOOLCHAIN_ARM_STD/MK22FN512xxx12.sct	Fri Apr 28 14:04:18 2017 +0100
@@ -51,10 +51,6 @@
 */
 #define __ram_vector_table__            1
 
-/* Heap 1/4 of ram and stack 1/8 */
-#define __stack_size__       0x4000
-#define __heap_size__        0x8000
-
 #if (defined(__ram_vector_table__))
   #define __ram_vector_table_size__    0x00000400
 #else

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/device/TOOLCHAIN_ARM_STD/MK64FN1M0xxx12.sct	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/device/TOOLCHAIN_ARM_STD/MK64FN1M0xxx12.sct	Fri Apr 28 14:04:18 2017 +0100
@@ -50,10 +50,6 @@
 */
 #define __ram_vector_table__            1
 
-/* Heap 1/4 of ram and stack 1/8 */
-#define __stack_size__       0x8000
-#define __heap_size__        0x10000
-
 #if (defined(__ram_vector_table__))
   #define __ram_vector_table_size__    0x00000400
 #else

--- a/targets/TARGET_Maxim/TARGET_MAX32630/sleep.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/sleep.c	Fri Apr 28 14:04:18 2017 +0100
@@ -34,13 +34,13 @@
 #include "sleep_api.h"
 #include "lp.h"
 
-void sleep(void)
+void hal_sleep(void)
 {
     LP_EnterLP2();
 }
 
 // Low-power stop mode
-void deepsleep(void)
+void hal_deepsleep(void)
 {
-    sleep();
+    hal_sleep();
 }

--- a/targets/TARGET_NORDIC/TARGET_NRF5/us_ticker.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/us_ticker.c	Fri Apr 28 14:04:18 2017 +0100
@@ -42,6 +42,7 @@
 #include "nrf_drv_common.h"
 #include "nrf_drv_config.h"
 #include "lp_ticker_api.h"
+#include "mbed_critical.h"
 
 
 //------------------------------------------------------------------------------
@@ -52,12 +53,25 @@
 bool              m_common_rtc_enabled = false;
 uint32_t volatile m_common_rtc_overflows = 0;
 
+__STATIC_INLINE void rtc_ovf_event_check(void)
+{
+    if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW)) {
+        nrf_rtc_event_clear(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW);
+        // Don't disable this event. It shall occur periodically.
+
+        ++m_common_rtc_overflows;
+    }
+}
+
 #if defined(TARGET_MCU_NRF51822)
 void common_rtc_irq_handler(void)
 #else
 void COMMON_RTC_IRQ_HANDLER(void)
 #endif
 {
+
+    rtc_ovf_event_check();
+
     if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, US_TICKER_EVENT)) {
         us_ticker_irq_handler();
     }
@@ -69,12 +83,6 @@
     }
 #endif
 
-    if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW)) {
-        nrf_rtc_event_clear(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW);
-        // Don't disable this event. It shall occur periodically.
-
-        ++m_common_rtc_overflows;
-    }
 }
 
 #if (defined (__ICCARM__)) && defined(TARGET_MCU_NRF51822)//IAR
@@ -142,13 +150,37 @@
     m_common_rtc_enabled = true;
 }
 
+__STATIC_INLINE void rtc_ovf_event_safe_check(void)
+{
+    core_util_critical_section_enter();
+
+    rtc_ovf_event_check();
+
+    core_util_critical_section_exit();
+}
+
+
 uint32_t common_rtc_32bit_ticks_get(void)
 {
-    uint32_t ticks = nrf_rtc_counter_get(COMMON_RTC_INSTANCE);
-    // The counter used for time measurements is less than 32 bit wide,
-    // so its value is complemented with the number of registered overflows
-    // of the counter.
-    ticks += (m_common_rtc_overflows << RTC_COUNTER_BITS);
+    uint32_t ticks;
+    uint32_t prev_overflows;
+
+    do {
+        prev_overflows = m_common_rtc_overflows;
+
+        ticks = nrf_rtc_counter_get(COMMON_RTC_INSTANCE);
+        // The counter used for time measurements is less than 32 bit wide,
+        // so its value is complemented with the number of registered overflows
+        // of the counter.
+        ticks += (m_common_rtc_overflows << RTC_COUNTER_BITS);
+
+        // Check in case that OVF occurred during execution of a RTC handler (apply if call was from RTC handler)
+        // m_common_rtc_overflows might been updated in this call.
+        rtc_ovf_event_safe_check();
+
+        // If call was made from a low priority level m_common_rtc_overflows might have been updated in RTC handler.
+    } while (m_common_rtc_overflows != prev_overflows);
+
     return ticks;
 }
 
@@ -185,6 +217,8 @@
     uint32_t compare_value =
         (uint32_t)CEIL_DIV((timestamp64) * RTC_INPUT_FREQ, 1000000);
 
+
+    core_util_critical_section_enter();
     // The COMPARE event occurs when the value in compare register is N and
     // the counter value changes from N-1 to N. Therefore, the minimal safe
     // difference between the compare value to be set and the current counter
@@ -197,6 +231,8 @@
 
     nrf_rtc_cc_set(COMMON_RTC_INSTANCE, cc_channel, RTC_WRAP(compare_value));
     nrf_rtc_event_enable(COMMON_RTC_INSTANCE, int_mask);
+
+    core_util_critical_section_exit();
 }
 //------------------------------------------------------------------------------
 

--- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/us_ticker.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/us_ticker.c	Fri Apr 28 14:04:18 2017 +0100
@@ -55,32 +55,36 @@
 bool              m_common_rtc_enabled   = false;
 uint32_t volatile m_common_rtc_overflows = 0;
 
+__STATIC_INLINE void rtc_ovf_event_check(void)
+{
+    if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW)) {
+        nrf_rtc_event_clear(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW);
+        // Don't disable this event. It shall occur periodically.
+
+        ++m_common_rtc_overflows;
+    }
+}
+
 #if defined(TARGET_MCU_NRF51822)
 void common_rtc_irq_handler(void)
 #else
 void COMMON_RTC_IRQ_HANDLER(void)
 #endif
 {
-    if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, US_TICKER_EVENT))
-    {
+
+    rtc_ovf_event_check();
+
+    if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, US_TICKER_EVENT)) {
         us_ticker_irq_handler();
     }
 
 #if DEVICE_LOWPOWERTIMER
-    if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, LP_TICKER_EVENT))
-    {
+    if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, LP_TICKER_EVENT)) {
 
         lp_ticker_irq_handler();
     }
 #endif
 
-    if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW))
-    {
-        nrf_rtc_event_clear(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW);
-        // Don't disable this event. It shall occur periodically.
-
-        ++m_common_rtc_overflows;
-    }
 }
 
 // Function for fix errata 20: RTC Register values are invalid
@@ -107,8 +111,7 @@
 
 void common_rtc_init(void)
 {
-    if (m_common_rtc_enabled)
-    {
+    if (m_common_rtc_enabled) {
         return;
     }
 
@@ -168,13 +171,37 @@
     m_common_rtc_enabled = true;
 }
 
+__STATIC_INLINE void rtc_ovf_event_safe_check(void)
+{
+    core_util_critical_section_enter();
+
+    rtc_ovf_event_check();
+
+    core_util_critical_section_exit();
+}
+
+
 uint32_t common_rtc_32bit_ticks_get(void)
 {
-    uint32_t ticks = nrf_rtc_counter_get(COMMON_RTC_INSTANCE);
-    // The counter used for time measurements is less than 32 bit wide,
-    // so its value is complemented with the number of registered overflows
-    // of the counter.
-    ticks += (m_common_rtc_overflows << RTC_COUNTER_BITS);
+    uint32_t ticks;
+    uint32_t prev_overflows;
+
+    do {
+        prev_overflows = m_common_rtc_overflows;
+
+        ticks = nrf_rtc_counter_get(COMMON_RTC_INSTANCE);
+        // The counter used for time measurements is less than 32 bit wide,
+        // so its value is complemented with the number of registered overflows
+        // of the counter.
+        ticks += (m_common_rtc_overflows << RTC_COUNTER_BITS);
+
+        // Check in case that OVF occurred during execution of a RTC handler (apply if call was from RTC handler)
+        // m_common_rtc_overflows might been updated in this call.
+        rtc_ovf_event_safe_check();
+
+        // If call was made from a low priority level m_common_rtc_overflows might have been updated in RTC handler.
+    } while (m_common_rtc_overflows != prev_overflows);
+
     return ticks;
 }
 
@@ -200,12 +227,10 @@
     uint64_t current_time64 = common_rtc_64bit_us_get();
     // [add upper 32 bits from the current time to the timestamp value]
     uint64_t timestamp64 = us_timestamp +
-                           (current_time64 & ~(uint64_t)0xFFFFFFFF);
-
+        (current_time64 & ~(uint64_t)0xFFFFFFFF);
     // [if the original timestamp value happens to be after the 32 bit counter
     //  of microsends overflows, correct the upper 32 bits accordingly]
-    if (us_timestamp < (uint32_t)(current_time64 & 0xFFFFFFFF))
-    {
+    if (us_timestamp < (uint32_t)(current_time64 & 0xFFFFFFFF)) {
         timestamp64 += ((uint64_t)1 << 32);
     }
     // [microseconds -> ticks, always round the result up to avoid too early
@@ -213,19 +238,20 @@
     uint32_t compare_value =
         (uint32_t)CEIL_DIV((timestamp64) * RTC_INPUT_FREQ, 1000000);
 
+    core_util_critical_section_enter();
     // The COMPARE event occurs when the value in compare register is N and
     // the counter value changes from N-1 to N. Therefore, the minimal safe
     // difference between the compare value to be set and the current counter
     // value is 2 ticks. This guarantees that the compare trigger is properly
     // setup before the compare condition occurs.
     uint32_t closest_safe_compare = common_rtc_32bit_ticks_get() + 2;
-    if ((int)(compare_value - closest_safe_compare) <= 0)
-    {
+    if ((int)(compare_value - closest_safe_compare) <= 0) {
         compare_value = closest_safe_compare;
     }
 
     nrf_rtc_cc_set(COMMON_RTC_INSTANCE, cc_channel, RTC_WRAP(compare_value));
     nrf_rtc_event_enable(COMMON_RTC_INSTANCE, int_mask);
+    core_util_critical_section_exit();
 }
 //------------------------------------------------------------------------------
 
@@ -284,7 +310,7 @@
  */
 MBED_WEAK uint32_t const os_trv;
 MBED_WEAK uint32_t const os_clockrate;
-MBED_WEAK void OS_Tick_Handler()
+MBED_WEAK void OS_Tick_Handler(void)
 {
 }
 
@@ -431,14 +457,11 @@
 {
     uint32_t delta = 0;
 
-    if (os_clockrate != 1000)
-    {
+    if (os_clockrate != 1000) {
         // In RTX, by default SYSTICK is is used.
         // A tick event is generated  every os_trv + 1 clock cycles of the system timer.
         delta = os_trv + 1;
-    }
-    else
-    {
+    } else {
         // If the clockrate is set to 1000us then 1000 tick should happen every second.
         // Unfortunatelly, when clockrate is set to 1000, os_trv is equal to 31.
         // If (os_trv + 1) is used as the delta value between two ticks, 1000 ticks will be
@@ -454,24 +477,19 @@
         // Every five ticks (20%, 200 delta in one second), the delta is equal to 32
         // The remaining (32) deltas equal to 32 are distributed using primes numbers.
         static uint32_t counter = 0;
-        if ((counter % 5) == 0 || (counter % 31) == 0 || (counter % 139) == 0 || (counter == 503))
-        {
+        if ((counter % 5) == 0 || (counter % 31) == 0 || (counter % 139) == 0 || (counter == 503)) {
             delta = 32;
-        }
-        else
-        {
+        } else {
             delta = 33;
         }
         ++counter;
-        if (counter == 1000)
-        {
+        if (counter == 1000) {
             counter = 0;
         }
     }
     return delta;
 }
 
-
 static inline void clear_tick_interrupt()
 {
     nrf_rtc_event_clear(COMMON_RTC_INSTANCE, OS_TICK_EVENT);
@@ -489,27 +507,18 @@
 {
     // regular case, begin < end
     // return true if  begin <= val < end
-    if (begin < end)
-    {
-        if (begin <= val && val < end)
-        {
+    if (begin < end) {
+        if (begin <= val && val < end) {
             return true;
-        }
-        else
-        {
+        } else {
             return false;
         }
-    }
-    else
-    {
+    } else {
         // In this case end < begin because it has wrap around the limits
         // return false if end < val < begin
-        if (end < val && val < begin)
-        {
+        if (end < val && val < begin)  {
             return false;
-        }
-        else
-        {
+        } else {
             return true;
         }
     }
@@ -536,8 +545,7 @@
     uint32_t current_counter = nrf_rtc_counter_get(COMMON_RTC_INSTANCE);
 
     // If an overflow occur, set the next tick in COUNTER + delta clock cycles
-    if (is_in_wrapped_range(previous_tick_cc_value, new_compare_value, current_counter + 1) == false)
-    {
+    if (is_in_wrapped_range(previous_tick_cc_value, new_compare_value, current_counter + 1) == false) {
         new_compare_value = current_counter + delta;
     }
     nrf_rtc_cc_set(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL, new_compare_value);
@@ -603,29 +611,20 @@
     uint32_t next_tick_cc_value = nrf_rtc_cc_get(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL);
 
     // do not use os_tick_ovf because its counter value can be different
-    if (is_in_wrapped_range(previous_tick_cc_value, next_tick_cc_value, current_counter))
-    {
-        if (next_tick_cc_value > previous_tick_cc_value)
-        {
+    if(is_in_wrapped_range(previous_tick_cc_value, next_tick_cc_value, current_counter)) {
+        if (next_tick_cc_value > previous_tick_cc_value) {
             return next_tick_cc_value - current_counter;
-        }
-        else if (current_counter <= next_tick_cc_value)
-        {
+        } else if(current_counter <= next_tick_cc_value) {
             return next_tick_cc_value - current_counter;
-        }
-        else
-        {
+        } else {
             return next_tick_cc_value + (MAX_RTC_COUNTER_VAL - current_counter);
         }
-    }
-    else
-    {
+    } else {
         // use (os_trv + 1) has the base step, can be totally inacurate ...
         uint32_t clock_cycles_by_tick = os_trv + 1;
 
         // if current counter has wrap arround, add the limit to it.
-        if (current_counter < next_tick_cc_value)
-        {
+        if (current_counter < next_tick_cc_value) {
             current_counter = current_counter + MAX_RTC_COUNTER_VAL;
         }
 

--- a/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_MICRO/M453.sct	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_MICRO/M453.sct	Fri Apr 28 14:04:18 2017 +0100
@@ -1,6 +1,15 @@
+#! armcc -E
 
-LR_IROM1 0x00000000 {
-  ER_IROM1 0x00000000 {  ; load address = execution address
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x00000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x00040000
+#endif
+
+LR_IROM1 MBED_APP_START {
+  ER_IROM1 MBED_APP_START {  ; load address = execution address
    *(RESET, +First)
    *(InRoot$$Sections)
    .ANY (+RO)
@@ -23,6 +32,6 @@
   ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000 + 0x8000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
   }
 }
-ScatterAssert(LoadLimit(LR_IROM1) <= 0x00040000)    ; 256 KB APROM
+ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE))    ; 256 KB APROM
 ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x20008000)   ; 32 KB SRAM
 

--- a/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_STD/M453.sct	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_STD/M453.sct	Fri Apr 28 14:04:18 2017 +0100
@@ -1,6 +1,15 @@
+#! armcc -E
 
-LR_IROM1 0x00000000 {
-  ER_IROM1 0x00000000 {  ; load address = execution address
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x00000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x00040000
+#endif
+
+LR_IROM1 MBED_APP_START {
+  ER_IROM1 MBED_APP_START {  ; load address = execution address
    *(RESET, +First)
    *(InRoot$$Sections)
    .ANY (+RO)
@@ -23,6 +32,6 @@
   ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000 + 0x8000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
   }
 }
-ScatterAssert(LoadLimit(LR_IROM1) <= 0x00040000)    ; 256 KB APROM
+ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE))    ; 256 KB APROM
 ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x20008000)   ; 32 KB SRAM
 

--- a/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_GCC_ARM/M453.ld	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_GCC_ARM/M453.ld	Fri Apr 28 14:04:18 2017 +0100
@@ -2,12 +2,20 @@
  * Nuvoton M453 GCC linker script file
  */
 
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x00000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x00040000
+#endif 
+
 StackSize = 0x800;
 
 MEMORY
 {
-  VECTORS (rx)          : ORIGIN = 0x00000000, LENGTH = 0x00000400
-  FLASH (rx)            : ORIGIN = 0x00000400, LENGTH = 0x00040000 - 0x00000400
+  VECTORS (rx)          : ORIGIN = MBED_APP_START, LENGTH = 0x00000400
+  FLASH (rx)            : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x00000400
   RAM_INTERN (rwx)      : ORIGIN = 0x20000000, LENGTH = 0x00008000 - 0x00000000
 }
 

--- a/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_IAR/M453.icf	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_IAR/M453.icf	Fri Apr 28 14:04:18 2017 +0100
@@ -1,11 +1,13 @@
 /*###ICF### Section handled by ICF editor, don't touch! ****/
 /*-Editor annotation file-*/
 /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x00000000; }
+if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x00040000; }
 /*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
 /*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x00040000;
+define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
+define symbol __ICFEDIT_region_ROM_end__   = MBED_APP_START + MBED_APP_SIZE - 1;
 define symbol __ICFEDIT_region_IRAM_start__ = 0x20000000;
 define symbol __ICFEDIT_region_IRAM_end__   = 0x20008000;
 /*-Sizes-*/

--- a/targets/TARGET_NUVOTON/TARGET_M451/device/cmsis_nvic.h	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M451/device/cmsis_nvic.h	Fri Apr 28 14:04:18 2017 +0100
@@ -32,8 +32,18 @@
 #   define NVIC_RAM_VECTOR_ADDRESS  ((uint32_t) &__start_vector_table__)
 #endif
 
-
-#define NVIC_FLASH_VECTOR_ADDRESS 0
+#if defined(__CC_ARM)
+    extern uint32_t Load$$LR$$LR_IROM1$$Base[];
+    #define NVIC_FLASH_VECTOR_ADDRESS   ((uint32_t)Load$$LR$$LR_IROM1$$Base)
+#elif defined(__ICCARM__)
+    #pragma section=".intvec"
+    #define NVIC_FLASH_VECTOR_ADDRESS   ((uint32_t)__section_begin(".intvec"))
+#elif defined(__GNUC__)
+      extern uint32_t __vector_table;
+      #define NVIC_FLASH_VECTOR_ADDRESS   ((uint32_t)&__vector_table)
+#else
+    #error "Flash vector address not set for this toolchain"
+#endif
 
 #ifdef __cplusplus
 extern "C" {

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M451/flash_api.c	Fri Apr 28 14:04:18 2017 +0100
@@ -0,0 +1,79 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_api.h"
+#include "flash_data.h"
+#include "mbed_critical.h"
+
+// This is a flash algo binary blob. It is PIC (position independent code) that should be stored in RAM
+// NOTE: On ARMv7-M/ARMv8-M, instruction fetches are always little-endian.
+static uint32_t FLASH_ALGO[] = {
+    0x4603b530, 0x2164460c, 0x4dd72059, 0x20166028, 0xf8c5070d, 0x20880100, 0x0100f8c5, 0xf8d006c0, 
+    0xf0000100, 0xb9080001, 0xbd302001, 0x680048cf, 0x0004f040, 0x4580f04f, 0x0200f8c5, 0xf8d04628, 
+    0xf0400204, 0xf8c50004, 0xbf000204, 0xf1a11e08, 0xd1fb0101, 0x680048c6, 0x002df040, 0x60284dc4, 
+    0x68004628, 0x0001f000, 0x2001b908, 0x48c0e7dd, 0xf0406800, 0x4dbe0040, 0x20006028, 0x4601e7d5, 
+    0x48bbbf00, 0xf0006900, 0x28000001, 0x48b8d1f9, 0xf0206800, 0x4ab6002d, 0x20006010, 0x60104ab2, 
+    0x46014770, 0x48b2bf00, 0xf0006900, 0x28000001, 0x48afd1f9, 0xf0406800, 0x4aad0040, 0x20226010, 
+    0xf02160d0, 0x60500003, 0x61102001, 0x8f60f3bf, 0x48a7bf00, 0xf0006900, 0x28000001, 0x48a4d1f9, 
+    0xf0006800, 0xb1380040, 0x680048a1, 0x0040f040, 0x60104a9f, 0x47702001, 0xe7fc2000, 0x4604b570, 
+    0x4615460b, 0x46292200, 0x000ff103, 0x030ff020, 0x4897bf00, 0xf0006900, 0x28000001, 0x4894d1f9, 
+    0xf0406800, 0x4e920040, 0xf0246030, 0x6070000f, 0x60f02027, 0x1c524610, 0x0020f851, 0x36804e8c, 
+    0x46106030, 0xf8511c52, 0x4e890020, 0x0084f8c6, 0x1c524610, 0x0020f851, 0x36884e85, 0x46106030, 
+    0xf8511c52, 0x1d360020, 0x20016030, 0x61304e80, 0xe02c3b10, 0x487ebf00, 0x680030c0, 0x0030f000, 
+    0xd1f82800, 0x1c524610, 0x0020f851, 0x36804e78, 0x46106030, 0xf8511c52, 0x4e750020, 0x0084f8c6, 
+    0x4873bf00, 0x680030c0, 0x00c0f000, 0xd1f82800, 0x1c524610, 0x0020f851, 0x36884e6d, 0x46106030, 
+    0xf8511c52, 0x4e6a0020, 0x008cf8c6, 0x2b003b10, 0xbf00d1d0, 0x69004866, 0x0001f000, 0xd1f92800, 
+    0xb510bd70, 0x1cc84603, 0x0103f020, 0x4860bf00, 0xf0006900, 0x28000001, 0x485dd1f9, 0xf0406800, 
+    0x4c5b0040, 0x20216020, 0xe02060e0, 0x0003f023, 0x60604c57, 0x60a06810, 0x61202001, 0x8f60f3bf, 
+    0x4853bf00, 0xf0006900, 0x28000001, 0x4850d1f9, 0xf0006800, 0xb1380040, 0x6800484d, 0x0040f040, 
+    0x60204c4b, 0xbd102001, 0x1d121d1b, 0x29001f09, 0x2000d1dc, 0xe92de7f7, 0x460547f0, 0x4616460c, 
+    0x0800f04f, 0xbf0046c2, 0x69004841, 0x0001f000, 0xd1f92800, 0x6800483e, 0x0040f040, 0x6008493c, 
+    0xf0201ce0, 0xe02d0403, 0xb958b2e8, 0xd9092cff, 0x7780f44f, 0x0208eb06, 0x46284639, 0xff2ef7ff, 
+    0xe0164682, 0x0008f3c5, 0x2c10b958, 0xf024d309, 0xeb06070f, 0x46390208, 0xf7ff4628, 0x4682ff1f, 
+    0x4627e007, 0x0208eb06, 0x46284639, 0xff89f7ff, 0x443d4682, 0x1be444b8, 0x0f00f1ba, 0x2001d002, 
+    0x87f0e8bd, 0xd1cf2c00, 0xe7f92000, 0x1ccbb510, 0x0103f023, 0x4b1ebf00, 0xf003691b, 0x2b000301, 
+    0x4b1bd1f9, 0xf043681b, 0x4c190340, 0x23006023, 0xe02560e3, 0x0303f020, 0x60634c15, 0x60a32300, 
+    0x61232301, 0x8f60f3bf, 0x4b11bf00, 0xf003691b, 0x2b000301, 0x4b0ed1f9, 0xf003681b, 0xb1330340, 
+    0x681b4b0b, 0x0340f043, 0x60234c09, 0x4b08bd10, 0x6814689b, 0xd00042a3, 0x1d00e7f8, 0x1f091d12, 
+    0xd1d72900, 0xe7f1bf00, 0x40000100, 0x40000200, 0x4000c000, 0x00000000, 
+};
+
+static const flash_algo_t flash_algo_config = {
+    .init = 0x00000001,
+    .uninit = 0x0000007f,
+    .erase_sector = 0x000000a3,
+    .program_page = 0x00000257,
+    .static_base = 0x00000374,
+    .algo_blob = FLASH_ALGO
+};
+
+static const sector_info_t sectors_info[] = {
+    {0x0, 0x800},           // (start, sector size)
+};
+
+static const flash_target_config_t flash_target_config = {
+    .page_size  = 0x800,    // 2 KB
+    .flash_start = 0x0,
+    .flash_size = 0x40000,  // 256 KB
+    .sectors = sectors_info,
+    .sector_info_count = sizeof(sectors_info) / sizeof(sector_info_t)
+};
+
+void flash_set_target_config(flash_t *obj)
+{
+    obj->flash_algo = &flash_algo_config;
+    obj->target_config = &flash_target_config;
+}

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_MICRO/TARGET_NU_XRAM_SUPPORTED/NUC472.sct	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_MICRO/TARGET_NU_XRAM_SUPPORTED/NUC472.sct	Fri Apr 28 14:04:18 2017 +0100
@@ -1,6 +1,15 @@
+#! armcc -E
 
-LR_IROM1 0x00000000 {
-  ER_IROM1 0x00000000 {  ; load address = execution address
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x00000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x00080000
+#endif
+
+LR_IROM1 MBED_APP_START {
+  ER_IROM1 MBED_APP_START {  ; load address = execution address
    *(RESET, +First)
    *(InRoot$$Sections)
    .ANY (+RO)
@@ -29,7 +38,7 @@
   ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x60000000 + 0x100000 - AlignExpr(ImageLimit(ER_XRAM1), 16)) {
   }
 }
-ScatterAssert(LoadLimit(LR_IROM1) <= 0x00080000)    ; 512 KB APROM
+ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE))    ; 512 KB APROM
 ScatterAssert(ImageLimit(RW_IRAM1) <= 0x20010000)   ; 64 KB SRAM (internal)
 ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x60100000)   ; 1 MB SRAM (external)
 

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_MICRO/TARGET_NU_XRAM_UNSUPPORTED/NUC472.sct	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_MICRO/TARGET_NU_XRAM_UNSUPPORTED/NUC472.sct	Fri Apr 28 14:04:18 2017 +0100
@@ -1,6 +1,15 @@
+#! armcc -E
 
-LR_IROM1 0x00000000 {
-  ER_IROM1 0x00000000 {  ; load address = execution address
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x00000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x00080000
+#endif
+
+LR_IROM1 MBED_APP_START {
+  ER_IROM1 MBED_APP_START {  ; load address = execution address
    *(RESET, +First)
    *(InRoot$$Sections)
    .ANY (+RO)
@@ -24,6 +33,6 @@
   ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000 + 0x10000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
   }
 }
-ScatterAssert(LoadLimit(LR_IROM1) <= 0x00080000)    ; 512 KB APROM
+ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE))    ; 512 KB APROM
 ScatterAssert(ImageLimit(RW_IRAM1) <= 0x20010000)   ; 64 KB SRAM (internal)
 

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_STD/TARGET_NU_XRAM_SUPPORTED/NUC472.sct	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_STD/TARGET_NU_XRAM_SUPPORTED/NUC472.sct	Fri Apr 28 14:04:18 2017 +0100
@@ -1,6 +1,15 @@
+#! armcc -E
 
-LR_IROM1 0x00000000 {
-  ER_IROM1 0x00000000 {  ; load address = execution address
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x00000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x00080000
+#endif
+
+LR_IROM1 MBED_APP_START {
+  ER_IROM1 MBED_APP_START {  ; load address = execution address
    *(RESET, +First)
    *(InRoot$$Sections)
    .ANY (+RO)
@@ -31,7 +40,7 @@
   ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x60000000 + 0x100000 - AlignExpr(ImageLimit(ER_XRAM1), 16)) {
   }
 }
-ScatterAssert(LoadLimit(LR_IROM1) <= 0x00080000)    ; 512 KB APROM
+ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE))    ; 512 KB APROM
 ScatterAssert(ImageLimit(RW_IRAM1) <= 0x20010000)   ; 64 KB SRAM (internal)
 ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x60100000)   ; 1 MB SRAM (external)
 

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_STD/TARGET_NU_XRAM_UNSUPPORTED/NUC472.sct	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_STD/TARGET_NU_XRAM_UNSUPPORTED/NUC472.sct	Fri Apr 28 14:04:18 2017 +0100
@@ -1,6 +1,15 @@
+#! armcc -E
 
-LR_IROM1 0x00000000 {
-  ER_IROM1 0x00000000 {  ; load address = execution address
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x00000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x00080000
+#endif
+
+LR_IROM1 MBED_APP_START {
+  ER_IROM1 MBED_APP_START {  ; load address = execution address
    *(RESET, +First)
    *(InRoot$$Sections)
    .ANY (+RO)
@@ -24,6 +33,6 @@
   ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000 + 0x10000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
   }
 }
-ScatterAssert(LoadLimit(LR_IROM1) <= 0x00080000)    ; 512 KB APROM
+ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE))    ; 512 KB APROM
 ScatterAssert(ImageLimit(RW_IRAM1) <= 0x20010000)   ; 64 KB SRAM (internal)
 

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_GCC_ARM/TARGET_NU_XRAM_SUPPORTED/NUC472.ld	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_GCC_ARM/TARGET_NU_XRAM_SUPPORTED/NUC472.ld	Fri Apr 28 14:04:18 2017 +0100
@@ -2,13 +2,21 @@
  * Nuvoton NUC472 GCC linker script file
  */
 
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x00000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x00080000
+#endif 
+
 StackSize = 0x800;
 
 MEMORY
 {
     
-  VECTORS (rx)          : ORIGIN = 0x00000000, LENGTH = 0x00000400
-  FLASH (rx)            : ORIGIN = 0x00000400, LENGTH = 0x00080000 - 0x00000400
+  VECTORS (rx)          : ORIGIN = MBED_APP_START, LENGTH = 0x00000400
+  FLASH (rx)            : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x00000400
   RAM_INTERN (rwx)      : ORIGIN = 0x20000000, LENGTH = 0x00010000 - 0x00000000
   RAM_EXTERN (rwx)      : ORIGIN = 0x60000000, LENGTH = 0x00100000
 }

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_GCC_ARM/TARGET_NU_XRAM_UNSUPPORTED/NUC472.ld	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_GCC_ARM/TARGET_NU_XRAM_UNSUPPORTED/NUC472.ld	Fri Apr 28 14:04:18 2017 +0100
@@ -2,13 +2,21 @@
  * Nuvoton NUC472 GCC linker script file
  */
 
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x00000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x00080000
+#endif 
+ 
 StackSize = 0x800;
 
 MEMORY
 {
     
-  VECTORS (rx)          : ORIGIN = 0x00000000, LENGTH = 0x00000400
-  FLASH (rx)            : ORIGIN = 0x00000400, LENGTH = 0x00080000 - 0x00000400
+  VECTORS (rx)          : ORIGIN = MBED_APP_START, LENGTH = 0x00000400
+  FLASH (rx)            : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x00000400
   RAM_INTERN (rwx)      : ORIGIN = 0x20000000, LENGTH = 0x00010000 - 0x00000000
 }
 

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_IAR/TARGET_NU_XRAM_SUPPORTED/NUC472_442.icf	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_IAR/TARGET_NU_XRAM_SUPPORTED/NUC472_442.icf	Fri Apr 28 14:04:18 2017 +0100
@@ -1,11 +1,13 @@
 /*###ICF### Section handled by ICF editor, don't touch! ****/
 /*-Editor annotation file-*/
 /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x00000000; }
+if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x00080000; }
 /*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
 /*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x00080000;
+define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
+define symbol __ICFEDIT_region_ROM_end__   = MBED_APP_START + MBED_APP_SIZE - 1;
 define symbol __ICFEDIT_region_IRAM_start__ = 0x20000000;
 define symbol __ICFEDIT_region_IRAM_end__   = 0x20010000;
 define symbol __ICFEDIT_region_XRAM_start__ = 0x60000000;

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_IAR/TARGET_NU_XRAM_UNSUPPORTED/NUC472_442.icf	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_IAR/TARGET_NU_XRAM_UNSUPPORTED/NUC472_442.icf	Fri Apr 28 14:04:18 2017 +0100
@@ -1,11 +1,13 @@
 /*###ICF### Section handled by ICF editor, don't touch! ****/
 /*-Editor annotation file-*/
 /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x00000000; }
+if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x00080000; }
 /*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
 /*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x00080000;
+define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
+define symbol __ICFEDIT_region_ROM_end__   = MBED_APP_START + MBED_APP_SIZE - 1;
 define symbol __ICFEDIT_region_IRAM_start__ = 0x20000000;
 define symbol __ICFEDIT_region_IRAM_end__   = 0x20010000;
 /*-Sizes-*/

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/cmsis_nvic.h	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/cmsis_nvic.h	Fri Apr 28 14:04:18 2017 +0100
@@ -32,8 +32,18 @@
 #   define NVIC_RAM_VECTOR_ADDRESS  ((uint32_t) &__start_vector_table__)
 #endif
 
-
-#define NVIC_FLASH_VECTOR_ADDRESS 0
+#if defined(__CC_ARM)
+    extern uint32_t Load$$LR$$LR_IROM1$$Base[];
+    #define NVIC_FLASH_VECTOR_ADDRESS   ((uint32_t)Load$$LR$$LR_IROM1$$Base)
+#elif defined(__ICCARM__)
+    #pragma section=".intvec"
+    #define NVIC_FLASH_VECTOR_ADDRESS   ((uint32_t)__section_begin(".intvec"))
+#elif defined(__GNUC__)
+      extern uint32_t __vector_table;
+      #define NVIC_FLASH_VECTOR_ADDRESS   ((uint32_t)&__vector_table)
+#else
+    #error "Flash vector address not set for this toolchain"
+#endif
 
 #ifdef __cplusplus
 extern "C" {

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/flash_api.c	Fri Apr 28 14:04:18 2017 +0100
@@ -0,0 +1,81 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_api.h"
+#include "flash_data.h"
+#include "mbed_critical.h"
+
+// This is a flash algo binary blob. It is PIC (position independent code) that should be stored in RAM
+// NOTE: On ARMv7-M/ARMv8-M, instruction fetches are always little-endian.
+static uint32_t FLASH_ALGO[] = {
+    0x4603b530, 0x2164460c, 0x4de72059, 0x20166028, 0xf8c5070d, 0x20880100, 0x0100f8c5, 0xf8d006c0, 
+    0xf0000100, 0xb9080001, 0xbd302001, 0x680048df, 0x0004f040, 0x4580f04f, 0x0200f8c5, 0xf8d04628, 
+    0xf0400204, 0xf8c50004, 0xbf000204, 0xf1a11e08, 0xd1fb0101, 0x680048d6, 0x0029f040, 0x60284dd4, 
+    0x68004628, 0x0001f000, 0x2001b908, 0xf04fe7dd, 0x4dcf30ff, 0x46286468, 0x1c406c40, 0x2001b108, 
+    0x48cbe7d3, 0xf0406800, 0x4dc90040, 0x20006028, 0x4601e7cb, 0x48c6bf00, 0xf0006900, 0x28000001, 
+    0x48c3d1f9, 0xf0206800, 0x4ac10029, 0x20006010, 0x60104abd, 0x46014770, 0x48bdbf00, 0xf0006900, 
+    0x28000001, 0x48bad1f9, 0xf0406800, 0x4ab80040, 0x20226010, 0xf02160d0, 0x60500003, 0x61102001, 
+    0x8f60f3bf, 0x48b2bf00, 0xf0006900, 0x28000001, 0x48afd1f9, 0xf0006800, 0xb1380040, 0x680048ac, 
+    0x0040f040, 0x60104aaa, 0x47702001, 0xe7fc2000, 0x4603b570, 0x2500460c, 0x4629e009, 0xf8531c6d, 
+    0xf7ff0021, 0x1e06ffc8, 0x4630d001, 0x42a5bd70, 0x2000d3f3, 0xb570e7fa, 0x460b4604, 0x22004615, 
+    0xf1034629, 0xf020000f, 0xbf00030f, 0x69004898, 0x0001f000, 0xd1f92800, 0x68004895, 0x0040f040, 
+    0x60304e93, 0x000ff024, 0x20276070, 0x461060f0, 0xf8511c52, 0x4e8e0020, 0x60303680, 0x1c524610, 
+    0x0020f851, 0xf8c64e8a, 0x46100084, 0xf8511c52, 0x4e870020, 0x60303688, 0x1c524610, 0x0020f851, 
+    0x60301d36, 0x4e822001, 0x3b106130, 0xbf00e02c, 0x30c0487f, 0xf0006800, 0x28000030, 0x4610d1f8, 
+    0xf8511c52, 0x4e7a0020, 0x60303680, 0x1c524610, 0x0020f851, 0xf8c64e76, 0xbf000084, 0x30c04874, 
+    0xf0006800, 0x280000c0, 0x4610d1f8, 0xf8511c52, 0x4e6f0020, 0x60303688, 0x1c524610, 0x0020f851, 
+    0xf8c64e6b, 0x3b10008c, 0xd1d02b00, 0x4868bf00, 0xf0006900, 0x28000001, 0xbd70d1f9, 0x4603b510, 
+    0xf0201cc8, 0xbf000103, 0x69004861, 0x0001f000, 0xd1f92800, 0x6800485e, 0x0040f040, 0x60204c5c, 
+    0x60e02021, 0xf023e020, 0x4c590003, 0x68106060, 0x200160a0, 0xf3bf6120, 0xbf008f60, 0x69004854, 
+    0x0001f000, 0xd1f92800, 0x68004851, 0x0040f000, 0x484fb138, 0xf0406800, 0x4c4d0040, 0x20016020, 
+    0x1d1bbd10, 0x1f091d12, 0xd1dc2900, 0xe7f72000, 0x47f0e92d, 0x460c4605, 0xf04f4616, 0x46c20800, 
+    0x4843bf00, 0xf0006900, 0x28000001, 0x4840d1f9, 0xf0406800, 0x493e0040, 0x1ce06008, 0x0403f020, 
+    0xf3c5e02f, 0xb9600008, 0x7f00f5b4, 0xf44fd309, 0xeb067700, 0x46390208, 0xf7ff4628, 0x4682ff2c, 
+    0xf3c5e016, 0xb9580008, 0xd3092c10, 0x070ff024, 0x0208eb06, 0x46284639, 0xff1df7ff, 0xe0074682, 
+    0xeb064627, 0x46390208, 0xf7ff4628, 0x4682ff87, 0x44b8443d, 0xf1ba1be4, 0xd0020f00, 0xe8bd2001, 
+    0x2c0087f0, 0x2000d1cd, 0xb510e7f9, 0xf0231ccb, 0xbf000103, 0x691b4b1e, 0x0301f003, 0xd1f92b00, 
+    0x681b4b1b, 0x0340f043, 0x60234c19, 0x60e32300, 0xf020e025, 0x4c160303, 0x23006063, 0x230160a3, 
+    0xf3bf6123, 0xbf008f60, 0x691b4b11, 0x0301f003, 0xd1f92b00, 0x681b4b0e, 0x0340f003, 0x4b0cb133, 
+    0xf043681b, 0x4c0a0340, 0xbd106023, 0x689b4b08, 0x42a36814, 0xe7f8d000, 0x1d121d00, 0x29001f09, 
+    0xbf00d1d7, 0x0000e7f1, 0x40000100, 0x40000200, 0x4000c000, 0x00000000, 
+};
+
+static const flash_algo_t flash_algo_config = {
+    .init = 0x00000001,
+    .uninit = 0x00000093,
+    .erase_sector = 0x000000b7,
+    .program_page = 0x00000291,
+    .static_base = 0x000003b4,
+    .algo_blob = FLASH_ALGO
+};
+
+static const sector_info_t sectors_info[] = {
+    {0x0, 0x800},           // (start, sector size)
+};
+
+static const flash_target_config_t flash_target_config = {
+    .page_size  = 0x800,    // 2 KB
+    .flash_start = 0x0,
+    .flash_size = 0x80000,  // 512 KB
+    .sectors = sectors_info,
+    .sector_info_count = sizeof(sectors_info) / sizeof(sector_info_t)
+};
+
+void flash_set_target_config(flash_t *obj)
+{
+    obj->flash_algo = &flash_algo_config;
+    obj->target_config = &flash_target_config;
+}

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/trng_api.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/trng_api.c	Fri Apr 28 14:04:18 2017 +0100
@@ -31,12 +31,16 @@
  * Get Random number generator.
  */
 static volatile int  g_PRNG_done;
+volatile int  g_AES_done;
 
 void CRYPTO_IRQHandler()
 {
     if (PRNG_GET_INT_FLAG()) {
         g_PRNG_done = 1;
         PRNG_CLR_INT_FLAG();
+    }  else if (AES_GET_INT_FLAG()) {
+        g_AES_done = 1;
+        AES_CLR_INT_FLAG();
     }
 } 
 
@@ -86,7 +90,7 @@
         memcpy(output, &tmpBuff, length);
         *output_length = length;
     } else {
-        for (size_t i = 0; i < (length/32); i++) {
+        for (int i = 0; i < (length/32); i++) {
             trng_get(output);
             *output_length += 32;
             output += 32;

--- a/targets/TARGET_NXP/TARGET_LPC176X/TARGET_MBED_LPC1768/PinNames.h	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC176X/TARGET_MBED_LPC1768/PinNames.h	Fri Apr 28 14:04:18 2017 +0100
@@ -106,11 +106,17 @@
     A4 = P1_30,
     A5 = P1_31,
 
-    I2C_SCL = D15,
-    I2C_SDA = D14,
+    // Not connected
+    NC = (int)0xFFFFFFFF,
 
-    // Not connected
-    NC = (int)0xFFFFFFFF
+    I2C_SCL0 = NC,
+    I2C_SDA0 = NC,
+    I2C_SCL1 = p10,
+    I2C_SDA1 = p9,
+    I2C_SCL2 = p27, // pin used by application board
+    I2C_SDA2 = p28, // pin used by application board
+    I2C_SCL = I2C_SCL2,
+    I2C_SDA = I2C_SDA2,
 } PinName;
 
 typedef enum {

--- a/targets/TARGET_STM/PeripheralPins.h	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/PeripheralPins.h	Fri Apr 28 14:04:18 2017 +0100
@@ -37,6 +37,7 @@
 //*** ADC ***
 #ifdef DEVICE_ANALOGIN
 extern const PinMap PinMap_ADC[];
+extern const PinMap PinMap_ADC_Internal[];
 #endif
 
 //*** DAC ***

--- a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/PeripheralPins.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/PeripheralPins.c	Fri Apr 28 14:04:18 2017 +0100
@@ -87,6 +87,10 @@
     {PF_8,       ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)},  // ADC3_IN6
     {PF_9,       ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)},  // ADC3_IN7
     {PF_10,      ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8
+    {NC,         NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP,   ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VREF,   ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VBAT,   ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used
@@ -107,7 +111,7 @@
 //  {PB_7,  I2C_1   , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // LED2
     {PB_9,  I2C_1   , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
     {PB_11, I2C_2   , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
-    {PC_9,  I2C_3   , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+//  {PC_9,  I2C_3   , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // no I2C_3 SCL available
     {PF_0,  I2C_2   , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
     {NC,    NC,    0}
 };

--- a/targets/TARGET_STM/TARGET_STM32F2/analogin_api.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F2/analogin_api.c	Fri Apr 28 14:04:18 2017 +0100
@@ -40,6 +40,9 @@
 
 void analogin_init(analogin_t *obj, PinName pin)
 {
+    uint32_t function = (uint32_t)NC;
+    obj->adc = (ADCName)NC;
+
 #if defined(ADC1)
     static int adc1_inited = 0;
 #endif
@@ -49,21 +52,28 @@
 #if defined(ADC3)
     static int adc3_inited = 0;
 #endif
-    // Get the peripheral name from the pin and assign it to the object
-    obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+    // ADC Internal Channels "pins"  (Temperature, Vref, Vbat, ...)
+    //   are described in PinNames.h and PeripheralPins.c
+    //   Pin value must be between 0xF0 and 0xFF
+    if ((pin < 0xF0) || (pin >= 0x100)) {
+        // Normal channels
+        // Get the peripheral name from the pin and assign it to the object
+        obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+        // Get the functions (adc channel) from the pin and assign it to the object
+        function = pinmap_function(pin, PinMap_ADC);
+        // Configure GPIO
+        pinmap_pinout(pin, PinMap_ADC);
+    } else {
+        // Internal channels
+        obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC_Internal);
+        function = pinmap_function(pin, PinMap_ADC_Internal);
+        // No GPIO configuration for internal channels
+    }
     MBED_ASSERT(obj->adc != (ADCName)NC);
-
-    // Get the functions (adc channel) from the pin and assign it to the object
-    uint32_t function = pinmap_function(pin, PinMap_ADC);
     MBED_ASSERT(function != (uint32_t)NC);
+
     obj->channel = STM_PIN_CHANNEL(function);
 
-    // Configure GPIO excepted for internal channels (Temperature, Vref, Vbat, ...)
-    // ADC Internal Channels "pins" are described in PinNames.h and must have a value >= 0xF0
-    if (pin < 0xF0) {
-        pinmap_pinout(pin, PinMap_ADC);
-    }
-
     // Save pin number for the read function
     obj->pin = pin;
 

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PeripheralPins.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PeripheralPins.c	Fri Apr 28 14:04:18 2017 +0100
@@ -55,6 +55,10 @@
     {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
     {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
     {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PeripheralPins.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PeripheralPins.c	Fri Apr 28 14:04:18 2017 +0100
@@ -55,6 +55,10 @@
     {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
     {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
     {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PeripheralPins.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PeripheralPins.c	Fri Apr 28 14:04:18 2017 +0100
@@ -50,6 +50,10 @@
     {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8,  0)}, // ADC1_IN8
     {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9,  0)}, // ADC1_IN9
     {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/PeripheralPins.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/PeripheralPins.c	Fri Apr 28 14:04:18 2017 +0100
@@ -55,6 +55,10 @@
     {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
     {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
     {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PeripheralPins.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PeripheralPins.c	Fri Apr 28 14:04:18 2017 +0100
@@ -41,8 +41,8 @@
 const PinMap PinMap_ADC[] = {
     {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0,  0)}, // ADC1_IN0
     {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1,  0)}, // ADC1_IN1
-    {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2,  0)}, // ADC1_IN2
-    {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3,  0)}, // ADC1_IN3
+//  {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2,  0)}, // ADC1_IN2 // SERIAL_TX
+//  {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3,  0)}, // ADC1_IN3 // SERIAL_RX
     {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4,  0)}, // ADC1_IN4
     {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5,  0)}, // ADC1_IN5
     {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6,  0)}, // ADC1_IN6
@@ -55,6 +55,10 @@
     {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
     {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
     {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used
@@ -88,12 +92,12 @@
 //  {PA_0,  PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
     {PA_1,  PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
 //  {PA_1,  PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
-    {PA_2,  PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
-//  {PA_2,  PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
-//  {PA_2,  PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
-    {PA_3,  PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
-//  {PA_3,  PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
-//  {PA_3,  PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+//  {PA_2,  PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // SERIAL_TX
+//  {PA_2,  PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // SERIAL_TX
+//  {PA_2,  PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 // SERIAL_TX
+//  {PA_3,  PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // SERIAL_RX
+//  {PA_3,  PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // SERIAL_RX
+//  {PA_3,  PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 // SERIAL_RX
     {PA_5,  PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
     {PA_6,  PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
     {PA_7,  PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - ARDUINO
@@ -133,7 +137,7 @@
 //*** SERIAL ***
 
 const PinMap PinMap_UART_TX[] = {
-    {PA_2,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_2,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // SERIAL_TX
     {PA_9,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
     {PB_6,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
@@ -142,7 +146,7 @@
 };
 
 const PinMap PinMap_UART_RX[] = {
-    {PA_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // SERIAL_RX
     {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
     {PB_7,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/PeripheralPins.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/PeripheralPins.c	Fri Apr 28 14:04:18 2017 +0100
@@ -58,6 +58,10 @@
     {NC,   NC,    0}
 };
 
+const PinMap PinMap_ADC_Internal[] = {
+    {NC,   NC,    0}
+};
+
 
 //*** DAC ***
 

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/PeripheralPins.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/PeripheralPins.c	Fri Apr 28 14:04:18 2017 +0100
@@ -55,6 +55,10 @@
     {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
     {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
     {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/PeripheralPins.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/PeripheralPins.c	Fri Apr 28 14:04:18 2017 +0100
@@ -41,8 +41,8 @@
 const PinMap PinMap_ADC[] = {
     {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0,  0)}, // ADC1_IN0
     {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1,  0)}, // ADC1_IN1
-    {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2,  0)}, // ADC1_IN2
-    {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3,  0)}, // ADC1_IN3
+//  {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2,  0)}, // ADC1_IN2 // SERIAL_TX
+//  {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3,  0)}, // ADC1_IN3 // SERIAL_RX
     {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4,  0)}, // ADC1_IN4
     {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5,  0)}, // ADC1_IN5
     {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6,  0)}, // ADC1_IN6
@@ -55,6 +55,10 @@
     {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
     {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
     {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PeripheralPins.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PeripheralPins.c	Fri Apr 28 14:04:18 2017 +0100
@@ -55,6 +55,10 @@
     {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
     {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
     {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/PeripheralPins.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/PeripheralPins.c	Fri Apr 28 14:04:18 2017 +0100
@@ -41,8 +41,8 @@
 const PinMap PinMap_ADC[] = {
     {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0,  0)}, // ADC1_IN0
     {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1,  0)}, // ADC1_IN1
-    {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2,  0)}, // ADC1_IN2
-    {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3,  0)}, // ADC1_IN3
+//  {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2,  0)}, // ADC1_IN2 // SERIAL_TX
+//  {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3,  0)}, // ADC1_IN3 // SERIAL_RX
     {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4,  0)}, // ADC1_IN4
     {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5,  0)}, // ADC1_IN5
     {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6,  0)}, // ADC1_IN6
@@ -55,6 +55,10 @@
     {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
     {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
     {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used
@@ -90,12 +94,12 @@
 //  {PA_0,  PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
     {PA_1,  PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
 //  {PA_1,  PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
-    {PA_2,  PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
-//  {PA_2,  PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
-//  {PA_2,  PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
-    {PA_3,  PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
-//  {PA_3,  PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
-//  {PA_3,  PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+//  {PA_2,  PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // SERIAL_TX
+//  {PA_2,  PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // SERIAL_TX
+//  {PA_2,  PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 // SERIAL_TX
+//  {PA_3,  PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // SERIAL_RX
+//  {PA_3,  PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // SERIAL_RX
+//  {PA_3,  PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 // SERIAL_RX
     {PA_5,  PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
     {PA_6,  PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
     {PA_7,  PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - ARDUINO
@@ -135,7 +139,7 @@
 //*** SERIAL ***
 
 const PinMap PinMap_UART_TX[] = {
-    {PA_2,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_2,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // SERIAL_TX
     {PA_9,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
     {PA_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
@@ -145,7 +149,7 @@
 };
 
 const PinMap PinMap_UART_RX[] = {
-    {PA_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // SERIAL_RX
     {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
     {PB_3,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PeripheralPins.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PeripheralPins.c	Fri Apr 28 14:04:18 2017 +0100
@@ -40,6 +40,10 @@
     {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 - A2
     {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 - A4
     {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 - A5
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_IAR/stm32f412xx.icf	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_IAR/stm32f412xx.icf	Fri Apr 28 14:04:18 2017 +0100
@@ -15,7 +15,6 @@
 define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
 
 /* Stack and Heap */
-/*Heap 1/4 of ram and stack 1/8*/
 define symbol __size_cstack__ = 0x8000;
 define symbol __size_heap__   = 0x10000;
 define block CSTACK    with alignment = 8, size = __size_cstack__   { };

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/PeripheralPins.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/PeripheralPins.c	Fri Apr 28 14:04:18 2017 +0100
@@ -63,6 +63,10 @@
     {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6,  0)}, // ADC3_IN6
     {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7,  0)}, // ADC3_IN7
     {PF_10,ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8,  0)}, // ADC3_IN8
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PeripheralPins.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PeripheralPins.c	Fri Apr 28 14:04:18 2017 +0100
@@ -87,6 +87,10 @@
     {PF_8,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6
     {PF_9,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7
     {PF_10,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8 - ARDUINO A5
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PeripheralPins.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PeripheralPins.c	Fri Apr 28 14:04:18 2017 +0100
@@ -47,6 +47,10 @@
     {NC,   NC,    0}
 };
 
+const PinMap PinMap_ADC_Internal[] = {
+    {NC,   NC,    0}
+};
+
 //*** I2C ***
 
 

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/system_stm32f4xx.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/system_stm32f4xx.c	Fri Apr 28 14:04:18 2017 +0100
@@ -21,20 +21,20 @@
   *                                 during program execution.
   *
   * This file configures the system clock as follows:
-  *--------------------------------------------------------------------------------------
-  * System clock source                | PLL_HSE_XTAL           | PLL_HSE_XTAL           
-  *                                    | (external 8 MHz clock) | (external 8 MHz clock) 
-  *--------------------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 168                    | 84                    
-  *--------------------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 168                    | 84                   
-  *--------------------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 42                     | 42                     
-  *--------------------------------------------------------------------------------------
-  * APB2CLK (MHz)                      | 84                     | 84                     
-  *--------------------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | YES                    | YES                     
-  *--------------------------------------------------------------------------------------
+  *----------------------------------------------------------------------------------------------------------------------------------------
+  * System clock source                | PLL_HSE_XTAL           | PLL_HSE_XTAL           | PLL_HSE_XTAL           | PLL_HSE_XTAL
+  *                                    | (external 8 MHz clock) | (external 8 MHz clock) | (external 12 MHz clock)| (external 12 MHz clock)
+  *----------------------------------------------------------------------------------------------------------------------------------------
+  * SYSCLK(MHz)                        | 168                    | 84                     | 168                    | 84
+  *----------------------------------------------------------------------------------------------------------------------------------------
+  * AHBCLK (MHz)                       | 168                    | 84                     | 168                    | 84
+  *----------------------------------------------------------------------------------------------------------------------------------------
+  * APB1CLK (MHz)                      | 42                     | 42                     | 42                     | 42
+  *----------------------------------------------------------------------------------------------------------------------------------------
+  * APB2CLK (MHz)                      | 84                     | 84                     | 84                     | 84
+  *----------------------------------------------------------------------------------------------------------------------------------------
+  * USB capable (48 MHz precise clock) | YES                    | YES                    | YES                    | YES
+  *----------------------------------------------------------------------------------------------------------------------------------------
   ******************************************************************************
   * @attention
   *
@@ -136,8 +136,8 @@
   */
 
 /* Select the SYSCLOCK  to start with (0=OFF, 1=ON) */
-#define USE_SYSCLOCK_168 (1) /* Use external 8MHz xtal and sets SYSCLK to 168MHz */
-#define USE_SYSCLOCK_84 (0) /* Use external 8MHz xtal and sets SYSCLK to 84MHz */
+#define USE_SYSCLOCK_168 (1) /* Use external 8MHz or 12 MHz xtal and sets SYSCLK to 168MHz */
+#define USE_SYSCLOCK_84 (0) /* Use external 8MHz or 12 MHz xtal and sets SYSCLK to 84MHz */
 
 /**
   * @}
@@ -801,7 +801,11 @@
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
   RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+#ifdef USE_DEBUG_8MHz_XTAL
   RCC_OscInitStruct.PLL.PLLM = 8;
+#else
+  RCC_OscInitStruct.PLL.PLLM = 12;
+#endif
   RCC_OscInitStruct.PLL.PLLN = 336;
   RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
   RCC_OscInitStruct.PLL.PLLQ = 7;
@@ -838,7 +842,11 @@
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
   RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+#ifdef USE_DEBUG_8MHz_XTAL
   RCC_OscInitStruct.PLL.PLLM = 8;
+#else
+  RCC_OscInitStruct.PLL.PLLM = 12;
+#endif
   RCC_OscInitStruct.PLL.PLLN = 336;
   RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
   RCC_OscInitStruct.PLL.PLLQ = 7;
@@ -869,4 +877,4 @@
 /**
   * @}
   */    
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\ No newline at end of file

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PeripheralPins.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PeripheralPins.c	Fri Apr 28 14:04:18 2017 +0100
@@ -87,6 +87,10 @@
     {PF_8,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6
     {PF_9,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7
     {PF_10,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8 - ARDUINO A5
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/PeripheralPins.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/PeripheralPins.c	Fri Apr 28 14:04:18 2017 +0100
@@ -55,6 +55,10 @@
     {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
     {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
     {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PeripheralPins.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PeripheralPins.c	Fri Apr 28 14:04:18 2017 +0100
@@ -41,8 +41,8 @@
 const PinMap PinMap_ADC[] = {
     {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0,  0)}, // ADC1_IN0 - ARDUINO A0
     {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1,  0)}, // ADC1_IN1 - ARDUINO A1
-    {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2,  0)}, // ADC1_IN2
-    {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3,  0)}, // ADC1_IN3
+//  {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2,  0)}, // ADC1_IN2 // SERIAL_TX
+//  {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3,  0)}, // ADC1_IN3 // SERIAL_RX
     {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4,  0)}, // ADC1_IN4 - ARDUINO A2
     {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5,  0)}, // ADC1_IN5
     {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6,  0)}, // ADC1_IN6
@@ -55,6 +55,10 @@
     {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
     {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
     {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used
@@ -99,12 +103,12 @@
 //  {PA_0,  PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
     {PA_1,  PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
 //  {PA_1,  PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
-    {PA_2,  PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
-//  {PA_2,  PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
-//  {PA_2,  PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
-    {PA_3,  PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
-//  {PA_3,  PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
-//  {PA_3,  PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+//  {PA_2,  PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // SERIAL_TX
+//  {PA_2,  PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // SERIAL_TX
+//  {PA_2,  PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 // SERIAL_TX
+//  {PA_3,  PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // SERIAL_RX
+//  {PA_3,  PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // SERIAL_RX
+//  {PA_3,  PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 // SERIAL_RX
     {PA_5,  PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
 //  {PA_5,  PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
     {PA_6,  PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
@@ -162,7 +166,7 @@
 
 const PinMap PinMap_UART_TX[] = {
     {PA_0,  UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
-    {PA_2,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_2,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // SERIAL_TX
     {PA_9,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PB_6,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
@@ -175,7 +179,7 @@
 
 const PinMap PinMap_UART_RX[] = {
     {PA_1,  UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
-    {PA_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // SERIAL_RX
     {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PB_7,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PC_5,  UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PeripheralPins.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PeripheralPins.c	Fri Apr 28 14:04:18 2017 +0100
@@ -89,6 +89,10 @@
     {PF_8,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6
     {PF_9,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7
     {PF_10,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8 - ARDUINO A5
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used
@@ -107,12 +111,12 @@
 
 const PinMap PinMap_I2C_SDA[] = {
     {PB_3,  I2C_2   , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
-    {PB_4,  I2C_3   , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    //{PB_4,  I2C_3   , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // no I2C_3 SCL available
     //{PB_7,  I2C_1   , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // (used by LED2)
     {PB_9,  I2C_1   , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
     {PB_11, I2C_2   , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
     //{PC_7,  FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
-    {PC_9,  I2C_3   , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    //{PC_9,  I2C_3   , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // no I2C_3 SCL available
     {PC_12, I2C_2   , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
     //{PD_13, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},
     //{PD_15, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PeripheralPins.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PeripheralPins.c	Fri Apr 28 14:04:18 2017 +0100
@@ -63,6 +63,10 @@
     {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6,  0)}, // ADC3_IN6
     {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7,  0)}, // ADC3_IN7
     {PF_10,ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8,  0)}, // ADC3_IN8
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used
@@ -84,7 +88,7 @@
 const PinMap PinMap_I2C_SDA[] = {
     {PB_7,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
     {PB_9,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
-    {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+//  {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // SERIAL_RX
     {PC_9,  I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
     {PF_0,  I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
     {PH_5,  I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
@@ -96,7 +100,7 @@
     {PA_8,  I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
     {PB_6,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
     {PB_8,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
-    {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+//  {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // SERIAL_TX
     {PF_1,  I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
     {PH_4,  I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
     {PH_7,  I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
@@ -141,8 +145,8 @@
 //  {PB_8,  PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10,1, 0)},  // TIM10_CH1
     {PB_9,  PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)},  // TIM4_CH4
 //  {PB_9,  PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11,1, 0)},  // TIM11_CH1
-    {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)},  // TIM2_CH3
-    {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)},  // TIM2_CH4
+//  {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)},  // TIM2_CH3 // SERIAL_TX
+//  {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)},  // TIM2_CH4 // SERIAL_RX
     {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)},  // TIM1_CH1N
     {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)},  // TIM1_CH2N
 //  {PB_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)},  // TIM8_CH2N
@@ -202,7 +206,7 @@
     {PA_2,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
     {PA_9,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PB_6,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
-    {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // SERIAL_TX
     {PC_6,  UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
     {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
     // {PC_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
@@ -221,7 +225,7 @@
     {PA_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
     {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PB_7,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
-    {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // SERIAL_RX
     {PC_7,  UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
     {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
     // {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
@@ -298,7 +302,7 @@
     {PA_9,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
     {PB_3,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
     // {PB_3,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
-    {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    // {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // SERIAL_TX
     {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
     {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
     {PD_3,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_IAR/stm32f469xx.icf	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_IAR/stm32f469xx.icf	Fri Apr 28 14:04:18 2017 +0100
@@ -15,9 +15,8 @@
 define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
 
 /* Stack and Heap */
-/*Heap 1/4 of ram and stack 1/8*/
 define symbol __size_cstack__ = 0x4000;
-define symbol __size_heap__   = 0x8000;
+define symbol __size_heap__   = 0x10000;
 define block CSTACK    with alignment = 8, size = __size_cstack__   { };
 define block HEAP      with alignment = 8, size = __size_heap__     { };
 define block STACKHEAP with fixed order { block HEAP, block CSTACK };

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/PeripheralPins.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/PeripheralPins.c	Fri Apr 28 14:04:18 2017 +0100
@@ -54,6 +54,11 @@
     {NC,   NC,    0}
 };
 
+const PinMap PinMap_ADC_Internal[] = {
+    {NC,   NC,    0}
+};
+
+
 //*** I2C ***
 
 const PinMap PinMap_I2C_SDA[] = {

--- a/targets/TARGET_STM/TARGET_STM32F4/analogin_api.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/analogin_api.c	Fri Apr 28 14:04:18 2017 +0100
@@ -40,6 +40,9 @@
 
 void analogin_init(analogin_t *obj, PinName pin)
 {
+    uint32_t function = (uint32_t)NC;
+    obj->adc = (ADCName)NC;
+
 #if defined(ADC1)
     static int adc1_inited = 0;
 #endif
@@ -49,21 +52,28 @@
 #if defined(ADC3)
     static int adc3_inited = 0;
 #endif
-    // Get the peripheral name from the pin and assign it to the object
-    obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+    // ADC Internal Channels "pins"  (Temperature, Vref, Vbat, ...)
+    //   are described in PinNames.h and PeripheralPins.c
+    //   Pin value must be >= 0xF0
+    if (pin < 0xF0) {
+        // Normal channels
+        // Get the peripheral name from the pin and assign it to the object
+        obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+        // Get the functions (adc channel) from the pin and assign it to the object
+        function = pinmap_function(pin, PinMap_ADC);
+        // Configure GPIO
+        pinmap_pinout(pin, PinMap_ADC);
+    } else {
+        // Internal channels
+        obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC_Internal);
+        function = pinmap_function(pin, PinMap_ADC_Internal);
+        // No GPIO configuration for internal channels
+    }
     MBED_ASSERT(obj->adc != (ADCName)NC);
-
-    // Get the functions (adc channel) from the pin and assign it to the object
-    uint32_t function = pinmap_function(pin, PinMap_ADC);
     MBED_ASSERT(function != (uint32_t)NC);
+
     obj->channel = STM_PIN_CHANNEL(function);
 
-    // Configure GPIO excepted for internal channels (Temperature, Vref, Vbat, ...)
-    // ADC Internal Channels "pins" are described in PinNames.h and must have a value >= 0xF0
-    if (pin < 0xF0) {
-        pinmap_pinout(pin, PinMap_ADC);
-    }
-
     // Save pin number for the read function
     obj->pin = pin;
 

--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PeripheralPins.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PeripheralPins.c	Fri Apr 28 14:04:18 2017 +0100
@@ -47,6 +47,10 @@
     {PF_8,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6 - ARDUINO A3
     {PF_9,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7 - ARDUINO A2
     {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8 - ARDUINO A1
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used

--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PeripheralPins.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PeripheralPins.c	Fri Apr 28 14:04:18 2017 +0100
@@ -65,6 +65,10 @@
     {PF_8,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6
     {PF_9,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7
     {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8 - ARDUINO A5
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used

--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PeripheralPins.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PeripheralPins.c	Fri Apr 28 14:04:18 2017 +0100
@@ -65,6 +65,10 @@
     {PF_8,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6
     {PF_9,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7
     {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8 - ARDUINO A5
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used

--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/TOOLCHAIN_IAR/stm32f756xg.icf	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/TOOLCHAIN_IAR/stm32f756xg.icf	Fri Apr 28 14:04:18 2017 +0100
@@ -19,9 +19,8 @@
 define region ITCMRAM_region = mem:[from __region_ITCMRAM_start__ to __region_ITCMRAM_end__];
 
 /* Stack and Heap */
-/*Heap 1/4 of ram and stack 1/8*/
 define symbol __size_cstack__ = 0x4000;
-define symbol __size_heap__   = 0x8000;
+define symbol __size_heap__   = 0x10000;
 define block CSTACK    with alignment = 8, size = __size_cstack__   { };
 define block HEAP      with alignment = 8, size = __size_heap__     { };
 define block STACKHEAP with fixed order { block HEAP, block CSTACK };

--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PeripheralPins.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PeripheralPins.c	Fri Apr 28 14:04:18 2017 +0100
@@ -65,6 +65,10 @@
     {PF_8,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6
     {PF_9,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7
     {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8 - ARDUINO A5
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used

--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_IAR/stm32f767xi.icf	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_IAR/stm32f767xi.icf	Fri Apr 28 14:04:18 2017 +0100
@@ -19,9 +19,8 @@
 define region ITCMRAM_region = mem:[from __region_ITCMRAM_start__ to __region_ITCMRAM_end__];
 
 /* Stack and Heap */
-/*Heap 1/4 of ram and stack 1/8*/
 define symbol __size_cstack__ = 0x8000;
-define symbol __size_heap__   = 0x8000;
+define symbol __size_heap__   = 0x10000;
 define block CSTACK    with alignment = 8, size = __size_cstack__   { };
 define block HEAP      with alignment = 8, size = __size_heap__     { };
 define block STACKHEAP with fixed order { block HEAP, block CSTACK };

--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PeripheralPins.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PeripheralPins.c	Fri Apr 28 14:04:18 2017 +0100
@@ -52,6 +52,10 @@
     {PF_8,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6 - ARDUINO A4
     {PF_9,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7 - ARDUINO A5
     {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8 - ARDUINO A3
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used

--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/TOOLCHAIN_IAR/stm32f769xi.icf	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/TOOLCHAIN_IAR/stm32f769xi.icf	Fri Apr 28 14:04:18 2017 +0100
@@ -19,9 +19,8 @@
 define region ITCMRAM_region = mem:[from __region_ITCMRAM_start__ to __region_ITCMRAM_end__];
 
 /* Stack and Heap */
-/*Heap 1/4 of ram and stack 1/8*/
 define symbol __size_cstack__ = 0x8000;
-define symbol __size_heap__   = 0x8000;
+define symbol __size_heap__   = 0x10000;
 define block CSTACK    with alignment = 8, size = __size_cstack__   { };
 define block HEAP      with alignment = 8, size = __size_heap__     { };
 define block STACKHEAP with fixed order { block HEAP, block CSTACK };

--- a/targets/TARGET_STM/TARGET_STM32F7/analogin_api.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/analogin_api.c	Fri Apr 28 14:04:18 2017 +0100
@@ -40,6 +40,9 @@
 
 void analogin_init(analogin_t *obj, PinName pin)
 {
+    uint32_t function = (uint32_t)NC;
+    obj->adc = (ADCName)NC;
+
 #if defined(ADC1)
     static int adc1_inited = 0;
 #endif
@@ -49,22 +52,28 @@
 #if defined(ADC3)
     static int adc3_inited = 0;
 #endif
-
-    // Get the peripheral name from the pin and assign it to the object
-    obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+    // ADC Internal Channels "pins"  (Temperature, Vref, Vbat, ...)
+    //   are described in PinNames.h and PeripheralPins.c
+    //   Pin value must be >= 0xF0
+    if (pin < 0xF0) {
+        // Normal channels
+        // Get the peripheral name from the pin and assign it to the object
+        obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+        // Get the functions (adc channel) from the pin and assign it to the object
+        function = pinmap_function(pin, PinMap_ADC);
+        // Configure GPIO
+        pinmap_pinout(pin, PinMap_ADC);
+    } else {
+        // Internal channels
+        obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC_Internal);
+        function = pinmap_function(pin, PinMap_ADC_Internal);
+        // No GPIO configuration for internal channels
+    }
     MBED_ASSERT(obj->adc != (ADCName)NC);
-
-    // Get the functions (adc channel) from the pin and assign it to the object
-    uint32_t function = pinmap_function(pin, PinMap_ADC);
     MBED_ASSERT(function != (uint32_t)NC);
+
     obj->channel = STM_PIN_CHANNEL(function);
 
-    // Configure GPIO excepted for internal channels (Temperature, Vref, Vbat, ...)
-    // ADC Internal Channels "pins" are described in PinNames.h and must have a value >= 0xF0
-    if (pin < 0xF0) {
-        pinmap_pinout(pin, PinMap_ADC);
-    }
-
     // Save pin number for the read function
     obj->pin = pin;
 

--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralPins.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralPins.c	Fri Apr 28 14:04:18 2017 +0100
@@ -49,6 +49,10 @@
     {PA_7,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
     {PB_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
 //  {PB_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16 - does not support channel >= 16
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,  0, 0)},
     {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},

--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PeripheralPins.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PeripheralPins.c	Fri Apr 28 14:04:18 2017 +0100
@@ -55,6 +55,10 @@
     {PC_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  4, 0)}, // IN4
     {PC_4,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // IN13
     {PC_5,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 14, 0)}, // IN14
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,  0, 0)},
     {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},

--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PeripheralPins.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PeripheralPins.c	Fri Apr 28 14:04:18 2017 +0100
@@ -55,6 +55,10 @@
     {PC_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  4, 0)}, // IN4
     {PC_4,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // IN13
     {PC_5,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 14, 0)}, // IN14
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,  0, 0)},
     {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},

--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/PeripheralPins.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/PeripheralPins.c	Fri Apr 28 14:04:18 2017 +0100
@@ -41,8 +41,8 @@
 const PinMap PinMap_ADC[] = {
     {PA_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  5, 0)}, // IN5 - ARDUINO A0
     {PA_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  6, 0)}, // IN6 - ARDUINO A1
-    {PA_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  7, 0)}, // IN7
-    {PA_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  8, 0)}, // IN8
+//  {PA_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  7, 0)}, // IN7 // PA_2 is used as SERIAL_TX
+//  {PA_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  8, 0)}, // IN8 // PA_3 is used as SERIAL_RX
     {PA_4,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  9, 0)}, // IN9 - ARDUINO A2
     {PA_5,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 10, 0)}, // IN10
     {PA_6,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 11, 0)}, // IN11
@@ -55,6 +55,10 @@
     {PC_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  4, 0)}, // IN4
     {PC_4,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // IN13
     {PC_5,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 14, 0)}, // IN14
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,  0, 0)},
     {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
@@ -98,10 +102,10 @@
     {PA_1,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)},  // TIM2_CH2
 //  {PA_1,  PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)},  // TIM5_CH2 (used by us_ticker)
 //  {PA_1,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)},// TIM15_CH1N
-    {PA_2,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)},  // TIM2_CH3
+//  {PA_2,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)},  // TIM2_CH3 // PA_2 is used as SERIAL_TX
 //  {PA_2,  PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)},  // TIM5_CH3 (used by us_ticker)
 //  {PA_2,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)},// TIM15_CH1
-    {PA_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)},  // TIM2_CH4
+//  {PA_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)},  // TIM2_CH4 // PA_3 is used as SERIAL_RX
 //  {PA_3,  PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)},  // TIM5_CH4 (used by us_ticker)
 //  {PA_3,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)},// TIM15_CH2
     {PA_5,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},  // TIM2_CH1
@@ -159,11 +163,11 @@
 
 const PinMap PinMap_UART_TX[] = {
     {PA_0,  UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
-    {PA_2,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_2,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // SERIAL_TX
     {PA_9,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PB_6,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
-//  {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Already used by UART_RX
+    {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
     {PC_1,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
     {PC_4,  UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
     {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
@@ -174,10 +178,10 @@
 
 const PinMap PinMap_UART_RX[] = {
     {PA_1,  UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
-    {PA_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // SERIAL_RX
     {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PB_7,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
-//  {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Already used by UART_TX
+    {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
     {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
     {PC_0,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
     {PC_5,  UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},

--- a/targets/TARGET_STM/TARGET_STM32L4/analogin_api.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/analogin_api.c	Fri Apr 28 14:04:18 2017 +0100
@@ -42,21 +42,31 @@
 
 void analogin_init(analogin_t *obj, PinName pin)
 {
-    // Get the peripheral name from the pin and assign it to the object
-    obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+    uint32_t function = (uint32_t)NC;
+    obj->adc = (ADCName)NC;
+
+    // ADC Internal Channels "pins"  (Temperature, Vref, Vbat, ...)
+    //   are described in PinNames.h and PeripheralPins.c
+    //   Pin value must be >= 0xF0
+    if (pin < 0xF0) {
+        // Normal channels
+        // Get the peripheral name from the pin and assign it to the object
+        obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+        // Get the functions (adc channel) from the pin and assign it to the object
+        function = pinmap_function(pin, PinMap_ADC);
+        // Configure GPIO
+        pinmap_pinout(pin, PinMap_ADC);
+    } else {
+        // Internal channels
+        obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC_Internal);
+        function = pinmap_function(pin, PinMap_ADC_Internal);
+        // No GPIO configuration for internal channels
+    }
     MBED_ASSERT(obj->adc != (ADCName)NC);
-
-    // Get the pin function and assign the used channel to the object
-    uint32_t function = pinmap_function(pin, PinMap_ADC);
     MBED_ASSERT(function != (uint32_t)NC);
+
     obj->channel = STM_PIN_CHANNEL(function);
 
-    // Configure GPIO excepted for internal channels (Temperature, Vref, Vbat, ...)
-    // ADC Internal Channels "pins" are described in PinNames.h and must have a value >= 0xF0
-    if (pin < 0xF0) {
-        pinmap_pinout(pin, PinMap_ADC);
-    }
-
     // Save pin number for the read function
     obj->pin = pin;
 

--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/PeripheralPins.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/PeripheralPins.c	Fri Apr 28 14:04:18 2017 +0100
@@ -100,6 +100,37 @@
     {PF7,  I2C_0, 30},
     {PA0,  I2C_0, 31},
 
+    {PA7, I2C_1, 0},
+    {PA8, I2C_1, 1},
+    {PA9, I2C_1, 2},
+    {PI2, I2C_1, 3},
+    {PI3, I2C_1, 4},
+    {PB6, I2C_1, 5},
+    {PB7, I2C_1, 6},
+    {PB8, I2C_1, 7},
+    {PB9, I2C_1, 8},
+    {PB10, I2C_1, 9},
+    {PJ14, I2C_1, 10},
+    {PJ15, I2C_1, 11},
+    {PC0, I2C_1, 12},
+    {PC1, I2C_1, 13},
+    {PC2, I2C_1, 14},
+    {PC3, I2C_1, 15},
+    {PC4, I2C_1, 16},
+    {PC5, I2C_1, 17},
+    {PF8, I2C_1, 20},
+    {PF9, I2C_1, 21},
+    {PF10, I2C_1, 22},
+    {PF11, I2C_1, 23},
+    {PF12, I2C_1, 24},
+    {PF13, I2C_1, 25},
+    {PF14, I2C_1, 26},
+    {PF15, I2C_1, 27},
+    {PK0, I2C_1, 28},
+    {PK1, I2C_1, 29},
+    {PK2, I2C_1, 30},
+    {PA6, I2C_1, 31},
+
     {NC  , NC   , NC}
 };
 
@@ -139,7 +170,39 @@
     {PF6,  I2C_0, 30},
     {PF7,  I2C_0, 31},
 
+    {PA6, I2C_1, 0},
+    {PA7, I2C_1, 1},
+    {PA8, I2C_1, 2},
+    {PA9, I2C_1, 3},
+    {PI2, I2C_1, 4},
+    {PI3, I2C_1, 5},
+    {PB6, I2C_1, 6},
+    {PB7, I2C_1, 7},
+    {PB8, I2C_1, 8},
+    {PB9, I2C_1, 9},
+    {PB10, I2C_1, 10},
+    {PJ14, I2C_1, 11},
+    {PJ15, I2C_1, 12},
+    {PC0, I2C_1, 13},
+    {PC1, I2C_1, 14},
+    {PC2, I2C_1, 15},
+    {PC3, I2C_1, 16},
+    {PC4, I2C_1, 17},
+    {PC5, I2C_1, 18},
+    {PF8, I2C_1, 21},
+    {PF9, I2C_1, 22},
+    {PF10, I2C_1, 23},
+    {PF11, I2C_1, 24},
+    {PF12, I2C_1, 25},
+    {PF13, I2C_1, 26},
+    {PF14, I2C_1, 27},
+    {PF15, I2C_1, 28},
+    {PK0, I2C_1, 29},
+    {PK1, I2C_1, 30},
+    {PK2, I2C_1, 31},
+
     /* Not connected */
+
     {NC  , NC   , NC}
 };
 
@@ -220,6 +283,42 @@
     {PF6,  SPI_1, 30},
     {PF7,  SPI_1, 31},
 
+    /* USART2 */
+    {PA6,  SPI_2, 1},
+    {PA7,  SPI_2, 2},
+    {PA8,  SPI_2, 3},
+    {PA9,  SPI_2, 4},
+    {PI0,  SPI_2, 5},
+    {PI1,  SPI_2, 6},
+    {PI2,  SPI_2, 7},
+    {PI3,  SPI_2, 8},
+    {PB6,  SPI_2, 9},
+    {PB7,  SPI_2, 10},
+    {PB8,  SPI_2, 11},
+    {PB9,  SPI_2, 12},
+    {PB10, SPI_2, 13},
+    {PF8,  SPI_2, 21},
+    {PF9,  SPI_2, 22},
+    {PF10, SPI_2, 23},
+    {PF11, SPI_2, 24},
+    {PF12, SPI_2, 25},
+    {PF13, SPI_2, 26},
+    {PF14, SPI_2, 27},
+    {PF15, SPI_2, 28},
+    {PK0,  SPI_2, 29},
+    {PK1,  SPI_2, 30},
+    {PK2,  SPI_2, 31},
+
+    /* USART3 */
+    {PJ14, SPI_3, 16},
+    {PJ15, SPI_3, 17},
+    {PC0,  SPI_3, 18},
+    {PC1,  SPI_3, 19},
+    {PC2,  SPI_3, 20},
+    {PC3,  SPI_3, 21},
+    {PC4,  SPI_3, 22},
+    {PC5,  SPI_3, 23},
+
     {NC  , NC   , NC}
 };
 
@@ -262,6 +361,42 @@
     {PF7,  SPI_1, 30},
     {PA0,  SPI_1, 31},
 
+    /* USART2 */
+    {PA6,  SPI_2, 0},
+    {PA7,  SPI_2, 1},
+    {PA8,  SPI_2, 2},
+    {PA9,  SPI_2, 3},
+    {PI0,  SPI_2, 4},
+    {PI1,  SPI_2, 5},
+    {PI2,  SPI_2, 6},
+    {PI3,  SPI_2, 7},
+    {PB6,  SPI_2, 8},
+    {PB7,  SPI_2, 9},
+    {PB8,  SPI_2, 10},
+    {PB9,  SPI_2, 11},
+    {PB10, SPI_2, 12},
+    {PF8,  SPI_2, 20},
+    {PF9,  SPI_2, 21},
+    {PF10, SPI_2, 22},
+    {PF11, SPI_2, 23},
+    {PF12, SPI_2, 24},
+    {PF13, SPI_2, 25},
+    {PF14, SPI_2, 26},
+    {PF15, SPI_2, 27},
+    {PK0,  SPI_2, 28},
+    {PK1,  SPI_2, 29},
+    {PK2,  SPI_2, 30},
+
+    /* USART3 */
+    {PJ14, SPI_3, 15},
+    {PJ15, SPI_3, 16},
+    {PC0,  SPI_3, 17},
+    {PC1,  SPI_3, 18},
+    {PC2,  SPI_3, 19},
+    {PC3,  SPI_3, 20},
+    {PC4,  SPI_3, 21},
+    {PC5,  SPI_3, 22},
+
     {NC  , NC   , NC}
 };
 
@@ -305,6 +440,42 @@
     {PA0,  SPI_1, 30},
     {PA1,  SPI_1, 31},
 
+    /* USART2 */
+    {PA7,  SPI_2, 0},
+    {PA8,  SPI_2, 1},
+    {PA9,  SPI_2, 2},
+    {PI0,  SPI_2, 3},
+    {PI1,  SPI_2, 4},
+    {PI2,  SPI_2, 5},
+    {PI3,  SPI_2, 6},
+    {PB6,  SPI_2, 7},
+    {PB7,  SPI_2, 8},
+    {PB8,  SPI_2, 9},
+    {PB9,  SPI_2, 10},
+    {PB10, SPI_2, 11},
+    {PF8,  SPI_2, 19},
+    {PF9,  SPI_2, 20},
+    {PF10, SPI_2, 21},
+    {PF11, SPI_2, 22},
+    {PF12, SPI_2, 23},
+    {PF13, SPI_2, 24},
+    {PF14, SPI_2, 25},
+    {PF15, SPI_2, 26},
+    {PK0,  SPI_2, 27},
+    {PK1,  SPI_2, 28},
+    {PK2,  SPI_2, 29},
+    {PA6,  SPI_2, 31},
+
+    /* USART3 */
+    {PJ14, SPI_3, 14},
+    {PJ15, SPI_3, 15},
+    {PC0,  SPI_3, 16},
+    {PC1,  SPI_3, 17},
+    {PC2,  SPI_3, 18},
+    {PC3,  SPI_3, 19},
+    {PC4,  SPI_3, 20},
+    {PC5,  SPI_3, 21},
+
     {NC  , NC   , NC}
 };
 
@@ -346,6 +517,42 @@
     {PF6,  SPI_1, 27},
     {PF7,  SPI_1, 28},
 
+    /* USART2 */
+    {PA8,  SPI_2, 0},
+    {PA9,  SPI_2, 1},
+    {PI0,  SPI_2, 2},
+    {PI1,  SPI_2, 3},
+    {PI2,  SPI_2, 4},
+    {PI3,  SPI_2, 5},
+    {PB6,  SPI_2, 6},
+    {PB7,  SPI_2, 7},
+    {PB8,  SPI_2, 8},
+    {PB9,  SPI_2, 9},
+    {PB10, SPI_2, 10},
+    {PF8,  SPI_2, 18},
+    {PF9,  SPI_2, 19},
+    {PF10, SPI_2, 20},
+    {PF11, SPI_2, 21},
+    {PF12, SPI_2, 22},
+    {PF13, SPI_2, 23},
+    {PF14, SPI_2, 24},
+    {PF15, SPI_2, 25},
+    {PK0,  SPI_2, 26},
+    {PK1,  SPI_2, 27},
+    {PK2,  SPI_2, 28},
+    {PA6,  SPI_2, 30},
+    {PA7,  SPI_2, 31},
+
+    /* USART3 */
+    {PJ14, SPI_3, 13},
+    {PJ15, SPI_3, 14},
+    {PC0,  SPI_3, 15},
+    {PC1,  SPI_3, 16},
+    {PC2,  SPI_3, 17},
+    {PC3,  SPI_3, 18},
+    {PC4,  SPI_3, 19},
+    {PC5,  SPI_3, 20},
+
     {NC  , NC   , NC}
 };
 
@@ -385,6 +592,42 @@
     {PF6,  USART_1, 30},
     {PF7,  USART_1, 31},
 
+    /* USART2 */
+    {PA6,  USART_2, 1},
+    {PA7,  USART_2, 2},
+    {PA8,  USART_2, 3},
+    {PA9,  USART_2, 4},
+    {PI0,  USART_2, 5},
+    {PI1,  USART_2, 6},
+    {PI2,  USART_2, 7},
+    {PI3,  USART_2, 8},
+    {PB6,  USART_2, 9},
+    {PB7,  USART_2, 10},
+    {PB8,  USART_2, 11},
+    {PB9,  USART_2, 12},
+    {PB10, USART_2, 13},
+    {PF8,  USART_2, 21},
+    {PF9,  USART_2, 22},
+    {PF10, USART_2, 23},
+    {PF11, USART_2, 24},
+    {PF12, USART_2, 25},
+    {PF13, USART_2, 26},
+    {PF14, USART_2, 27},
+    {PF15, USART_2, 28},
+    {PK0,  USART_2, 29},
+    {PK1,  USART_2, 30},
+    {PK2,  USART_2, 31},
+
+    /* USART3 */
+    {PJ14, USART_3, 16},
+    {PJ15, USART_3, 17},
+    {PC0,  USART_3, 18},
+    {PC1,  USART_3, 19},
+    {PC2,  USART_3, 20},
+    {PC3,  USART_3, 21},
+    {PC4,  USART_3, 22},
+    {PC5,  USART_3, 23},
+
     {NC  , NC   , NC}
 };
 
@@ -423,5 +666,41 @@
     {PF6,  USART_1, 29},
     {PF7,  USART_1, 30},
 
+    /* USART2 */
+    {PA6,  USART_2, 0},
+    {PA7,  USART_2, 1},
+    {PA8,  USART_2, 2},
+    {PA9,  USART_2, 3},
+    {PI0,  USART_2, 4},
+    {PI1,  USART_2, 5},
+    {PI2,  USART_2, 6},
+    {PI3,  USART_2, 7},
+    {PB6,  USART_2, 8},
+    {PB7,  USART_2, 9},
+    {PB8,  USART_2, 10},
+    {PB9,  USART_2, 11},
+    {PB10, USART_2, 12},
+    {PF8,  USART_2, 20},
+    {PF9,  USART_2, 21},
+    {PF10, USART_2, 22},
+    {PF11, USART_2, 23},
+    {PF12, USART_2, 24},
+    {PF13, USART_2, 25},
+    {PF14, USART_2, 26},
+    {PF15, USART_2, 27},
+    {PK0,  USART_2, 28},
+    {PK1,  USART_2, 29},
+    {PK2,  USART_2, 30},
+
+    /* USART3 */
+    {PJ14, USART_3, 15},
+    {PJ15, USART_3, 16},
+    {PC0,  USART_3, 17},
+    {PC1,  USART_3, 18},
+    {PC2,  USART_3, 19},
+    {PC3,  USART_3, 20},
+    {PC4,  USART_3, 21},
+    {PC5,  USART_3, 22},
+
     {NC  , NC   , NC}
 };

--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/PeripheralPins.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/PeripheralPins.c	Fri Apr 28 14:04:18 2017 +0100
@@ -100,6 +100,37 @@
     {PF7,  I2C_0, 30},
     {PA0,  I2C_0, 31},
 
+    {PA7, I2C_1, 0},
+    {PA8, I2C_1, 1},
+    {PA9, I2C_1, 2},
+    {PI2, I2C_1, 3},
+    {PI3, I2C_1, 4},
+    {PB6, I2C_1, 5},
+    {PB7, I2C_1, 6},
+    {PB8, I2C_1, 7},
+    {PB9, I2C_1, 8},
+    {PB10, I2C_1, 9},
+    {PJ14, I2C_1, 10},
+    {PJ15, I2C_1, 11},
+    {PC0, I2C_1, 12},
+    {PC1, I2C_1, 13},
+    {PC2, I2C_1, 14},
+    {PC3, I2C_1, 15},
+    {PC4, I2C_1, 16},
+    {PC5, I2C_1, 17},
+    {PF8, I2C_1, 20},
+    {PF9, I2C_1, 21},
+    {PF10, I2C_1, 22},
+    {PF11, I2C_1, 23},
+    {PF12, I2C_1, 24},
+    {PF13, I2C_1, 25},
+    {PF14, I2C_1, 26},
+    {PF15, I2C_1, 27},
+    {PK0, I2C_1, 28},
+    {PK1, I2C_1, 29},
+    {PK2, I2C_1, 30},
+    {PA6, I2C_1, 31},
+
     {NC  , NC   , NC}
 };
 
@@ -139,7 +170,39 @@
     {PF6,  I2C_0, 30},
     {PF7,  I2C_0, 31},
 
+    {PA6, I2C_1, 0},
+    {PA7, I2C_1, 1},
+    {PA8, I2C_1, 2},
+    {PA9, I2C_1, 3},
+    {PI2, I2C_1, 4},
+    {PI3, I2C_1, 5},
+    {PB6, I2C_1, 6},
+    {PB7, I2C_1, 7},
+    {PB8, I2C_1, 8},
+    {PB9, I2C_1, 9},
+    {PB10, I2C_1, 10},
+    {PJ14, I2C_1, 11},
+    {PJ15, I2C_1, 12},
+    {PC0, I2C_1, 13},
+    {PC1, I2C_1, 14},
+    {PC2, I2C_1, 15},
+    {PC3, I2C_1, 16},
+    {PC4, I2C_1, 17},
+    {PC5, I2C_1, 18},
+    {PF8, I2C_1, 21},
+    {PF9, I2C_1, 22},
+    {PF10, I2C_1, 23},
+    {PF11, I2C_1, 24},
+    {PF12, I2C_1, 25},
+    {PF13, I2C_1, 26},
+    {PF14, I2C_1, 27},
+    {PF15, I2C_1, 28},
+    {PK0, I2C_1, 29},
+    {PK1, I2C_1, 30},
+    {PK2, I2C_1, 31},
+
     /* Not connected */
+
     {NC  , NC   , NC}
 };
 
@@ -220,6 +283,42 @@
     {PF6,  SPI_1, 30},
     {PF7,  SPI_1, 31},
 
+    /* USART2 */
+    {PA6,  SPI_2, 1},
+    {PA7,  SPI_2, 2},
+    {PA8,  SPI_2, 3},
+    {PA9,  SPI_2, 4},
+    {PI0,  SPI_2, 5},
+    {PI1,  SPI_2, 6},
+    {PI2,  SPI_2, 7},
+    {PI3,  SPI_2, 8},
+    {PB6,  SPI_2, 9},
+    {PB7,  SPI_2, 10},
+    {PB8,  SPI_2, 11},
+    {PB9,  SPI_2, 12},
+    {PB10, SPI_2, 13},
+    {PF8,  SPI_2, 21},
+    {PF9,  SPI_2, 22},
+    {PF10, SPI_2, 23},
+    {PF11, SPI_2, 24},
+    {PF12, SPI_2, 25},
+    {PF13, SPI_2, 26},
+    {PF14, SPI_2, 27},
+    {PF15, SPI_2, 28},
+    {PK0,  SPI_2, 29},
+    {PK1,  SPI_2, 30},
+    {PK2,  SPI_2, 31},
+
+    /* USART3 */
+    {PJ14, SPI_3, 16},
+    {PJ15, SPI_3, 17},
+    {PC0,  SPI_3, 18},
+    {PC1,  SPI_3, 19},
+    {PC2,  SPI_3, 20},
+    {PC3,  SPI_3, 21},
+    {PC4,  SPI_3, 22},
+    {PC5,  SPI_3, 23},
+
     {NC  , NC   , NC}
 };
 
@@ -262,6 +361,42 @@
     {PF7,  SPI_1, 30},
     {PA0,  SPI_1, 31},
 
+    /* USART2 */
+    {PA6,  SPI_2, 0},
+    {PA7,  SPI_2, 1},
+    {PA8,  SPI_2, 2},
+    {PA9,  SPI_2, 3},
+    {PI0,  SPI_2, 4},
+    {PI1,  SPI_2, 5},
+    {PI2,  SPI_2, 6},
+    {PI3,  SPI_2, 7},
+    {PB6,  SPI_2, 8},
+    {PB7,  SPI_2, 9},
+    {PB8,  SPI_2, 10},
+    {PB9,  SPI_2, 11},
+    {PB10, SPI_2, 12},
+    {PF8,  SPI_2, 20},
+    {PF9,  SPI_2, 21},
+    {PF10, SPI_2, 22},
+    {PF11, SPI_2, 23},
+    {PF12, SPI_2, 24},
+    {PF13, SPI_2, 25},
+    {PF14, SPI_2, 26},
+    {PF15, SPI_2, 27},
+    {PK0,  SPI_2, 28},
+    {PK1,  SPI_2, 29},
+    {PK2,  SPI_2, 30},
+
+    /* USART3 */
+    {PJ14, SPI_3, 15},
+    {PJ15, SPI_3, 16},
+    {PC0,  SPI_3, 17},
+    {PC1,  SPI_3, 18},
+    {PC2,  SPI_3, 19},
+    {PC3,  SPI_3, 20},
+    {PC4,  SPI_3, 21},
+    {PC5,  SPI_3, 22},
+
     {NC  , NC   , NC}
 };
 
@@ -305,6 +440,42 @@
     {PA0,  SPI_1, 30},
     {PA1,  SPI_1, 31},
 
+    /* USART2 */
+    {PA7,  SPI_2, 0},
+    {PA8,  SPI_2, 1},
+    {PA9,  SPI_2, 2},
+    {PI0,  SPI_2, 3},
+    {PI1,  SPI_2, 4},
+    {PI2,  SPI_2, 5},
+    {PI3,  SPI_2, 6},
+    {PB6,  SPI_2, 7},
+    {PB7,  SPI_2, 8},
+    {PB8,  SPI_2, 9},
+    {PB9,  SPI_2, 10},
+    {PB10, SPI_2, 11},
+    {PF8,  SPI_2, 19},
+    {PF9,  SPI_2, 20},
+    {PF10, SPI_2, 21},
+    {PF11, SPI_2, 22},
+    {PF12, SPI_2, 23},
+    {PF13, SPI_2, 24},
+    {PF14, SPI_2, 25},
+    {PF15, SPI_2, 26},
+    {PK0,  SPI_2, 27},
+    {PK1,  SPI_2, 28},
+    {PK2,  SPI_2, 29},
+    {PA6,  SPI_2, 31},
+
+    /* USART3 */
+    {PJ14, SPI_3, 14},
+    {PJ15, SPI_3, 15},
+    {PC0,  SPI_3, 16},
+    {PC1,  SPI_3, 17},
+    {PC2,  SPI_3, 18},
+    {PC3,  SPI_3, 19},
+    {PC4,  SPI_3, 20},
+    {PC5,  SPI_3, 21},
+
     {NC  , NC   , NC}
 };
 
@@ -346,6 +517,42 @@
     {PF6,  SPI_1, 27},
     {PF7,  SPI_1, 28},
 
+    /* USART2 */
+    {PA8,  SPI_2, 0},
+    {PA9,  SPI_2, 1},
+    {PI0,  SPI_2, 2},
+    {PI1,  SPI_2, 3},
+    {PI2,  SPI_2, 4},
+    {PI3,  SPI_2, 5},
+    {PB6,  SPI_2, 6},
+    {PB7,  SPI_2, 7},
+    {PB8,  SPI_2, 8},
+    {PB9,  SPI_2, 9},
+    {PB10, SPI_2, 10},
+    {PF8,  SPI_2, 18},
+    {PF9,  SPI_2, 19},
+    {PF10, SPI_2, 20},
+    {PF11, SPI_2, 21},
+    {PF12, SPI_2, 22},
+    {PF13, SPI_2, 23},
+    {PF14, SPI_2, 24},
+    {PF15, SPI_2, 25},
+    {PK0,  SPI_2, 26},
+    {PK1,  SPI_2, 27},
+    {PK2,  SPI_2, 28},
+    {PA6,  SPI_2, 30},
+    {PA7,  SPI_2, 31},
+
+    /* USART3 */
+    {PJ14, SPI_3, 13},
+    {PJ15, SPI_3, 14},
+    {PC0,  SPI_3, 15},
+    {PC1,  SPI_3, 16},
+    {PC2,  SPI_3, 17},
+    {PC3,  SPI_3, 18},
+    {PC4,  SPI_3, 19},
+    {PC5,  SPI_3, 20},
+
     {NC  , NC   , NC}
 };
 
@@ -385,6 +592,42 @@
     {PF6,  USART_1, 30},
     {PF7,  USART_1, 31},
 
+    /* USART2 */
+    {PA6,  USART_2, 1},
+    {PA7,  USART_2, 2},
+    {PA8,  USART_2, 3},
+    {PA9,  USART_2, 4},
+    {PI0,  USART_2, 5},
+    {PI1,  USART_2, 6},
+    {PI2,  USART_2, 7},
+    {PI3,  USART_2, 8},
+    {PB6,  USART_2, 9},
+    {PB7,  USART_2, 10},
+    {PB8,  USART_2, 11},
+    {PB9,  USART_2, 12},
+    {PB10, USART_2, 13},
+    {PF8,  USART_2, 21},
+    {PF9,  USART_2, 22},
+    {PF10, USART_2, 23},
+    {PF11, USART_2, 24},
+    {PF12, USART_2, 25},
+    {PF13, USART_2, 26},
+    {PF14, USART_2, 27},
+    {PF15, USART_2, 28},
+    {PK0,  USART_2, 29},
+    {PK1,  USART_2, 30},
+    {PK2,  USART_2, 31},
+
+    /* USART3 */
+    {PJ14, USART_3, 16},
+    {PJ15, USART_3, 17},
+    {PC0,  USART_3, 18},
+    {PC1,  USART_3, 19},
+    {PC2,  USART_3, 20},
+    {PC3,  USART_3, 21},
+    {PC4,  USART_3, 22},
+    {PC5,  USART_3, 23},
+
     {NC  , NC   , NC}
 };
 
@@ -423,5 +666,41 @@
     {PF6,  USART_1, 29},
     {PF7,  USART_1, 30},
 
+    /* USART2 */
+    {PA6,  USART_2, 0},
+    {PA7,  USART_2, 1},
+    {PA8,  USART_2, 2},
+    {PA9,  USART_2, 3},
+    {PI0,  USART_2, 4},
+    {PI1,  USART_2, 5},
+    {PI2,  USART_2, 6},
+    {PI3,  USART_2, 7},
+    {PB6,  USART_2, 8},
+    {PB7,  USART_2, 9},
+    {PB8,  USART_2, 10},
+    {PB9,  USART_2, 11},
+    {PB10, USART_2, 12},
+    {PF8,  USART_2, 20},
+    {PF9,  USART_2, 21},
+    {PF10, USART_2, 22},
+    {PF11, USART_2, 23},
+    {PF12, USART_2, 24},
+    {PF13, USART_2, 25},
+    {PF14, USART_2, 26},
+    {PF15, USART_2, 27},
+    {PK0,  USART_2, 28},
+    {PK1,  USART_2, 29},
+    {PK2,  USART_2, 30},
+
+    /* USART3 */
+    {PJ14, USART_3, 15},
+    {PJ15, USART_3, 16},
+    {PC0,  USART_3, 17},
+    {PC1,  USART_3, 18},
+    {PC2,  USART_3, 19},
+    {PC3,  USART_3, 20},
+    {PC4,  USART_3, 21},
+    {PC5,  USART_3, 22},
+
     {NC  , NC   , NC}
 };

--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/objects.h	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/objects.h	Fri Apr 28 14:04:18 2017 +0100
@@ -59,6 +59,7 @@
 #if DEVICE_I2C
 struct i2c_s {
     I2C_TypeDef *i2c;
+    uint32_t location;
 #if DEVICE_I2C_ASYNCH
     uint32_t events;
     I2C_TransferSeq_TypeDef xfer;
@@ -116,7 +117,8 @@
 #if DEVICE_SPI
 struct spi_s {
     USART_TypeDef *spi;
-    int location;
+    uint32_t location;
+    uint32_t route;
     uint8_t bits;
     uint8_t master;
 #if DEVICE_SPI_ASYNCH

--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/i2c_api.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/i2c_api.c	Fri Apr 28 14:04:18 2017 +0100
@@ -121,11 +121,13 @@
     int loc = pinmap_merge(loc_sda, loc_scl);
     MBED_ASSERT(loc != NC);
     /* Set location */
+    obj->i2c.location = I2C_ROUTE_SDAPEN | I2C_ROUTE_SCLPEN | (loc << _I2C_ROUTE_LOCATION_SHIFT);
     obj->i2c.i2c->ROUTE = I2C_ROUTE_SDAPEN | I2C_ROUTE_SCLPEN | (loc << _I2C_ROUTE_LOCATION_SHIFT);
 #else
     obj->i2c.i2c->ROUTEPEN  = I2C_ROUTEPEN_SDAPEN | I2C_ROUTEPEN_SCLPEN;
-    obj->i2c.i2c->ROUTELOC0 = (pin_location(sda, PinMap_I2C_SDA) << _I2C_ROUTELOC0_SDALOC_SHIFT) |
-                              (pin_location(scl, PinMap_I2C_SCL) << _I2C_ROUTELOC0_SCLLOC_SHIFT);
+    obj->i2c.location = (pin_location(sda, PinMap_I2C_SDA) << _I2C_ROUTELOC0_SDALOC_SHIFT) |
+                        (pin_location(scl, PinMap_I2C_SCL) << _I2C_ROUTELOC0_SCLLOC_SHIFT);
+    obj->i2c.i2c->ROUTELOC0 = obj->i2c.location;
 #endif
 
     /* Set up the pins for I2C use */
@@ -215,6 +217,13 @@
 {
     I2C_TypeDef *i2c = obj->i2c.i2c;
 
+    /* Restore pin configuration in case we changed I2C object */
+#ifdef I2C_ROUTE_SDAPEN
+    obj->i2c.i2c->ROUTE = obj->i2c.location;
+#else
+    obj->i2c.i2c->ROUTELOC0 = obj->i2c.location;
+#endif
+
     /* Ensure buffers are empty */
     i2c->CMD = I2C_CMD_CLEARPC | I2C_CMD_CLEARTX;
     if (i2c->IF & I2C_IF_RXDATAV) {
@@ -410,7 +419,6 @@
         data[count] = i2c_byte_read(obj, 0);
     }
 
-
     return count;
 
 }
@@ -459,6 +467,12 @@
     if((tx_length == 0) && (rx_length == 0)) return;
     // For now, we are assuming a solely interrupt-driven implementation.
 
+#ifdef I2C_ROUTE_SDAPEN
+    obj->i2c.i2c->ROUTE = obj->i2c.location;
+#else
+    obj->i2c.i2c->ROUTELOC0 = obj->i2c.location;
+#endif
+
     // Store transfer config
     obj->i2c.xfer.addr = address;
 

--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c	Fri Apr 28 14:04:18 2017 +0100
@@ -131,7 +131,7 @@
         return true;
     }
 #else
-    if(PWM_TIMER->ROUTE & (TIMER_ROUTE_CC0PEN | TIMER_ROUTE_CC1PEN | TIMER_ROUTE_CC2PEN)) {
+    if (!(PWM_TIMER->ROUTE & (TIMER_ROUTE_CC0PEN | TIMER_ROUTE_CC1PEN | TIMER_ROUTE_CC2PEN))) {
         return true;
     }
 #endif
@@ -210,10 +210,11 @@
 #else
     // On P1, the route location is statically defined for the entire timer.
     PWM_TIMER->ROUTE &= ~_TIMER_ROUTE_LOCATION_MASK;
-if(pwmout_all_inactive()) {
+    // Make sure the route location is not overwritten
+    if(pwmout_all_inactive()) {
         PWM_TIMER->ROUTE |= pinmap_find_function(pin,PinMap_PWM) << _TIMER_ROUTE_LOCATION_SHIFT;
     } else {
-        MBED_ASSERT((pinmap_find_function(pin,PinMap_PWM) << _TIMER_ROUTE_LOCATION_SHIFT) == (PWM_TIMER->ROUTE & _TIMER_ROUTE_LOCATION_MASK));
+        MBED_ASSERT(PWM_TIMER->ROUTE & _TIMER_ROUTE_LOCATION_MASK == pinmap_find_function(pin,PinMap_PWM) << _TIMER_ROUTE_LOCATION_SHIFT);
     }
 #endif
 

--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c	Fri Apr 28 14:04:18 2017 +0100
@@ -213,10 +213,12 @@
         obj->spi.spi->ROUTELOC0 &= ~_USART_ROUTELOC0_CSLOC_MASK;
         obj->spi.spi->ROUTELOC0 |= pin_location(cs, PinMap_SPI_MOSI)<<_USART_ROUTELOC0_CSLOC_SHIFT;
     }
+    obj->spi.location = obj->spi.spi->ROUTELOC0;
+    obj->spi.route = route;
     obj->spi.spi->ROUTEPEN = route;
 }
 #else
-    uint32_t route = USART_ROUTE_CLKPEN | (obj->spi.location << _USART_ROUTE_LOCATION_SHIFT);
+    uint32_t route = USART_ROUTE_CLKPEN;
 
     if (mosi != NC) {
         route |= USART_ROUTE_TXPEN;
@@ -227,7 +229,9 @@
     if (!obj->spi.master) {
         route |= USART_ROUTE_CSPEN;
     }
+    route |= obj->spi.location << _USART_ROUTE_LOCATION_SHIFT;
     obj->spi.spi->ROUTE = route;
+    obj->spi.route = route;
 }
 #endif
 void spi_enable(spi_t *obj, uint8_t enable)
@@ -324,14 +328,6 @@
         default:
             clockMode = usartClockMode0;
     }
-
-    //save state
-#ifdef _USART_ROUTEPEN_RESETVALUE
-    uint32_t route = obj->spi.spi->ROUTEPEN;
-    uint32_t loc = obj->spi.spi->ROUTELOC0;
-#else
-    uint32_t route = obj->spi.spi->ROUTE;
-#endif
     uint32_t iflags = obj->spi.spi->IEN;
     bool enabled = (obj->spi.spi->STATUS & (USART_STATUS_RXENS | USART_STATUS_TXENS)) != 0;
 
@@ -339,10 +335,10 @@
 
     //restore state
 #ifdef _USART_ROUTEPEN_RESETVALUE
-    obj->spi.spi->ROUTEPEN = route;
-    obj->spi.spi->ROUTELOC0 = loc;
+    obj->spi.spi->ROUTEPEN = obj->spi.route;
+    obj->spi.spi->ROUTELOC0 = obj->spi.location;
 #else
-    obj->spi.spi->ROUTE = route;
+    obj->spi.spi->ROUTE = obj->spi.route;
 #endif
     obj->spi.spi->IEN = iflags;
 

--- a/targets/targets.json	Wed Apr 12 16:21:43 2017 +0100
+++ b/targets/targets.json	Fri Apr 28 14:04:18 2017 +0100
@@ -1340,13 +1340,21 @@
         "default_toolchain": "ARM",
         "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
         "extra_labels": ["STM", "STM32F4", "STM32F437", "STM32F437VG", "STM32F437xx", "STM32F437xG"],
-        "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2", "RTC_LSI=1"],
+        "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2", "RTC_LSI=1", "HSE_VALUE=12000000"],
         "inherits": ["Target"],
         "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "RTC", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
-        "features": ["LWIP"],        
-        "release_versions": ["5"],
+        "features": ["LWIP"],
+        "public": false,
         "device_name": "STM32F437VG"
-        },
+    },
+    "UBLOX_C030_U201": {
+        "inherits": ["UBLOX_C030"],
+        "release_versions": ["5"]
+    },
+    "UBLOX_C030_N211": {
+        "inherits": ["UBLOX_C030"],
+        "release_versions": ["5"]
+    },
     "NZ32_SC151": {
         "inherits": ["Target"],
         "core": "Cortex-M3",
@@ -2724,14 +2732,15 @@
     "NUMAKER_PFM_NUC472": {
         "core": "Cortex-M4F",
         "default_toolchain": "ARM",
-        "extra_labels": ["NUVOTON", "NUC472", "NU_XRAM_SUPPORTED"],
+        "extra_labels": ["NUVOTON", "NUC472", "NU_XRAM_SUPPORTED", "FLASH_CMSIS_ALGO"],
         "is_disk_virtual": true,
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
         "inherits": ["Target"],
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "TRNG", "CAN"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "TRNG", "CAN", "FLASH"],
         "features": ["LWIP"],
         "release_versions": ["5"],
-        "device_name": "NUC472HI8AE"
+        "device_name": "NUC472HI8AE",
+        "bootloader_supported": true    
     },
     "NCS36510": {
         "inherits": ["Target"],
@@ -2772,14 +2781,15 @@
     "NUMAKER_PFM_M453": {
         "core": "Cortex-M4F",
         "default_toolchain": "ARM",
-        "extra_labels": ["NUVOTON", "M451", "NUMAKER_PFM_M453"],
+        "extra_labels": ["NUVOTON", "M451", "NUMAKER_PFM_M453", "FLASH_CMSIS_ALGO"],
         "is_disk_virtual": true,
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
         "inherits": ["Target"],
         "progen": {"target": "numaker-pfm-m453"},
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "CAN"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "CAN", "FLASH"],
         "release_versions": ["2", "5"],
-        "device_name": "M453VG6AE"
+        "device_name": "M453VG6AE",
+        "bootloader_supported": true    
     },
     "HI2110": {
         "inherits": ["Target"],