bernard borredon / sram23x

SPI SRAM 23X library

sram23x.cpp@0:bdd299c0e8e6, 2012-07-14 (annotated)

Committer:
bborredon
Date:
Sat Jul 14 08:23:30 2012 +0000
Revision:
0:bdd299c0e8e6
[mbed] converted /SramSpi/sram23x

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bborredon 0:bdd299c0e8e6 1 /***********************************************************
bborredon 0:bdd299c0e8e6 2 Author: Bernard Borredon
bborredon 0:bdd299c0e8e6 3 Date: 27 december 2011
bborredon 0:bdd299c0e8e6 4 Version: 1.0
bborredon 0:bdd299c0e8e6 5 ************************************************************/
bborredon 0:bdd299c0e8e6 6 #include "sram23x.h"
bborredon 0:bdd299c0e8e6 7
bborredon 0:bdd299c0e8e6 8 #define HIGH(x) (x >> 8)
bborredon 0:bdd299c0e8e6 9 #define LOW(x) (x & 0xff)
bborredon 0:bdd299c0e8e6 10
bborredon 0:bdd299c0e8e6 11 SRAM23X::SRAM23X(PinName mosi, PinName miso, PinName sclk, PinName cs, TypeSram type) : _spi(mosi, miso, sclk)
bborredon 0:bdd299c0e8e6 12 {
bborredon 0:bdd299c0e8e6 13
bborredon 0:bdd299c0e8e6 14 _errnum = SRAM23X_NoError;
bborredon 0:bdd299c0e8e6 15 _type = type;
bborredon 0:bdd299c0e8e6 16 _cs = new DigitalOut(cs);
bborredon 0:bdd299c0e8e6 17 if(_cs == NULL)
bborredon 0:bdd299c0e8e6 18 _errnum = SRAM23X_CsError;
bborredon 0:bdd299c0e8e6 19
bborredon 0:bdd299c0e8e6 20 // Don't select chip
bborredon 0:bdd299c0e8e6 21 deselect();
bborredon 0:bdd299c0e8e6 22
bborredon 0:bdd299c0e8e6 23 // Size in bytes
bborredon 0:bdd299c0e8e6 24 _size = _type;
bborredon 0:bdd299c0e8e6 25
bborredon 0:bdd299c0e8e6 26 // Set SPI frequency
bborredon 0:bdd299c0e8e6 27 _spi.frequency(10000000);
bborredon 0:bdd299c0e8e6 28
bborredon 0:bdd299c0e8e6 29 // Set format
bborredon 0:bdd299c0e8e6 30 _spi.format(8,0);
bborredon 0:bdd299c0e8e6 31
bborredon 0:bdd299c0e8e6 32 // Mode sequential
bborredon 0:bdd299c0e8e6 33 select();
bborredon 0:bdd299c0e8e6 34 writeStatus(SRAM23X_SEQ);
bborredon 0:bdd299c0e8e6 35 deselect();
bborredon 0:bdd299c0e8e6 36 }
bborredon 0:bdd299c0e8e6 37
bborredon 0:bdd299c0e8e6 38 // Initialization
bborredon 0:bdd299c0e8e6 39 uint8_t SRAM23X::init(uint16_t address, uint16_t size, uint8_t mode)
bborredon 0:bdd299c0e8e6 40 {
bborredon 0:bdd299c0e8e6 41
bborredon 0:bdd299c0e8e6 42 // Check error
bborredon 0:bdd299c0e8e6 43 if(_errnum)
bborredon 0:bdd299c0e8e6 44 return(_errnum);
bborredon 0:bdd299c0e8e6 45
bborredon 0:bdd299c0e8e6 46 // Check address
bborredon 0:bdd299c0e8e6 47 if(!checkAddress(address)) {
bborredon 0:bdd299c0e8e6 48 _errnum = SRAM23X_OutOfRange;
bborredon 0:bdd299c0e8e6 49 return(_errnum);
bborredon 0:bdd299c0e8e6 50 }
bborredon 0:bdd299c0e8e6 51
bborredon 0:bdd299c0e8e6 52 // Check address
bborredon 0:bdd299c0e8e6 53 if(!checkAddress(address + size - 1)) {
bborredon 0:bdd299c0e8e6 54 _errnum = SRAM23X_OutOfRange;
bborredon 0:bdd299c0e8e6 55 return(_errnum);
bborredon 0:bdd299c0e8e6 56 }
bborredon 0:bdd299c0e8e6 57
bborredon 0:bdd299c0e8e6 58 // No error
bborredon 0:bdd299c0e8e6 59 _errnum = SRAM23X_NoError;
bborredon 0:bdd299c0e8e6 60
bborredon 0:bdd299c0e8e6 61 select();
bborredon 0:bdd299c0e8e6 62 // Acces instruction
bborredon 0:bdd299c0e8e6 63 _spi.write(mode);
bborredon 0:bdd299c0e8e6 64
bborredon 0:bdd299c0e8e6 65 // High address part
bborredon 0:bdd299c0e8e6 66 _spi.write(HIGH(address));
bborredon 0:bdd299c0e8e6 67
bborredon 0:bdd299c0e8e6 68 // Low address part
bborredon 0:bdd299c0e8e6 69 _spi.write(LOW(address));
bborredon 0:bdd299c0e8e6 70
bborredon 0:bdd299c0e8e6 71 return(_errnum);
bborredon 0:bdd299c0e8e6 72 }
bborredon 0:bdd299c0e8e6 73
bborredon 0:bdd299c0e8e6 74 // Sequential read bytes
bborredon 0:bdd299c0e8e6 75 void SRAM23X::read(uint16_t address, int8_t *data, uint16_t size)
bborredon 0:bdd299c0e8e6 76 {
bborredon 0:bdd299c0e8e6 77 uint8_t ret;
bborredon 0:bdd299c0e8e6 78 uint16_t i;
bborredon 0:bdd299c0e8e6 79
bborredon 0:bdd299c0e8e6 80 ret = init(address,size,SRAM23X_READ);
bborredon 0:bdd299c0e8e6 81 if(ret != 0) {
bborredon 0:bdd299c0e8e6 82 // Deselect chip
bborredon 0:bdd299c0e8e6 83 deselect();
bborredon 0:bdd299c0e8e6 84 return;
bborredon 0:bdd299c0e8e6 85 }
bborredon 0:bdd299c0e8e6 86
bborredon 0:bdd299c0e8e6 87 // Datas
bborredon 0:bdd299c0e8e6 88 for(i = 0;i < size;i++) {
bborredon 0:bdd299c0e8e6 89 data[i] = _spi.write(0);
bborredon 0:bdd299c0e8e6 90 }
bborredon 0:bdd299c0e8e6 91
bborredon 0:bdd299c0e8e6 92 // Deselect chip
bborredon 0:bdd299c0e8e6 93 deselect();
bborredon 0:bdd299c0e8e6 94
bborredon 0:bdd299c0e8e6 95 }
bborredon 0:bdd299c0e8e6 96
bborredon 0:bdd299c0e8e6 97 // Sequential read anything
bborredon 0:bdd299c0e8e6 98 void SRAM23X::read(uint16_t address, void *data, uint16_t size)
bborredon 0:bdd299c0e8e6 99 {
bborredon 0:bdd299c0e8e6 100 int8_t *cmd = NULL;
bborredon 0:bdd299c0e8e6 101
bborredon 0:bdd299c0e8e6 102 cmd = (int8_t *)malloc(size);
bborredon 0:bdd299c0e8e6 103 if(cmd == NULL) {
bborredon 0:bdd299c0e8e6 104 _errnum = SRAM23X_MallocError;
bborredon 0:bdd299c0e8e6 105 return;
bborredon 0:bdd299c0e8e6 106 }
bborredon 0:bdd299c0e8e6 107
bborredon 0:bdd299c0e8e6 108 read(address,cmd,size);
bborredon 0:bdd299c0e8e6 109
bborredon 0:bdd299c0e8e6 110 memcpy(data,cmd,size);
bborredon 0:bdd299c0e8e6 111
bborredon 0:bdd299c0e8e6 112 free(cmd);
bborredon 0:bdd299c0e8e6 113 }
bborredon 0:bdd299c0e8e6 114
bborredon 0:bdd299c0e8e6 115 // Sequential read int16
bborredon 0:bdd299c0e8e6 116 void SRAM23X::read(uint16_t address, int16_t *data, uint16_t size)
bborredon 0:bdd299c0e8e6 117 {
bborredon 0:bdd299c0e8e6 118 uint16_t i,j;
bborredon 0:bdd299c0e8e6 119 uint8_t cmd[2];
bborredon 0:bdd299c0e8e6 120 uint8_t ret;
bborredon 0:bdd299c0e8e6 121
bborredon 0:bdd299c0e8e6 122 ret = init(address,size,SRAM23X_READ);
bborredon 0:bdd299c0e8e6 123 if(ret != 0) {
bborredon 0:bdd299c0e8e6 124 // Deselect chip
bborredon 0:bdd299c0e8e6 125 deselect();
bborredon 0:bdd299c0e8e6 126 return;
bborredon 0:bdd299c0e8e6 127 }
bborredon 0:bdd299c0e8e6 128
bborredon 0:bdd299c0e8e6 129 // Datas
bborredon 0:bdd299c0e8e6 130 for(i = 0;i < size / 2;i = i + 2) {
bborredon 0:bdd299c0e8e6 131 for(j = 0;j < 2;j++)
bborredon 0:bdd299c0e8e6 132 cmd[j] = _spi.write(0);
bborredon 0:bdd299c0e8e6 133 memcpy(&data[i],cmd,2);
bborredon 0:bdd299c0e8e6 134 }
bborredon 0:bdd299c0e8e6 135
bborredon 0:bdd299c0e8e6 136 // Deselect chip
bborredon 0:bdd299c0e8e6 137 deselect();
bborredon 0:bdd299c0e8e6 138
bborredon 0:bdd299c0e8e6 139 }
bborredon 0:bdd299c0e8e6 140
bborredon 0:bdd299c0e8e6 141 // Sequential read int32
bborredon 0:bdd299c0e8e6 142 void SRAM23X::read(uint16_t address, int32_t *data, uint16_t size)
bborredon 0:bdd299c0e8e6 143 {
bborredon 0:bdd299c0e8e6 144 uint16_t i,j;
bborredon 0:bdd299c0e8e6 145 uint8_t cmd[4];
bborredon 0:bdd299c0e8e6 146 uint8_t ret;
bborredon 0:bdd299c0e8e6 147
bborredon 0:bdd299c0e8e6 148 ret = init(address,size,SRAM23X_READ);
bborredon 0:bdd299c0e8e6 149 if(ret != 0) {
bborredon 0:bdd299c0e8e6 150 // Deselect chip
bborredon 0:bdd299c0e8e6 151 deselect();
bborredon 0:bdd299c0e8e6 152 return;
bborredon 0:bdd299c0e8e6 153 }
bborredon 0:bdd299c0e8e6 154
bborredon 0:bdd299c0e8e6 155 // Datas
bborredon 0:bdd299c0e8e6 156 for(i = 0;i < size / 4;i = i + 4) {
bborredon 0:bdd299c0e8e6 157 for(j = 0;j < 4;j++)
bborredon 0:bdd299c0e8e6 158 cmd[j] = _spi.write(0);
bborredon 0:bdd299c0e8e6 159 memcpy(&data[i],cmd,4);
bborredon 0:bdd299c0e8e6 160 }
bborredon 0:bdd299c0e8e6 161
bborredon 0:bdd299c0e8e6 162 // Deselect chip
bborredon 0:bdd299c0e8e6 163 deselect();
bborredon 0:bdd299c0e8e6 164
bborredon 0:bdd299c0e8e6 165 }
bborredon 0:bdd299c0e8e6 166
bborredon 0:bdd299c0e8e6 167 // Sequential read float
bborredon 0:bdd299c0e8e6 168 void SRAM23X::read(uint16_t address, float *data, uint16_t size)
bborredon 0:bdd299c0e8e6 169 {
bborredon 0:bdd299c0e8e6 170 uint16_t i,j;
bborredon 0:bdd299c0e8e6 171 uint8_t cmd[4];
bborredon 0:bdd299c0e8e6 172 uint8_t ret;
bborredon 0:bdd299c0e8e6 173
bborredon 0:bdd299c0e8e6 174 ret = init(address,size,SRAM23X_READ);
bborredon 0:bdd299c0e8e6 175 if(ret != 0) {
bborredon 0:bdd299c0e8e6 176 // Deselect chip
bborredon 0:bdd299c0e8e6 177 deselect();
bborredon 0:bdd299c0e8e6 178 return;
bborredon 0:bdd299c0e8e6 179 }
bborredon 0:bdd299c0e8e6 180
bborredon 0:bdd299c0e8e6 181 // Datas
bborredon 0:bdd299c0e8e6 182 for(i = 0;i < size / 4;i = i + 4) {
bborredon 0:bdd299c0e8e6 183 for(j = 0;j < 4;j++)
bborredon 0:bdd299c0e8e6 184 cmd[j] = _spi.write(0);
bborredon 0:bdd299c0e8e6 185 memcpy(&data[i],cmd,4);
bborredon 0:bdd299c0e8e6 186 }
bborredon 0:bdd299c0e8e6 187
bborredon 0:bdd299c0e8e6 188 // Deselect chip
bborredon 0:bdd299c0e8e6 189 deselect();
bborredon 0:bdd299c0e8e6 190
bborredon 0:bdd299c0e8e6 191 }
bborredon 0:bdd299c0e8e6 192
bborredon 0:bdd299c0e8e6 193 // Sequential write bytes
bborredon 0:bdd299c0e8e6 194 void SRAM23X::write(uint16_t address, int8_t *data, uint16_t size)
bborredon 0:bdd299c0e8e6 195 {
bborredon 0:bdd299c0e8e6 196 uint16_t i;
bborredon 0:bdd299c0e8e6 197 uint8_t ret;
bborredon 0:bdd299c0e8e6 198
bborredon 0:bdd299c0e8e6 199 ret = init(address,size,SRAM23X_WRITE);
bborredon 0:bdd299c0e8e6 200 if(ret != 0) {
bborredon 0:bdd299c0e8e6 201 // Deselect chip
bborredon 0:bdd299c0e8e6 202 deselect();
bborredon 0:bdd299c0e8e6 203 return;
bborredon 0:bdd299c0e8e6 204 }
bborredon 0:bdd299c0e8e6 205
bborredon 0:bdd299c0e8e6 206 // Datas
bborredon 0:bdd299c0e8e6 207 for(i = 0;i < size;i++) {
bborredon 0:bdd299c0e8e6 208 _spi.write(data[i]);
bborredon 0:bdd299c0e8e6 209 }
bborredon 0:bdd299c0e8e6 210
bborredon 0:bdd299c0e8e6 211 // Deselect chip
bborredon 0:bdd299c0e8e6 212 deselect();
bborredon 0:bdd299c0e8e6 213
bborredon 0:bdd299c0e8e6 214 }
bborredon 0:bdd299c0e8e6 215
bborredon 0:bdd299c0e8e6 216 // Sequential write anything
bborredon 0:bdd299c0e8e6 217 void SRAM23X::write(uint16_t address, void *data, uint16_t size)
bborredon 0:bdd299c0e8e6 218 {
bborredon 0:bdd299c0e8e6 219 int8_t *cmd = NULL;
bborredon 0:bdd299c0e8e6 220
bborredon 0:bdd299c0e8e6 221 cmd = (int8_t *)malloc(size);
bborredon 0:bdd299c0e8e6 222 if(cmd == NULL) {
bborredon 0:bdd299c0e8e6 223 _errnum = SRAM23X_MallocError;
bborredon 0:bdd299c0e8e6 224 return;
bborredon 0:bdd299c0e8e6 225 }
bborredon 0:bdd299c0e8e6 226
bborredon 0:bdd299c0e8e6 227 memcpy(cmd,data,size);
bborredon 0:bdd299c0e8e6 228
bborredon 0:bdd299c0e8e6 229 write(address,cmd,size);
bborredon 0:bdd299c0e8e6 230
bborredon 0:bdd299c0e8e6 231 free(cmd);
bborredon 0:bdd299c0e8e6 232 }
bborredon 0:bdd299c0e8e6 233
bborredon 0:bdd299c0e8e6 234 // Sequential write int16
bborredon 0:bdd299c0e8e6 235 void SRAM23X::write(uint16_t address, int16_t *data, uint16_t size)
bborredon 0:bdd299c0e8e6 236 {
bborredon 0:bdd299c0e8e6 237 uint16_t i,j;
bborredon 0:bdd299c0e8e6 238 uint8_t ret;
bborredon 0:bdd299c0e8e6 239 uint8_t cmd[2];
bborredon 0:bdd299c0e8e6 240
bborredon 0:bdd299c0e8e6 241 ret = init(address,size,SRAM23X_WRITE);
bborredon 0:bdd299c0e8e6 242 if(ret != 0) {
bborredon 0:bdd299c0e8e6 243 // Deselect chip
bborredon 0:bdd299c0e8e6 244 deselect();
bborredon 0:bdd299c0e8e6 245 return;
bborredon 0:bdd299c0e8e6 246 }
bborredon 0:bdd299c0e8e6 247
bborredon 0:bdd299c0e8e6 248 // Datas
bborredon 0:bdd299c0e8e6 249 for(i = 0;i < size / 2;i = i + 2) {
bborredon 0:bdd299c0e8e6 250 memcpy(cmd,&data[i],2);
bborredon 0:bdd299c0e8e6 251 for(j = 0;j < 2;j++)
bborredon 0:bdd299c0e8e6 252 _spi.write(cmd[j]);
bborredon 0:bdd299c0e8e6 253 }
bborredon 0:bdd299c0e8e6 254
bborredon 0:bdd299c0e8e6 255 // Deselect chip
bborredon 0:bdd299c0e8e6 256 deselect();
bborredon 0:bdd299c0e8e6 257
bborredon 0:bdd299c0e8e6 258 }
bborredon 0:bdd299c0e8e6 259
bborredon 0:bdd299c0e8e6 260 // Sequential write int32
bborredon 0:bdd299c0e8e6 261 void SRAM23X::write(uint16_t address, int32_t *data, uint16_t size)
bborredon 0:bdd299c0e8e6 262 {
bborredon 0:bdd299c0e8e6 263 uint16_t i,j;
bborredon 0:bdd299c0e8e6 264 uint8_t ret;
bborredon 0:bdd299c0e8e6 265 uint8_t cmd[4];
bborredon 0:bdd299c0e8e6 266
bborredon 0:bdd299c0e8e6 267 ret = init(address,size,SRAM23X_WRITE);
bborredon 0:bdd299c0e8e6 268 if(ret != 0) {
bborredon 0:bdd299c0e8e6 269 // Deselect chip
bborredon 0:bdd299c0e8e6 270 deselect();
bborredon 0:bdd299c0e8e6 271 return;
bborredon 0:bdd299c0e8e6 272 }
bborredon 0:bdd299c0e8e6 273
bborredon 0:bdd299c0e8e6 274 // Datas
bborredon 0:bdd299c0e8e6 275 for(i = 0;i < size / 4;i = i + 4) {
bborredon 0:bdd299c0e8e6 276 memcpy(cmd,&data[i],4);
bborredon 0:bdd299c0e8e6 277 for(j = 0;j < 4;j++)
bborredon 0:bdd299c0e8e6 278 _spi.write(cmd[j]);
bborredon 0:bdd299c0e8e6 279 }
bborredon 0:bdd299c0e8e6 280
bborredon 0:bdd299c0e8e6 281 // Deselect chip
bborredon 0:bdd299c0e8e6 282 deselect();
bborredon 0:bdd299c0e8e6 283
bborredon 0:bdd299c0e8e6 284 }
bborredon 0:bdd299c0e8e6 285
bborredon 0:bdd299c0e8e6 286 // Sequential write float
bborredon 0:bdd299c0e8e6 287 void SRAM23X::write(uint16_t address, float *data, uint16_t size)
bborredon 0:bdd299c0e8e6 288 {
bborredon 0:bdd299c0e8e6 289 uint16_t i,j;
bborredon 0:bdd299c0e8e6 290 uint8_t ret;
bborredon 0:bdd299c0e8e6 291 uint8_t cmd[4];
bborredon 0:bdd299c0e8e6 292
bborredon 0:bdd299c0e8e6 293 ret = init(address,size,SRAM23X_WRITE);
bborredon 0:bdd299c0e8e6 294 if(ret != 0) {
bborredon 0:bdd299c0e8e6 295 // Deselect chip
bborredon 0:bdd299c0e8e6 296 deselect();
bborredon 0:bdd299c0e8e6 297 return;
bborredon 0:bdd299c0e8e6 298 }
bborredon 0:bdd299c0e8e6 299
bborredon 0:bdd299c0e8e6 300 // Datas
bborredon 0:bdd299c0e8e6 301 for(i = 0;i < size / 4;i = i + 4) {
bborredon 0:bdd299c0e8e6 302 memcpy(cmd,&data[i],4);
bborredon 0:bdd299c0e8e6 303 for(j = 0;j < 4;j++)
bborredon 0:bdd299c0e8e6 304 _spi.write(cmd[j]);
bborredon 0:bdd299c0e8e6 305 }
bborredon 0:bdd299c0e8e6 306
bborredon 0:bdd299c0e8e6 307 // Deselect chip
bborredon 0:bdd299c0e8e6 308 deselect();
bborredon 0:bdd299c0e8e6 309
bborredon 0:bdd299c0e8e6 310 }
bborredon 0:bdd299c0e8e6 311
bborredon 0:bdd299c0e8e6 312 // Get SRAM size in bytes
bborredon 0:bdd299c0e8e6 313 uint16_t SRAM23X::getSize(void)
bborredon 0:bdd299c0e8e6 314 {
bborredon 0:bdd299c0e8e6 315 return(_size);
bborredon 0:bdd299c0e8e6 316 }
bborredon 0:bdd299c0e8e6 317
bborredon 0:bdd299c0e8e6 318 // Select chip
bborredon 0:bdd299c0e8e6 319 void SRAM23X::select(void)
bborredon 0:bdd299c0e8e6 320 {
bborredon 0:bdd299c0e8e6 321 _cs->write(0);
bborredon 0:bdd299c0e8e6 322 wait_us(10.0);
bborredon 0:bdd299c0e8e6 323 }
bborredon 0:bdd299c0e8e6 324
bborredon 0:bdd299c0e8e6 325 // Deselect chip
bborredon 0:bdd299c0e8e6 326 void SRAM23X::deselect(void)
bborredon 0:bdd299c0e8e6 327 {
bborredon 0:bdd299c0e8e6 328
bborredon 0:bdd299c0e8e6 329 wait_us(10.0);
bborredon 0:bdd299c0e8e6 330 _cs->write(1);
bborredon 0:bdd299c0e8e6 331 }
bborredon 0:bdd299c0e8e6 332
bborredon 0:bdd299c0e8e6 333 // Read status register
bborredon 0:bdd299c0e8e6 334 uint8_t SRAM23X::readStatus(void)
bborredon 0:bdd299c0e8e6 335 {
bborredon 0:bdd299c0e8e6 336 uint8_t ret;
bborredon 0:bdd299c0e8e6 337
bborredon 0:bdd299c0e8e6 338 select();
bborredon 0:bdd299c0e8e6 339 _spi.write(SRAM23X_RDSR);
bborredon 0:bdd299c0e8e6 340 ret = _spi.write(0);
bborredon 0:bdd299c0e8e6 341 deselect();
bborredon 0:bdd299c0e8e6 342
bborredon 0:bdd299c0e8e6 343 return(ret);
bborredon 0:bdd299c0e8e6 344 }
bborredon 0:bdd299c0e8e6 345
bborredon 0:bdd299c0e8e6 346 // Write status register
bborredon 0:bdd299c0e8e6 347 void SRAM23X::writeStatus(uint8_t status)
bborredon 0:bdd299c0e8e6 348 {
bborredon 0:bdd299c0e8e6 349
bborredon 0:bdd299c0e8e6 350 select();
bborredon 0:bdd299c0e8e6 351 _spi.write(SRAM23X_WRSR);
bborredon 0:bdd299c0e8e6 352 _spi.write(status);
bborredon 0:bdd299c0e8e6 353 deselect();
bborredon 0:bdd299c0e8e6 354 }
bborredon 0:bdd299c0e8e6 355
bborredon 0:bdd299c0e8e6 356 // Check address
bborredon 0:bdd299c0e8e6 357 bool SRAM23X::checkAddress(uint16_t address)
bborredon 0:bdd299c0e8e6 358 {
bborredon 0:bdd299c0e8e6 359 bool ret = true;
bborredon 0:bdd299c0e8e6 360
bborredon 0:bdd299c0e8e6 361 if(address >= _type)
bborredon 0:bdd299c0e8e6 362 ret = false;
bborredon 0:bdd299c0e8e6 363
bborredon 0:bdd299c0e8e6 364 return(ret);
bborredon 0:bdd299c0e8e6 365 }
bborredon 0:bdd299c0e8e6 366
bborredon 0:bdd299c0e8e6 367 // Get current error number
bborredon 0:bdd299c0e8e6 368 uint8_t SRAM23X::getError(void)
bborredon 0:bdd299c0e8e6 369 {
bborredon 0:bdd299c0e8e6 370 return(_errnum);
bborredon 0:bdd299c0e8e6 371 }