kao yi / Mbed 2 deprecated Boboobooov4

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Dependencies:   mbed-rtos mbed

Fork of Bov3 by kao yi

TFC.cpp@19:4869b10a962e, 2014-07-02 (annotated)

Committer:
backman
Date:
Wed Jul 02 03:23:07 2014 +0000
Revision:
19:4869b10a962e
wang

Who changed what in which revision?

UserRevisionLine numberNew contents of line
backman 19:4869b10a962e 1 #include "mbed.h"
backman 19:4869b10a962e 2 #include "TFC.h"
backman 19:4869b10a962e 3
backman 19:4869b10a962e 4 #define FTM1_CLK_PRESCALE 6 // Prescale Selector value - see comments in Status Control (SC) section for more details
backman 19:4869b10a962e 5 #define SERVO_DEFAULT_PERIOD (float)(.010) // Desired Frequency of PWM Signal - Here 50Hz => 20ms period
backman 19:4869b10a962e 6 #define TAOS_CLK_COUNT 200 // Number of cycles for CLK Signal on camera
backman 19:4869b10a962e 7
backman 19:4869b10a962e 8 // use these to dial in servo steering to your particular servo
backman 19:4869b10a962e 9 #define SERVO_MIN_PULSE_WIDTH_DEFAULT (float)(.0005) // The number here should be be *pulse width* in seconds to move servo to its left limit
backman 19:4869b10a962e 10 #define SERVO_MAX_PULSE_WIDTH_DEFAULT (float)(.002) // The number here should be be *pulse width* in seconds to move servo to its left limit
backman 19:4869b10a962e 11
backman 19:4869b10a962e 12
backman 19:4869b10a962e 13 #define FTM0_CLOCK (SystemCoreClock/2)
backman 19:4869b10a962e 14 #define FTM0_CLK_PRESCALE (0) // Prescale Selector value - see comments in Status Control (SC) section for more details
backman 19:4869b10a962e 15 #define FTM0_DEFAULT_SWITCHING_FREQUENCY (4000.0)
backman 19:4869b10a962e 16
backman 19:4869b10a962e 17 #define ADC_MAX_CODE (4095)
backman 19:4869b10a962e 18
backman 19:4869b10a962e 19 #define TAOS_CLK_HIGH PTE->PSOR = (1<<1)
backman 19:4869b10a962e 20 #define TAOS_CLK_LOW PTE->PCOR = (1<<1)
backman 19:4869b10a962e 21 #define TAOS_SI_HIGH PTD->PSOR = (1<<7)
backman 19:4869b10a962e 22 #define TAOS_SI_LOW PTD->PCOR = (1<<7)
backman 19:4869b10a962e 23
backman 19:4869b10a962e 24 #define ADC_STATE_INIT 0
backman 19:4869b10a962e 25 #define ADC_STATE_CAPTURE_POT_0 1
backman 19:4869b10a962e 26 #define ADC_STATE_CAPTURE_POT_1 2
backman 19:4869b10a962e 27 #define ADC_STATE_CAPTURE_BATTERY_LEVEL 3
backman 19:4869b10a962e 28 #define ADC_STATE_CAPTURE_LINE_SCAN 4
backman 19:4869b10a962e 29
backman 19:4869b10a962e 30
backman 19:4869b10a962e 31 #define TFC_POT_0_ADC_CHANNEL 13
backman 19:4869b10a962e 32 #define TFC_POT_1_ADC_CHANNEL 12
backman 19:4869b10a962e 33 #define TFC_BAT_SENSE_CHANNEL 4
backman 19:4869b10a962e 34 #define TFC_LINESCAN0_ADC_CHANNEL 6
backman 19:4869b10a962e 35 #define TFC_LINESCAN1_ADC_CHANNEL 7
backman 19:4869b10a962e 36
backman 19:4869b10a962e 37
backman 19:4869b10a962e 38 #define ADC0_irq_no 57
backman 19:4869b10a962e 39 #define ADC1_irq_no 58
backman 19:4869b10a962e 40
backman 19:4869b10a962e 41 #define ADC0_CHANA 19 // set to desired ADC0 channel trigger A
backman 19:4869b10a962e 42 #define ADC0_CHANB 20 // set to desired ADC0 channel trigger B
backman 19:4869b10a962e 43
backman 19:4869b10a962e 44 #define ADC1_CHANA 20 // set to desired ADC1 channel trigger A 20 defaults to potentiometer in TWRK60
backman 19:4869b10a962e 45 #define ADC1_CHANB 20 // set to desired ADC1 channel trigger B
backman 19:4869b10a962e 46
backman 19:4869b10a962e 47 #define ADC0_DLYA 0x2000 // ADC0 trigger A delay
backman 19:4869b10a962e 48 #define ADC0_DLYB 0x4000 // ADC0 trigger B delay
backman 19:4869b10a962e 49 #define ADC1_DLYA 0x6000 // ADC1 trigger A delay
backman 19:4869b10a962e 50 #define ADC1_DLYB 0x7fff // ADC1 trigger B delay
backman 19:4869b10a962e 51
backman 19:4869b10a962e 52
backman 19:4869b10a962e 53 #define ADC0A_DONE 0x01
backman 19:4869b10a962e 54 #define ADC0B_DONE 0x02
backman 19:4869b10a962e 55 #define ADC1A_DONE 0x04
backman 19:4869b10a962e 56 #define ADC1B_DONE 0x08
backman 19:4869b10a962e 57
backman 19:4869b10a962e 58
backman 19:4869b10a962e 59 // Bit shifting of bitfiled is already taken into account so
backman 19:4869b10a962e 60 // bitfiled values are always represented as relative to their position.
backman 19:4869b10a962e 61
backman 19:4869b10a962e 62 /************************* #Defines ******************************************/
backman 19:4869b10a962e 63
backman 19:4869b10a962e 64 #define A 0x0
backman 19:4869b10a962e 65 #define B 0x1
backman 19:4869b10a962e 66
backman 19:4869b10a962e 67 /////// NOTE: the following defines relate to the ADC register definitions
backman 19:4869b10a962e 68 /////// and the content follows the reference manual, using the same symbols.
backman 19:4869b10a962e 69
backman 19:4869b10a962e 70
backman 19:4869b10a962e 71 //// ADCSC1 (register)
backman 19:4869b10a962e 72
backman 19:4869b10a962e 73 // Conversion Complete (COCO) mask
backman 19:4869b10a962e 74 #define COCO_COMPLETE ADC_SC1_COCO_MASK
backman 19:4869b10a962e 75 #define COCO_NOT 0x00
backman 19:4869b10a962e 76
backman 19:4869b10a962e 77 // ADC interrupts: enabled, or disabled.
backman 19:4869b10a962e 78 #define AIEN_ON ADC_SC1_AIEN_MASK
backman 19:4869b10a962e 79 #define AIEN_OFF 0x00
backman 19:4869b10a962e 80
backman 19:4869b10a962e 81 // Differential or Single ended ADC input
backman 19:4869b10a962e 82 #define DIFF_SINGLE 0x00
backman 19:4869b10a962e 83 #define DIFF_DIFFERENTIAL ADC_SC1_DIFF_MASK
backman 19:4869b10a962e 84
backman 19:4869b10a962e 85 //// ADCCFG1
backman 19:4869b10a962e 86
backman 19:4869b10a962e 87 // Power setting of ADC
backman 19:4869b10a962e 88 #define ADLPC_LOW ADC_CFG1_ADLPC_MASK
backman 19:4869b10a962e 89 #define ADLPC_NORMAL 0x00
backman 19:4869b10a962e 90
backman 19:4869b10a962e 91 // Clock divisor
backman 19:4869b10a962e 92 #define ADIV_1 0x00
backman 19:4869b10a962e 93 #define ADIV_2 0x01
backman 19:4869b10a962e 94 #define ADIV_4 0x02
backman 19:4869b10a962e 95 #define ADIV_8 0x03
backman 19:4869b10a962e 96
backman 19:4869b10a962e 97 // Long samle time, or Short sample time
backman 19:4869b10a962e 98 #define ADLSMP_LONG ADC_CFG1_ADLSMP_MASK
backman 19:4869b10a962e 99 #define ADLSMP_SHORT 0x00
backman 19:4869b10a962e 100
backman 19:4869b10a962e 101 // How many bits for the conversion? 8, 12, 10, or 16 (single ended).
backman 19:4869b10a962e 102 #define MODE_8 0x00
backman 19:4869b10a962e 103 #define MODE_12 0x01
backman 19:4869b10a962e 104 #define MODE_10 0x02
backman 19:4869b10a962e 105 #define MODE_16 0x03
backman 19:4869b10a962e 106
backman 19:4869b10a962e 107
backman 19:4869b10a962e 108
backman 19:4869b10a962e 109 // ADC Input Clock Source choice? Bus clock, Bus clock/2, "altclk", or the
backman 19:4869b10a962e 110 // ADC's own asynchronous clock for less noise
backman 19:4869b10a962e 111 #define ADICLK_BUS 0x00
backman 19:4869b10a962e 112 #define ADICLK_BUS_2 0x01
backman 19:4869b10a962e 113 #define ADICLK_ALTCLK 0x02
backman 19:4869b10a962e 114 #define ADICLK_ADACK 0x03
backman 19:4869b10a962e 115
backman 19:4869b10a962e 116 //// ADCCFG2
backman 19:4869b10a962e 117
backman 19:4869b10a962e 118 // Select between B or A channels
backman 19:4869b10a962e 119 #define MUXSEL_ADCB ADC_CFG2_MUXSEL_MASK
backman 19:4869b10a962e 120 #define MUXSEL_ADCA 0x00
backman 19:4869b10a962e 121
backman 19:4869b10a962e 122 // Ansync clock output enable: enable, or disable the output of it
backman 19:4869b10a962e 123 #define ADACKEN_ENABLED ADC_CFG2_ADACKEN_MASK
backman 19:4869b10a962e 124 #define ADACKEN_DISABLED 0x00
backman 19:4869b10a962e 125
backman 19:4869b10a962e 126 // High speed or low speed conversion mode
backman 19:4869b10a962e 127 #define ADHSC_HISPEED ADC_CFG2_ADHSC_MASK
backman 19:4869b10a962e 128 #define ADHSC_NORMAL 0x00
backman 19:4869b10a962e 129
backman 19:4869b10a962e 130 // Long Sample Time selector: 20, 12, 6, or 2 extra clocks for a longer sample time
backman 19:4869b10a962e 131 #define ADLSTS_20 0x00
backman 19:4869b10a962e 132 #define ADLSTS_12 0x01
backman 19:4869b10a962e 133 #define ADLSTS_6 0x02
backman 19:4869b10a962e 134 #define ADLSTS_2 0x03
backman 19:4869b10a962e 135
backman 19:4869b10a962e 136 ////ADCSC2
backman 19:4869b10a962e 137
backman 19:4869b10a962e 138 // Read-only status bit indicating conversion status
backman 19:4869b10a962e 139 #define ADACT_ACTIVE ADC_SC2_ADACT_MASK
backman 19:4869b10a962e 140 #define ADACT_INACTIVE 0x00
backman 19:4869b10a962e 141
backman 19:4869b10a962e 142 // Trigger for starting conversion: Hardware trigger, or software trigger.
backman 19:4869b10a962e 143 // For using PDB, the Hardware trigger option is selected.
backman 19:4869b10a962e 144 #define ADTRG_HW ADC_SC2_ADTRG_MASK
backman 19:4869b10a962e 145 #define ADTRG_SW 0x00
backman 19:4869b10a962e 146
backman 19:4869b10a962e 147 // ADC Compare Function Enable: Disabled, or Enabled.
backman 19:4869b10a962e 148 #define ACFE_DISABLED 0x00
backman 19:4869b10a962e 149 #define ACFE_ENABLED ADC_SC2_ACFE_MASK
backman 19:4869b10a962e 150
backman 19:4869b10a962e 151 // Compare Function Greater Than Enable: Greater, or Less.
backman 19:4869b10a962e 152 #define ACFGT_GREATER ADC_SC2_ACFGT_MASK
backman 19:4869b10a962e 153 #define ACFGT_LESS 0x00
backman 19:4869b10a962e 154
backman 19:4869b10a962e 155 // Compare Function Range Enable: Enabled or Disabled.
backman 19:4869b10a962e 156 #define ACREN_ENABLED ADC_SC2_ACREN_MASK
backman 19:4869b10a962e 157 #define ACREN_DISABLED 0x00
backman 19:4869b10a962e 158
backman 19:4869b10a962e 159 // DMA enable: enabled or disabled.
backman 19:4869b10a962e 160 #define DMAEN_ENABLED ADC_SC2_DMAEN_MASK
backman 19:4869b10a962e 161 #define DMAEN_DISABLED 0x00
backman 19:4869b10a962e 162
backman 19:4869b10a962e 163 // Voltage Reference selection for the ADC conversions
backman 19:4869b10a962e 164 // (***not*** the PGA which uses VREFO only).
backman 19:4869b10a962e 165 // VREFH and VREFL (0) , or VREFO (1).
backman 19:4869b10a962e 166
backman 19:4869b10a962e 167 #define REFSEL_EXT 0x00
backman 19:4869b10a962e 168 #define REFSEL_ALT 0x01
backman 19:4869b10a962e 169 #define REFSEL_RES 0x02 /* reserved */
backman 19:4869b10a962e 170 #define REFSEL_RES_EXT 0x03 /* reserved but defaults to Vref */
backman 19:4869b10a962e 171
backman 19:4869b10a962e 172 ////ADCSC3
backman 19:4869b10a962e 173
backman 19:4869b10a962e 174 // Calibration begin or off
backman 19:4869b10a962e 175 #define CAL_BEGIN ADC_SC3_CAL_MASK
backman 19:4869b10a962e 176 #define CAL_OFF 0x00
backman 19:4869b10a962e 177
backman 19:4869b10a962e 178 // Status indicating Calibration failed, or normal success
backman 19:4869b10a962e 179 #define CALF_FAIL ADC_SC3_CALF_MASK
backman 19:4869b10a962e 180 #define CALF_NORMAL 0x00
backman 19:4869b10a962e 181
backman 19:4869b10a962e 182 // ADC to continously convert, or do a sinle conversion
backman 19:4869b10a962e 183 #define ADCO_CONTINUOUS ADC_SC3_ADCO_MASK
backman 19:4869b10a962e 184 #define ADCO_SINGLE 0x00
backman 19:4869b10a962e 185
backman 19:4869b10a962e 186 // Averaging enabled in the ADC, or not.
backman 19:4869b10a962e 187 #define AVGE_ENABLED ADC_SC3_AVGE_MASK
backman 19:4869b10a962e 188 #define AVGE_DISABLED 0x00
backman 19:4869b10a962e 189
backman 19:4869b10a962e 190 // How many to average prior to "interrupting" the MCU? 4, 8, 16, or 32
backman 19:4869b10a962e 191 #define AVGS_4 0x00
backman 19:4869b10a962e 192 #define AVGS_8 0x01
backman 19:4869b10a962e 193 #define AVGS_16 0x02
backman 19:4869b10a962e 194 #define AVGS_32 0x03
backman 19:4869b10a962e 195
backman 19:4869b10a962e 196 ////PGA
backman 19:4869b10a962e 197
backman 19:4869b10a962e 198 // PGA enabled or not?
backman 19:4869b10a962e 199 #define PGAEN_ENABLED ADC_PGA_PGAEN_MASK
backman 19:4869b10a962e 200 #define PGAEN_DISABLED 0x00
backman 19:4869b10a962e 201
backman 19:4869b10a962e 202 // Chopper stabilization of the amplifier, or not.
backman 19:4869b10a962e 203 #define PGACHP_CHOP ADC_PGA_PGACHP_MASK
backman 19:4869b10a962e 204 #define PGACHP_NOCHOP 0x00
backman 19:4869b10a962e 205
backman 19:4869b10a962e 206 // PGA in low power mode, or normal mode.
backman 19:4869b10a962e 207 #define PGALP_LOW ADC_PGA_PGALP_MASK
backman 19:4869b10a962e 208 #define PGALP_NORMAL 0x00
backman 19:4869b10a962e 209
backman 19:4869b10a962e 210 // Gain of PGA. Selectable from 1 to 64.
backman 19:4869b10a962e 211 #define PGAG_1 0x00
backman 19:4869b10a962e 212 #define PGAG_2 0x01
backman 19:4869b10a962e 213 #define PGAG_4 0x02
backman 19:4869b10a962e 214 #define PGAG_8 0x03
backman 19:4869b10a962e 215 #define PGAG_16 0x04
backman 19:4869b10a962e 216 #define PGAG_32 0x05
backman 19:4869b10a962e 217 #define PGAG_64 0x06
backman 19:4869b10a962e 218
backman 19:4869b10a962e 219
backman 19:4869b10a962e 220 #define ADC_STATE_INIT 0
backman 19:4869b10a962e 221 #define ADC_STATE_CAPTURE_POT_0 1
backman 19:4869b10a962e 222 #define ADC_STATE_CAPTURE_POT_1 2
backman 19:4869b10a962e 223 #define ADC_STATE_CAPTURE_BATTERY_LEVEL 3
backman 19:4869b10a962e 224 #define ADC_STATE_CAPTURE_LINE_SCAN 4
backman 19:4869b10a962e 225
backman 19:4869b10a962e 226
backman 19:4869b10a962e 227 /////////// The above values fit into the structure below to select ADC/PGA
backman 19:4869b10a962e 228 /////////// configuration desired:
backman 19:4869b10a962e 229
backman 19:4869b10a962e 230 typedef struct adc_cfg {
backman 19:4869b10a962e 231 uint8_t CONFIG1;
backman 19:4869b10a962e 232 uint8_t CONFIG2;
backman 19:4869b10a962e 233 uint16_t COMPARE1;
backman 19:4869b10a962e 234 uint16_t COMPARE2;
backman 19:4869b10a962e 235 uint8_t STATUS2;
backman 19:4869b10a962e 236 uint8_t STATUS3;
backman 19:4869b10a962e 237 uint8_t STATUS1A;
backman 19:4869b10a962e 238 uint8_t STATUS1B;
backman 19:4869b10a962e 239 uint32_t PGA;
backman 19:4869b10a962e 240 } *tADC_ConfigPtr, tADC_Config ;
backman 19:4869b10a962e 241
backman 19:4869b10a962e 242
backman 19:4869b10a962e 243 #define CAL_BLK_NUMREC 18
backman 19:4869b10a962e 244
backman 19:4869b10a962e 245 typedef struct adc_cal {
backman 19:4869b10a962e 246
backman 19:4869b10a962e 247 uint16_t OFS;
backman 19:4869b10a962e 248 uint16_t PG;
backman 19:4869b10a962e 249 uint16_t MG;
backman 19:4869b10a962e 250 uint8_t CLPD;
backman 19:4869b10a962e 251 uint8_t CLPS;
backman 19:4869b10a962e 252 uint16_t CLP4;
backman 19:4869b10a962e 253 uint16_t CLP3;
backman 19:4869b10a962e 254 uint8_t CLP2;
backman 19:4869b10a962e 255 uint8_t CLP1;
backman 19:4869b10a962e 256 uint8_t CLP0;
backman 19:4869b10a962e 257 uint8_t dummy;
backman 19:4869b10a962e 258 uint8_t CLMD;
backman 19:4869b10a962e 259 uint8_t CLMS;
backman 19:4869b10a962e 260 uint16_t CLM4;
backman 19:4869b10a962e 261 uint16_t CLM3;
backman 19:4869b10a962e 262 uint8_t CLM2;
backman 19:4869b10a962e 263 uint8_t CLM1;
backman 19:4869b10a962e 264 uint8_t CLM0;
backman 19:4869b10a962e 265 } tADC_Cal_Blk ;
backman 19:4869b10a962e 266
backman 19:4869b10a962e 267 typedef struct ADC_MemMap {
backman 19:4869b10a962e 268 uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
backman 19:4869b10a962e 269 uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
backman 19:4869b10a962e 270 uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
backman 19:4869b10a962e 271 uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
backman 19:4869b10a962e 272 uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
backman 19:4869b10a962e 273 uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
backman 19:4869b10a962e 274 uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
backman 19:4869b10a962e 275 uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
backman 19:4869b10a962e 276 uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
backman 19:4869b10a962e 277 uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
backman 19:4869b10a962e 278 uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
backman 19:4869b10a962e 279 uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
backman 19:4869b10a962e 280 uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
backman 19:4869b10a962e 281 uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
backman 19:4869b10a962e 282 uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
backman 19:4869b10a962e 283 uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
backman 19:4869b10a962e 284 uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
backman 19:4869b10a962e 285 uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
backman 19:4869b10a962e 286 uint8_t RESERVED_0[4];
backman 19:4869b10a962e 287 uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
backman 19:4869b10a962e 288 uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
backman 19:4869b10a962e 289 uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
backman 19:4869b10a962e 290 uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
backman 19:4869b10a962e 291 uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
backman 19:4869b10a962e 292 uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
backman 19:4869b10a962e 293 uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
backman 19:4869b10a962e 294 } volatile *ADC_MemMapPtr;
backman 19:4869b10a962e 295
backman 19:4869b10a962e 296
backman 19:4869b10a962e 297
backman 19:4869b10a962e 298 /* ADC - Register accessors */
backman 19:4869b10a962e 299 #define ADC_SC1_REG(base,index) ((base)->SC1[index])
backman 19:4869b10a962e 300 #define ADC_CFG1_REG(base) ((base)->CFG1)
backman 19:4869b10a962e 301 #define ADC_CFG2_REG(base) ((base)->CFG2)
backman 19:4869b10a962e 302 #define ADC_R_REG(base,index) ((base)->R[index])
backman 19:4869b10a962e 303 #define ADC_CV1_REG(base) ((base)->CV1)
backman 19:4869b10a962e 304 #define ADC_CV2_REG(base) ((base)->CV2)
backman 19:4869b10a962e 305 #define ADC_SC2_REG(base) ((base)->SC2)
backman 19:4869b10a962e 306 #define ADC_SC3_REG(base) ((base)->SC3)
backman 19:4869b10a962e 307 #define ADC_OFS_REG(base) ((base)->OFS)
backman 19:4869b10a962e 308 #define ADC_PG_REG(base) ((base)->PG)
backman 19:4869b10a962e 309 #define ADC_MG_REG(base) ((base)->MG)
backman 19:4869b10a962e 310 #define ADC_CLPD_REG(base) ((base)->CLPD)
backman 19:4869b10a962e 311 #define ADC_CLPS_REG(base) ((base)->CLPS)
backman 19:4869b10a962e 312 #define ADC_CLP4_REG(base) ((base)->CLP4)
backman 19:4869b10a962e 313 #define ADC_CLP3_REG(base) ((base)->CLP3)
backman 19:4869b10a962e 314 #define ADC_CLP2_REG(base) ((base)->CLP2)
backman 19:4869b10a962e 315 #define ADC_CLP1_REG(base) ((base)->CLP1)
backman 19:4869b10a962e 316 #define ADC_CLP0_REG(base) ((base)->CLP0)
backman 19:4869b10a962e 317 #define ADC_CLMD_REG(base) ((base)->CLMD)
backman 19:4869b10a962e 318 #define ADC_CLMS_REG(base) ((base)->CLMS)
backman 19:4869b10a962e 319 #define ADC_CLM4_REG(base) ((base)->CLM4)
backman 19:4869b10a962e 320 #define ADC_CLM3_REG(base) ((base)->CLM3)
backman 19:4869b10a962e 321 #define ADC_CLM2_REG(base) ((base)->CLM2)
backman 19:4869b10a962e 322 #define ADC_CLM1_REG(base) ((base)->CLM1)
backman 19:4869b10a962e 323 #define ADC_CLM0_REG(base) ((base)->CLM0)
backman 19:4869b10a962e 324
backman 19:4869b10a962e 325 #define ADC0_BASE_PTR ((ADC_MemMapPtr)0x4003B000u)
backman 19:4869b10a962e 326 /** Array initializer of ADC peripheral base pointers */
backman 19:4869b10a962e 327 #define ADC_BASE_PTRS { ADC0_BASE_PTR }
backman 19:4869b10a962e 328
backman 19:4869b10a962e 329
backman 19:4869b10a962e 330 float _ServoDutyCycleMin;
backman 19:4869b10a962e 331 float _ServoDutyCycleMax;
backman 19:4869b10a962e 332 float _ServoPeriod;
backman 19:4869b10a962e 333
backman 19:4869b10a962e 334 volatile uint16_t QueuedServo0Val;
backman 19:4869b10a962e 335 volatile uint16_t QueuedServo1Val;
backman 19:4869b10a962e 336
backman 19:4869b10a962e 337 volatile uint16_t *LineScanImage0WorkingBuffer;
backman 19:4869b10a962e 338 volatile uint16_t *LineScanImage1WorkingBuffer;
backman 19:4869b10a962e 339
backman 19:4869b10a962e 340 volatile uint16_t LineScanImage0Buffer[2][128];
backman 19:4869b10a962e 341 volatile uint16_t LineScanImage1Buffer[2][128];
backman 19:4869b10a962e 342 volatile uint8_t LineScanWorkingBuffer;
backman 19:4869b10a962e 343
backman 19:4869b10a962e 344 volatile uint16_t * TFC_LineScanImage0;
backman 19:4869b10a962e 345 volatile uint16_t * TFC_LineScanImage1;
backman 19:4869b10a962e 346 volatile uint8_t TFC_LineScanImageReady;
backman 19:4869b10a962e 347
backman 19:4869b10a962e 348 volatile uint16_t PotADC_Value[2];
backman 19:4869b10a962e 349 volatile uint16_t BatSenseADC_Value;
backman 19:4869b10a962e 350 volatile uint16_t CurrentADC_State;
backman 19:4869b10a962e 351 volatile uint8_t CurrentLineScanPixel;
backman 19:4869b10a962e 352 volatile uint8_t CurrentLineScanChannel;
backman 19:4869b10a962e 353 volatile uint32_t TFC_ServoTicker;
backman 19:4869b10a962e 354
backman 19:4869b10a962e 355
backman 19:4869b10a962e 356 void TFC_SetServoDutyCycle(uint8_t ServoNumber, float DutyCycle);
backman 19:4869b10a962e 357 void TFC_InitLineScanCamera();
backman 19:4869b10a962e 358 uint8_t ADC_Cal(ADC_MemMapPtr adcmap);
backman 19:4869b10a962e 359 void ADC_Config_Alt(ADC_MemMapPtr adcmap, tADC_ConfigPtr ADC_CfgPtr);
backman 19:4869b10a962e 360 void ADC_Read_Cal(ADC_MemMapPtr adcmap, tADC_Cal_Blk *blk);
backman 19:4869b10a962e 361 void TFC_InitADC0();
backman 19:4869b10a962e 362 void TFC_InitADC_System();
backman 19:4869b10a962e 363 void TFC_GPIO_Init();
backman 19:4869b10a962e 364 void ADC0_Handler();
backman 19:4869b10a962e 365 void TPM1_Handler();
backman 19:4869b10a962e 366
backman 19:4869b10a962e 367
backman 19:4869b10a962e 368 void TFC_Init()
backman 19:4869b10a962e 369 {
backman 19:4869b10a962e 370
backman 19:4869b10a962e 371 TFC_GPIO_Init();
backman 19:4869b10a962e 372
backman 19:4869b10a962e 373 TFC_InitADC_System(); // Always call this before the Servo init function.... The IRQ for the Servo code modifies ADC registers and the clocks need enable to the ADC peripherals 1st!
backman 19:4869b10a962e 374
backman 19:4869b10a962e 375 TFC_InitLineScanCamera();
backman 19:4869b10a962e 376
backman 19:4869b10a962e 377 // TFC_InitServos(SERVO_MIN_PULSE_WIDTH_DEFAULT , SERVO_MAX_PULSE_WIDTH_DEFAULT, SERVO_DEFAULT_PERIOD);
backman 19:4869b10a962e 378
backman 19:4869b10a962e 379 // TFC_ServoTicker = 0;
backman 19:4869b10a962e 380
backman 19:4869b10a962e 381 // TFC_InitMotorPWM(FTM0_DEFAULT_SWITCHING_FREQUENCY);
backman 19:4869b10a962e 382
backman 19:4869b10a962e 383 }
backman 19:4869b10a962e 384
backman 19:4869b10a962e 385
backman 19:4869b10a962e 386 void TFC_GPIO_Init()
backman 19:4869b10a962e 387 {
backman 19:4869b10a962e 388
backman 19:4869b10a962e 389 //enable Clocks to all ports
backman 19:4869b10a962e 390
backman 19:4869b10a962e 391 SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTE_MASK;
backman 19:4869b10a962e 392
backman 19:4869b10a962e 393 //Setup Pins as GPIO
backman 19:4869b10a962e 394 PORTE->PCR[21] = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
backman 19:4869b10a962e 395 PORTE->PCR[20] = PORT_PCR_MUX(1);
backman 19:4869b10a962e 396
backman 19:4869b10a962e 397 //Port for Pushbuttons
backman 19:4869b10a962e 398 PORTC->PCR[13] = PORT_PCR_MUX(1);
backman 19:4869b10a962e 399 PORTC->PCR[17] = PORT_PCR_MUX(1);
backman 19:4869b10a962e 400
backman 19:4869b10a962e 401
backman 19:4869b10a962e 402 //Ports for DIP Switches
backman 19:4869b10a962e 403 PORTE->PCR[2] = PORT_PCR_MUX(1);
backman 19:4869b10a962e 404 PORTE->PCR[3] = PORT_PCR_MUX(1);
backman 19:4869b10a962e 405 PORTE->PCR[4] = PORT_PCR_MUX(1);
backman 19:4869b10a962e 406 PORTE->PCR[5] = PORT_PCR_MUX(1);
backman 19:4869b10a962e 407
backman 19:4869b10a962e 408 //Ports for LEDs
backman 19:4869b10a962e 409 PORTB->PCR[8] = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
backman 19:4869b10a962e 410 PORTB->PCR[9] = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
backman 19:4869b10a962e 411 PORTB->PCR[10] = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
backman 19:4869b10a962e 412 PORTB->PCR[11] = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
backman 19:4869b10a962e 413
backman 19:4869b10a962e 414
backman 19:4869b10a962e 415 //Setup the output pins
backman 19:4869b10a962e 416 PTE->PDDR = TFC_HBRIDGE_EN_LOC;
backman 19:4869b10a962e 417 PTB->PDDR = TFC_BAT_LED0_LOC | TFC_BAT_LED1_LOC | TFC_BAT_LED2_LOC | TFC_BAT_LED3_LOC;
backman 19:4869b10a962e 418
backman 19:4869b10a962e 419 TFC_SetBatteryLED(0);
backman 19:4869b10a962e 420 TFC_HBRIDGE_DISABLE;
backman 19:4869b10a962e 421 }
backman 19:4869b10a962e 422
backman 19:4869b10a962e 423 void TFC_SetBatteryLED(uint8_t Value)
backman 19:4869b10a962e 424 {
backman 19:4869b10a962e 425 if(Value & 0x01)
backman 19:4869b10a962e 426 TFC_BAT_LED0_ON;
backman 19:4869b10a962e 427 else
backman 19:4869b10a962e 428 TFC_BAT_LED0_OFF;
backman 19:4869b10a962e 429
backman 19:4869b10a962e 430 if(Value & 0x02)
backman 19:4869b10a962e 431 TFC_BAT_LED1_ON;
backman 19:4869b10a962e 432 else
backman 19:4869b10a962e 433 TFC_BAT_LED1_OFF;
backman 19:4869b10a962e 434
backman 19:4869b10a962e 435 if(Value & 0x04)
backman 19:4869b10a962e 436 TFC_BAT_LED2_ON;
backman 19:4869b10a962e 437 else
backman 19:4869b10a962e 438 TFC_BAT_LED2_OFF;
backman 19:4869b10a962e 439
backman 19:4869b10a962e 440 if(Value & 0x08)
backman 19:4869b10a962e 441 TFC_BAT_LED3_ON;
backman 19:4869b10a962e 442 else
backman 19:4869b10a962e 443 TFC_BAT_LED3_OFF;
backman 19:4869b10a962e 444 }
backman 19:4869b10a962e 445
backman 19:4869b10a962e 446 uint8_t TFC_GetDIP_Switch()
backman 19:4869b10a962e 447 {
backman 19:4869b10a962e 448 uint8_t DIP_Val=0;
backman 19:4869b10a962e 449
backman 19:4869b10a962e 450 DIP_Val = (PTE->PDIR>>2) & 0xF;
backman 19:4869b10a962e 451
backman 19:4869b10a962e 452 return DIP_Val;
backman 19:4869b10a962e 453 }
backman 19:4869b10a962e 454
backman 19:4869b10a962e 455 uint8_t TFC_ReadPushButton(uint8_t Index)
backman 19:4869b10a962e 456 {
backman 19:4869b10a962e 457 if(Index == 0) {
backman 19:4869b10a962e 458 return TFC_PUSH_BUTTON_0_PRESSED;
backman 19:4869b10a962e 459 } else {
backman 19:4869b10a962e 460 return TFC_PUSH_BUTTON_1_PRESSED;
backman 19:4869b10a962e 461 }
backman 19:4869b10a962e 462 }
backman 19:4869b10a962e 463
backman 19:4869b10a962e 464 extern "C" void TPM1_IRQHandler()
backman 19:4869b10a962e 465 {
backman 19:4869b10a962e 466 //Clear the overflow mask if set. According to the reference manual, we clear by writing a logic one!
backman 19:4869b10a962e 467 if(TPM1->SC & TPM_SC_TOF_MASK)
backman 19:4869b10a962e 468 TPM1->SC |= TPM_SC_TOF_MASK;
backman 19:4869b10a962e 469
backman 19:4869b10a962e 470 //Dump the queued values to the timer channels
backman 19:4869b10a962e 471 TPM1->CONTROLS[0].CnV = QueuedServo0Val;
backman 19:4869b10a962e 472 TPM1->CONTROLS[1].CnV = QueuedServo1Val;
backman 19:4869b10a962e 473
backman 19:4869b10a962e 474
backman 19:4869b10a962e 475 //Prime the next ADC capture cycle
backman 19:4869b10a962e 476 TAOS_SI_HIGH;
backman 19:4869b10a962e 477 //Prime the ADC pump and start capturing POT 0
backman 19:4869b10a962e 478 CurrentADC_State = ADC_STATE_CAPTURE_POT_0;
backman 19:4869b10a962e 479
backman 19:4869b10a962e 480 ADC0->CFG2 &= ~ADC_CFG2_MUXSEL_MASK; //Select the A side of the mux
backman 19:4869b10a962e 481 ADC0->SC1[0] = TFC_POT_0_ADC_CHANNEL | ADC_SC1_AIEN_MASK; //Start the State machine at POT0
backman 19:4869b10a962e 482
backman 19:4869b10a962e 483 //Flag that a new cervo cycle will start
backman 19:4869b10a962e 484 if (TFC_ServoTicker < 0xffffffff)//if servo tick less than max value, count up...
backman 19:4869b10a962e 485 TFC_ServoTicker++;
backman 19:4869b10a962e 486
backman 19:4869b10a962e 487 }
backman 19:4869b10a962e 488
backman 19:4869b10a962e 489
backman 19:4869b10a962e 490 void TFC_InitServos(float PulseWidthMin, float PulseWidthMax, float ServoPeriod)
backman 19:4869b10a962e 491 {
backman 19:4869b10a962e 492
backman 19:4869b10a962e 493 SIM->SCGC5 |= SIM_SCGC5_PORTB_MASK;
backman 19:4869b10a962e 494
backman 19:4869b10a962e 495 _ServoPeriod = ServoPeriod;
backman 19:4869b10a962e 496 _ServoDutyCycleMin = PulseWidthMin/ServoPeriod;
backman 19:4869b10a962e 497 _ServoDutyCycleMax = PulseWidthMax/ServoPeriod;
backman 19:4869b10a962e 498
backman 19:4869b10a962e 499 //Clock Setup for the TPM requires a couple steps.
backman 19:4869b10a962e 500 SIM->SCGC6 &= ~SIM_SCGC6_TPM1_MASK;
backman 19:4869b10a962e 501 //1st, set the clock mux
backman 19:4869b10a962e 502 //See Page 124 of f the KL25 Sub-Family Reference Manual, Rev. 3, September 2012
backman 19:4869b10a962e 503 SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK;// We Want MCGPLLCLK/2 (See Page 196 of the KL25 Sub-Family Reference Manual, Rev. 3, September 2012)
backman 19:4869b10a962e 504 SIM->SOPT2 &= ~(SIM_SOPT2_TPMSRC_MASK);
backman 19:4869b10a962e 505 SIM->SOPT2 |= SIM_SOPT2_TPMSRC(1);
backman 19:4869b10a962e 506
backman 19:4869b10a962e 507 //Enable the Clock to the FTM0 Module
backman 19:4869b10a962e 508 //See Page 207 of f the KL25 Sub-Family Reference Manual, Rev. 3, September 2012
backman 19:4869b10a962e 509 SIM->SCGC6 |= SIM_SCGC6_TPM1_MASK;
backman 19:4869b10a962e 510
backman 19:4869b10a962e 511 //The TPM Module has Clock. Now set up the peripheral
backman 19:4869b10a962e 512
backman 19:4869b10a962e 513 //Blow away the control registers to ensure that the counter is not running
backman 19:4869b10a962e 514 TPM1->SC = 0;
backman 19:4869b10a962e 515 TPM1->CONF = 0;
backman 19:4869b10a962e 516
backman 19:4869b10a962e 517 //While the counter is disabled we can setup the prescaler
backman 19:4869b10a962e 518
backman 19:4869b10a962e 519 TPM1->SC = TPM_SC_PS(FTM1_CLK_PRESCALE);
backman 19:4869b10a962e 520 TPM1->SC |= TPM_SC_TOIE_MASK; //Enable Interrupts for the Timer Overflow
backman 19:4869b10a962e 521
backman 19:4869b10a962e 522 //Setup the mod register to get the correct PWM Period
backman 19:4869b10a962e 523
backman 19:4869b10a962e 524 TPM1->MOD = (SystemCoreClock/(1<<(FTM1_CLK_PRESCALE))) * _ServoPeriod;
backman 19:4869b10a962e 525 //Setup Channels 0 and 1
backman 19:4869b10a962e 526
backman 19:4869b10a962e 527 TPM1->CONTROLS[0].CnSC = TPM_CnSC_MSB_MASK | TPM_CnSC_ELSB_MASK;
backman 19:4869b10a962e 528 TPM1->CONTROLS[1].CnSC = TPM_CnSC_MSB_MASK | TPM_CnSC_ELSB_MASK;
backman 19:4869b10a962e 529
backman 19:4869b10a962e 530
backman 19:4869b10a962e 531 //Set the Default duty cycle to servo neutral
backman 19:4869b10a962e 532 TFC_SetServo(0, 0.0);
backman 19:4869b10a962e 533 TFC_SetServo(1, 0.0);
backman 19:4869b10a962e 534
backman 19:4869b10a962e 535 //Enable the TPM COunter
backman 19:4869b10a962e 536 TPM1->SC |= TPM_SC_CMOD(1);
backman 19:4869b10a962e 537
backman 19:4869b10a962e 538 //Enable TPM1 IRQ on the NVIC
backman 19:4869b10a962e 539
backman 19:4869b10a962e 540 //NVIC_SetVector(TPM1_IRQn,(uint32_t)TPM1_Handler);
backman 19:4869b10a962e 541 NVIC_EnableIRQ(TPM1_IRQn);
backman 19:4869b10a962e 542
backman 19:4869b10a962e 543 //Enable the FTM functions on the the port
backman 19:4869b10a962e 544
backman 19:4869b10a962e 545 PORTB->PCR[0] = PORT_PCR_MUX(3);
backman 19:4869b10a962e 546 PORTB->PCR[1] = PORT_PCR_MUX(3);
backman 19:4869b10a962e 547
backman 19:4869b10a962e 548 }
backman 19:4869b10a962e 549
backman 19:4869b10a962e 550
backman 19:4869b10a962e 551 void TFC_SetServoDutyCycle(uint8_t ServoNumber, float DutyCycle)
backman 19:4869b10a962e 552 {
backman 19:4869b10a962e 553 switch(ServoNumber) {
backman 19:4869b10a962e 554 default:
backman 19:4869b10a962e 555 case 0:
backman 19:4869b10a962e 556
backman 19:4869b10a962e 557 QueuedServo0Val = TPM1->MOD * DutyCycle;
backman 19:4869b10a962e 558
backman 19:4869b10a962e 559 break;
backman 19:4869b10a962e 560
backman 19:4869b10a962e 561 case 1:
backman 19:4869b10a962e 562
backman 19:4869b10a962e 563 QueuedServo1Val = TPM1->MOD * DutyCycle;
backman 19:4869b10a962e 564
backman 19:4869b10a962e 565 break;
backman 19:4869b10a962e 566 }
backman 19:4869b10a962e 567 }
backman 19:4869b10a962e 568
backman 19:4869b10a962e 569 void TFC_SetServo(uint8_t ServoNumber, float Position)
backman 19:4869b10a962e 570 {
backman 19:4869b10a962e 571 TFC_SetServoDutyCycle(ServoNumber ,
backman 19:4869b10a962e 572 ((Position + 1.0)/2) * ((_ServoDutyCycleMax - _ServoDutyCycleMin))+_ServoDutyCycleMin) ;
backman 19:4869b10a962e 573
backman 19:4869b10a962e 574 }
backman 19:4869b10a962e 575
backman 19:4869b10a962e 576 //********************************************************************************************************
backman 19:4869b10a962e 577 //********************************************************************************************************
backman 19:4869b10a962e 578 //********************************************************************************************************
backman 19:4869b10a962e 579 // _____ _____ ______ _ _ _ _ _____ _______ _____ ____ _ _ _____
backman 19:4869b10a962e 580 // /\ | __ \ / ____| | ____| | | | \ | |/ ____|__ __|_ _/ __ \| \ | |/ ____|
backman 19:4869b10a962e 581 // / \ | | | | | | |__ | | | | \| | | | | | || | | | \| | (___
backman 19:4869b10a962e 582 // / /\ \ | | | | | | __| | | | | . ` | | | | | || | | | . ` |\___ \
backman 19:4869b10a962e 583 // / ____ \| |__| | |____ | | | |__| | |\ | |____ | | _| || |__| | |\ |____) |
backman 19:4869b10a962e 584 // /_/ \_\_____/ \_____| |_| \____/|_| \_|\_____| |_| |_____\____/|_| \_|_____/
backman 19:4869b10a962e 585 // ********************************************************************************************************
backman 19:4869b10a962e 586 // ********************************************************************************************************
backman 19:4869b10a962e 587 // ********************************************************************************************************
backman 19:4869b10a962e 588
backman 19:4869b10a962e 589
backman 19:4869b10a962e 590
backman 19:4869b10a962e 591
backman 19:4869b10a962e 592
backman 19:4869b10a962e 593 uint8_t ADC_Cal(ADC_MemMapPtr adcmap)
backman 19:4869b10a962e 594 {
backman 19:4869b10a962e 595
backman 19:4869b10a962e 596 uint16_t cal_var;
backman 19:4869b10a962e 597
backman 19:4869b10a962e 598 ADC_SC2_REG(adcmap) &= ~ADC_SC2_ADTRG_MASK ; // Enable Software Conversion Trigger for Calibration Process - ADC0_SC2 = ADC0_SC2 | ADC_SC2_ADTRGW(0);
backman 19:4869b10a962e 599 ADC_SC3_REG(adcmap) &= ( ~ADC_SC3_ADCO_MASK & ~ADC_SC3_AVGS_MASK ); // set single conversion, clear avgs bitfield for next writing
backman 19:4869b10a962e 600 ADC_SC3_REG(adcmap) |= ( ADC_SC3_AVGE_MASK | ADC_SC3_AVGS(AVGS_32) ); // Turn averaging ON and set at max value ( 32 )
backman 19:4869b10a962e 601
backman 19:4869b10a962e 602
backman 19:4869b10a962e 603 ADC_SC3_REG(adcmap) |= ADC_SC3_CAL_MASK ; // Start CAL
backman 19:4869b10a962e 604 while ( (ADC_SC1_REG(adcmap,A) & ADC_SC1_COCO_MASK ) == COCO_NOT ); // Wait calibration end
backman 19:4869b10a962e 605
backman 19:4869b10a962e 606 if ((ADC_SC3_REG(adcmap)& ADC_SC3_CALF_MASK) == CALF_FAIL ) {
backman 19:4869b10a962e 607 return(1); // Check for Calibration fail error and return
backman 19:4869b10a962e 608 }
backman 19:4869b10a962e 609 // Calculate plus-side calibration
backman 19:4869b10a962e 610 cal_var = 0x00;
backman 19:4869b10a962e 611
backman 19:4869b10a962e 612 cal_var = ADC_CLP0_REG(adcmap);
backman 19:4869b10a962e 613 cal_var += ADC_CLP1_REG(adcmap);
backman 19:4869b10a962e 614 cal_var += ADC_CLP2_REG(adcmap);
backman 19:4869b10a962e 615 cal_var += ADC_CLP3_REG(adcmap);
backman 19:4869b10a962e 616 cal_var += ADC_CLP4_REG(adcmap);
backman 19:4869b10a962e 617 cal_var += ADC_CLPS_REG(adcmap);
backman 19:4869b10a962e 618
backman 19:4869b10a962e 619 cal_var = cal_var/2;
backman 19:4869b10a962e 620 cal_var |= 0x8000; // Set MSB
backman 19:4869b10a962e 621
backman 19:4869b10a962e 622 ADC_PG_REG(adcmap) = ADC_PG_PG(cal_var);
backman 19:4869b10a962e 623
backman 19:4869b10a962e 624
backman 19:4869b10a962e 625 // Calculate minus-side calibration
backman 19:4869b10a962e 626 cal_var = 0x00;
backman 19:4869b10a962e 627
backman 19:4869b10a962e 628 cal_var = ADC_CLM0_REG(adcmap);
backman 19:4869b10a962e 629 cal_var += ADC_CLM1_REG(adcmap);
backman 19:4869b10a962e 630 cal_var += ADC_CLM2_REG(adcmap);
backman 19:4869b10a962e 631 cal_var += ADC_CLM3_REG(adcmap);
backman 19:4869b10a962e 632 cal_var += ADC_CLM4_REG(adcmap);
backman 19:4869b10a962e 633 cal_var += ADC_CLMS_REG(adcmap);
backman 19:4869b10a962e 634
backman 19:4869b10a962e 635 cal_var = cal_var/2;
backman 19:4869b10a962e 636
backman 19:4869b10a962e 637 cal_var |= 0x8000; // Set MSB
backman 19:4869b10a962e 638
backman 19:4869b10a962e 639 ADC_MG_REG(adcmap) = ADC_MG_MG(cal_var);
backman 19:4869b10a962e 640
backman 19:4869b10a962e 641 ADC_SC3_REG(adcmap) &= ~ADC_SC3_CAL_MASK ; /* Clear CAL bit */
backman 19:4869b10a962e 642
backman 19:4869b10a962e 643 return(0);
backman 19:4869b10a962e 644 }
backman 19:4869b10a962e 645
backman 19:4869b10a962e 646
backman 19:4869b10a962e 647 void ADC_Config_Alt(ADC_MemMapPtr adcmap, tADC_ConfigPtr ADC_CfgPtr)
backman 19:4869b10a962e 648 {
backman 19:4869b10a962e 649 ADC_CFG1_REG(adcmap) = ADC_CfgPtr->CONFIG1;
backman 19:4869b10a962e 650 ADC_CFG2_REG(adcmap) = ADC_CfgPtr->CONFIG2;
backman 19:4869b10a962e 651 ADC_CV1_REG(adcmap) = ADC_CfgPtr->COMPARE1;
backman 19:4869b10a962e 652 ADC_CV2_REG(adcmap) = ADC_CfgPtr->COMPARE2;
backman 19:4869b10a962e 653 ADC_SC2_REG(adcmap) = ADC_CfgPtr->STATUS2;
backman 19:4869b10a962e 654 ADC_SC3_REG(adcmap) = ADC_CfgPtr->STATUS3;
backman 19:4869b10a962e 655 //ADC_PGA_REG(adcmap) = ADC_CfgPtr->PGA;
backman 19:4869b10a962e 656 ADC_SC1_REG(adcmap,A)= ADC_CfgPtr->STATUS1A;
backman 19:4869b10a962e 657 ADC_SC1_REG(adcmap,B)= ADC_CfgPtr->STATUS1B;
backman 19:4869b10a962e 658 }
backman 19:4869b10a962e 659
backman 19:4869b10a962e 660
backman 19:4869b10a962e 661 void ADC_Read_Cal(ADC_MemMapPtr adcmap, tADC_Cal_Blk *blk)
backman 19:4869b10a962e 662 {
backman 19:4869b10a962e 663 blk->OFS = ADC_OFS_REG(adcmap);
backman 19:4869b10a962e 664 blk->PG = ADC_PG_REG(adcmap);
backman 19:4869b10a962e 665 blk->MG = ADC_MG_REG(adcmap);
backman 19:4869b10a962e 666 blk->CLPD = ADC_CLPD_REG(adcmap);
backman 19:4869b10a962e 667 blk->CLPS = ADC_CLPS_REG(adcmap);
backman 19:4869b10a962e 668 blk->CLP4 = ADC_CLP4_REG(adcmap);
backman 19:4869b10a962e 669 blk->CLP3 = ADC_CLP3_REG(adcmap);
backman 19:4869b10a962e 670 blk->CLP2 = ADC_CLP2_REG(adcmap);
backman 19:4869b10a962e 671 blk->CLP1 = ADC_CLP1_REG(adcmap);
backman 19:4869b10a962e 672 blk->CLP0 = ADC_CLP0_REG(adcmap);
backman 19:4869b10a962e 673 blk->CLMD = ADC_CLMD_REG(adcmap);
backman 19:4869b10a962e 674 blk->CLMS = ADC_CLMS_REG(adcmap);
backman 19:4869b10a962e 675 blk->CLM4 = ADC_CLM4_REG(adcmap);
backman 19:4869b10a962e 676 blk->CLM3 = ADC_CLM3_REG(adcmap);
backman 19:4869b10a962e 677 blk->CLM2 = ADC_CLM2_REG(adcmap);
backman 19:4869b10a962e 678 blk->CLM1 = ADC_CLM1_REG(adcmap);
backman 19:4869b10a962e 679 blk->CLM0 = ADC_CLM0_REG(adcmap);
backman 19:4869b10a962e 680
backman 19:4869b10a962e 681 }
backman 19:4869b10a962e 682
backman 19:4869b10a962e 683
backman 19:4869b10a962e 684 void TFC_InitADC0()
backman 19:4869b10a962e 685 {
backman 19:4869b10a962e 686 tADC_Config Master_Adc0_Config;
backman 19:4869b10a962e 687
backman 19:4869b10a962e 688
backman 19:4869b10a962e 689 SIM->SCGC6 |= (SIM_SCGC6_ADC0_MASK);
backman 19:4869b10a962e 690
backman 19:4869b10a962e 691 //Lets calibrate the ADC. 1st setup how the channel will be used.
backman 19:4869b10a962e 692
backman 19:4869b10a962e 693
backman 19:4869b10a962e 694 Master_Adc0_Config.CONFIG1 = ADLPC_NORMAL //No low power mode
backman 19:4869b10a962e 695 | ADC_CFG1_ADIV(ADIV_4) //divide input by 4
backman 19:4869b10a962e 696 | ADLSMP_LONG //long sample time
backman 19:4869b10a962e 697 | ADC_CFG1_MODE(MODE_12)//single ended 8-bit conversion
backman 19:4869b10a962e 698 | ADC_CFG1_ADICLK(ADICLK_BUS);
backman 19:4869b10a962e 699
backman 19:4869b10a962e 700 Master_Adc0_Config.CONFIG2 = MUXSEL_ADCA // select the A side of the ADC channel.
backman 19:4869b10a962e 701 | ADACKEN_DISABLED
backman 19:4869b10a962e 702 | ADHSC_HISPEED
backman 19:4869b10a962e 703 | ADC_CFG2_ADLSTS(ADLSTS_2);//Extra long sample Time (20 extra clocks)
backman 19:4869b10a962e 704
backman 19:4869b10a962e 705
backman 19:4869b10a962e 706 Master_Adc0_Config.COMPARE1 = 00000; // Comparators don't matter for calibration
backman 19:4869b10a962e 707 Master_Adc0_Config.COMPARE1 = 0xFFFF;
backman 19:4869b10a962e 708
backman 19:4869b10a962e 709 Master_Adc0_Config.STATUS2 = ADTRG_HW //hardware triggers for calibration
backman 19:4869b10a962e 710 | ACFE_DISABLED //disable comparator
backman 19:4869b10a962e 711 | ACFGT_GREATER
backman 19:4869b10a962e 712 | ACREN_ENABLED
backman 19:4869b10a962e 713 | DMAEN_DISABLED //Disable DMA
backman 19:4869b10a962e 714 | ADC_SC2_REFSEL(REFSEL_EXT); //External Reference
backman 19:4869b10a962e 715
backman 19:4869b10a962e 716 Master_Adc0_Config.STATUS3 = CAL_OFF
backman 19:4869b10a962e 717 | ADCO_SINGLE
backman 19:4869b10a962e 718 | AVGE_ENABLED;
backman 19:4869b10a962e 719 // | ADC_SC3_AVGS(AVGS_4);
backman 19:4869b10a962e 720
backman 19:4869b10a962e 721 Master_Adc0_Config.PGA = 0; // Disable the PGA
backman 19:4869b10a962e 722
backman 19:4869b10a962e 723
backman 19:4869b10a962e 724 // Configure ADC as it will be used, but because ADC_SC1_ADCH is 31,
backman 19:4869b10a962e 725 // the ADC will be inactive. Channel 31 is just disable function.
backman 19:4869b10a962e 726 // There really is no channel 31.
backman 19:4869b10a962e 727
backman 19:4869b10a962e 728 Master_Adc0_Config.STATUS1A = AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(31);
backman 19:4869b10a962e 729
backman 19:4869b10a962e 730
backman 19:4869b10a962e 731 ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc0_Config); // config ADC
backman 19:4869b10a962e 732
backman 19:4869b10a962e 733 // Calibrate the ADC in the configuration in which it will be used:
backman 19:4869b10a962e 734 ADC_Cal(ADC0_BASE_PTR); // do the calibration
backman 19:4869b10a962e 735
backman 19:4869b10a962e 736
backman 19:4869b10a962e 737 Master_Adc0_Config.STATUS2 = ACFE_DISABLED //disable comparator
backman 19:4869b10a962e 738 | ACFGT_GREATER
backman 19:4869b10a962e 739 | ACREN_ENABLED
backman 19:4869b10a962e 740 | DMAEN_DISABLED //Disable DMA
backman 19:4869b10a962e 741 | ADC_SC2_REFSEL(REFSEL_EXT); //External Reference
backman 19:4869b10a962e 742
backman 19:4869b10a962e 743 Master_Adc0_Config.STATUS3 = CAL_OFF
backman 19:4869b10a962e 744 | ADCO_SINGLE;
backman 19:4869b10a962e 745
backman 19:4869b10a962e 746
backman 19:4869b10a962e 747
backman 19:4869b10a962e 748 ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc0_Config);
backman 19:4869b10a962e 749 }
backman 19:4869b10a962e 750
backman 19:4869b10a962e 751
backman 19:4869b10a962e 752 void TFC_InitADC_System()
backman 19:4869b10a962e 753 {
backman 19:4869b10a962e 754
backman 19:4869b10a962e 755 TFC_InitADC0();
backman 19:4869b10a962e 756
backman 19:4869b10a962e 757
backman 19:4869b10a962e 758 //All Adc processing of the Pots and linescan will be done in the ADC0 IRQ!
backman 19:4869b10a962e 759 //A state machine will scan through the channels.
backman 19:4869b10a962e 760 //This is done to automate the linescan capture on Channel 0 to ensure that timing is very even
backman 19:4869b10a962e 761 CurrentADC_State = ADC_STATE_INIT;
backman 19:4869b10a962e 762
backman 19:4869b10a962e 763 //The pump will be primed with the TPM1 interrupt. upon timeout/interrupt it will set the SI signal high
backman 19:4869b10a962e 764 //for the camera and then start the conversions for the pots.
backman 19:4869b10a962e 765
backman 19:4869b10a962e 766 // NVIC_SetVector(ADC0_IRQn,(uint32_t)ADC0_Handler);
backman 19:4869b10a962e 767 NVIC_EnableIRQ(ADC0_IRQn);
backman 19:4869b10a962e 768
backman 19:4869b10a962e 769 }
backman 19:4869b10a962e 770
backman 19:4869b10a962e 771 extern "C" void ADC0_IRQHandler()
backman 19:4869b10a962e 772 {
backman 19:4869b10a962e 773 uint8_t Junk;
backman 19:4869b10a962e 774
backman 19:4869b10a962e 775 switch(CurrentADC_State) {
backman 19:4869b10a962e 776 default:
backman 19:4869b10a962e 777 Junk = ADC0->R[0];
backman 19:4869b10a962e 778 break;
backman 19:4869b10a962e 779
backman 19:4869b10a962e 780 case ADC_STATE_CAPTURE_POT_0:
backman 19:4869b10a962e 781
backman 19:4869b10a962e 782 PotADC_Value[0] = ADC0->R[0];
backman 19:4869b10a962e 783 ADC0->CFG2 &= ~ADC_CFG2_MUXSEL_MASK; //Select the A side of the mux
backman 19:4869b10a962e 784 ADC0->SC1[0] = TFC_POT_1_ADC_CHANNEL | ADC_SC1_AIEN_MASK;
backman 19:4869b10a962e 785 CurrentADC_State = ADC_STATE_CAPTURE_POT_1;
backman 19:4869b10a962e 786
backman 19:4869b10a962e 787 break;
backman 19:4869b10a962e 788
backman 19:4869b10a962e 789 case ADC_STATE_CAPTURE_POT_1:
backman 19:4869b10a962e 790
backman 19:4869b10a962e 791 PotADC_Value[1] = ADC0->R[0];
backman 19:4869b10a962e 792 ADC0->CFG2 |= ADC_CFG2_MUXSEL_MASK; //Select the B side of the mux
backman 19:4869b10a962e 793 ADC0->SC1[0] = TFC_BAT_SENSE_CHANNEL| ADC_SC1_AIEN_MASK;
backman 19:4869b10a962e 794 CurrentADC_State = ADC_STATE_CAPTURE_BATTERY_LEVEL;
backman 19:4869b10a962e 795
backman 19:4869b10a962e 796 break;
backman 19:4869b10a962e 797
backman 19:4869b10a962e 798 case ADC_STATE_CAPTURE_BATTERY_LEVEL:
backman 19:4869b10a962e 799
backman 19:4869b10a962e 800 BatSenseADC_Value = ADC0->R[0];
backman 19:4869b10a962e 801
backman 19:4869b10a962e 802 //Now we will start the sequence for the Linescan camera
backman 19:4869b10a962e 803
backman 19:4869b10a962e 804 TAOS_CLK_HIGH;
backman 19:4869b10a962e 805
backman 19:4869b10a962e 806 for(Junk = 0; Junk<TAOS_CLK_COUNT/2; Junk++) {
backman 19:4869b10a962e 807 }
backman 19:4869b10a962e 808
backman 19:4869b10a962e 809 TAOS_SI_LOW;
backman 19:4869b10a962e 810
backman 19:4869b10a962e 811
backman 19:4869b10a962e 812 CurrentLineScanPixel = 0;
backman 19:4869b10a962e 813 CurrentLineScanChannel = 0;
backman 19:4869b10a962e 814 CurrentADC_State = ADC_STATE_CAPTURE_LINE_SCAN;
backman 19:4869b10a962e 815 ADC0->CFG2 |= ADC_CFG2_MUXSEL_MASK; //Select the B side of the mux
backman 19:4869b10a962e 816 ADC0->SC1[0] = TFC_LINESCAN0_ADC_CHANNEL | ADC_SC1_AIEN_MASK;
backman 19:4869b10a962e 817
backman 19:4869b10a962e 818 break;
backman 19:4869b10a962e 819
backman 19:4869b10a962e 820 case ADC_STATE_CAPTURE_LINE_SCAN:
backman 19:4869b10a962e 821
backman 19:4869b10a962e 822 if(CurrentLineScanPixel<128) {
backman 19:4869b10a962e 823 if(CurrentLineScanChannel == 0) {
backman 19:4869b10a962e 824 LineScanImage0WorkingBuffer[CurrentLineScanPixel] = ADC0->R[0];
backman 19:4869b10a962e 825 ADC0->SC1[0] = TFC_LINESCAN1_ADC_CHANNEL | ADC_SC1_AIEN_MASK;
backman 19:4869b10a962e 826 CurrentLineScanChannel = 1;
backman 19:4869b10a962e 827
backman 19:4869b10a962e 828 } else {
backman 19:4869b10a962e 829 LineScanImage1WorkingBuffer[CurrentLineScanPixel] = ADC0->R[0];
backman 19:4869b10a962e 830 ADC0->SC1[0] = TFC_LINESCAN0_ADC_CHANNEL | ADC_SC1_AIEN_MASK;
backman 19:4869b10a962e 831 CurrentLineScanChannel = 0;
backman 19:4869b10a962e 832 CurrentLineScanPixel++;
backman 19:4869b10a962e 833
backman 19:4869b10a962e 834 TAOS_CLK_LOW;
backman 19:4869b10a962e 835 for(Junk = 0; Junk<TAOS_CLK_COUNT/2; Junk++) {
backman 19:4869b10a962e 836 }
backman 19:4869b10a962e 837 TAOS_CLK_HIGH;
backman 19:4869b10a962e 838
backman 19:4869b10a962e 839 }
backman 19:4869b10a962e 840
backman 19:4869b10a962e 841 } else {
backman 19:4869b10a962e 842 // done with the capture sequence. we can wait for the PIT0 IRQ to restart
backman 19:4869b10a962e 843
backman 19:4869b10a962e 844 TAOS_CLK_HIGH;
backman 19:4869b10a962e 845
backman 19:4869b10a962e 846 for(Junk = 0; Junk<TAOS_CLK_COUNT/2; Junk++) {
backman 19:4869b10a962e 847 }
backman 19:4869b10a962e 848
backman 19:4869b10a962e 849 TAOS_CLK_LOW;
backman 19:4869b10a962e 850 CurrentADC_State = ADC_STATE_INIT;
backman 19:4869b10a962e 851
backman 19:4869b10a962e 852 //swap the buffer
backman 19:4869b10a962e 853
backman 19:4869b10a962e 854 if(LineScanWorkingBuffer == 0) {
backman 19:4869b10a962e 855 LineScanWorkingBuffer = 1;
backman 19:4869b10a962e 856
backman 19:4869b10a962e 857 LineScanImage0WorkingBuffer = &LineScanImage0Buffer[1][0];
backman 19:4869b10a962e 858 LineScanImage1WorkingBuffer = &LineScanImage1Buffer[1][0];
backman 19:4869b10a962e 859
backman 19:4869b10a962e 860 TFC_LineScanImage0 = &LineScanImage0Buffer[0][0];
backman 19:4869b10a962e 861 TFC_LineScanImage1 = &LineScanImage1Buffer[0][0];
backman 19:4869b10a962e 862 } else {
backman 19:4869b10a962e 863 LineScanWorkingBuffer = 0;
backman 19:4869b10a962e 864 LineScanImage0WorkingBuffer = &LineScanImage0Buffer[0][0];
backman 19:4869b10a962e 865 LineScanImage1WorkingBuffer = &LineScanImage1Buffer[0][0];
backman 19:4869b10a962e 866
backman 19:4869b10a962e 867 TFC_LineScanImage0 = &LineScanImage0Buffer[1][0];
backman 19:4869b10a962e 868 TFC_LineScanImage1 = &LineScanImage1Buffer[1][0];
backman 19:4869b10a962e 869 }
backman 19:4869b10a962e 870
backman 19:4869b10a962e 871 TFC_LineScanImageReady++;
backman 19:4869b10a962e 872 }
backman 19:4869b10a962e 873
backman 19:4869b10a962e 874 break;
backman 19:4869b10a962e 875 }
backman 19:4869b10a962e 876
backman 19:4869b10a962e 877 }
backman 19:4869b10a962e 878
backman 19:4869b10a962e 879 void TFC_InitLineScanCamera()
backman 19:4869b10a962e 880 {
backman 19:4869b10a962e 881 SIM->SCGC5 |= SIM_SCGC5_PORTE_MASK | SIM_SCGC5_PORTD_MASK; //Make sure the clock is enabled for PORTE;
backman 19:4869b10a962e 882 PORTE->PCR[1] = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK; //Enable GPIO on on the pin for the CLOCK Signal
backman 19:4869b10a962e 883 PORTD->PCR[7] = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK; //Enable GPIO on on the pin for SI signal
backman 19:4869b10a962e 884
backman 19:4869b10a962e 885 PORTD->PCR[5] = PORT_PCR_MUX(0); //Make sure AO signal goes to an analog input
backman 19:4869b10a962e 886 PORTD->PCR[6] = PORT_PCR_MUX(0); //Make sure AO signal goes to an analog input
backman 19:4869b10a962e 887
backman 19:4869b10a962e 888 //Make sure the Clock and SI pins are outputs
backman 19:4869b10a962e 889 PTD->PDDR |= (1<<7);
backman 19:4869b10a962e 890 PTE->PDDR |= (1<<1);
backman 19:4869b10a962e 891
backman 19:4869b10a962e 892 TAOS_CLK_LOW;
backman 19:4869b10a962e 893 TAOS_SI_LOW;
backman 19:4869b10a962e 894
backman 19:4869b10a962e 895 LineScanWorkingBuffer = 0;
backman 19:4869b10a962e 896
backman 19:4869b10a962e 897 LineScanImage0WorkingBuffer = &LineScanImage0Buffer[LineScanWorkingBuffer][0];
backman 19:4869b10a962e 898 LineScanImage1WorkingBuffer = &LineScanImage1Buffer[LineScanWorkingBuffer][0];
backman 19:4869b10a962e 899
backman 19:4869b10a962e 900 TFC_LineScanImage0 = &LineScanImage0Buffer[1][0];
backman 19:4869b10a962e 901 TFC_LineScanImage1 = &LineScanImage1Buffer[1][0];
backman 19:4869b10a962e 902 }
backman 19:4869b10a962e 903
backman 19:4869b10a962e 904
backman 19:4869b10a962e 905
backman 19:4869b10a962e 906
backman 19:4869b10a962e 907
backman 19:4869b10a962e 908 /** Initialized TPM0 to be used for generating PWM signals for the the dual drive motors. This method is called in the TFC constructor with a default value of 4000.0Hz
backman 19:4869b10a962e 909 *
backman 19:4869b10a962e 910 * @param SwitchingFrequency PWM Switching Frequency in floating point format. Pick something between 1000 and 9000. Maybe you can modulate it and make a tune.
backman 19:4869b10a962e 911 */
backman 19:4869b10a962e 912 void TFC_InitMotorPWM(float SwitchingFrequency)
backman 19:4869b10a962e 913 {
backman 19:4869b10a962e 914 //Clock Setup for the TPM requires a couple steps.
backman 19:4869b10a962e 915
backman 19:4869b10a962e 916 //1st, set the clock mux
backman 19:4869b10a962e 917 //See Page 124 of f the KL25 Sub-Family Reference Manual, Rev. 3, September 2012
backman 19:4869b10a962e 918 SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK;// We Want MCGPLLCLK/2 (See Page 196 of the KL25 Sub-Family Reference Manual, Rev. 3, September 2012)
backman 19:4869b10a962e 919 SIM->SOPT2 &= ~(SIM_SOPT2_TPMSRC_MASK);
backman 19:4869b10a962e 920 SIM->SOPT2 |= SIM_SOPT2_TPMSRC(1); //We want the MCGPLLCLK/2 (See Page 196 of the KL25 Sub-Family Reference Manual, Rev. 3, September 2012)
backman 19:4869b10a962e 921
backman 19:4869b10a962e 922
backman 19:4869b10a962e 923 //Enable the Clock to the FTM0 Module
backman 19:4869b10a962e 924 //See Page 207 of f the KL25 Sub-Family Reference Manual, Rev. 3, September 2012
backman 19:4869b10a962e 925 SIM->SCGC6 |= SIM_SCGC6_TPM0_MASK;
backman 19:4869b10a962e 926
backman 19:4869b10a962e 927 //The TPM Module has Clock. Now set up the peripheral
backman 19:4869b10a962e 928
backman 19:4869b10a962e 929 //Blow away the control registers to ensure that the counter is not running
backman 19:4869b10a962e 930 TPM0->SC = 0;
backman 19:4869b10a962e 931 TPM0->CONF = 0;
backman 19:4869b10a962e 932
backman 19:4869b10a962e 933 //While the counter is disabled we can setup the prescaler
backman 19:4869b10a962e 934
backman 19:4869b10a962e 935 TPM0->SC = TPM_SC_PS(FTM0_CLK_PRESCALE);
backman 19:4869b10a962e 936
backman 19:4869b10a962e 937 //Setup the mod register to get the correct PWM Period
backman 19:4869b10a962e 938
backman 19:4869b10a962e 939 TPM0->MOD = (uint32_t)((float)(FTM0_CLOCK/(1<<FTM0_CLK_PRESCALE))/SwitchingFrequency);
backman 19:4869b10a962e 940
backman 19:4869b10a962e 941 //Setup Channels 0,1,2,3
backman 19:4869b10a962e 942 TPM0->CONTROLS[0].CnSC = TPM_CnSC_MSB_MASK | TPM_CnSC_ELSB_MASK;
backman 19:4869b10a962e 943 TPM0->CONTROLS[1].CnSC = TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK; // invert the second PWM signal for a complimentary output;
backman 19:4869b10a962e 944 TPM0->CONTROLS[2].CnSC = TPM_CnSC_MSB_MASK | TPM_CnSC_ELSB_MASK;
backman 19:4869b10a962e 945 TPM0->CONTROLS[3].CnSC = TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK; // invert the second PWM signal for a complimentary output;
backman 19:4869b10a962e 946
backman 19:4869b10a962e 947 //Enable the Counter
backman 19:4869b10a962e 948
backman 19:4869b10a962e 949 //Set the Default duty cycle to 50% duty cycle
backman 19:4869b10a962e 950 TFC_SetMotorPWM(0.0,0.0);
backman 19:4869b10a962e 951
backman 19:4869b10a962e 952 //Enable the TPM COunter
backman 19:4869b10a962e 953 TPM0->SC |= TPM_SC_CMOD(1);
backman 19:4869b10a962e 954
backman 19:4869b10a962e 955 //Enable the FTM functions on the the port
backman 19:4869b10a962e 956 PORTC->PCR[1] = PORT_PCR_MUX(4);
backman 19:4869b10a962e 957 PORTC->PCR[2] = PORT_PCR_MUX(4);
backman 19:4869b10a962e 958 PORTC->PCR[3] = PORT_PCR_MUX(4);
backman 19:4869b10a962e 959 PORTC->PCR[4] = PORT_PCR_MUX(4);
backman 19:4869b10a962e 960
backman 19:4869b10a962e 961 }
backman 19:4869b10a962e 962
backman 19:4869b10a962e 963 void TFC_SetMotorPWM(float MotorA , float MotorB)
backman 19:4869b10a962e 964 {
backman 19:4869b10a962e 965 if(MotorA>1.0)
backman 19:4869b10a962e 966 MotorA = 1.0;
backman 19:4869b10a962e 967 else if(MotorA<-1.0)
backman 19:4869b10a962e 968 MotorA = -1.0;
backman 19:4869b10a962e 969
backman 19:4869b10a962e 970 if(MotorB>1.0)
backman 19:4869b10a962e 971 MotorB = 1.0;
backman 19:4869b10a962e 972 else if(MotorB<-1.0)
backman 19:4869b10a962e 973 MotorB = -1.0;
backman 19:4869b10a962e 974
backman 19:4869b10a962e 975 TPM0->CONTROLS[2].CnV = (uint16_t) ((float)TPM0->MOD * (float)((MotorA + 1.0)/2.0));
backman 19:4869b10a962e 976 TPM0->CONTROLS[3].CnV = TPM0->CONTROLS[2].CnV;
backman 19:4869b10a962e 977 TPM0->CONTROLS[0].CnV = (uint16_t) ((float)TPM0->MOD * (float)((MotorB + 1.0)/2.0));
backman 19:4869b10a962e 978 TPM0->CONTROLS[1].CnV = TPM0->CONTROLS[0].CnV;
backman 19:4869b10a962e 979
backman 19:4869b10a962e 980 }
backman 19:4869b10a962e 981
backman 19:4869b10a962e 982 //Pot Reading is Scaled to return a value of -1.0 to 1.0
backman 19:4869b10a962e 983 float TFC_ReadPot(uint8_t Channel)
backman 19:4869b10a962e 984 {
backman 19:4869b10a962e 985 if(Channel == 0)
backman 19:4869b10a962e 986 return ((float)PotADC_Value[0]/-((float)ADC_MAX_CODE/2.0))+1.0;
backman 19:4869b10a962e 987 else
backman 19:4869b10a962e 988 return ((float)PotADC_Value[1]/-((float)ADC_MAX_CODE/2.0))+1.0;
backman 19:4869b10a962e 989 }
backman 19:4869b10a962e 990
backman 19:4869b10a962e 991 float TFC_ReadBatteryVoltage()
backman 19:4869b10a962e 992 {
backman 19:4869b10a962e 993 return (((float)BatSenseADC_Value/(float)(ADC_MAX_CODE)) * 3.0);// * ((47000.0+10000.0)/10000.0);
backman 19:4869b10a962e 994 }
backman 19:4869b10a962e 995
backman 19:4869b10a962e 996
backman 19:4869b10a962e 997 void TFC_SetBatteryLED_Level(uint8_t BattLevel)
backman 19:4869b10a962e 998 {
backman 19:4869b10a962e 999 switch(BattLevel)
backman 19:4869b10a962e 1000 {
backman 19:4869b10a962e 1001 default:
backman 19:4869b10a962e 1002 case 0:
backman 19:4869b10a962e 1003 TFC_BAT_LED0_OFF;
backman 19:4869b10a962e 1004 TFC_BAT_LED1_OFF;
backman 19:4869b10a962e 1005 TFC_BAT_LED2_OFF;
backman 19:4869b10a962e 1006 TFC_BAT_LED3_OFF;
backman 19:4869b10a962e 1007 break;
backman 19:4869b10a962e 1008
backman 19:4869b10a962e 1009 case 1:
backman 19:4869b10a962e 1010 TFC_BAT_LED0_ON;
backman 19:4869b10a962e 1011 TFC_BAT_LED1_OFF;
backman 19:4869b10a962e 1012 TFC_BAT_LED2_OFF;
backman 19:4869b10a962e 1013 TFC_BAT_LED3_OFF;
backman 19:4869b10a962e 1014 break;
backman 19:4869b10a962e 1015
backman 19:4869b10a962e 1016 case 2:
backman 19:4869b10a962e 1017 TFC_BAT_LED0_ON;
backman 19:4869b10a962e 1018 TFC_BAT_LED1_ON;
backman 19:4869b10a962e 1019 TFC_BAT_LED2_OFF;
backman 19:4869b10a962e 1020 TFC_BAT_LED3_OFF;
backman 19:4869b10a962e 1021 break;
backman 19:4869b10a962e 1022
backman 19:4869b10a962e 1023 case 3:
backman 19:4869b10a962e 1024 TFC_BAT_LED0_ON;
backman 19:4869b10a962e 1025 TFC_BAT_LED1_ON;
backman 19:4869b10a962e 1026 TFC_BAT_LED2_ON;
backman 19:4869b10a962e 1027 TFC_BAT_LED3_OFF;
backman 19:4869b10a962e 1028 break;
backman 19:4869b10a962e 1029
backman 19:4869b10a962e 1030 case 4:
backman 19:4869b10a962e 1031 TFC_BAT_LED0_ON;
backman 19:4869b10a962e 1032 TFC_BAT_LED1_ON;
backman 19:4869b10a962e 1033 TFC_BAT_LED2_ON;
backman 19:4869b10a962e 1034 TFC_BAT_LED3_ON;
backman 19:4869b10a962e 1035 break;
backman 19:4869b10a962e 1036
backman 19:4869b10a962e 1037 }
backman 19:4869b10a962e 1038 }