Austin Brown / Mbed 2 deprecated MikeEtekController

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Show/hide line numbers Inverter.cpp Source File

Inverter.cpp

00001 #include "Inverter.h"
00002 
00003 
00004 
00005 //Condensing all hardware related variables into just this file.
00006 //This includes all the register diddling, assigning duty cycles, etc. 
00007 //should probably have a class called "inverter" but thats a lot of effort
00008 
00009 Inverter::Inverter(){
00010 
00011     
00012     }
00013 
00014 void Inverter::Init_PWM(void){
00015     
00016     printf("\nStarting Hardware PWM\n\r");
00017     
00018     RCC->AHBENR |= RCC_AHBENR_GPIOAEN;                 // enable the clock to GPIOA
00019     RCC->APB2ENR |= RCC_APB2ENR_TIM1EN;                // enable TIM1 clock
00020 
00021     
00022     //PWM Setup
00023     TIM1->CCMR1 |= 0x0070;                             // Enable output compare 1 PWM mode 2 (inverted for low side shunts)
00024     TIM1->CCER |= TIM_CCER_CC1E;                        // enable outputs 1
00025     //no dead time needed!
00026     TIM1->BDTR |= TIM_BDTR_MOE;                         //main output enable = 1
00027     TIM1->PSC = 0x0;                                   // no prescaler
00028     TIM1->ARR = PWM_ARR;                               // set auto reload, 20 khz
00029     TIM1->CR1 |= TIM_CR1_ARPE;                         // autoreload on, 
00030     RCC->CFGR3 |= RCC_CFGR3_TIM1SW;                    // bump tim1 up to 144MHz
00031     
00032     //hardware pin setup
00033     GPIOA->MODER   |= GPIO_MODER_MODER8_1 ;
00034     GPIOA->AFR[1]    |= 0x00000006;                    // PA8 to alternate function 6
00035     
00036     //interrupt generation
00037     NVIC_EnableIRQ(TIM1_UP_TIM16_IRQn);   //Enable TIM1 IRQ                     //dafuq is this TIM16 BS?
00038     TIM1->DIER |= TIM_DIER_UIE;           // enable update interrupt
00039     TIM1->CR1 |= 0x40;                    //CMS = 10, interrupt only when counting up
00040     TIM1->RCR |= 0x001;                   // update event once per up/down count of tim1 
00041     TIM1->EGR |= TIM_EGR_UG;
00042     
00043     TIM1->CR1 |= TIM_CR1_CEN;   //go!
00044 
00045     }
00046 
00047 void Inverter::Init_ADC(void){
00048         // ADC Setup
00049     RCC->AHBENR |= RCC_AHBENR_GPIOAEN; 
00050     RCC->AHBENR |= RCC_AHBENR_GPIOBEN;
00051     RCC->AHBENR |= RCC_AHBENR_ADC12EN;                        // clock for ADC1 and 2 enable 
00052     //RCC->AHBENR |= RCC_AHBENR_GPIOAEN;     //page 149 on the ref manual
00053     
00054     ADC12_COMMON->CCR |= 0x20001;                 // Regular simultaneous mode plus injected conversions
00055     
00056 
00057     //for board 3
00058     ADC1->SQR1 = 0x40;                            // use PA_0 as input, ADC1 in1
00059     ADC2->SQR1 = 0x40;                            // use PA_4 as input, ADC2 in1
00060     GPIOA->MODER |= 0x00000303;                   // Alternate function, PA_0, PA_4 are analog inputs 
00061 
00062     ADC1->SMPR1 = 32;     //19.5 adc cock cycles for sample
00063     ADC2->SMPR1 = 32;     //19.5 adc cock cycles for sample. 
00064     
00065     ADC2->CR |= ADC_CR_ADEN;
00066     ADC1->CR |= ADC_CR_ADEN;
00067     
00068     wait_ms(10);
00069 
00070 }
00071 
00072 
00073 
00074 
00075 void Inverter::Init(){
00076     wait_ms(100);
00077     Init_ADC();
00078     wait(0.1);         
00079     Init_PWM();
00080     
00081     }
00082     
00083 void Inverter::zero_current(){
00084     int adc1_offset_s = 0;
00085     int adc2_offset_s = 0;
00086     int n = 1024;
00087     for (int i = 0; i<n; i++){
00088         ADC1->CR  |= ADC_CR_ADSTART;  
00089         //wait_us(5);
00090         for (volatile int t = 0; t < 16; t++) {}
00091         adc2_offset_s += ADC2->DR;
00092         adc1_offset_s += ADC1->DR;
00093         }
00094     adc1_offset = adc1_offset_s/n;
00095     adc2_offset = adc2_offset_s/n;
00096 
00097     }
00098     
00099 void Inverter::ADCsync() {
00100     //EXTEN[1:0] = 01
00101     //EXTSEL[3:0] = 1010
00102     
00103     //this code works to slave to center of TIM1 update
00104     ADC1->CFGR |= ADC_CFGR_EXTEN_0 | ADC_CFGR_EXTEN_1;
00105     ADC1->CFGR |= ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1;
00106     TIM1->CR2 |= TIM_CR2_MMS2_1;
00107     ADC1->CR  |= ADC_CR_ADSTART; 
00108 }
00109 
00110 
00111