Mirror with some correction
Dependencies: mbed FastIO FastPWM USBDevice
FreescaleIAP/IAP.s@116:7a67265d7c19, 2021-10-01 (annotated)
- Committer:
- arnoz
- Date:
- Fri Oct 01 08:19:46 2021 +0000
- Revision:
- 116:7a67265d7c19
- Parent:
- 101:755f44622abc
- Correct information regarding your last merge
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mjr | 76:7f5912b6340e | 1 | ; FreescaleIAP assembly functions |
mjr | 76:7f5912b6340e | 2 | ; |
mjr | 79:682ae3171a08 | 3 | ; The hardware manual warns that FTFA commands must be executed entirely |
mjr | 79:682ae3171a08 | 4 | ; from RAM code, since we can't have any flash reads occur while an erase |
mjr | 79:682ae3171a08 | 5 | ; or write operation is executing. If the code executing and waiting for |
mjr | 79:682ae3171a08 | 6 | ; the FTFA command were in flash, the CPU might have to fetch an instruction |
mjr | 79:682ae3171a08 | 7 | ; from flash in the course of the loop, which could freeze the CPU. |
mjr | 79:682ae3171a08 | 8 | ; Empirically, it seems that this isn't truly necessary, despite the manual's |
mjr | 79:682ae3171a08 | 9 | ; warnings. The M0+ instruction cache is big enough to hold the whole |
mjr | 101:755f44622abc | 10 | ; execute-and-wait loop instruction sequence, even when written in C++, so |
mjr | 79:682ae3171a08 | 11 | ; in practice this can run as flash-resident C++ code. We're implementing |
mjr | 79:682ae3171a08 | 12 | ; it as assembler anyway to follow the best practices as laid out in the |
mjr | 79:682ae3171a08 | 13 | ; hardware manual. |
mjr | 79:682ae3171a08 | 14 | ; |
mjr | 79:682ae3171a08 | 15 | ; Tell the linker to put our code in RAM by making it read-write. |
mjr | 79:682ae3171a08 | 16 | AREA iap_ram_asm_code, CODE, READWRITE |
mjr | 76:7f5912b6340e | 17 | |
mjr | 76:7f5912b6340e | 18 | |
mjr | 79:682ae3171a08 | 19 | ; iapExecAndWait() |
mjr | 77:0b96f6867312 | 20 | ; |
mjr | 79:682ae3171a08 | 21 | ; Launches the currently loaded FTFA command and waits for completion. |
mjr | 79:682ae3171a08 | 22 | ; Before calling, the caller must set up the FTFA command registers with |
mjr | 79:682ae3171a08 | 23 | ; the command code and any address and data parameters required. The |
mjr | 79:682ae3171a08 | 24 | ; caller should also disable interrupts, since an interrupt handler could |
mjr | 79:682ae3171a08 | 25 | ; cause a branch into code resident in flash memory, which would violate |
mjr | 79:682ae3171a08 | 26 | ; the rule against accessing flash while an FTFA command is running. |
mjr | 77:0b96f6867312 | 27 | |
mjr | 77:0b96f6867312 | 28 | EXPORT iapExecAndWait |
mjr | 77:0b96f6867312 | 29 | iapExecAndWait |
mjr | 76:7f5912b6340e | 30 | ; save registers |
mjr | 79:682ae3171a08 | 31 | STMFD R13!, {R1,R2,LR} |
mjr | 77:0b96f6867312 | 32 | |
mjr | 79:682ae3171a08 | 33 | ; disable interrupts |
mjr | 79:682ae3171a08 | 34 | CPSID I ; set the PRIMASK to disable interrupts |
mjr | 78:1e00b3fa11af | 35 | DSB ; data synchronization barrier |
mjr | 77:0b96f6867312 | 36 | ISB ; instruction synchronization barrier |
mjr | 79:682ae3171a08 | 37 | |
mjr | 77:0b96f6867312 | 38 | ; Launch the command by writing the CCIF bit to FTFA_FSTAT |
mjr | 79:682ae3171a08 | 39 | LDR R0, FTFA_FSTAT |
mjr | 79:682ae3171a08 | 40 | MOVS R2, #0x80 ; CCIF (0x80) |
mjr | 79:682ae3171a08 | 41 | STRB R2, [R0] ; FTFA->FSTAT = CCIF |
mjr | 76:7f5912b6340e | 42 | |
mjr | 77:0b96f6867312 | 43 | ; Wait for the command to complete. The FTFA sets the CCIF |
mjr | 77:0b96f6867312 | 44 | ; bit in FTFA_FSTAT when the command is finished, so spin until |
mjr | 77:0b96f6867312 | 45 | ; the bit reads as set. |
mjr | 77:0b96f6867312 | 46 | Lew0 |
mjr | 77:0b96f6867312 | 47 | LDRB R1, [R0] ; R1 <- FTFA->FSTAT |
mjr | 77:0b96f6867312 | 48 | TSTS R1, R2 ; test R1 & CCIF |
mjr | 77:0b96f6867312 | 49 | BEQ Lew0 ; if zero, the command is still running |
mjr | 77:0b96f6867312 | 50 | |
mjr | 79:682ae3171a08 | 51 | ; re-enable interrupts |
mjr | 79:682ae3171a08 | 52 | CPSIE I |
mjr | 77:0b96f6867312 | 53 | |
mjr | 76:7f5912b6340e | 54 | ; pop registers and return |
mjr | 79:682ae3171a08 | 55 | LDMFD R13!, {R1,R2,PC} |
mjr | 77:0b96f6867312 | 56 | |
mjr | 78:1e00b3fa11af | 57 | ALIGN |
mjr | 79:682ae3171a08 | 58 | FTFA_FSTAT DCD 0x40020000 |
mjr | 78:1e00b3fa11af | 59 | |
mjr | 59:94eb9265b6d7 | 60 | END |