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Dependencies:   F7_Ethernet WebSocketClient mbed mcp3008

Fork of Nucleo_F746ZG_Ethernet by Dieter Graef

mbed-rtos/rtx/TARGET_CORTEX_A/rt_HAL_CA.h@0:f9b6112278fe, 2016-06-18 (annotated)

Committer:
DieterGraef
Date:
Sat Jun 18 10:49:12 2016 +0000
Revision:
0:f9b6112278fe
Ethernet for the NUCLEO STM32F746 Board Testprogram uses DHCP and NTP to set the clock

Who changed what in which revision?

UserRevisionLine numberNew contents of line
DieterGraef 0:f9b6112278fe 1 /*----------------------------------------------------------------------------
DieterGraef 0:f9b6112278fe 2 * RL-ARM - RTX
DieterGraef 0:f9b6112278fe 3 *----------------------------------------------------------------------------
DieterGraef 0:f9b6112278fe 4 * Name: RT_HAL_CA.H
DieterGraef 0:f9b6112278fe 5 * Purpose: Hardware Abstraction Layer for Cortex-A definitions
DieterGraef 0:f9b6112278fe 6 * Rev.: 14th Jan 2014
DieterGraef 0:f9b6112278fe 7 *----------------------------------------------------------------------------
DieterGraef 0:f9b6112278fe 8 *
DieterGraef 0:f9b6112278fe 9 * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
DieterGraef 0:f9b6112278fe 10 * All rights reserved.
DieterGraef 0:f9b6112278fe 11 * Redistribution and use in source and binary forms, with or without
DieterGraef 0:f9b6112278fe 12 * modification, are permitted provided that the following conditions are met:
DieterGraef 0:f9b6112278fe 13 * - Redistributions of source code must retain the above copyright
DieterGraef 0:f9b6112278fe 14 * notice, this list of conditions and the following disclaimer.
DieterGraef 0:f9b6112278fe 15 * - Redistributions in binary form must reproduce the above copyright
DieterGraef 0:f9b6112278fe 16 * notice, this list of conditions and the following disclaimer in the
DieterGraef 0:f9b6112278fe 17 * documentation and/or other materials provided with the distribution.
DieterGraef 0:f9b6112278fe 18 * - Neither the name of ARM nor the names of its contributors may be used
DieterGraef 0:f9b6112278fe 19 * to endorse or promote products derived from this software without
DieterGraef 0:f9b6112278fe 20 * specific prior written permission.
DieterGraef 0:f9b6112278fe 21 *
DieterGraef 0:f9b6112278fe 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
DieterGraef 0:f9b6112278fe 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
DieterGraef 0:f9b6112278fe 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
DieterGraef 0:f9b6112278fe 25 * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
DieterGraef 0:f9b6112278fe 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
DieterGraef 0:f9b6112278fe 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
DieterGraef 0:f9b6112278fe 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
DieterGraef 0:f9b6112278fe 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
DieterGraef 0:f9b6112278fe 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
DieterGraef 0:f9b6112278fe 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
DieterGraef 0:f9b6112278fe 32 * POSSIBILITY OF SUCH DAMAGE.
DieterGraef 0:f9b6112278fe 33 *---------------------------------------------------------------------------*/
DieterGraef 0:f9b6112278fe 34
DieterGraef 0:f9b6112278fe 35 /* Definitions */
DieterGraef 0:f9b6112278fe 36 #define INIT_CPSR_SYS 0x4000001F
DieterGraef 0:f9b6112278fe 37 #define INIT_CPSR_USER 0x40000010
DieterGraef 0:f9b6112278fe 38
DieterGraef 0:f9b6112278fe 39 #define CPSR_T_BIT 0x20
DieterGraef 0:f9b6112278fe 40 #define CPSR_I_BIT 0x80
DieterGraef 0:f9b6112278fe 41 #define CPSR_F_BIT 0x40
DieterGraef 0:f9b6112278fe 42
DieterGraef 0:f9b6112278fe 43 #define MODE_USR 0x10
DieterGraef 0:f9b6112278fe 44 #define MODE_FIQ 0x11
DieterGraef 0:f9b6112278fe 45 #define MODE_IRQ 0x12
DieterGraef 0:f9b6112278fe 46 #define MODE_SVC 0x13
DieterGraef 0:f9b6112278fe 47 #define MODE_ABT 0x17
DieterGraef 0:f9b6112278fe 48 #define MODE_UND 0x1B
DieterGraef 0:f9b6112278fe 49 #define MODE_SYS 0x1F
DieterGraef 0:f9b6112278fe 50
DieterGraef 0:f9b6112278fe 51 #define MAGIC_WORD 0xE25A2EA5
DieterGraef 0:f9b6112278fe 52
DieterGraef 0:f9b6112278fe 53 #include "core_ca9.h"
DieterGraef 0:f9b6112278fe 54
DieterGraef 0:f9b6112278fe 55 #if defined (__CC_ARM) /* ARM Compiler */
DieterGraef 0:f9b6112278fe 56
DieterGraef 0:f9b6112278fe 57 #if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M || __TARGET_ARCH_7_A) && !defined(NO_EXCLUSIVE_ACCESS))
DieterGraef 0:f9b6112278fe 58 #define __USE_EXCLUSIVE_ACCESS
DieterGraef 0:f9b6112278fe 59 #else
DieterGraef 0:f9b6112278fe 60 #undef __USE_EXCLUSIVE_ACCESS
DieterGraef 0:f9b6112278fe 61 #endif
DieterGraef 0:f9b6112278fe 62
DieterGraef 0:f9b6112278fe 63 #elif defined (__GNUC__) /* GNU Compiler */
DieterGraef 0:f9b6112278fe 64
DieterGraef 0:f9b6112278fe 65 #undef __USE_EXCLUSIVE_ACCESS
DieterGraef 0:f9b6112278fe 66
DieterGraef 0:f9b6112278fe 67 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
DieterGraef 0:f9b6112278fe 68 #define __TARGET_FPU_VFP 1
DieterGraef 0:f9b6112278fe 69 #else
DieterGraef 0:f9b6112278fe 70 #define __TARGET_FPU_VFP 0
DieterGraef 0:f9b6112278fe 71 #endif
DieterGraef 0:f9b6112278fe 72
DieterGraef 0:f9b6112278fe 73 #define __inline inline
DieterGraef 0:f9b6112278fe 74 #define __weak __attribute__((weak))
DieterGraef 0:f9b6112278fe 75
DieterGraef 0:f9b6112278fe 76 #elif defined (__ICCARM__) /* IAR Compiler */
DieterGraef 0:f9b6112278fe 77
DieterGraef 0:f9b6112278fe 78 #endif
DieterGraef 0:f9b6112278fe 79
DieterGraef 0:f9b6112278fe 80 static U8 priority = 0xff;
DieterGraef 0:f9b6112278fe 81
DieterGraef 0:f9b6112278fe 82 extern const U32 GICDistributor_BASE;
DieterGraef 0:f9b6112278fe 83 extern const U32 GICInterface_BASE;
DieterGraef 0:f9b6112278fe 84
DieterGraef 0:f9b6112278fe 85 /* GIC registers - Distributor */
DieterGraef 0:f9b6112278fe 86 #define GICD_ICDICER0 (*((volatile U32 *)(GICDistributor_BASE + 0x180))) /* - RW - Interrupt Clear-Enable Registers */
DieterGraef 0:f9b6112278fe 87 #define GICD_ICDISER0 (*((volatile U32 *)(GICDistributor_BASE + 0x100))) /* - RW - Interrupt Set-Enable Registers */
DieterGraef 0:f9b6112278fe 88 #define GICD_ICDIPR0 (*((volatile U32 *)(GICDistributor_BASE + 0x400))) /* - RW - Interrupt Priority Registers */
DieterGraef 0:f9b6112278fe 89 #define GICD_ICDSGIR (*((volatile U32 *)(GICDistributor_BASE + 0xf00))) /* - RW - Interrupt Software Interrupt Register */
DieterGraef 0:f9b6112278fe 90 #define GICD_ICDICERx(irq) *(volatile U32 *)(&GICD_ICDICER0 + irq/32)
DieterGraef 0:f9b6112278fe 91 #define GICD_ICDISERx(irq) *(volatile U32 *)(&GICD_ICDISER0 + irq/32)
DieterGraef 0:f9b6112278fe 92
DieterGraef 0:f9b6112278fe 93 /* GIC register - CPU Interface */
DieterGraef 0:f9b6112278fe 94 #define GICI_ICCPMR (*((volatile U32 *)(GICInterface_BASE + 0x004))) /* - RW - Interrupt Priority Mask Register */
DieterGraef 0:f9b6112278fe 95
DieterGraef 0:f9b6112278fe 96 #define SGI_PENDSV 0 /* SGI0 */
DieterGraef 0:f9b6112278fe 97 #define SGI_PENDSV_BIT ((U32)(1 << (SGI_PENDSV & 0xf)))
DieterGraef 0:f9b6112278fe 98
DieterGraef 0:f9b6112278fe 99 //Increase priority filter to prevent timer and PendSV interrupts signaling. Guarantees that interrupts will not be forwarded.
DieterGraef 0:f9b6112278fe 100 #if defined (__ICCARM__)
DieterGraef 0:f9b6112278fe 101 #define OS_LOCK() int irq_dis = __disable_irq_iar();\
DieterGraef 0:f9b6112278fe 102 priority = GICI_ICCPMR; \
DieterGraef 0:f9b6112278fe 103 GICI_ICCPMR = 0xff; \
DieterGraef 0:f9b6112278fe 104 GICI_ICCPMR = GICI_ICCPMR - 1; \
DieterGraef 0:f9b6112278fe 105 __DSB();\
DieterGraef 0:f9b6112278fe 106 if(!irq_dis) __enable_irq(); \
DieterGraef 0:f9b6112278fe 107
DieterGraef 0:f9b6112278fe 108 #else
DieterGraef 0:f9b6112278fe 109 #define OS_LOCK() int irq_dis = __disable_irq();\
DieterGraef 0:f9b6112278fe 110 priority = GICI_ICCPMR; \
DieterGraef 0:f9b6112278fe 111 GICI_ICCPMR = 0xff; \
DieterGraef 0:f9b6112278fe 112 GICI_ICCPMR = GICI_ICCPMR - 1; \
DieterGraef 0:f9b6112278fe 113 __DSB();\
DieterGraef 0:f9b6112278fe 114 if(!irq_dis) __enable_irq(); \
DieterGraef 0:f9b6112278fe 115
DieterGraef 0:f9b6112278fe 116 #endif
DieterGraef 0:f9b6112278fe 117
DieterGraef 0:f9b6112278fe 118 //Restore priority filter. Re-enable timer and PendSV signaling
DieterGraef 0:f9b6112278fe 119 #define OS_UNLOCK() __DSB(); \
DieterGraef 0:f9b6112278fe 120 GICI_ICCPMR = priority; \
DieterGraef 0:f9b6112278fe 121
DieterGraef 0:f9b6112278fe 122 #define OS_PEND_IRQ() GICD_ICDSGIR = 0x0010000 | SGI_PENDSV
DieterGraef 0:f9b6112278fe 123 #define OS_PEND(fl,p) if(p) OS_PEND_IRQ();
DieterGraef 0:f9b6112278fe 124 #define OS_UNPEND(fl)
DieterGraef 0:f9b6112278fe 125
DieterGraef 0:f9b6112278fe 126 /* HW initialization needs to be done in os_tick_init (void) -RTX_Conf_CM.c-
DieterGraef 0:f9b6112278fe 127 * OS_X_INIT enables the IRQ n in the GIC */
DieterGraef 0:f9b6112278fe 128 #define OS_X_INIT(n) volatile char *reg; \
DieterGraef 0:f9b6112278fe 129 reg = (char *)(&GICD_ICDIPR0 + n / 4); \
DieterGraef 0:f9b6112278fe 130 reg += n % 4; \
DieterGraef 0:f9b6112278fe 131 *reg = (char)0xff; \
DieterGraef 0:f9b6112278fe 132 *reg = *reg - 1; \
DieterGraef 0:f9b6112278fe 133 GICD_ICDISERx(n) = (U32)(1 << n % 32);
DieterGraef 0:f9b6112278fe 134 #define OS_X_LOCK(n) OS_LOCK()
DieterGraef 0:f9b6112278fe 135 #define OS_X_UNLOCK(n) OS_UNLOCK()
DieterGraef 0:f9b6112278fe 136 #define OS_X_PEND_IRQ() OS_PEND_IRQ()
DieterGraef 0:f9b6112278fe 137 #define OS_X_PEND(fl,p) if(p) OS_X_PEND_IRQ();
DieterGraef 0:f9b6112278fe 138 #define OS_X_UNPEND(fl)
DieterGraef 0:f9b6112278fe 139
DieterGraef 0:f9b6112278fe 140
DieterGraef 0:f9b6112278fe 141 /* Functions */
DieterGraef 0:f9b6112278fe 142 #ifdef __USE_EXCLUSIVE_ACCESS
DieterGraef 0:f9b6112278fe 143 #define rt_inc(p) while(__strex((__ldrex(p)+1),p))
DieterGraef 0:f9b6112278fe 144 #define rt_dec(p) while(__strex((__ldrex(p)-1),p))
DieterGraef 0:f9b6112278fe 145 #else
DieterGraef 0:f9b6112278fe 146 #if defined (__ICCARM__)
DieterGraef 0:f9b6112278fe 147 #define rt_inc(p) { int irq_dis = __disable_irq_iar();(*p)++;if(!irq_dis) __enable_irq(); }
DieterGraef 0:f9b6112278fe 148 #define rt_dec(p) { int irq_dis = __disable_irq_iar();(*p)--;if(!irq_dis) __enable_irq(); }
DieterGraef 0:f9b6112278fe 149 #else
DieterGraef 0:f9b6112278fe 150 #define rt_inc(p) { int irq_dis = __disable_irq();(*p)++;if(!irq_dis) __enable_irq(); }
DieterGraef 0:f9b6112278fe 151 #define rt_dec(p) { int irq_dis = __disable_irq();(*p)--;if(!irq_dis) __enable_irq(); }
DieterGraef 0:f9b6112278fe 152 #endif /* __ICCARM__ */
DieterGraef 0:f9b6112278fe 153 #endif /* __USE_EXCLUSIVE_ACCESS */
DieterGraef 0:f9b6112278fe 154
DieterGraef 0:f9b6112278fe 155 __inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
DieterGraef 0:f9b6112278fe 156 U32 cnt,c2;
DieterGraef 0:f9b6112278fe 157 #ifdef __USE_EXCLUSIVE_ACCESS
DieterGraef 0:f9b6112278fe 158 do {
DieterGraef 0:f9b6112278fe 159 if ((cnt = __ldrex(count)) == size) {
DieterGraef 0:f9b6112278fe 160 __clrex();
DieterGraef 0:f9b6112278fe 161 return (cnt); }
DieterGraef 0:f9b6112278fe 162 } while (__strex(cnt+1, count));
DieterGraef 0:f9b6112278fe 163 do {
DieterGraef 0:f9b6112278fe 164 c2 = (cnt = __ldrex(first)) + 1;
DieterGraef 0:f9b6112278fe 165 if (c2 == size) c2 = 0;
DieterGraef 0:f9b6112278fe 166 } while (__strex(c2, first));
DieterGraef 0:f9b6112278fe 167 #else
DieterGraef 0:f9b6112278fe 168 int irq_dis;
DieterGraef 0:f9b6112278fe 169 #if defined (__ICCARM__)
DieterGraef 0:f9b6112278fe 170 irq_dis = __disable_irq_iar();
DieterGraef 0:f9b6112278fe 171 #else
DieterGraef 0:f9b6112278fe 172 irq_dis = __disable_irq();
DieterGraef 0:f9b6112278fe 173 #endif /* __ICCARM__ */
DieterGraef 0:f9b6112278fe 174 if ((cnt = *count) < size) {
DieterGraef 0:f9b6112278fe 175 *count = cnt+1;
DieterGraef 0:f9b6112278fe 176 c2 = (cnt = *first) + 1;
DieterGraef 0:f9b6112278fe 177 if (c2 == size) c2 = 0;
DieterGraef 0:f9b6112278fe 178 *first = c2;
DieterGraef 0:f9b6112278fe 179 }
DieterGraef 0:f9b6112278fe 180 if(!irq_dis) __enable_irq ();
DieterGraef 0:f9b6112278fe 181 #endif
DieterGraef 0:f9b6112278fe 182 return (cnt);
DieterGraef 0:f9b6112278fe 183 }
DieterGraef 0:f9b6112278fe 184
DieterGraef 0:f9b6112278fe 185 __inline static void rt_systick_init (void) {
DieterGraef 0:f9b6112278fe 186 /* Cortex-A doesn't have a Systick. User needs to provide an alternative timer using RTX_Conf_CM configuration */
DieterGraef 0:f9b6112278fe 187 /* HW initialization needs to be done in os_tick_init (void) -RTX_Conf_CM.c- */
DieterGraef 0:f9b6112278fe 188 }
DieterGraef 0:f9b6112278fe 189
DieterGraef 0:f9b6112278fe 190 __inline static U32 rt_systick_val (void) {
DieterGraef 0:f9b6112278fe 191 /* Cortex-A doesn't have a Systick. User needs to provide an alternative timer using RTX_Conf_CM configuration */
DieterGraef 0:f9b6112278fe 192 /* HW initialization needs to be done in os_tick_init (void) -RTX_Conf_CM.c- */
DieterGraef 0:f9b6112278fe 193 return 0;
DieterGraef 0:f9b6112278fe 194 }
DieterGraef 0:f9b6112278fe 195
DieterGraef 0:f9b6112278fe 196 __inline static U32 rt_systick_ovf (void) {
DieterGraef 0:f9b6112278fe 197 /* Cortex-A doesn't have a Systick. User needs to provide an alternative timer using RTX_Conf_CM configuration */
DieterGraef 0:f9b6112278fe 198 /* HW initialization needs to be done in os_tick_init (void) -RTX_Conf_CM.c- */
DieterGraef 0:f9b6112278fe 199 return 0;
DieterGraef 0:f9b6112278fe 200 }
DieterGraef 0:f9b6112278fe 201
DieterGraef 0:f9b6112278fe 202 __inline static void rt_svc_init (void) {
DieterGraef 0:f9b6112278fe 203 /* Register pendSV - through SGI */
DieterGraef 0:f9b6112278fe 204 volatile char *reg;
DieterGraef 0:f9b6112278fe 205
DieterGraef 0:f9b6112278fe 206 reg = (char *)(&GICD_ICDIPR0 + SGI_PENDSV/4);
DieterGraef 0:f9b6112278fe 207 reg += SGI_PENDSV % 4;
DieterGraef 0:f9b6112278fe 208 /* Write 0xff to read priority level */
DieterGraef 0:f9b6112278fe 209 *reg = (char)0xff;
DieterGraef 0:f9b6112278fe 210 /* Read priority level and set the lowest possible*/
DieterGraef 0:f9b6112278fe 211 *reg = *reg - 1;
DieterGraef 0:f9b6112278fe 212
DieterGraef 0:f9b6112278fe 213 GICD_ICDISERx(SGI_PENDSV) = (U32)SGI_PENDSV_BIT;
DieterGraef 0:f9b6112278fe 214 }
DieterGraef 0:f9b6112278fe 215
DieterGraef 0:f9b6112278fe 216 extern void rt_set_PSP (U32 stack);
DieterGraef 0:f9b6112278fe 217 extern U32 rt_get_PSP (void);
DieterGraef 0:f9b6112278fe 218 extern void os_set_env (P_TCB p_TCB);
DieterGraef 0:f9b6112278fe 219 extern void *_alloc_box (void *box_mem);
DieterGraef 0:f9b6112278fe 220 extern int _free_box (void *box_mem, void *box);
DieterGraef 0:f9b6112278fe 221
DieterGraef 0:f9b6112278fe 222 extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
DieterGraef 0:f9b6112278fe 223 extern void rt_ret_val (P_TCB p_TCB, U32 v0);
DieterGraef 0:f9b6112278fe 224 extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1);
DieterGraef 0:f9b6112278fe 225
DieterGraef 0:f9b6112278fe 226 extern void dbg_init (void);
DieterGraef 0:f9b6112278fe 227 extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
DieterGraef 0:f9b6112278fe 228 extern void dbg_task_switch (U32 task_id);
DieterGraef 0:f9b6112278fe 229
DieterGraef 0:f9b6112278fe 230 #define DBG_INIT()
DieterGraef 0:f9b6112278fe 231 #define DBG_TASK_NOTIFY(p_tcb,create)
DieterGraef 0:f9b6112278fe 232 #define DBG_TASK_SWITCH(task_id)
DieterGraef 0:f9b6112278fe 233
DieterGraef 0:f9b6112278fe 234 /*----------------------------------------------------------------------------
DieterGraef 0:f9b6112278fe 235 * end of file
DieterGraef 0:f9b6112278fe 236 *---------------------------------------------------------------------------*/
DieterGraef 0:f9b6112278fe 237