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core_cm0plus.h
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00001 /**************************************************************************//** 00002 * @file core_cm0plus.h 00003 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File 00004 * @version V4.10 00005 * @date 18. March 2015 00006 * 00007 * @note 00008 * 00009 ******************************************************************************/ 00010 /* Copyright (c) 2009 - 2015 ARM LIMITED 00011 00012 All rights reserved. 00013 Redistribution and use in source and binary forms, with or without 00014 modification, are permitted provided that the following conditions are met: 00015 - Redistributions of source code must retain the above copyright 00016 notice, this list of conditions and the following disclaimer. 00017 - Redistributions in binary form must reproduce the above copyright 00018 notice, this list of conditions and the following disclaimer in the 00019 documentation and/or other materials provided with the distribution. 00020 - Neither the name of ARM nor the names of its contributors may be used 00021 to endorse or promote products derived from this software without 00022 specific prior written permission. 00023 * 00024 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 00027 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 00028 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 00029 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 00030 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 00031 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 00032 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 00033 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 00034 POSSIBILITY OF SUCH DAMAGE. 00035 ---------------------------------------------------------------------------*/ 00036 00037 00038 #if defined ( __ICCARM__ ) 00039 #pragma system_include /* treat file as system include file for MISRA check */ 00040 #endif 00041 00042 #ifndef __CORE_CM0PLUS_H_GENERIC 00043 #define __CORE_CM0PLUS_H_GENERIC 00044 00045 #ifdef __cplusplus 00046 extern "C" { 00047 #endif 00048 00049 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 00050 CMSIS violates the following MISRA-C:2004 rules: 00051 00052 \li Required Rule 8.5, object/function definition in header file.<br> 00053 Function definitions in header files are used to allow 'inlining'. 00054 00055 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 00056 Unions are used for effective representation of core registers. 00057 00058 \li Advisory Rule 19.7, Function-like macro defined.<br> 00059 Function-like macros are used to allow more efficient code. 00060 */ 00061 00062 00063 /******************************************************************************* 00064 * CMSIS definitions 00065 ******************************************************************************/ 00066 /** \ingroup Cortex-M0+ 00067 @{ 00068 */ 00069 00070 /* CMSIS CM0P definitions */ 00071 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ 00072 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ 00073 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ 00074 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ 00075 00076 #define __CORTEX_M (0x00) /*!< Cortex-M Core */ 00077 00078 00079 #if defined ( __CC_ARM ) 00080 #define __ASM __asm /*!< asm keyword for ARM Compiler */ 00081 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ 00082 #define __STATIC_INLINE static __inline 00083 00084 #elif defined ( __GNUC__ ) 00085 #define __ASM __asm /*!< asm keyword for GNU Compiler */ 00086 #define __INLINE inline /*!< inline keyword for GNU Compiler */ 00087 #define __STATIC_INLINE static inline 00088 00089 #elif defined ( __ICCARM__ ) 00090 #define __ASM __asm /*!< asm keyword for IAR Compiler */ 00091 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ 00092 #define __STATIC_INLINE static inline 00093 00094 #elif defined ( __TMS470__ ) 00095 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ 00096 #define __STATIC_INLINE static inline 00097 00098 #elif defined ( __TASKING__ ) 00099 #define __ASM __asm /*!< asm keyword for TASKING Compiler */ 00100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */ 00101 #define __STATIC_INLINE static inline 00102 00103 #elif defined ( __CSMC__ ) 00104 #define __packed 00105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ 00106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ 00107 #define __STATIC_INLINE static inline 00108 00109 #endif 00110 00111 /** __FPU_USED indicates whether an FPU is used or not. 00112 This core does not support an FPU at all 00113 */ 00114 #define __FPU_USED 0 00115 00116 #if defined ( __CC_ARM ) 00117 #if defined __TARGET_FPU_VFP 00118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00119 #endif 00120 00121 #elif defined ( __GNUC__ ) 00122 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 00123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00124 #endif 00125 00126 #elif defined ( __ICCARM__ ) 00127 #if defined __ARMVFP__ 00128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00129 #endif 00130 00131 #elif defined ( __TMS470__ ) 00132 #if defined __TI__VFP_SUPPORT____ 00133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00134 #endif 00135 00136 #elif defined ( __TASKING__ ) 00137 #if defined __FPU_VFP__ 00138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00139 #endif 00140 00141 #elif defined ( __CSMC__ ) /* Cosmic */ 00142 #if ( __CSMC__ & 0x400) // FPU present for parser 00143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00144 #endif 00145 #endif 00146 00147 #include <stdint.h> /* standard types definitions */ 00148 #include <core_cmInstr.h> /* Core Instruction Access */ 00149 #include <core_cmFunc.h> /* Core Function Access */ 00150 00151 #ifdef __cplusplus 00152 } 00153 #endif 00154 00155 #endif /* __CORE_CM0PLUS_H_GENERIC */ 00156 00157 #ifndef __CMSIS_GENERIC 00158 00159 #ifndef __CORE_CM0PLUS_H_DEPENDANT 00160 #define __CORE_CM0PLUS_H_DEPENDANT 00161 00162 #ifdef __cplusplus 00163 extern "C" { 00164 #endif 00165 00166 /* check device defines and use defaults */ 00167 #if defined __CHECK_DEVICE_DEFINES 00168 #ifndef __CM0PLUS_REV 00169 #define __CM0PLUS_REV 0x0000 00170 #warning "__CM0PLUS_REV not defined in device header file; using default!" 00171 #endif 00172 00173 #ifndef __MPU_PRESENT 00174 #define __MPU_PRESENT 0 00175 #warning "__MPU_PRESENT not defined in device header file; using default!" 00176 #endif 00177 00178 #ifndef __VTOR_PRESENT 00179 #define __VTOR_PRESENT 0 00180 #warning "__VTOR_PRESENT not defined in device header file; using default!" 00181 #endif 00182 00183 #ifndef __NVIC_PRIO_BITS 00184 #define __NVIC_PRIO_BITS 2 00185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 00186 #endif 00187 00188 #ifndef __Vendor_SysTickConfig 00189 #define __Vendor_SysTickConfig 0 00190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 00191 #endif 00192 #endif 00193 00194 /* IO definitions (access restrictions to peripheral registers) */ 00195 /** 00196 \defgroup CMSIS_glob_defs CMSIS Global Defines 00197 00198 <strong>IO Type Qualifiers</strong> are used 00199 \li to specify the access to peripheral variables. 00200 \li for automatic generation of peripheral register debug information. 00201 */ 00202 #ifdef __cplusplus 00203 #define __I volatile /*!< Defines 'read only' permissions */ 00204 #else 00205 #define __I volatile const /*!< Defines 'read only' permissions */ 00206 #endif 00207 #define __O volatile /*!< Defines 'write only' permissions */ 00208 #define __IO volatile /*!< Defines 'read / write' permissions */ 00209 00210 /*@} end of group Cortex-M0+ */ 00211 00212 00213 00214 /******************************************************************************* 00215 * Register Abstraction 00216 Core Register contain: 00217 - Core Register 00218 - Core NVIC Register 00219 - Core SCB Register 00220 - Core SysTick Register 00221 - Core MPU Register 00222 ******************************************************************************/ 00223 /** \defgroup CMSIS_core_register Defines and Type Definitions 00224 \brief Type definitions and defines for Cortex-M processor based devices. 00225 */ 00226 00227 /** \ingroup CMSIS_core_register 00228 \defgroup CMSIS_CORE Status and Control Registers 00229 \brief Core Register type definitions. 00230 @{ 00231 */ 00232 00233 /** \brief Union type to access the Application Program Status Register (APSR). 00234 */ 00235 typedef union 00236 { 00237 struct 00238 { 00239 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ 00240 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00241 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00242 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00243 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00244 } b; /*!< Structure used for bit access */ 00245 uint32_t w; /*!< Type used for word access */ 00246 } APSR_Type; 00247 00248 /* APSR Register Definitions */ 00249 #define APSR_N_Pos 31 /*!< APSR: N Position */ 00250 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 00251 00252 #define APSR_Z_Pos 30 /*!< APSR: Z Position */ 00253 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 00254 00255 #define APSR_C_Pos 29 /*!< APSR: C Position */ 00256 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 00257 00258 #define APSR_V_Pos 28 /*!< APSR: V Position */ 00259 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 00260 00261 00262 /** \brief Union type to access the Interrupt Program Status Register (IPSR). 00263 */ 00264 typedef union 00265 { 00266 struct 00267 { 00268 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00269 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 00270 } b; /*!< Structure used for bit access */ 00271 uint32_t w; /*!< Type used for word access */ 00272 } IPSR_Type; 00273 00274 /* IPSR Register Definitions */ 00275 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ 00276 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 00277 00278 00279 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 00280 */ 00281 typedef union 00282 { 00283 struct 00284 { 00285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ 00287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 00288 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ 00289 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00290 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00291 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00292 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00293 } b; /*!< Structure used for bit access */ 00294 uint32_t w; /*!< Type used for word access */ 00295 } xPSR_Type; 00296 00297 /* xPSR Register Definitions */ 00298 #define xPSR_N_Pos 31 /*!< xPSR: N Position */ 00299 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 00300 00301 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ 00302 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 00303 00304 #define xPSR_C_Pos 29 /*!< xPSR: C Position */ 00305 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 00306 00307 #define xPSR_V_Pos 28 /*!< xPSR: V Position */ 00308 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 00309 00310 #define xPSR_T_Pos 24 /*!< xPSR: T Position */ 00311 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 00312 00313 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ 00314 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 00315 00316 00317 /** \brief Union type to access the Control Registers (CONTROL). 00318 */ 00319 typedef union 00320 { 00321 struct 00322 { 00323 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 00324 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 00325 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ 00326 } b; /*!< Structure used for bit access */ 00327 uint32_t w; /*!< Type used for word access */ 00328 } CONTROL_Type; 00329 00330 /* CONTROL Register Definitions */ 00331 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ 00332 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 00333 00334 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */ 00335 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ 00336 00337 /*@} end of group CMSIS_CORE */ 00338 00339 00340 /** \ingroup CMSIS_core_register 00341 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 00342 \brief Type definitions for the NVIC Registers 00343 @{ 00344 */ 00345 00346 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 00347 */ 00348 typedef struct 00349 { 00350 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 00351 uint32_t RESERVED0[31]; 00352 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 00353 uint32_t RSERVED1[31]; 00354 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 00355 uint32_t RESERVED2[31]; 00356 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 00357 uint32_t RESERVED3[31]; 00358 uint32_t RESERVED4[64]; 00359 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ 00360 } NVIC_Type; 00361 00362 /*@} end of group CMSIS_NVIC */ 00363 00364 00365 /** \ingroup CMSIS_core_register 00366 \defgroup CMSIS_SCB System Control Block (SCB) 00367 \brief Type definitions for the System Control Block Registers 00368 @{ 00369 */ 00370 00371 /** \brief Structure type to access the System Control Block (SCB). 00372 */ 00373 typedef struct 00374 { 00375 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 00376 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 00377 #if (__VTOR_PRESENT == 1) 00378 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 00379 #else 00380 uint32_t RESERVED0; 00381 #endif 00382 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 00383 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 00384 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 00385 uint32_t RESERVED1; 00386 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ 00387 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 00388 } SCB_Type; 00389 00390 /* SCB CPUID Register Definitions */ 00391 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ 00392 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 00393 00394 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ 00395 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 00396 00397 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ 00398 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 00399 00400 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ 00401 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 00402 00403 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ 00404 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 00405 00406 /* SCB Interrupt Control State Register Definitions */ 00407 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ 00408 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 00409 00410 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ 00411 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 00412 00413 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ 00414 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 00415 00416 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ 00417 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 00418 00419 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ 00420 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 00421 00422 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ 00423 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 00424 00425 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ 00426 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 00427 00428 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ 00429 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 00430 00431 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ 00432 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 00433 00434 #if (__VTOR_PRESENT == 1) 00435 /* SCB Interrupt Control State Register Definitions */ 00436 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ 00437 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 00438 #endif 00439 00440 /* SCB Application Interrupt and Reset Control Register Definitions */ 00441 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ 00442 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 00443 00444 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ 00445 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 00446 00447 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ 00448 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 00449 00450 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ 00451 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 00452 00453 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ 00454 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 00455 00456 /* SCB System Control Register Definitions */ 00457 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ 00458 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 00459 00460 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ 00461 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 00462 00463 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ 00464 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 00465 00466 /* SCB Configuration Control Register Definitions */ 00467 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ 00468 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 00469 00470 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ 00471 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 00472 00473 /* SCB System Handler Control and State Register Definitions */ 00474 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ 00475 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 00476 00477 /*@} end of group CMSIS_SCB */ 00478 00479 00480 /** \ingroup CMSIS_core_register 00481 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 00482 \brief Type definitions for the System Timer Registers. 00483 @{ 00484 */ 00485 00486 /** \brief Structure type to access the System Timer (SysTick). 00487 */ 00488 typedef struct 00489 { 00490 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 00491 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 00492 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 00493 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 00494 } SysTick_Type; 00495 00496 /* SysTick Control / Status Register Definitions */ 00497 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ 00498 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 00499 00500 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ 00501 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 00502 00503 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ 00504 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 00505 00506 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ 00507 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 00508 00509 /* SysTick Reload Register Definitions */ 00510 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ 00511 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 00512 00513 /* SysTick Current Register Definitions */ 00514 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ 00515 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 00516 00517 /* SysTick Calibration Register Definitions */ 00518 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ 00519 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 00520 00521 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ 00522 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 00523 00524 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ 00525 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 00526 00527 /*@} end of group CMSIS_SysTick */ 00528 00529 #if (__MPU_PRESENT == 1) 00530 /** \ingroup CMSIS_core_register 00531 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 00532 \brief Type definitions for the Memory Protection Unit (MPU) 00533 @{ 00534 */ 00535 00536 /** \brief Structure type to access the Memory Protection Unit (MPU). 00537 */ 00538 typedef struct 00539 { 00540 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 00541 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 00542 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 00543 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 00544 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ 00545 } MPU_Type; 00546 00547 /* MPU Type Register */ 00548 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ 00549 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 00550 00551 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ 00552 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 00553 00554 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ 00555 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ 00556 00557 /* MPU Control Register */ 00558 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ 00559 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 00560 00561 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ 00562 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 00563 00564 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ 00565 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ 00566 00567 /* MPU Region Number Register */ 00568 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ 00569 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ 00570 00571 /* MPU Region Base Address Register */ 00572 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ 00573 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 00574 00575 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ 00576 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 00577 00578 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ 00579 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ 00580 00581 /* MPU Region Attribute and Size Register */ 00582 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ 00583 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 00584 00585 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ 00586 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 00587 00588 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ 00589 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 00590 00591 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ 00592 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 00593 00594 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ 00595 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ 00596 00597 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ 00598 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ 00599 00600 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ 00601 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ 00602 00603 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ 00604 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ 00605 00606 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ 00607 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ 00608 00609 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ 00610 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ 00611 00612 /*@} end of group CMSIS_MPU */ 00613 #endif 00614 00615 00616 /** \ingroup CMSIS_core_register 00617 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 00618 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) 00619 are only accessible over DAP and not via processor. Therefore 00620 they are not covered by the Cortex-M0 header file. 00621 @{ 00622 */ 00623 /*@} end of group CMSIS_CoreDebug */ 00624 00625 00626 /** \ingroup CMSIS_core_register 00627 \defgroup CMSIS_core_base Core Definitions 00628 \brief Definitions for base addresses, unions, and structures. 00629 @{ 00630 */ 00631 00632 /* Memory mapping of Cortex-M0+ Hardware */ 00633 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 00634 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 00635 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 00636 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 00637 00638 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 00639 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 00640 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 00641 00642 #if (__MPU_PRESENT == 1) 00643 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 00644 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 00645 #endif 00646 00647 /*@} */ 00648 00649 00650 00651 /******************************************************************************* 00652 * Hardware Abstraction Layer 00653 Core Function Interface contains: 00654 - Core NVIC Functions 00655 - Core SysTick Functions 00656 - Core Register Access Functions 00657 ******************************************************************************/ 00658 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 00659 */ 00660 00661 00662 00663 /* ########################## NVIC functions #################################### */ 00664 /** \ingroup CMSIS_Core_FunctionInterface 00665 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 00666 \brief Functions that manage interrupts and exceptions via the NVIC. 00667 @{ 00668 */ 00669 00670 /* Interrupt Priorities are WORD accessible only under ARMv6M */ 00671 /* The following MACROS handle generation of the register offset and byte masks */ 00672 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) 00673 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) 00674 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) 00675 00676 00677 /** \brief Enable External Interrupt 00678 00679 The function enables a device-specific interrupt in the NVIC interrupt controller. 00680 00681 \param [in] IRQn External interrupt number. Value cannot be negative. 00682 */ 00683 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) 00684 { 00685 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 00686 } 00687 00688 00689 /** \brief Disable External Interrupt 00690 00691 The function disables a device-specific interrupt in the NVIC interrupt controller. 00692 00693 \param [in] IRQn External interrupt number. Value cannot be negative. 00694 */ 00695 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) 00696 { 00697 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 00698 } 00699 00700 00701 /** \brief Get Pending Interrupt 00702 00703 The function reads the pending register in the NVIC and returns the pending bit 00704 for the specified interrupt. 00705 00706 \param [in] IRQn Interrupt number. 00707 00708 \return 0 Interrupt status is not pending. 00709 \return 1 Interrupt status is pending. 00710 */ 00711 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) 00712 { 00713 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 00714 } 00715 00716 00717 /** \brief Set Pending Interrupt 00718 00719 The function sets the pending bit of an external interrupt. 00720 00721 \param [in] IRQn Interrupt number. Value cannot be negative. 00722 */ 00723 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) 00724 { 00725 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 00726 } 00727 00728 00729 /** \brief Clear Pending Interrupt 00730 00731 The function clears the pending bit of an external interrupt. 00732 00733 \param [in] IRQn External interrupt number. Value cannot be negative. 00734 */ 00735 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) 00736 { 00737 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 00738 } 00739 00740 00741 /** \brief Set Interrupt Priority 00742 00743 The function sets the priority of an interrupt. 00744 00745 \note The priority cannot be set for every core interrupt. 00746 00747 \param [in] IRQn Interrupt number. 00748 \param [in] priority Priority to set. 00749 */ 00750 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 00751 { 00752 if((int32_t)(IRQn) < 0) { 00753 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 00754 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 00755 } 00756 else { 00757 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 00758 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 00759 } 00760 } 00761 00762 00763 /** \brief Get Interrupt Priority 00764 00765 The function reads the priority of an interrupt. The interrupt 00766 number can be positive to specify an external (device specific) 00767 interrupt, or negative to specify an internal (core) interrupt. 00768 00769 00770 \param [in] IRQn Interrupt number. 00771 \return Interrupt Priority. Value is aligned automatically to the implemented 00772 priority bits of the microcontroller. 00773 */ 00774 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) 00775 { 00776 00777 if((int32_t)(IRQn) < 0) { 00778 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); 00779 } 00780 else { 00781 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); 00782 } 00783 } 00784 00785 00786 /** \brief System Reset 00787 00788 The function initiates a system reset request to reset the MCU. 00789 */ 00790 __STATIC_INLINE void NVIC_SystemReset(void) 00791 { 00792 __DSB(); /* Ensure all outstanding memory accesses included 00793 buffered write are completed before reset */ 00794 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 00795 SCB_AIRCR_SYSRESETREQ_Msk); 00796 __DSB(); /* Ensure completion of memory access */ 00797 while(1) { __NOP(); } /* wait until reset */ 00798 } 00799 00800 /*@} end of CMSIS_Core_NVICFunctions */ 00801 00802 00803 00804 /* ################################## SysTick function ############################################ */ 00805 /** \ingroup CMSIS_Core_FunctionInterface 00806 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 00807 \brief Functions that configure the System. 00808 @{ 00809 */ 00810 00811 #if (__Vendor_SysTickConfig == 0) 00812 00813 /** \brief System Tick Configuration 00814 00815 The function initializes the System Timer and its interrupt, and starts the System Tick Timer. 00816 Counter is in free running mode to generate periodic interrupts. 00817 00818 \param [in] ticks Number of ticks between two interrupts. 00819 00820 \return 0 Function succeeded. 00821 \return 1 Function failed. 00822 00823 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 00824 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 00825 must contain a vendor-specific implementation of this function. 00826 00827 */ 00828 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 00829 { 00830 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */ 00831 00832 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 00833 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 00834 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 00835 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 00836 SysTick_CTRL_TICKINT_Msk | 00837 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 00838 return (0UL); /* Function successful */ 00839 } 00840 00841 #endif 00842 00843 /*@} end of CMSIS_Core_SysTickFunctions */ 00844 00845 00846 00847 00848 #ifdef __cplusplus 00849 } 00850 #endif 00851 00852 #endif /* __CORE_CM0PLUS_H_DEPENDANT */ 00853 00854 #endif /* __CMSIS_GENERIC */
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