Ant Robinson / X_NUCLEO_IKS01A1-f255a2c75ecb

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Dependencies:   X_NUCLEO_COMMON

Dependents:   trabalho

X_NUCLEO_IKS01A1-f255a2c75ecb/Components/hts221/hts221_class.cpp@0:14ddc33717d5, 2016-05-11 (annotated)

Committer:
antseggs
Date:
Wed May 11 11:13:00 2016 +0000
Revision:
0:14ddc33717d5
Time functions started;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
antseggs 0:14ddc33717d5 1 /**
antseggs 0:14ddc33717d5 2 ******************************************************************************
antseggs 0:14ddc33717d5 3 * @file hts221_class.cpp
antseggs 0:14ddc33717d5 4 * @author AST / EST
antseggs 0:14ddc33717d5 5 * @version V0.0.1
antseggs 0:14ddc33717d5 6 * @date 14-April-2015
antseggs 0:14ddc33717d5 7 * @brief Implementation file for the HTS221 driver class
antseggs 0:14ddc33717d5 8 ******************************************************************************
antseggs 0:14ddc33717d5 9 * @attention
antseggs 0:14ddc33717d5 10 *
antseggs 0:14ddc33717d5 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
antseggs 0:14ddc33717d5 12 *
antseggs 0:14ddc33717d5 13 * Redistribution and use in source and binary forms, with or without modification,
antseggs 0:14ddc33717d5 14 * are permitted provided that the following conditions are met:
antseggs 0:14ddc33717d5 15 * 1. Redistributions of source code must retain the above copyright notice,
antseggs 0:14ddc33717d5 16 * this list of conditions and the following disclaimer.
antseggs 0:14ddc33717d5 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
antseggs 0:14ddc33717d5 18 * this list of conditions and the following disclaimer in the documentation
antseggs 0:14ddc33717d5 19 * and/or other materials provided with the distribution.
antseggs 0:14ddc33717d5 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
antseggs 0:14ddc33717d5 21 * may be used to endorse or promote products derived from this software
antseggs 0:14ddc33717d5 22 * without specific prior written permission.
antseggs 0:14ddc33717d5 23 *
antseggs 0:14ddc33717d5 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
antseggs 0:14ddc33717d5 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
antseggs 0:14ddc33717d5 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
antseggs 0:14ddc33717d5 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
antseggs 0:14ddc33717d5 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
antseggs 0:14ddc33717d5 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
antseggs 0:14ddc33717d5 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
antseggs 0:14ddc33717d5 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
antseggs 0:14ddc33717d5 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
antseggs 0:14ddc33717d5 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
antseggs 0:14ddc33717d5 34 *
antseggs 0:14ddc33717d5 35 ******************************************************************************
antseggs 0:14ddc33717d5 36 */
antseggs 0:14ddc33717d5 37
antseggs 0:14ddc33717d5 38 /* Includes ------------------------------------------------------------------*/
antseggs 0:14ddc33717d5 39 #include "hts221_class.h"
antseggs 0:14ddc33717d5 40 #include "hts221.h"
antseggs 0:14ddc33717d5 41
antseggs 0:14ddc33717d5 42 /* Methods -------------------------------------------------------------------*/
antseggs 0:14ddc33717d5 43 /* betzw - based on:
antseggs 0:14ddc33717d5 44 X-CUBE-MEMS1/trunk/Drivers/BSP/Components/hts221/hts221.c: revision #410,
antseggs 0:14ddc33717d5 45 X-CUBE-MEMS1/trunk: revision #416
antseggs 0:14ddc33717d5 46 */
antseggs 0:14ddc33717d5 47
antseggs 0:14ddc33717d5 48 /**
antseggs 0:14ddc33717d5 49 * @brief HTS221 Calibration procedure
antseggs 0:14ddc33717d5 50 * @retval HUM_TEMP_OK in case of success, an error code otherwise
antseggs 0:14ddc33717d5 51 */
antseggs 0:14ddc33717d5 52 HUM_TEMP_StatusTypeDef HTS221::HTS221_Calibration(void)
antseggs 0:14ddc33717d5 53 {
antseggs 0:14ddc33717d5 54 /* Temperature Calibration */
antseggs 0:14ddc33717d5 55 /* Temperature in degree for calibration ( "/8" to obtain float) */
antseggs 0:14ddc33717d5 56 uint16_t T0_degC_x8_L, T0_degC_x8_H, T1_degC_x8_L, T1_degC_x8_H;
antseggs 0:14ddc33717d5 57 uint8_t H0_rh_x2, H1_rh_x2;
antseggs 0:14ddc33717d5 58 uint8_t tempReg[2] = {0, 0};
antseggs 0:14ddc33717d5 59
antseggs 0:14ddc33717d5 60 if(HTS221_IO_Read(tempReg, HTS221_T0_degC_X8_ADDR, 1) != HUM_TEMP_OK)
antseggs 0:14ddc33717d5 61 {
antseggs 0:14ddc33717d5 62 return HUM_TEMP_ERROR;
antseggs 0:14ddc33717d5 63 }
antseggs 0:14ddc33717d5 64
antseggs 0:14ddc33717d5 65 T0_degC_x8_L = (uint16_t)tempReg[0];
antseggs 0:14ddc33717d5 66
antseggs 0:14ddc33717d5 67 if(HTS221_IO_Read(tempReg, HTS221_T1_T0_MSB_X8_ADDR, 1) != HUM_TEMP_OK)
antseggs 0:14ddc33717d5 68 {
antseggs 0:14ddc33717d5 69 return HUM_TEMP_ERROR;
antseggs 0:14ddc33717d5 70 }
antseggs 0:14ddc33717d5 71
antseggs 0:14ddc33717d5 72 T0_degC_x8_H = (uint16_t) (tempReg[0] & 0x03);
antseggs 0:14ddc33717d5 73 T0_degC = ((float)((T0_degC_x8_H << 8) | (T0_degC_x8_L))) / 8;
antseggs 0:14ddc33717d5 74
antseggs 0:14ddc33717d5 75 if(HTS221_IO_Read(tempReg, HTS221_T1_degC_X8_ADDR, 1) != HUM_TEMP_OK)
antseggs 0:14ddc33717d5 76 {
antseggs 0:14ddc33717d5 77 return HUM_TEMP_ERROR;
antseggs 0:14ddc33717d5 78 }
antseggs 0:14ddc33717d5 79
antseggs 0:14ddc33717d5 80 T1_degC_x8_L = (uint16_t)tempReg[0];
antseggs 0:14ddc33717d5 81
antseggs 0:14ddc33717d5 82 if(HTS221_IO_Read(tempReg, HTS221_T1_T0_MSB_X8_ADDR, 1) != HUM_TEMP_OK)
antseggs 0:14ddc33717d5 83 {
antseggs 0:14ddc33717d5 84 return HUM_TEMP_ERROR;
antseggs 0:14ddc33717d5 85 }
antseggs 0:14ddc33717d5 86
antseggs 0:14ddc33717d5 87 T1_degC_x8_H = (uint16_t) (tempReg[0] & 0x0C);
antseggs 0:14ddc33717d5 88 T1_degC_x8_H = T1_degC_x8_H >> 2;
antseggs 0:14ddc33717d5 89 T1_degC = ((float)((T1_degC_x8_H << 8) | (T1_degC_x8_L))) / 8;
antseggs 0:14ddc33717d5 90
antseggs 0:14ddc33717d5 91 if(HTS221_IO_Read(tempReg, (HTS221_T0_OUT_L_ADDR | HTS221_I2C_MULTIPLEBYTE_CMD), 2) != HUM_TEMP_OK)
antseggs 0:14ddc33717d5 92 {
antseggs 0:14ddc33717d5 93 return HUM_TEMP_ERROR;
antseggs 0:14ddc33717d5 94 }
antseggs 0:14ddc33717d5 95
antseggs 0:14ddc33717d5 96 T0_out = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]);
antseggs 0:14ddc33717d5 97
antseggs 0:14ddc33717d5 98 if(HTS221_IO_Read(tempReg, (HTS221_T1_OUT_L_ADDR | HTS221_I2C_MULTIPLEBYTE_CMD), 2) != HUM_TEMP_OK)
antseggs 0:14ddc33717d5 99 {
antseggs 0:14ddc33717d5 100 return HUM_TEMP_ERROR;
antseggs 0:14ddc33717d5 101 }
antseggs 0:14ddc33717d5 102
antseggs 0:14ddc33717d5 103 T1_out = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]);
antseggs 0:14ddc33717d5 104
antseggs 0:14ddc33717d5 105 /* Humidity Calibration */
antseggs 0:14ddc33717d5 106 /* Humidity in degree for calibration ( "/2" to obtain float) */
antseggs 0:14ddc33717d5 107
antseggs 0:14ddc33717d5 108 if(HTS221_IO_Read(&H0_rh_x2, HTS221_H0_RH_X2_ADDR, 1) != HUM_TEMP_OK)
antseggs 0:14ddc33717d5 109 {
antseggs 0:14ddc33717d5 110 return HUM_TEMP_ERROR;
antseggs 0:14ddc33717d5 111 }
antseggs 0:14ddc33717d5 112
antseggs 0:14ddc33717d5 113 if(HTS221_IO_Read(&H1_rh_x2, HTS221_H1_RH_X2_ADDR, 1) != HUM_TEMP_OK)
antseggs 0:14ddc33717d5 114 {
antseggs 0:14ddc33717d5 115 return HUM_TEMP_ERROR;
antseggs 0:14ddc33717d5 116 }
antseggs 0:14ddc33717d5 117
antseggs 0:14ddc33717d5 118 if(HTS221_IO_Read(&tempReg[0], (HTS221_H0_T0_OUT_L_ADDR | HTS221_I2C_MULTIPLEBYTE_CMD),
antseggs 0:14ddc33717d5 119 2) != HUM_TEMP_OK)
antseggs 0:14ddc33717d5 120 {
antseggs 0:14ddc33717d5 121 return HUM_TEMP_ERROR;
antseggs 0:14ddc33717d5 122 }
antseggs 0:14ddc33717d5 123
antseggs 0:14ddc33717d5 124 H0_T0_out = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]);
antseggs 0:14ddc33717d5 125
antseggs 0:14ddc33717d5 126 if(HTS221_IO_Read(&tempReg[0], (HTS221_H1_T0_OUT_L_ADDR | HTS221_I2C_MULTIPLEBYTE_CMD),
antseggs 0:14ddc33717d5 127 2) != HUM_TEMP_OK)
antseggs 0:14ddc33717d5 128 {
antseggs 0:14ddc33717d5 129 return HUM_TEMP_ERROR;
antseggs 0:14ddc33717d5 130 }
antseggs 0:14ddc33717d5 131
antseggs 0:14ddc33717d5 132 H1_T0_out = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]);
antseggs 0:14ddc33717d5 133
antseggs 0:14ddc33717d5 134 H0_rh = ((float)H0_rh_x2) / 2;
antseggs 0:14ddc33717d5 135 H1_rh = ((float)H1_rh_x2) / 2;
antseggs 0:14ddc33717d5 136
antseggs 0:14ddc33717d5 137 return HUM_TEMP_OK;
antseggs 0:14ddc33717d5 138 }
antseggs 0:14ddc33717d5 139
antseggs 0:14ddc33717d5 140
antseggs 0:14ddc33717d5 141 /**
antseggs 0:14ddc33717d5 142 * @brief Set HTS221 Initialization
antseggs 0:14ddc33717d5 143 * @param HTS221_Init the configuration setting for the HTS221
antseggs 0:14ddc33717d5 144 * @retval HUM_TEMP_OK in case of success, an error code otherwise
antseggs 0:14ddc33717d5 145 */
antseggs 0:14ddc33717d5 146 HUM_TEMP_StatusTypeDef HTS221::HTS221_Init(HUM_TEMP_InitTypeDef *HTS221_Init)
antseggs 0:14ddc33717d5 147 {
antseggs 0:14ddc33717d5 148 uint8_t tmp = 0x00;
antseggs 0:14ddc33717d5 149
antseggs 0:14ddc33717d5 150 /* Configure the low level interface ---------------------------------------*/
antseggs 0:14ddc33717d5 151 if(HTS221_IO_Init() != HUM_TEMP_OK)
antseggs 0:14ddc33717d5 152 {
antseggs 0:14ddc33717d5 153 return HUM_TEMP_ERROR;
antseggs 0:14ddc33717d5 154 }
antseggs 0:14ddc33717d5 155
antseggs 0:14ddc33717d5 156 if(HTS221_Power_On() != HUM_TEMP_OK)
antseggs 0:14ddc33717d5 157 {
antseggs 0:14ddc33717d5 158 return HUM_TEMP_ERROR;
antseggs 0:14ddc33717d5 159 }
antseggs 0:14ddc33717d5 160
antseggs 0:14ddc33717d5 161 if(HTS221_Calibration() != HUM_TEMP_OK)
antseggs 0:14ddc33717d5 162 {
antseggs 0:14ddc33717d5 163 return HUM_TEMP_ERROR;
antseggs 0:14ddc33717d5 164 }
antseggs 0:14ddc33717d5 165
antseggs 0:14ddc33717d5 166 if(HTS221_IO_Read(&tmp, HTS221_CTRL_REG1_ADDR, 1) != HUM_TEMP_OK)
antseggs 0:14ddc33717d5 167 {
antseggs 0:14ddc33717d5 168 return HUM_TEMP_ERROR;
antseggs 0:14ddc33717d5 169 }
antseggs 0:14ddc33717d5 170
antseggs 0:14ddc33717d5 171 /* Output Data Rate selection */
antseggs 0:14ddc33717d5 172 tmp &= ~(HTS221_ODR_MASK);
antseggs 0:14ddc33717d5 173 tmp |= HTS221_Init->OutputDataRate;
antseggs 0:14ddc33717d5 174
antseggs 0:14ddc33717d5 175 if(HTS221_IO_Write(&tmp, HTS221_CTRL_REG1_ADDR, 1) != HUM_TEMP_OK)
antseggs 0:14ddc33717d5 176 {
antseggs 0:14ddc33717d5 177 return HUM_TEMP_ERROR;
antseggs 0:14ddc33717d5 178 }
antseggs 0:14ddc33717d5 179
antseggs 0:14ddc33717d5 180 HTS221_IO_ITConfig();
antseggs 0:14ddc33717d5 181
antseggs 0:14ddc33717d5 182 return HUM_TEMP_OK;
antseggs 0:14ddc33717d5 183 }
antseggs 0:14ddc33717d5 184
antseggs 0:14ddc33717d5 185 /**
antseggs 0:14ddc33717d5 186 * @brief Read ID address of HTS221
antseggs 0:14ddc33717d5 187 * @param ht_id the pointer where the ID of the device is stored
antseggs 0:14ddc33717d5 188 * @retval HUM_TEMP_OK in case of success, an error code otherwise
antseggs 0:14ddc33717d5 189 */
antseggs 0:14ddc33717d5 190 HUM_TEMP_StatusTypeDef HTS221::HTS221_ReadID(uint8_t *ht_id)
antseggs 0:14ddc33717d5 191 {
antseggs 0:14ddc33717d5 192 if(!ht_id)
antseggs 0:14ddc33717d5 193 {
antseggs 0:14ddc33717d5 194 return HUM_TEMP_ERROR;
antseggs 0:14ddc33717d5 195 }
antseggs 0:14ddc33717d5 196
antseggs 0:14ddc33717d5 197 return HTS221_IO_Read(ht_id, HTS221_WHO_AM_I_ADDR, 1);
antseggs 0:14ddc33717d5 198 }
antseggs 0:14ddc33717d5 199
antseggs 0:14ddc33717d5 200 /**
antseggs 0:14ddc33717d5 201 * @brief Reboot memory content of HTS221
antseggs 0:14ddc33717d5 202 * @retval HUM_TEMP_OK in case of success, an error code otherwise
antseggs 0:14ddc33717d5 203 */
antseggs 0:14ddc33717d5 204 HUM_TEMP_StatusTypeDef HTS221::HTS221_RebootCmd(void)
antseggs 0:14ddc33717d5 205 {
antseggs 0:14ddc33717d5 206 uint8_t tmpreg;
antseggs 0:14ddc33717d5 207
antseggs 0:14ddc33717d5 208 /* Read CTRL_REG2 register */
antseggs 0:14ddc33717d5 209 if(HTS221_IO_Read(&tmpreg, HTS221_CTRL_REG2_ADDR, 1) != HUM_TEMP_OK)
antseggs 0:14ddc33717d5 210 {
antseggs 0:14ddc33717d5 211 return HUM_TEMP_ERROR;
antseggs 0:14ddc33717d5 212 }
antseggs 0:14ddc33717d5 213
antseggs 0:14ddc33717d5 214 /* Enable or Disable the reboot memory */
antseggs 0:14ddc33717d5 215 tmpreg |= HTS221_BOOT_REBOOTMEMORY;
antseggs 0:14ddc33717d5 216
antseggs 0:14ddc33717d5 217 /* Write value to MEMS CTRL_REG2 regsister */
antseggs 0:14ddc33717d5 218 if(HTS221_IO_Write(&tmpreg, HTS221_CTRL_REG2_ADDR, 1) != HUM_TEMP_OK)
antseggs 0:14ddc33717d5 219 {
antseggs 0:14ddc33717d5 220 return HUM_TEMP_ERROR;
antseggs 0:14ddc33717d5 221 }
antseggs 0:14ddc33717d5 222
antseggs 0:14ddc33717d5 223 return HUM_TEMP_OK;
antseggs 0:14ddc33717d5 224 }
antseggs 0:14ddc33717d5 225
antseggs 0:14ddc33717d5 226
antseggs 0:14ddc33717d5 227 /**
antseggs 0:14ddc33717d5 228 * @brief Read HTS221 output register, and calculate the humidity
antseggs 0:14ddc33717d5 229 * @param pfData the pointer to data output
antseggs 0:14ddc33717d5 230 * @retval HUM_TEMP_OK in case of success, an error code otherwise
antseggs 0:14ddc33717d5 231 */
antseggs 0:14ddc33717d5 232 HUM_TEMP_StatusTypeDef HTS221::HTS221_GetHumidity(float* pfData)
antseggs 0:14ddc33717d5 233 {
antseggs 0:14ddc33717d5 234 int16_t H_T_out, humidity_t;
antseggs 0:14ddc33717d5 235 uint8_t tempReg[2] = {0, 0};
antseggs 0:14ddc33717d5 236 uint8_t tmp = 0x00;
antseggs 0:14ddc33717d5 237 float H_rh;
antseggs 0:14ddc33717d5 238
antseggs 0:14ddc33717d5 239 if(HTS221_IO_Read(&tmp, HTS221_CTRL_REG1_ADDR, 1) != HUM_TEMP_OK)
antseggs 0:14ddc33717d5 240 {
antseggs 0:14ddc33717d5 241 return HUM_TEMP_ERROR;
antseggs 0:14ddc33717d5 242 }
antseggs 0:14ddc33717d5 243
antseggs 0:14ddc33717d5 244 /* Output Data Rate selection */
antseggs 0:14ddc33717d5 245 tmp &= (HTS221_ODR_MASK);
antseggs 0:14ddc33717d5 246
antseggs 0:14ddc33717d5 247 if(tmp == 0x00)
antseggs 0:14ddc33717d5 248 {
antseggs 0:14ddc33717d5 249 if(HTS221_IO_Read(&tmp, HTS221_CTRL_REG2_ADDR, 1) != HUM_TEMP_OK)
antseggs 0:14ddc33717d5 250 {
antseggs 0:14ddc33717d5 251 return HUM_TEMP_ERROR;
antseggs 0:14ddc33717d5 252 }
antseggs 0:14ddc33717d5 253
antseggs 0:14ddc33717d5 254 /* Serial Interface Mode selection */
antseggs 0:14ddc33717d5 255 tmp &= ~(HTS221_ONE_SHOT_MASK);
antseggs 0:14ddc33717d5 256 tmp |= HTS221_ONE_SHOT_START;
antseggs 0:14ddc33717d5 257
antseggs 0:14ddc33717d5 258 if(HTS221_IO_Write(&tmp, HTS221_CTRL_REG2_ADDR, 1) != HUM_TEMP_OK)
antseggs 0:14ddc33717d5 259 {
antseggs 0:14ddc33717d5 260 return HUM_TEMP_ERROR;
antseggs 0:14ddc33717d5 261 }
antseggs 0:14ddc33717d5 262
antseggs 0:14ddc33717d5 263 do
antseggs 0:14ddc33717d5 264 {
antseggs 0:14ddc33717d5 265
antseggs 0:14ddc33717d5 266 if(HTS221_IO_Read(&tmp, HTS221_STATUS_REG_ADDR, 1) != HUM_TEMP_OK)
antseggs 0:14ddc33717d5 267 {
antseggs 0:14ddc33717d5 268 return HUM_TEMP_ERROR;
antseggs 0:14ddc33717d5 269 }
antseggs 0:14ddc33717d5 270
antseggs 0:14ddc33717d5 271 }
antseggs 0:14ddc33717d5 272 while(!(tmp & 0x02));
antseggs 0:14ddc33717d5 273 }
antseggs 0:14ddc33717d5 274
antseggs 0:14ddc33717d5 275
antseggs 0:14ddc33717d5 276 if(HTS221_IO_Read(&tempReg[0], (HTS221_HUMIDITY_OUT_L_ADDR | HTS221_I2C_MULTIPLEBYTE_CMD),
antseggs 0:14ddc33717d5 277 2) != HUM_TEMP_OK)
antseggs 0:14ddc33717d5 278 {
antseggs 0:14ddc33717d5 279 return HUM_TEMP_ERROR;
antseggs 0:14ddc33717d5 280 }
antseggs 0:14ddc33717d5 281
antseggs 0:14ddc33717d5 282 H_T_out = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]);
antseggs 0:14ddc33717d5 283
antseggs 0:14ddc33717d5 284 H_rh = ( float )(((( H_T_out - H0_T0_out ) * ( H1_rh - H0_rh )) / ( H1_T0_out - H0_T0_out )) + H0_rh );
antseggs 0:14ddc33717d5 285
antseggs 0:14ddc33717d5 286 // Truncate to specific number of decimal digits
antseggs 0:14ddc33717d5 287 humidity_t = (uint16_t)(H_rh * pow(10.0f, HUM_DECIMAL_DIGITS));
antseggs 0:14ddc33717d5 288 *pfData = ((float)humidity_t) / pow(10.0f, HUM_DECIMAL_DIGITS);
antseggs 0:14ddc33717d5 289
antseggs 0:14ddc33717d5 290 // Prevent data going below 0% and above 100% due to linear interpolation
antseggs 0:14ddc33717d5 291 if ( *pfData < 0.0f ) *pfData = 0.0f;
antseggs 0:14ddc33717d5 292 if ( *pfData > 100.0f ) *pfData = 100.0f;
antseggs 0:14ddc33717d5 293
antseggs 0:14ddc33717d5 294 return HUM_TEMP_OK;
antseggs 0:14ddc33717d5 295 }
antseggs 0:14ddc33717d5 296
antseggs 0:14ddc33717d5 297 /**
antseggs 0:14ddc33717d5 298 * @brief Read HTS221 output register, and calculate the temperature
antseggs 0:14ddc33717d5 299 * @param pfData the pointer to data output
antseggs 0:14ddc33717d5 300 * @retval HUM_TEMP_OK in case of success, an error code otherwise
antseggs 0:14ddc33717d5 301 */
antseggs 0:14ddc33717d5 302 HUM_TEMP_StatusTypeDef HTS221::HTS221_GetTemperature(float* pfData)
antseggs 0:14ddc33717d5 303 {
antseggs 0:14ddc33717d5 304 int16_t T_out, temperature_t;
antseggs 0:14ddc33717d5 305 uint8_t tempReg[2] = {0, 0};
antseggs 0:14ddc33717d5 306 uint8_t tmp = 0x00;
antseggs 0:14ddc33717d5 307 float T_degC;
antseggs 0:14ddc33717d5 308
antseggs 0:14ddc33717d5 309 if(HTS221_IO_Read(&tmp, HTS221_CTRL_REG1_ADDR, 1) != HUM_TEMP_OK)
antseggs 0:14ddc33717d5 310 {
antseggs 0:14ddc33717d5 311 return HUM_TEMP_ERROR;
antseggs 0:14ddc33717d5 312 }
antseggs 0:14ddc33717d5 313
antseggs 0:14ddc33717d5 314 /* Output Data Rate selection */
antseggs 0:14ddc33717d5 315 tmp &= (HTS221_ODR_MASK);
antseggs 0:14ddc33717d5 316
antseggs 0:14ddc33717d5 317 if(tmp == 0x00)
antseggs 0:14ddc33717d5 318 {
antseggs 0:14ddc33717d5 319 if(HTS221_IO_Read(&tmp, HTS221_CTRL_REG2_ADDR, 1) != HUM_TEMP_OK)
antseggs 0:14ddc33717d5 320 {
antseggs 0:14ddc33717d5 321 return HUM_TEMP_ERROR;
antseggs 0:14ddc33717d5 322 }
antseggs 0:14ddc33717d5 323
antseggs 0:14ddc33717d5 324 /* Serial Interface Mode selection */
antseggs 0:14ddc33717d5 325 tmp &= ~(HTS221_ONE_SHOT_MASK);
antseggs 0:14ddc33717d5 326 tmp |= HTS221_ONE_SHOT_START;
antseggs 0:14ddc33717d5 327
antseggs 0:14ddc33717d5 328 if(HTS221_IO_Write(&tmp, HTS221_CTRL_REG2_ADDR, 1) != HUM_TEMP_OK)
antseggs 0:14ddc33717d5 329 {
antseggs 0:14ddc33717d5 330 return HUM_TEMP_ERROR;
antseggs 0:14ddc33717d5 331 }
antseggs 0:14ddc33717d5 332
antseggs 0:14ddc33717d5 333 do
antseggs 0:14ddc33717d5 334 {
antseggs 0:14ddc33717d5 335
antseggs 0:14ddc33717d5 336 if(HTS221_IO_Read(&tmp, HTS221_STATUS_REG_ADDR, 1) != HUM_TEMP_OK)
antseggs 0:14ddc33717d5 337 {
antseggs 0:14ddc33717d5 338 return HUM_TEMP_ERROR;
antseggs 0:14ddc33717d5 339 }
antseggs 0:14ddc33717d5 340
antseggs 0:14ddc33717d5 341 }
antseggs 0:14ddc33717d5 342 while(!(tmp & 0x01));
antseggs 0:14ddc33717d5 343 }
antseggs 0:14ddc33717d5 344
antseggs 0:14ddc33717d5 345 if(HTS221_IO_Read(&tempReg[0], (HTS221_TEMP_OUT_L_ADDR | HTS221_I2C_MULTIPLEBYTE_CMD),
antseggs 0:14ddc33717d5 346 2) != HUM_TEMP_OK)
antseggs 0:14ddc33717d5 347 {
antseggs 0:14ddc33717d5 348 return HUM_TEMP_ERROR;
antseggs 0:14ddc33717d5 349 }
antseggs 0:14ddc33717d5 350
antseggs 0:14ddc33717d5 351 T_out = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]);
antseggs 0:14ddc33717d5 352
antseggs 0:14ddc33717d5 353 T_degC = ((float)(T_out - T0_out)) / (T1_out - T0_out) * (T1_degC - T0_degC) + T0_degC;
antseggs 0:14ddc33717d5 354
antseggs 0:14ddc33717d5 355 temperature_t = (int16_t)(T_degC * pow(10.0f, TEMP_DECIMAL_DIGITS));
antseggs 0:14ddc33717d5 356
antseggs 0:14ddc33717d5 357 *pfData = ((float)temperature_t) / pow(10.0f, TEMP_DECIMAL_DIGITS);
antseggs 0:14ddc33717d5 358
antseggs 0:14ddc33717d5 359 return HUM_TEMP_OK;
antseggs 0:14ddc33717d5 360 }
antseggs 0:14ddc33717d5 361
antseggs 0:14ddc33717d5 362
antseggs 0:14ddc33717d5 363 /**
antseggs 0:14ddc33717d5 364 * @brief Exit the shutdown mode for HTS221
antseggs 0:14ddc33717d5 365 * @retval HUM_TEMP_OK in case of success, an error code otherwise
antseggs 0:14ddc33717d5 366 */
antseggs 0:14ddc33717d5 367 HUM_TEMP_StatusTypeDef HTS221::HTS221_Power_On(void)
antseggs 0:14ddc33717d5 368 {
antseggs 0:14ddc33717d5 369 uint8_t tmpReg;
antseggs 0:14ddc33717d5 370
antseggs 0:14ddc33717d5 371 /* Read the register content */
antseggs 0:14ddc33717d5 372 if(HTS221_IO_Read(&tmpReg, HTS221_CTRL_REG1_ADDR, 1) != HUM_TEMP_OK)
antseggs 0:14ddc33717d5 373 {
antseggs 0:14ddc33717d5 374 return HUM_TEMP_ERROR;
antseggs 0:14ddc33717d5 375 }
antseggs 0:14ddc33717d5 376
antseggs 0:14ddc33717d5 377 /* Set the power down bit */
antseggs 0:14ddc33717d5 378 tmpReg |= HTS221_MODE_ACTIVE;
antseggs 0:14ddc33717d5 379
antseggs 0:14ddc33717d5 380 /* Write register */
antseggs 0:14ddc33717d5 381 if(HTS221_IO_Write(&tmpReg, HTS221_CTRL_REG1_ADDR, 1) != HUM_TEMP_OK)
antseggs 0:14ddc33717d5 382 {
antseggs 0:14ddc33717d5 383 return HUM_TEMP_ERROR;
antseggs 0:14ddc33717d5 384 }
antseggs 0:14ddc33717d5 385
antseggs 0:14ddc33717d5 386 return HUM_TEMP_OK;
antseggs 0:14ddc33717d5 387 }
antseggs 0:14ddc33717d5 388
antseggs 0:14ddc33717d5 389 /**
antseggs 0:14ddc33717d5 390 * @brief Enter the shutdown mode for HTS221
antseggs 0:14ddc33717d5 391 * @retval HUM_TEMP_OK in case of success, an error code otherwise
antseggs 0:14ddc33717d5 392 */
antseggs 0:14ddc33717d5 393 HUM_TEMP_StatusTypeDef HTS221::HTS221_Power_OFF(void)
antseggs 0:14ddc33717d5 394 {
antseggs 0:14ddc33717d5 395 uint8_t tmpReg;
antseggs 0:14ddc33717d5 396
antseggs 0:14ddc33717d5 397 /* Read the register content */
antseggs 0:14ddc33717d5 398 if(HTS221_IO_Read(&tmpReg, HTS221_CTRL_REG1_ADDR, 1) != HUM_TEMP_OK)
antseggs 0:14ddc33717d5 399 {
antseggs 0:14ddc33717d5 400 return HUM_TEMP_ERROR;
antseggs 0:14ddc33717d5 401 }
antseggs 0:14ddc33717d5 402
antseggs 0:14ddc33717d5 403 /* Reset the power down bit */
antseggs 0:14ddc33717d5 404 tmpReg &= ~(HTS221_MODE_ACTIVE);
antseggs 0:14ddc33717d5 405
antseggs 0:14ddc33717d5 406 /* Write register */
antseggs 0:14ddc33717d5 407 if(HTS221_IO_Write(&tmpReg, HTS221_CTRL_REG1_ADDR, 1) != HUM_TEMP_OK)
antseggs 0:14ddc33717d5 408 {
antseggs 0:14ddc33717d5 409 return HUM_TEMP_ERROR;
antseggs 0:14ddc33717d5 410 }
antseggs 0:14ddc33717d5 411
antseggs 0:14ddc33717d5 412 return HUM_TEMP_OK;
antseggs 0:14ddc33717d5 413 }
antseggs 0:14ddc33717d5 414
antseggs 0:14ddc33717d5 415 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/