wm8994.c

00001 /**
00002   ******************************************************************************
00003   * @file    wm8994.c
00004   * @author  MCD Application Team
00005   * @brief   This file provides the WM8994 Audio Codec driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035 
00036 /* Includes ------------------------------------------------------------------*/
00037 #include "wm8994.h"
00038 
00039 /** @addtogroup BSP
00040   * @{
00041   */
00042   
00043 /** @addtogroup Components
00044   * @{
00045   */ 
00046 
00047 /** @addtogroup wm8994
00048   * @brief     This file provides a set of functions needed to drive the 
00049   *            WM8994 audio codec.
00050   * @{
00051   */
00052 
00053 /** @defgroup WM8994_Private_Types
00054   * @{
00055   */
00056 
00057 /**
00058   * @}
00059   */ 
00060   
00061 /** @defgroup WM8994_Private_Defines
00062   * @{
00063   */
00064 /* Uncomment this line to enable verifying data sent to codec after each write 
00065    operation (for debug purpose) */
00066 #if !defined (VERIFY_WRITTENDATA)  
00067 /*#define VERIFY_WRITTENDATA*/
00068 #endif /* VERIFY_WRITTENDATA */
00069 /**
00070   * @}
00071   */ 
00072 
00073 /** @defgroup WM8994_Private_Macros
00074   * @{
00075   */
00076 
00077 /**
00078   * @}
00079   */ 
00080   
00081 /** @defgroup WM8994_Private_Variables
00082   * @{
00083   */
00084 
00085 /* Audio codec driver structure initialization */  
00086 AUDIO_DrvTypeDef wm8994_drv = 
00087 {
00088   wm8994_Init,
00089   wm8994_DeInit,
00090   wm8994_ReadID,
00091 
00092   wm8994_Play,
00093   wm8994_Pause,
00094   wm8994_Resume,
00095   wm8994_Stop,  
00096 
00097   wm8994_SetFrequency,
00098   wm8994_SetVolume,
00099   wm8994_SetMute,  
00100   wm8994_SetOutputMode,
00101 
00102   wm8994_Reset
00103 };
00104 
00105 static uint32_t outputEnabled = 0;
00106 static uint32_t inputEnabled = 0;
00107 static uint8_t ColdStartup = 1;
00108 
00109 /**
00110   * @}
00111   */ 
00112 
00113 /** @defgroup WM8994_Function_Prototypes
00114   * @{
00115   */
00116 static uint8_t CODEC_IO_Write(uint8_t Addr, uint16_t Reg, uint16_t Value);
00117 /**
00118   * @}
00119   */ 
00120 
00121 
00122 /** @defgroup WM8994_Private_Functions
00123   * @{
00124   */ 
00125 
00126 /**
00127   * @brief Initializes the audio codec and the control interface.
00128   * @param DeviceAddr: Device address on communication Bus.   
00129   * @param OutputInputDevice: can be OUTPUT_DEVICE_SPEAKER, OUTPUT_DEVICE_HEADPHONE,
00130   *  OUTPUT_DEVICE_BOTH, OUTPUT_DEVICE_AUTO, INPUT_DEVICE_DIGITAL_MICROPHONE_1,
00131   *  INPUT_DEVICE_DIGITAL_MICROPHONE_2, INPUT_DEVICE_DIGITAL_MIC1_MIC2, 
00132   *  INPUT_DEVICE_INPUT_LINE_1 or INPUT_DEVICE_INPUT_LINE_2.
00133   * @param Volume: Initial volume level (from 0 (Mute) to 100 (Max))
00134   * @param AudioFreq: Audio Frequency 
00135   * @retval 0 if correct communication, else wrong communication
00136   */
00137 uint32_t wm8994_Init(uint16_t DeviceAddr, uint16_t OutputInputDevice, uint8_t Volume, uint32_t AudioFreq)
00138 {
00139   uint32_t counter = 0;
00140   uint16_t output_device = OutputInputDevice & 0xFF;
00141   uint16_t input_device = OutputInputDevice & 0xFF00;
00142   uint16_t power_mgnt_reg_1 = 0;
00143   
00144   /* Initialize the Control interface of the Audio Codec */
00145   AUDIO_IO_Init();
00146   /* wm8994 Errata Work-Arounds */
00147   counter += CODEC_IO_Write(DeviceAddr, 0x102, 0x0003);
00148   counter += CODEC_IO_Write(DeviceAddr, 0x817, 0x0000);
00149   counter += CODEC_IO_Write(DeviceAddr, 0x102, 0x0000);
00150 
00151   /* Enable VMID soft start (fast), Start-up Bias Current Enabled */
00152   counter += CODEC_IO_Write(DeviceAddr, 0x39, 0x006C);
00153 
00154     /* Enable bias generator, Enable VMID */
00155   if (input_device > 0)
00156   {
00157     counter += CODEC_IO_Write(DeviceAddr, 0x01, 0x0013);
00158   }
00159   else
00160   {
00161     counter += CODEC_IO_Write(DeviceAddr, 0x01, 0x0003);
00162   }
00163 
00164   /* Add Delay */
00165   AUDIO_IO_Delay(50);
00166 
00167   /* Path Configurations for output */
00168   if (output_device > 0)
00169   {
00170     outputEnabled = 1;
00171 
00172     switch (output_device)
00173     {
00174     case OUTPUT_DEVICE_SPEAKER:
00175       /* Enable DAC1 (Left), Enable DAC1 (Right),
00176       Disable DAC2 (Left), Disable DAC2 (Right)*/
00177       counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0C0C);
00178 
00179       /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
00180       counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0000);
00181 
00182       /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
00183       counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0000);
00184 
00185       /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
00186       counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0002);
00187 
00188       /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
00189       counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0002);
00190       break;
00191 
00192     case OUTPUT_DEVICE_HEADPHONE:
00193       /* Disable DAC1 (Left), Disable DAC1 (Right),
00194       Enable DAC2 (Left), Enable DAC2 (Right)*/
00195       counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303);
00196 
00197       /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
00198       counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001);
00199 
00200       /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
00201       counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001);
00202 
00203       /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
00204       counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0000);
00205 
00206       /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
00207       counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0000);
00208       break;
00209 
00210     case OUTPUT_DEVICE_BOTH:
00211       if (input_device == INPUT_DEVICE_DIGITAL_MIC1_MIC2)
00212       {
00213         /* Enable DAC1 (Left), Enable DAC1 (Right),
00214         also Enable DAC2 (Left), Enable DAC2 (Right)*/
00215         counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303 | 0x0C0C);
00216         
00217         /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path
00218         Enable the AIF1 Timeslot 1 (Left) to DAC 1 (Left) mixer path */
00219         counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0003);
00220         
00221         /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path
00222         Enable the AIF1 Timeslot 1 (Right) to DAC 1 (Right) mixer path */
00223         counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0003);
00224         
00225         /* Enable the AIF1 Timeslot 0 (Left) to DAC 2 (Left) mixer path
00226         Enable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path  */
00227         counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0003);
00228         
00229         /* Enable the AIF1 Timeslot 0 (Right) to DAC 2 (Right) mixer path
00230         Enable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
00231         counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0003);
00232       }
00233       else
00234       {
00235         /* Enable DAC1 (Left), Enable DAC1 (Right),
00236         also Enable DAC2 (Left), Enable DAC2 (Right)*/
00237         counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303 | 0x0C0C);
00238         
00239         /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
00240         counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001);
00241         
00242         /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
00243         counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001);
00244         
00245         /* Enable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
00246         counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0002);
00247         
00248         /* Enable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
00249         counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0002);      
00250       }
00251       break;
00252 
00253     case OUTPUT_DEVICE_AUTO :
00254     default:
00255       /* Disable DAC1 (Left), Disable DAC1 (Right),
00256       Enable DAC2 (Left), Enable DAC2 (Right)*/
00257       counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303);
00258 
00259       /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
00260       counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001);
00261 
00262       /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
00263       counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001);
00264 
00265       /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
00266       counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0000);
00267 
00268       /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
00269       counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0000);
00270       break;
00271     }
00272   }
00273   else
00274   {
00275     outputEnabled = 0;
00276   }
00277 
00278   /* Path Configurations for input */
00279   if (input_device > 0)
00280   {
00281     inputEnabled = 1;
00282     switch (input_device)
00283     {
00284     case INPUT_DEVICE_DIGITAL_MICROPHONE_2 :
00285       /* Enable AIF1ADC2 (Left), Enable AIF1ADC2 (Right)
00286        * Enable DMICDAT2 (Left), Enable DMICDAT2 (Right)
00287        * Enable Left ADC, Enable Right ADC */
00288       counter += CODEC_IO_Write(DeviceAddr, 0x04, 0x0C30);
00289 
00290       /* Enable AIF1 DRC2 Signal Detect & DRC in AIF1ADC2 Left/Right Timeslot 1 */
00291       counter += CODEC_IO_Write(DeviceAddr, 0x450, 0x00DB);
00292 
00293       /* Disable IN1L, IN1R, IN2L, IN2R, Enable Thermal sensor & shutdown */
00294       counter += CODEC_IO_Write(DeviceAddr, 0x02, 0x6000);
00295 
00296       /* Enable the DMIC2(Left) to AIF1 Timeslot 1 (Left) mixer path */
00297       counter += CODEC_IO_Write(DeviceAddr, 0x608, 0x0002);
00298 
00299       /* Enable the DMIC2(Right) to AIF1 Timeslot 1 (Right) mixer path */
00300       counter += CODEC_IO_Write(DeviceAddr, 0x609, 0x0002);
00301 
00302       /* GPIO1 pin configuration GP1_DIR = output, GP1_FN = AIF1 DRC2 signal detect */
00303       counter += CODEC_IO_Write(DeviceAddr, 0x700, 0x000E);
00304       break;
00305 
00306     case INPUT_DEVICE_INPUT_LINE_1 :
00307       /* IN1LN_TO_IN1L, IN1LP_TO_VMID, IN1RN_TO_IN1R, IN1RP_TO_VMID */
00308       counter += CODEC_IO_Write(DeviceAddr, 0x28, 0x0011);
00309 
00310       /* Disable mute on IN1L_TO_MIXINL and +30dB on IN1L PGA output */
00311       counter += CODEC_IO_Write(DeviceAddr, 0x29, 0x0035);
00312 
00313       /* Disable mute on IN1R_TO_MIXINL, Gain = +30dB */
00314       counter += CODEC_IO_Write(DeviceAddr, 0x2A, 0x0035);
00315 
00316       /* Enable AIF1ADC1 (Left), Enable AIF1ADC1 (Right)
00317        * Enable Left ADC, Enable Right ADC */
00318       counter += CODEC_IO_Write(DeviceAddr, 0x04, 0x0303);
00319 
00320       /* Enable AIF1 DRC1 Signal Detect & DRC in AIF1ADC1 Left/Right Timeslot 0 */
00321       counter += CODEC_IO_Write(DeviceAddr, 0x440, 0x00DB);
00322 
00323       /* Enable IN1L and IN1R, Disable IN2L and IN2R, Enable Thermal sensor & shutdown */
00324       counter += CODEC_IO_Write(DeviceAddr, 0x02, 0x6350);
00325 
00326       /* Enable the ADCL(Left) to AIF1 Timeslot 0 (Left) mixer path */
00327       counter += CODEC_IO_Write(DeviceAddr, 0x606, 0x0002);
00328 
00329       /* Enable the ADCR(Right) to AIF1 Timeslot 0 (Right) mixer path */
00330       counter += CODEC_IO_Write(DeviceAddr, 0x607, 0x0002);
00331 
00332       /* GPIO1 pin configuration GP1_DIR = output, GP1_FN = AIF1 DRC1 signal detect */
00333       counter += CODEC_IO_Write(DeviceAddr, 0x700, 0x000D);
00334       break;
00335 
00336     case INPUT_DEVICE_DIGITAL_MICROPHONE_1 :
00337       /* Enable AIF1ADC1 (Left), Enable AIF1ADC1 (Right)
00338        * Enable DMICDAT1 (Left), Enable DMICDAT1 (Right)
00339        * Enable Left ADC, Enable Right ADC */
00340       counter += CODEC_IO_Write(DeviceAddr, 0x04, 0x030C);
00341 
00342       /* Enable AIF1 DRC2 Signal Detect & DRC in AIF1ADC1 Left/Right Timeslot 0 */
00343       counter += CODEC_IO_Write(DeviceAddr, 0x440, 0x00DB);
00344 
00345       /* Disable IN1L, IN1R, IN2L, IN2R, Enable Thermal sensor & shutdown */
00346       counter += CODEC_IO_Write(DeviceAddr, 0x02, 0x6350);
00347 
00348       /* Enable the DMIC2(Left) to AIF1 Timeslot 0 (Left) mixer path */
00349       counter += CODEC_IO_Write(DeviceAddr, 0x606, 0x0002);
00350 
00351       /* Enable the DMIC2(Right) to AIF1 Timeslot 0 (Right) mixer path */
00352       counter += CODEC_IO_Write(DeviceAddr, 0x607, 0x0002);
00353 
00354       /* GPIO1 pin configuration GP1_DIR = output, GP1_FN = AIF1 DRC1 signal detect */
00355       counter += CODEC_IO_Write(DeviceAddr, 0x700, 0x000D);
00356       break; 
00357     case INPUT_DEVICE_DIGITAL_MIC1_MIC2 :
00358       /* Enable AIF1ADC1 (Left), Enable AIF1ADC1 (Right)
00359        * Enable DMICDAT1 (Left), Enable DMICDAT1 (Right)
00360        * Enable Left ADC, Enable Right ADC */
00361       counter += CODEC_IO_Write(DeviceAddr, 0x04, 0x0F3C);
00362 
00363       /* Enable AIF1 DRC2 Signal Detect & DRC in AIF1ADC2 Left/Right Timeslot 1 */
00364       counter += CODEC_IO_Write(DeviceAddr, 0x450, 0x00DB);
00365       
00366       /* Enable AIF1 DRC2 Signal Detect & DRC in AIF1ADC1 Left/Right Timeslot 0 */
00367       counter += CODEC_IO_Write(DeviceAddr, 0x440, 0x00DB);
00368 
00369       /* Disable IN1L, IN1R, Enable IN2L, IN2R, Thermal sensor & shutdown */
00370       counter += CODEC_IO_Write(DeviceAddr, 0x02, 0x63A0);
00371 
00372       /* Enable the DMIC2(Left) to AIF1 Timeslot 0 (Left) mixer path */
00373       counter += CODEC_IO_Write(DeviceAddr, 0x606, 0x0002);
00374 
00375       /* Enable the DMIC2(Right) to AIF1 Timeslot 0 (Right) mixer path */
00376       counter += CODEC_IO_Write(DeviceAddr, 0x607, 0x0002);
00377 
00378       /* Enable the DMIC2(Left) to AIF1 Timeslot 1 (Left) mixer path */
00379       counter += CODEC_IO_Write(DeviceAddr, 0x608, 0x0002);
00380 
00381       /* Enable the DMIC2(Right) to AIF1 Timeslot 1 (Right) mixer path */
00382       counter += CODEC_IO_Write(DeviceAddr, 0x609, 0x0002);
00383       
00384       /* GPIO1 pin configuration GP1_DIR = output, GP1_FN = AIF1 DRC1 signal detect */
00385       counter += CODEC_IO_Write(DeviceAddr, 0x700, 0x000D);
00386       break;    
00387     case INPUT_DEVICE_INPUT_LINE_2 :
00388     default:
00389       /* Actually, no other input devices supported */
00390       counter++;
00391       break;
00392     }
00393   }
00394   else
00395   {
00396     inputEnabled = 0;
00397   }
00398   
00399   /*  Clock Configurations */
00400   switch (AudioFreq)
00401   {
00402   case  AUDIO_FREQUENCY_8K:
00403     /* AIF1 Sample Rate = 8 (KHz), ratio=256 */ 
00404     counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0003);
00405     break;
00406     
00407   case  AUDIO_FREQUENCY_16K:
00408     /* AIF1 Sample Rate = 16 (KHz), ratio=256 */ 
00409     counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0033);
00410     break;
00411 
00412   case  AUDIO_FREQUENCY_32K:
00413     /* AIF1 Sample Rate = 32 (KHz), ratio=256 */ 
00414     counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0063);
00415     break;
00416     
00417   case  AUDIO_FREQUENCY_48K:
00418     /* AIF1 Sample Rate = 48 (KHz), ratio=256 */ 
00419     counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0083);
00420     break;
00421     
00422   case  AUDIO_FREQUENCY_96K:
00423     /* AIF1 Sample Rate = 96 (KHz), ratio=256 */ 
00424     counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x00A3);
00425     break;
00426     
00427   case  AUDIO_FREQUENCY_11K:
00428     /* AIF1 Sample Rate = 11.025 (KHz), ratio=256 */ 
00429     counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0013);
00430     break;
00431     
00432   case  AUDIO_FREQUENCY_22K:
00433     /* AIF1 Sample Rate = 22.050 (KHz), ratio=256 */ 
00434     counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0043);
00435     break;
00436     
00437   case  AUDIO_FREQUENCY_44K:
00438     /* AIF1 Sample Rate = 44.1 (KHz), ratio=256 */ 
00439     counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0073);
00440     break; 
00441     
00442   default:
00443     /* AIF1 Sample Rate = 48 (KHz), ratio=256 */ 
00444     counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0083);
00445     break; 
00446   }
00447 
00448   if(input_device == INPUT_DEVICE_DIGITAL_MIC1_MIC2)
00449   {
00450   /* AIF1 Word Length = 16-bits, AIF1 Format = DSP mode */
00451   counter += CODEC_IO_Write(DeviceAddr, 0x300, 0x4018);    
00452   }
00453   else
00454   {
00455   /* AIF1 Word Length = 16-bits, AIF1 Format = I2S (Default Register Value) */
00456   counter += CODEC_IO_Write(DeviceAddr, 0x300, 0x4010);
00457   }
00458   
00459   /* slave mode */
00460   counter += CODEC_IO_Write(DeviceAddr, 0x302, 0x0000);
00461   
00462   /* Enable the DSP processing clock for AIF1, Enable the core clock */
00463   counter += CODEC_IO_Write(DeviceAddr, 0x208, 0x000A);
00464   
00465   /* Enable AIF1 Clock, AIF1 Clock Source = MCLK1 pin */
00466   counter += CODEC_IO_Write(DeviceAddr, 0x200, 0x0001);
00467 
00468   if (output_device > 0)  /* Audio output selected */
00469   {
00470     if (output_device == OUTPUT_DEVICE_HEADPHONE)
00471     {      
00472       /* Select DAC1 (Left) to Left Headphone Output PGA (HPOUT1LVOL) path */
00473       counter += CODEC_IO_Write(DeviceAddr, 0x2D, 0x0100);
00474       
00475       /* Select DAC1 (Right) to Right Headphone Output PGA (HPOUT1RVOL) path */
00476       counter += CODEC_IO_Write(DeviceAddr, 0x2E, 0x0100);    
00477             
00478       /* Startup sequence for Headphone */
00479       if(ColdStartup)
00480       {
00481         counter += CODEC_IO_Write(DeviceAddr,0x110,0x8100);
00482         
00483         ColdStartup=0;
00484         /* Add Delay */
00485         AUDIO_IO_Delay(300);
00486       }
00487       else /* Headphone Warm Start-Up */
00488       { 
00489         counter += CODEC_IO_Write(DeviceAddr,0x110,0x8108);
00490         /* Add Delay */
00491         AUDIO_IO_Delay(50);
00492       }
00493 
00494       /* Soft un-Mute the AIF1 Timeslot 0 DAC1 path L&R */
00495       counter += CODEC_IO_Write(DeviceAddr, 0x420, 0x0000);
00496     }
00497     /* Analog Output Configuration */
00498 
00499     /* Enable SPKRVOL PGA, Enable SPKMIXR, Enable SPKLVOL PGA, Enable SPKMIXL */
00500     counter += CODEC_IO_Write(DeviceAddr, 0x03, 0x0300);
00501 
00502     /* Left Speaker Mixer Volume = 0dB */
00503     counter += CODEC_IO_Write(DeviceAddr, 0x22, 0x0000);
00504 
00505     /* Speaker output mode = Class D, Right Speaker Mixer Volume = 0dB ((0x23, 0x0100) = class AB)*/
00506     counter += CODEC_IO_Write(DeviceAddr, 0x23, 0x0000);
00507 
00508     /* Unmute DAC2 (Left) to Left Speaker Mixer (SPKMIXL) path,
00509     Unmute DAC2 (Right) to Right Speaker Mixer (SPKMIXR) path */
00510     counter += CODEC_IO_Write(DeviceAddr, 0x36, 0x0300);
00511 
00512     /* Enable bias generator, Enable VMID, Enable SPKOUTL, Enable SPKOUTR */
00513     counter += CODEC_IO_Write(DeviceAddr, 0x01, 0x3003);
00514 
00515     /* Headphone/Speaker Enable */
00516 
00517     if (input_device == INPUT_DEVICE_DIGITAL_MIC1_MIC2)
00518     {
00519     /* Enable Class W, Class W Envelope Tracking = AIF1 Timeslots 0 and 1 */
00520     counter += CODEC_IO_Write(DeviceAddr, 0x51, 0x0205);
00521     }
00522     else
00523     {
00524     /* Enable Class W, Class W Envelope Tracking = AIF1 Timeslot 0 */
00525     counter += CODEC_IO_Write(DeviceAddr, 0x51, 0x0005);      
00526     }
00527 
00528     /* Enable bias generator, Enable VMID, Enable HPOUT1 (Left) and Enable HPOUT1 (Right) input stages */
00529     /* idem for Speaker */
00530     power_mgnt_reg_1 |= 0x0303 | 0x3003;
00531     counter += CODEC_IO_Write(DeviceAddr, 0x01, power_mgnt_reg_1);
00532 
00533     /* Enable HPOUT1 (Left) and HPOUT1 (Right) intermediate stages */
00534     counter += CODEC_IO_Write(DeviceAddr, 0x60, 0x0022);
00535 
00536     /* Enable Charge Pump */
00537     counter += CODEC_IO_Write(DeviceAddr, 0x4C, 0x9F25);
00538 
00539     /* Add Delay */
00540     AUDIO_IO_Delay(15);
00541 
00542     /* Select DAC1 (Left) to Left Headphone Output PGA (HPOUT1LVOL) path */
00543     counter += CODEC_IO_Write(DeviceAddr, 0x2D, 0x0001);
00544 
00545     /* Select DAC1 (Right) to Right Headphone Output PGA (HPOUT1RVOL) path */
00546     counter += CODEC_IO_Write(DeviceAddr, 0x2E, 0x0001);
00547 
00548     /* Enable Left Output Mixer (MIXOUTL), Enable Right Output Mixer (MIXOUTR) */
00549     /* idem for SPKOUTL and SPKOUTR */
00550     counter += CODEC_IO_Write(DeviceAddr, 0x03, 0x0030 | 0x0300);
00551 
00552     /* Enable DC Servo and trigger start-up mode on left and right channels */
00553     counter += CODEC_IO_Write(DeviceAddr, 0x54, 0x0033);
00554 
00555     /* Add Delay */
00556     AUDIO_IO_Delay(257);
00557 
00558     /* Enable HPOUT1 (Left) and HPOUT1 (Right) intermediate and output stages. Remove clamps */
00559     counter += CODEC_IO_Write(DeviceAddr, 0x60, 0x00EE);
00560 
00561     /* Unmutes */
00562 
00563     /* Unmute DAC 1 (Left) */
00564     counter += CODEC_IO_Write(DeviceAddr, 0x610, 0x00C0);
00565 
00566     /* Unmute DAC 1 (Right) */
00567     counter += CODEC_IO_Write(DeviceAddr, 0x611, 0x00C0);
00568 
00569     /* Unmute the AIF1 Timeslot 0 DAC path */
00570     counter += CODEC_IO_Write(DeviceAddr, 0x420, 0x0010);
00571 
00572     /* Unmute DAC 2 (Left) */
00573     counter += CODEC_IO_Write(DeviceAddr, 0x612, 0x00C0);
00574 
00575     /* Unmute DAC 2 (Right) */
00576     counter += CODEC_IO_Write(DeviceAddr, 0x613, 0x00C0);
00577 
00578     /* Unmute the AIF1 Timeslot 1 DAC2 path */
00579     counter += CODEC_IO_Write(DeviceAddr, 0x422, 0x0010);
00580     
00581     /* Volume Control */
00582     wm8994_SetVolume(DeviceAddr, Volume);
00583   }
00584 
00585   if (input_device > 0) /* Audio input selected */
00586   {
00587     if ((input_device == INPUT_DEVICE_DIGITAL_MICROPHONE_1) || (input_device == INPUT_DEVICE_DIGITAL_MICROPHONE_2))
00588     {
00589       /* Enable Microphone bias 1 generator, Enable VMID */
00590       power_mgnt_reg_1 |= 0x0013;
00591       counter += CODEC_IO_Write(DeviceAddr, 0x01, power_mgnt_reg_1);
00592 
00593       /* ADC oversample enable */
00594       counter += CODEC_IO_Write(DeviceAddr, 0x620, 0x0002);
00595 
00596       /* AIF ADC2 HPF enable, HPF cut = voice mode 1 fc=127Hz at fs=8kHz */
00597       counter += CODEC_IO_Write(DeviceAddr, 0x411, 0x3800);
00598     }
00599     else if(input_device == INPUT_DEVICE_DIGITAL_MIC1_MIC2)
00600     {
00601       /* Enable Microphone bias 1 generator, Enable VMID */
00602       power_mgnt_reg_1 |= 0x0013;
00603       counter += CODEC_IO_Write(DeviceAddr, 0x01, power_mgnt_reg_1);
00604 
00605       /* ADC oversample enable */
00606       counter += CODEC_IO_Write(DeviceAddr, 0x620, 0x0002);
00607     
00608       /* AIF ADC1 HPF enable, HPF cut = voice mode 1 fc=127Hz at fs=8kHz */
00609       counter += CODEC_IO_Write(DeviceAddr, 0x410, 0x1800);
00610       
00611       /* AIF ADC2 HPF enable, HPF cut = voice mode 1 fc=127Hz at fs=8kHz */
00612       counter += CODEC_IO_Write(DeviceAddr, 0x411, 0x1800);      
00613     }    
00614     else if ((input_device == INPUT_DEVICE_INPUT_LINE_1) || (input_device == INPUT_DEVICE_INPUT_LINE_2))
00615     {
00616 
00617       /* Disable mute on IN1L, IN1L Volume = +0dB */
00618       counter += CODEC_IO_Write(DeviceAddr, 0x18, 0x000B);
00619 
00620       /* Disable mute on IN1R, IN1R Volume = +0dB */
00621       counter += CODEC_IO_Write(DeviceAddr, 0x1A, 0x000B);
00622 
00623       /* AIF ADC1 HPF enable, HPF cut = hifi mode fc=4Hz at fs=48kHz */
00624       counter += CODEC_IO_Write(DeviceAddr, 0x410, 0x1800);
00625     }
00626     /* Volume Control */
00627     wm8994_SetVolume(DeviceAddr, Volume);
00628   }
00629   /* Return communication control value */
00630   return counter;  
00631 }
00632 
00633 /**
00634   * @brief  Deinitializes the audio codec.
00635   * @param  None
00636   * @retval  None
00637   */
00638 void wm8994_DeInit(void)
00639 {
00640   /* Deinitialize Audio Codec interface */
00641   AUDIO_IO_DeInit();
00642 }
00643 
00644 /**
00645   * @brief  Get the WM8994 ID.
00646   * @param DeviceAddr: Device address on communication Bus.
00647   * @retval The WM8994 ID 
00648   */
00649 uint32_t wm8994_ReadID(uint16_t DeviceAddr)
00650 {
00651   /* Initialize the Control interface of the Audio Codec */
00652   AUDIO_IO_Init();
00653 
00654   return ((uint32_t)AUDIO_IO_Read(DeviceAddr, WM8994_CHIPID_ADDR));
00655 }
00656 
00657 /**
00658   * @brief Start the audio Codec play feature.
00659   * @note For this codec no Play options are required.
00660   * @param DeviceAddr: Device address on communication Bus.   
00661   * @retval 0 if correct communication, else wrong communication
00662   */
00663 uint32_t wm8994_Play(uint16_t DeviceAddr, uint16_t* pBuffer, uint16_t Size)
00664 {
00665   uint32_t counter = 0;
00666  
00667   /* Resumes the audio file playing */  
00668   /* Unmute the output first */
00669   counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_OFF);
00670   
00671   return counter;
00672 }
00673 
00674 /**
00675   * @brief Pauses playing on the audio codec.
00676   * @param DeviceAddr: Device address on communication Bus. 
00677   * @retval 0 if correct communication, else wrong communication
00678   */
00679 uint32_t wm8994_Pause(uint16_t DeviceAddr)
00680 {  
00681   uint32_t counter = 0;
00682  
00683   /* Pause the audio file playing */
00684   /* Mute the output first */
00685   counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_ON);
00686   
00687   /* Put the Codec in Power save mode */
00688   counter += CODEC_IO_Write(DeviceAddr, 0x02, 0x01);
00689  
00690   return counter;
00691 }
00692 
00693 /**
00694   * @brief Resumes playing on the audio codec.
00695   * @param DeviceAddr: Device address on communication Bus. 
00696   * @retval 0 if correct communication, else wrong communication
00697   */
00698 uint32_t wm8994_Resume(uint16_t DeviceAddr)
00699 {
00700   uint32_t counter = 0;
00701  
00702   /* Resumes the audio file playing */  
00703   /* Unmute the output first */
00704   counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_OFF);
00705   
00706   return counter;
00707 }
00708 
00709 /**
00710   * @brief Stops audio Codec playing. It powers down the codec.
00711   * @param DeviceAddr: Device address on communication Bus. 
00712   * @param CodecPdwnMode: selects the  power down mode.
00713   *          - CODEC_PDWN_SW: only mutes the audio codec. When resuming from this 
00714   *                           mode the codec keeps the previous initialization
00715   *                           (no need to re-Initialize the codec registers).
00716   *          - CODEC_PDWN_HW: Physically power down the codec. When resuming from this
00717   *                           mode, the codec is set to default configuration 
00718   *                           (user should re-Initialize the codec in order to 
00719   *                            play again the audio stream).
00720   * @retval 0 if correct communication, else wrong communication
00721   */
00722 uint32_t wm8994_Stop(uint16_t DeviceAddr, uint32_t CodecPdwnMode)
00723 {
00724   uint32_t counter = 0;
00725 
00726   if (outputEnabled != 0)
00727   {
00728     /* Mute the output first */
00729     counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_ON);
00730 
00731     if (CodecPdwnMode == CODEC_PDWN_SW)
00732     {
00733       /* Only output mute required*/
00734     }
00735     else /* CODEC_PDWN_HW */
00736     {
00737       /* Mute the AIF1 Timeslot 0 DAC1 path */
00738       counter += CODEC_IO_Write(DeviceAddr, 0x420, 0x0200);
00739 
00740       /* Mute the AIF1 Timeslot 1 DAC2 path */
00741       counter += CODEC_IO_Write(DeviceAddr, 0x422, 0x0200);
00742 
00743       /* Disable DAC1L_TO_HPOUT1L */
00744       counter += CODEC_IO_Write(DeviceAddr, 0x2D, 0x0000);
00745 
00746       /* Disable DAC1R_TO_HPOUT1R */
00747       counter += CODEC_IO_Write(DeviceAddr, 0x2E, 0x0000);
00748 
00749       /* Disable DAC1 and DAC2 */
00750       counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0000);
00751 
00752       /* Reset Codec by writing in 0x0000 address register */
00753       counter += CODEC_IO_Write(DeviceAddr, 0x0000, 0x0000);
00754 
00755       outputEnabled = 0;
00756     }
00757   }
00758   return counter;
00759 }
00760 
00761 /**
00762   * @brief Sets higher or lower the codec volume level.
00763   * @param DeviceAddr: Device address on communication Bus.
00764   * @param Volume: a byte value from 0 to 255 (refer to codec registers 
00765   *         description for more details).
00766   * @retval 0 if correct communication, else wrong communication
00767   */
00768 uint32_t wm8994_SetVolume(uint16_t DeviceAddr, uint8_t Volume)
00769 {
00770   uint32_t counter = 0;
00771   uint8_t convertedvol = VOLUME_CONVERT(Volume);
00772 
00773   /* Output volume */
00774   if (outputEnabled != 0)
00775   {
00776     if(convertedvol > 0x3E)
00777     {
00778       /* Unmute audio codec */
00779       counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_OFF);
00780 
00781       /* Left Headphone Volume */
00782       counter += CODEC_IO_Write(DeviceAddr, 0x1C, 0x3F | 0x140);
00783 
00784       /* Right Headphone Volume */
00785       counter += CODEC_IO_Write(DeviceAddr, 0x1D, 0x3F | 0x140);
00786 
00787       /* Left Speaker Volume */
00788       counter += CODEC_IO_Write(DeviceAddr, 0x26, 0x3F | 0x140);
00789 
00790       /* Right Speaker Volume */
00791       counter += CODEC_IO_Write(DeviceAddr, 0x27, 0x3F | 0x140);
00792     }
00793     else if (Volume == 0)
00794     {
00795       /* Mute audio codec */
00796       counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_ON);
00797     }
00798     else
00799     {
00800       /* Unmute audio codec */
00801       counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_OFF);
00802 
00803       /* Left Headphone Volume */
00804       counter += CODEC_IO_Write(DeviceAddr, 0x1C, convertedvol | 0x140);
00805 
00806       /* Right Headphone Volume */
00807       counter += CODEC_IO_Write(DeviceAddr, 0x1D, convertedvol | 0x140);
00808 
00809       /* Left Speaker Volume */
00810       counter += CODEC_IO_Write(DeviceAddr, 0x26, convertedvol | 0x140);
00811 
00812       /* Right Speaker Volume */
00813       counter += CODEC_IO_Write(DeviceAddr, 0x27, convertedvol | 0x140);
00814     }
00815   }
00816 
00817   /* Input volume */
00818   if (inputEnabled != 0)
00819   {
00820     convertedvol = VOLUME_IN_CONVERT(Volume);
00821 
00822     /* Left AIF1 ADC1 volume */
00823     counter += CODEC_IO_Write(DeviceAddr, 0x400, convertedvol | 0x100);
00824 
00825     /* Right AIF1 ADC1 volume */
00826     counter += CODEC_IO_Write(DeviceAddr, 0x401, convertedvol | 0x100);
00827 
00828     /* Left AIF1 ADC2 volume */
00829     counter += CODEC_IO_Write(DeviceAddr, 0x404, convertedvol | 0x100);
00830 
00831     /* Right AIF1 ADC2 volume */
00832     counter += CODEC_IO_Write(DeviceAddr, 0x405, convertedvol | 0x100);
00833   }
00834   return counter;
00835 }
00836 
00837 /**
00838   * @brief Enables or disables the mute feature on the audio codec.
00839   * @param DeviceAddr: Device address on communication Bus.   
00840   * @param Cmd: AUDIO_MUTE_ON to enable the mute or AUDIO_MUTE_OFF to disable the
00841   *             mute mode.
00842   * @retval 0 if correct communication, else wrong communication
00843   */
00844 uint32_t wm8994_SetMute(uint16_t DeviceAddr, uint32_t Cmd)
00845 {
00846   uint32_t counter = 0;
00847   
00848   if (outputEnabled != 0)
00849   {
00850     /* Set the Mute mode */
00851     if(Cmd == AUDIO_MUTE_ON)
00852     {
00853       /* Soft Mute the AIF1 Timeslot 0 DAC1 path L&R */
00854       counter += CODEC_IO_Write(DeviceAddr, 0x420, 0x0200);
00855 
00856       /* Soft Mute the AIF1 Timeslot 1 DAC2 path L&R */
00857       counter += CODEC_IO_Write(DeviceAddr, 0x422, 0x0200);
00858     }
00859     else /* AUDIO_MUTE_OFF Disable the Mute */
00860     {
00861       /* Unmute the AIF1 Timeslot 0 DAC1 path L&R */
00862       counter += CODEC_IO_Write(DeviceAddr, 0x420, 0x0010);
00863 
00864       /* Unmute the AIF1 Timeslot 1 DAC2 path L&R */
00865       counter += CODEC_IO_Write(DeviceAddr, 0x422, 0x0010);
00866     }
00867   }
00868   return counter;
00869 }
00870 
00871 /**
00872   * @brief Switch dynamically (while audio file is played) the output target 
00873   *         (speaker or headphone).
00874   * @param DeviceAddr: Device address on communication Bus.
00875   * @param Output: specifies the audio output target: OUTPUT_DEVICE_SPEAKER,
00876   *         OUTPUT_DEVICE_HEADPHONE, OUTPUT_DEVICE_BOTH or OUTPUT_DEVICE_AUTO 
00877   * @retval 0 if correct communication, else wrong communication
00878   */
00879 uint32_t wm8994_SetOutputMode(uint16_t DeviceAddr, uint8_t Output)
00880 {
00881   uint32_t counter = 0; 
00882   
00883   switch (Output) 
00884   {
00885   case OUTPUT_DEVICE_SPEAKER:
00886     /* Enable DAC1 (Left), Enable DAC1 (Right), 
00887     Disable DAC2 (Left), Disable DAC2 (Right)*/
00888     counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0C0C);
00889     
00890     /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
00891     counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0000);
00892     
00893     /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
00894     counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0000);
00895     
00896     /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
00897     counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0002);
00898     
00899     /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
00900     counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0002);
00901     break;
00902     
00903   case OUTPUT_DEVICE_HEADPHONE:
00904     /* Disable DAC1 (Left), Disable DAC1 (Right), 
00905     Enable DAC2 (Left), Enable DAC2 (Right)*/
00906     counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303);
00907     
00908     /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
00909     counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001);
00910     
00911     /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
00912     counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001);
00913     
00914     /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
00915     counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0000);
00916     
00917     /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
00918     counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0000);
00919     break;
00920     
00921   case OUTPUT_DEVICE_BOTH:
00922     /* Enable DAC1 (Left), Enable DAC1 (Right), 
00923     also Enable DAC2 (Left), Enable DAC2 (Right)*/
00924     counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303 | 0x0C0C);
00925     
00926     /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
00927     counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001);
00928     
00929     /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
00930     counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001);
00931     
00932     /* Enable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
00933     counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0002);
00934     
00935     /* Enable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
00936     counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0002);
00937     break;
00938     
00939   default:
00940     /* Disable DAC1 (Left), Disable DAC1 (Right), 
00941     Enable DAC2 (Left), Enable DAC2 (Right)*/
00942     counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303);
00943     
00944     /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
00945     counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001);
00946     
00947     /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
00948     counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001);
00949     
00950     /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
00951     counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0000);
00952     
00953     /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
00954     counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0000);
00955     break;    
00956   }  
00957   return counter;
00958 }
00959 
00960 /**
00961   * @brief Sets new frequency.
00962   * @param DeviceAddr: Device address on communication Bus.
00963   * @param AudioFreq: Audio frequency used to play the audio stream.
00964   * @retval 0 if correct communication, else wrong communication
00965   */
00966 uint32_t wm8994_SetFrequency(uint16_t DeviceAddr, uint32_t AudioFreq)
00967 {
00968   uint32_t counter = 0;
00969  
00970   /*  Clock Configurations */
00971   switch (AudioFreq)
00972   {
00973   case  AUDIO_FREQUENCY_8K:
00974     /* AIF1 Sample Rate = 8 (KHz), ratio=256 */ 
00975     counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0003);
00976     break;
00977     
00978   case  AUDIO_FREQUENCY_16K:
00979     /* AIF1 Sample Rate = 16 (KHz), ratio=256 */ 
00980     counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0033);
00981     break;
00982 
00983   case  AUDIO_FREQUENCY_32K:
00984     /* AIF1 Sample Rate = 32 (KHz), ratio=256 */ 
00985     counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0063);
00986     break;
00987     
00988   case  AUDIO_FREQUENCY_48K:
00989     /* AIF1 Sample Rate = 48 (KHz), ratio=256 */ 
00990     counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0083);
00991     break;
00992     
00993   case  AUDIO_FREQUENCY_96K:
00994     /* AIF1 Sample Rate = 96 (KHz), ratio=256 */ 
00995     counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x00A3);
00996     break;
00997     
00998   case  AUDIO_FREQUENCY_11K:
00999     /* AIF1 Sample Rate = 11.025 (KHz), ratio=256 */ 
01000     counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0013);
01001     break;
01002     
01003   case  AUDIO_FREQUENCY_22K:
01004     /* AIF1 Sample Rate = 22.050 (KHz), ratio=256 */ 
01005     counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0043);
01006     break;
01007     
01008   case  AUDIO_FREQUENCY_44K:
01009     /* AIF1 Sample Rate = 44.1 (KHz), ratio=256 */ 
01010     counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0073);
01011     break; 
01012     
01013   default:
01014     /* AIF1 Sample Rate = 48 (KHz), ratio=256 */ 
01015     counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0083);
01016     break; 
01017   }
01018   return counter;
01019 }
01020 
01021 /**
01022   * @brief Resets wm8994 registers.
01023   * @param DeviceAddr: Device address on communication Bus. 
01024   * @retval 0 if correct communication, else wrong communication
01025   */
01026 uint32_t wm8994_Reset(uint16_t DeviceAddr)
01027 {
01028   uint32_t counter = 0;
01029   
01030   /* Reset Codec by writing in 0x0000 address register */
01031   counter = CODEC_IO_Write(DeviceAddr, 0x0000, 0x0000);
01032   outputEnabled = 0;
01033   inputEnabled=0;
01034 
01035   return counter;
01036 }
01037 
01038 /**
01039   * @brief  Writes/Read a single data.
01040   * @param  Addr: I2C address
01041   * @param  Reg: Reg address 
01042   * @param  Value: Data to be written
01043   * @retval None
01044   */
01045 static uint8_t CODEC_IO_Write(uint8_t Addr, uint16_t Reg, uint16_t Value)
01046 {
01047   uint32_t result = 0;
01048   
01049  AUDIO_IO_Write(Addr, Reg, Value);
01050   
01051 #ifdef VERIFY_WRITTENDATA
01052   /* Verify that the data has been correctly written */
01053   result = (AUDIO_IO_Read(Addr, Reg) == Value)? 0:1;
01054 #endif /* VERIFY_WRITTENDATA */
01055   
01056   return result;
01057 }
01058 
01059 /**
01060   * @}
01061   */
01062 
01063 /**
01064   * @}
01065   */
01066 
01067 /**
01068   * @}
01069   */
01070 
01071 /**
01072   * @}
01073   */
01074 
01075 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/