Anh Tran
test public
Dependencies: HttpServer_snapshot_mbed-os
Embed:
(wiki syntax)
Show/hide line numbers
gr_board_vdc5.h
Go to the documentation of this file.
00001 /******************************************************************************* 00002 * DISCLAIMER 00003 * This software is supplied by Renesas Electronics Corporation and is only 00004 * intended for use with Renesas products. No other uses are authorized. This 00005 * software is owned by Renesas Electronics Corporation and is protected under 00006 * all applicable laws, including copyright laws. 00007 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING 00008 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT 00009 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE 00010 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. 00011 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS 00012 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE 00013 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR 00014 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE 00015 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 00016 * Renesas reserves the right, without notice, to make changes to this software 00017 * and to discontinue the availability of this software. By using this software, 00018 * you agree to the additional terms and conditions found by accessing the 00019 * following link: 00020 * http://www.renesas.com/disclaimer 00021 * Copyright (C) 2017 Renesas Electronics Corporation. All rights reserved. 00022 *******************************************************************************/ 00023 /**************************************************************************//** 00024 * @file gr_board_vdc5.h 00025 * @version 1.00 00026 * $Rev: 199 $ 00027 * $Date:: 2014-05-23 16:33:52 +0900#$ 00028 * @brief Graphics driver wrapper function definitions in C 00029 ******************************************************************************/ 00030 00031 #ifndef GR_BOARD_VDC5_H 00032 #define GR_BOARD_VDC5_H 00033 00034 /****************************************************************************** 00035 Includes <System Includes> , "Project Includes" 00036 ******************************************************************************/ 00037 #include <stdlib.h> 00038 00039 #include "r_typedefs.h" 00040 #if defined(TARGET_RZ_A1XX) 00041 #include "r_vdc5.h" 00042 #else 00043 #include "r_vdc.h" 00044 #define vdc5_irq_handler vdc_irq_handler 00045 #define vdc5_int_type_t vdc_int_type_t 00046 #endif 00047 #include "pinmap.h" 00048 00049 #ifdef __cplusplus 00050 extern "C" 00051 { 00052 #endif /* __cplusplus */ 00053 00054 /****************************************************************************** 00055 Macro definitions 00056 ******************************************************************************/ 00057 00058 #define VSYNC_1_2_FH_TIMING (858u) /* Vsync signal 1/2fH phase timing */ 00059 #define VSYNC_1_4_FH_TIMING (429u) /* Vsync signal 1/4fH phase timing */ 00060 #define DEFAULT_INPUT_CLOCK (66.67) /* P1 clock VDC5 */ 00061 #define DEFAULT_OUTPUT_CLOCK (66.67) /* LVDS output clock */ 00062 00063 #define IMGCAP_SIZE_NTSC_HS (122u) 00064 #define IMGCAP_SIZE_NTSC_HW (720u) 00065 #define IMGCAP_SIZE_NTSC_VS (16u) 00066 #define IMGCAP_SIZE_NTSC_VW (240u) 00067 00068 #define IMGCAP_SIZE_PAL_HS (132u) 00069 #define IMGCAP_SIZE_PAL_HW (720u) 00070 #define IMGCAP_SIZE_PAL_VS (19u) 00071 #define IMGCAP_SIZE_PAL_VW (280u) 00072 00073 typedef void (*vdc5_irq_handler)(uint32_t int_sense); 00074 00075 /* video channel select */ 00076 typedef enum { 00077 DRV_VIDEO_INPUT_CHANNEL_0 = 0, /* video input channel 0 */ 00078 DRV_VIDEO_INPUT_CHANNEL_1 /* video input channel 1 */ 00079 } drv_video_input_channel_t; 00080 00081 /* input pin control */ 00082 typedef enum { 00083 DRV_VIDEO_ADC_VINSEL_VIN1 = 0, /* VIN1 input */ 00084 DRV_VIDEO_ADC_VINSEL_VIN2 /* VIN2 input */ 00085 } drv_video_adc_vinsel_t; 00086 00087 /* graphics layer select */ 00088 typedef enum { 00089 DRV_GRAPHICS_LAYER_0 = 0, /* graphics layer 0 */ 00090 DRV_GRAPHICS_LAYER_1, /* graphics layer 1 */ 00091 DRV_GRAPHICS_LAYER_2, /* graphics layer 2 */ 00092 DRV_GRAPHICS_LAYER_3 /* graphics layer 3 */ 00093 } drv_graphics_layer_t; 00094 00095 /* error codes */ 00096 typedef enum { 00097 DRV_GRAPHICS_OK = 0, /* Normal termination */ 00098 DRV_GRAPHICS_VDC5_ERR = -1, /* VDC5 error */ 00099 DRV_GRAPHICS_FORMAT_ERR = -2, /* Not support format */ 00100 DRV_GRAPHICS_LAYER_ERR = -3, /* Invalid layer ID error */ 00101 DRV_GRAPHICS_CHANNEL_ERR = -4, /* Invalid channel error */ 00102 DRV_GRAPHICS_VIDEO_NTSC_SIZE_ERR = -5, /* Video Write */ 00103 DRV_GRAPHICS_VIDEO_PAL_SIZE_ERR = -6, /* Video Write */ 00104 DRV_GRAPHICS_PARAM_RANGE_ERR = -7 /* Parameter range error */ 00105 } drv_graphics_error_t; 00106 00107 /* graphics layer format select */ 00108 typedef enum { 00109 DRV_GRAPHICS_FORMAT_YCBCR422 = 0, /* YCbCr422 */ 00110 DRV_GRAPHICS_FORMAT_RGB565, /* RGB565 */ 00111 DRV_GRAPHICS_FORMAT_RGB888, /* RGB888 */ 00112 DRV_GRAPHICS_FORMAT_ARGB8888, /* ARGB8888 */ 00113 DRV_GRAPHICS_FORMAT_ARGB4444, /* ARGB4444 */ 00114 DRV_GRAPHICS_FORMAT_CLUT8, /* CLUT8 */ 00115 DRV_GRAPHICS_FORMAT_CLUT4, /* CLUT4 */ 00116 DRV_GRAPHICS_FORMAT_CLUT1 /* CLUT1 */ 00117 } drv_graphics_format_t; 00118 00119 /* video writing format select */ 00120 typedef enum { 00121 DRV_VIDEO_FORMAT_YCBCR422 = 0, /* YCbCr422 */ 00122 DRV_VIDEO_FORMAT_RGB565, /* RGB565 */ 00123 DRV_VIDEO_FORMAT_RGB888, /* RGB888 */ 00124 DRV_VIDEO_FORMAT_RAW8 /* RAW8 */ 00125 } drv_video_format_t; 00126 00127 00128 /* lcd tcon output pin select */ 00129 typedef enum { 00130 DRV_LCD_TCON_PIN_NON = -1, /* Not using output */ 00131 DRV_LCD_TCON_PIN_0, /* LCD_TCON0 */ 00132 DRV_LCD_TCON_PIN_1, /* LCD_TCON1 */ 00133 DRV_LCD_TCON_PIN_2 /* LCD_TCON2 */ 00134 } drv_lcd_tcon_pin_t; 00135 00136 /* lcd output format select */ 00137 typedef enum { 00138 DRV_LCD_OUTFORMAT_RGB888 = 0, /* RGB888 or LVDS */ 00139 DRV_LCD_OUTFORMAT_RGB666, /* RGB666 */ 00140 DRV_LCD_OUTFORMAT_RGB565 /* RGB565 */ 00141 } drv_lcd_outformat_t; 00142 00143 /* frame buffer swap setting */ 00144 typedef enum { 00145 DRV_WR_RD_WRSWA_NON = 0, /* Not swapped: 1-2-3-4-5-6-7-8 */ 00146 DRV_WR_RD_WRSWA_8BIT, /* Swapped in 8-bit units: 2-1-4-3-6-5-8-7 */ 00147 DRV_WR_RD_WRSWA_16BIT, /* Swapped in 16-bit units: 3-4-1-2-7-8-5-6 */ 00148 DRV_WR_RD_WRSWA_16_8BIT, /* Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5 */ 00149 DRV_WR_RD_WRSWA_32BIT, /* Swapped in 32-bit units: 5-6-7-8-1-2-3-4 */ 00150 DRV_WR_RD_WRSWA_32_8BIT, /* Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3 */ 00151 DRV_WR_RD_WRSWA_32_16BIT, /* Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2 */ 00152 DRV_WR_RD_WRSWA_32_16_8BIT, /* Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1 */ 00153 } drv_wr_rd_swa_t; 00154 00155 /* edge of a signal */ 00156 typedef enum { 00157 DRV_EDGE_RISING = 0, /* Rising edge */ 00158 DRV_EDGE_FALLING = 1 /* Falling edge */ 00159 } drv_edge_t; 00160 00161 /* lcd type */ 00162 typedef enum { 00163 DRV_LCD_TYPE_LVDS = 0, /* LVDS signal control */ 00164 DRV_LCD_TYPE_PARALLEL_RGB /* RGB parallel signal control */ 00165 } drv_lcd_type_t; 00166 00167 /* Polarity of a signal */ 00168 typedef enum { 00169 DRV_SIG_POL_NOT_INVERTED = 0, /* Not inverted */ 00170 DRV_SIG_POL_INVERTED /* Inverted */ 00171 } drv_sig_pol_t; 00172 00173 /* Video color system */ 00174 typedef enum { 00175 DRV_COL_SYS_NTSC_358 = 0, /* NTSC-3.58 */ 00176 DVV_COL_SYS_NTSC_443 = 1, /* NTSC-4.43 */ 00177 DRV_COL_SYS_PAL_443 = 2, /* PAL-4.43 */ 00178 DRV_COL_SYS_PAL_M = 3, /* PAL-M */ 00179 DRV_COL_SYS_PAL_N = 4, /* PAL-N */ 00180 DRV_COL_SYS_SECAM = 5, /* SECAM */ 00181 DRV_COL_SYS_NTSC_443_60 = 6, /* NTSC-4.43 (60Hz) */ 00182 DRV_COL_SYS_PAL_60 = 7, /* PAL-60 */ 00183 } drv_graphics_video_col_sys_t; 00184 00185 /* External Input select */ 00186 typedef enum { 00187 DRV_INPUT_SEL_VDEC = 0, /*!< Video decoder output signals */ 00188 DRV_INPUT_SEL_EXT = 1, /*!< Signals supplied via the external input pins */ 00189 DRV_INPUT_SEL_CEU = 2, /*!< Signals supplied via the CEU input pins */ 00190 DRV_INPUT_SEL_MIPI = 3 /*!< Signals supplied via the MIPI input pins */ 00191 } drv_video_input_sel_t ; 00192 00193 /* External input format select */ 00194 typedef enum { 00195 DRV_VIDEO_EXTIN_FORMAT_RGB888 = 0, /*!< RGB888 Not support */ 00196 DRV_VIDEO_EXTIN_FORMAT_RGB666 , /*!< RGB666 */ 00197 DRV_VIDEO_EXTIN_FORMAT_RGB565 , /*!< RGB565 */ 00198 DRV_VIDEO_EXTIN_FORMAT_BT656 , /*!< BT6556 */ 00199 DRV_VIDEO_EXTIN_FORMAT_BT601 , /*!< BT6501 */ 00200 DRV_VIDEO_EXTIN_FORMAT_YCBCR422 , /*!< YCbCr422 */ 00201 DRV_VIDEO_EXTIN_FORMAT_YCBCR444 , /*!< YCbCr444 Not support */ 00202 } drv_video_extin_format_t ; 00203 00204 /* On/off */ 00205 typedef enum { 00206 DRV_OFF = 0, /*!< Off */ 00207 DRV_ON = 1 /*!< On */ 00208 } drv_onoff_t ; 00209 00210 /* Number of lines for BT.656 external input */ 00211 typedef enum { 00212 DRV_EXTIN_LINE_525 = 0, /*!< 525 lines */ 00213 DRV_EXTIN_LINE_625 = 1 /*!< 625 lines */ 00214 } drv_extin_input_line_t ; 00215 00216 /* Y/Cb/Y/Cr data string start timing */ 00217 typedef enum { 00218 DRV_EXTIN_H_POS_CBYCRY = 0, /*!< Cb/Y/Cr/Y (BT656/601), Cb/Cr (YCbCr422) */ 00219 DRV_EXTIN_H_POS_YCRYCB , /*!< Y/Cr/Y/Cb (BT656/601), setting prohibited (YCbCr422) */ 00220 DRV_EXTIN_H_POS_CRYCBY , /*!< Cr/Y/Cb/Y (BT656/601), setting prohibited (YCbCr422) */ 00221 DRV_EXTIN_H_POS_YCBYCR , /*!< Y/Cb/Y/Cr (BT656/601), Cr/Cb (YCbCr422) */ 00222 } drv_extin_h_pos_t ; 00223 00224 /* The relative position within the graphics display area */ 00225 typedef struct { 00226 uint16_t vs; /* Vertical start pos */ 00227 uint16_t vw; /* Vertical width (height) */ 00228 uint16_t hs; /* Horizontal start pos */ 00229 uint16_t hw; /* Horizontal width */ 00230 } drv_rect_t; 00231 00232 /*! CLUT setup parameter */ 00233 typedef struct { 00234 uint32_t color_num ; /*!< The number of colors in CLUT */ 00235 const uint32_t * clut ; /*!< Address of the area storing the CLUT data (in ARGB8888 format) */ 00236 } drv_clut_t ; 00237 00238 /* lcd configuration */ 00239 typedef struct { 00240 drv_lcd_type_t lcd_type; /* LVDS or Pararel RGB */ 00241 double intputClock; /* P1 clk [MHz] ex. 66.67 */ 00242 double outputClock; /* LCD clk [MHz] ex. 33.33 */ 00243 00244 drv_lcd_outformat_t lcd_outformat; /* Output format select */ 00245 drv_edge_t lcd_edge; /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */ 00246 00247 uint16_t h_toatal_period; /* Free-running Hsync period */ 00248 uint16_t v_toatal_period; /* Free-running Vsync period */ 00249 uint16_t h_disp_widht; /* LCD display area size, horizontal width */ 00250 uint16_t v_disp_widht; /* LCD display area size, vertical width */ 00251 uint16_t h_back_porch; /* LCD display horizontal back porch period */ 00252 uint16_t v_back_porch; /* LCD display vertical back porch period */ 00253 00254 drv_lcd_tcon_pin_t h_sync_port; /* TCONn or Not use(-1) */ 00255 drv_sig_pol_t h_sync_port_polarity; /* Polarity inversion control of signal */ 00256 uint16_t h_sync_width; /* Hsync width */ 00257 00258 drv_lcd_tcon_pin_t v_sync_port; /* TCONn or Not use(-1) */ 00259 drv_sig_pol_t v_sync_port_polarity; /* Polarity inversion control of signal */ 00260 uint16_t v_sync_width; /* Vsync width */ 00261 00262 drv_lcd_tcon_pin_t de_port; /* TCONn or Not use(-1) */ 00263 drv_sig_pol_t de_port_polarity; /* Polarity inversion control of signal */ 00264 00265 } drv_lcd_config_t; 00266 00267 /* Digital video input configuration */ 00268 typedef struct { 00269 drv_video_extin_format_t inp_format; /*!< External Input Format Select */ 00270 drv_edge_t inp_pxd_edge; /*!< Clock Edge Select for Capturing External Input Video Image */ 00271 drv_edge_t inp_vs_edge; /*!< Clock Edge Select for Capturing External Input Vsync Signal */ 00272 drv_edge_t inp_hs_edge; /*!< Clock Edge Select for Capturing External Input Hsync Signal */ 00273 drv_onoff_t inp_endian_on; /*!< External Input B/R Signal Swap On/Off Control */ 00274 drv_onoff_t inp_swap_on; /*!< External Input Bit Endian Change On/Off Control */ 00275 drv_sig_pol_t inp_vs_inv; /*!< External Input Vsync Signal DV_VSYNC Inversion Control */ 00276 drv_sig_pol_t inp_hs_inv; /*!< External Input Hsync Signal DV_HSYNC Inversion Control */ 00277 drv_extin_input_line_t inp_f525_625; /*!< Number of lines for BT.656 external input */ 00278 drv_extin_h_pos_t inp_h_pos; /*!< Y/Cb/Y/Cr data string start timing to Hsync reference */ 00279 unsigned short cap_vs_pos; /*!< Capture start position from Vsync */ 00280 unsigned short cap_hs_pos; /*!< Capture start position form Hsync */ 00281 unsigned short cap_width; /*!< Capture width */ 00282 unsigned short cap_height; /*!< Capture height should be a multiple of 4.*/ 00283 } drv_video_ext_in_config_t; 00284 00285 /* mipi phy timing struct */ 00286 typedef struct 00287 { 00288 uint16_t mipi_ths_prepare; /*!< Setting of the duration of the LP-00 state (immediately before entry to the HS-0 state) */ 00289 uint16_t mipi_ths_settle; /*!< Setting of the period in which a transition to the HS state is ignored after the TTHS_PREPARE period begins */ 00290 uint16_t mipi_tclk_prepare; /*!< Setting of the duration of the LP-00 state (immediately before entry to the HS-0) */ 00291 uint16_t mipi_tclk_settle; /*!< Setting of the period in which a transition to the HS state is ignored after the TCLK_PREPARE period begins */ 00292 uint16_t mipi_tclk_miss; /*!< Setting of the period in which the absence of the clock is detected, and the HS-RX is disabled */ 00293 uint16_t mipi_t_init_slave; /*!< Minimum duration of the INIT state */ 00294 } drv_mipi_phy_timing_t; 00295 00296 /* mipi parameter struct */ 00297 typedef struct 00298 { 00299 uint8_t mipi_lanenum; /*!< Mipi Lane Num */ 00300 uint8_t mipi_vc; /*!< Mipi Virtual Channel */ 00301 uint8_t mipi_interlace; /*!< Interlace or Progressive */ 00302 uint8_t mipi_laneswap; /*!< Mipi Lane Swap Setting */ 00303 uint16_t mipi_frametop; /*!< (for Interlace)Top Field Packet ID */ 00304 uint16_t mipi_outputrate; /*!< Mipi Data Send Speed(Mbit per sec) */ 00305 drv_mipi_phy_timing_t mipi_phy_timing; /*!< Mipi D-PHY timing settings */ 00306 } drv_mipi_param_t; 00307 00308 /*! Vin parameter Struct */ 00309 typedef struct 00310 { 00311 uint16_t vin_preclip_starty ; /*!< Pre Area Clip Start Line */ 00312 uint16_t vin_preclip_endy ; /*!< Pre Area Clip End Line */ 00313 uint16_t vin_preclip_startx ; /*!< Pre Area Clip Start Column */ 00314 uint16_t vin_preclip_endx ; /*!< Pre Area Clip End Column */ 00315 } drv_vin_preclip_t ; 00316 00317 typedef struct 00318 { 00319 uint8_t vin_scaleon; /*!< Scaling On or OFF */ 00320 uint8_t vin_interpolation; /*!< Scaling Interpolation */ 00321 uint16_t vin_scale_h; /*!< Horizontal multiple */ 00322 uint16_t vin_scale_v; /*!< vertical multiple */ 00323 } drv_vin_scale_t; 00324 00325 typedef struct 00326 { 00327 uint16_t vin_afterclip_size_x; /*!< After Area Clip horizontal size */ 00328 uint16_t vin_afterclip_size_y; /*!< After Area Clip vertical size */ 00329 } drv_vin_afterclip_t; 00330 00331 /*! YCbCr422 input data alignment */ 00332 typedef enum 00333 { 00334 __VIN_Y_UPPER = 0, /*!< Upper bit is Y, lower bit is CbCr */ 00335 __VIN_CB_UPPER , /*!< Upper bit is CbCr, lower bit is Y */ 00336 } drv_vin_input_align_t ; 00337 00338 /*! Output data byte swap mode */ 00339 typedef enum 00340 { 00341 __VIN_SWAP_OFF = 0, /*!< Not swap */ 00342 __VIN_SWAP_ON , /*!< Swap */ 00343 } drv_vin_output_swap_t ; 00344 00345 typedef struct 00346 { 00347 drv_vin_preclip_t vin_preclip; /*!< Pre Area Clip Parameter */ 00348 drv_vin_scale_t vin_scale; /*!< Scale Parameter */ 00349 drv_vin_afterclip_t vin_afterclip; /*!< After Area Clip Parameter */ 00350 uint8_t vin_yuv_clip; /*!< YUV Range Clip Parameter */ 00351 uint8_t vin_lut; /*!< LUT Conversion On or OFF */ 00352 uint8_t vin_inputformat; /*!< Input Image Format */ 00353 uint8_t vin_outputformat; /*!< Output Image Format */ 00354 uint8_t vin_outputendian; /*!< Output Data Endian*/ 00355 uint8_t vin_dither; /*!< (for RGB565 or ARGB1555)Output Data Dithering On or Off */ 00356 uint8_t vin_interlace; /*!< (for Interlace input)Capture Method */ 00357 uint8_t vin_alpha_val8; /*!< (for ARGB8888)Alpha Value */ 00358 uint8_t vin_alpha_val1; /*!< (for ARGB1555)Alpha Value */ 00359 uint16_t vin_stride; /*!< Stride (byte) */ 00360 uint32_t vin_ycoffset; /*!< (for YC separate output)Address Offset Value */ 00361 drv_vin_input_align_t vin_input_align; /*!< YCbCr422 input data alignment */ 00362 drv_vin_output_swap_t vin_output_swap; /*!< Output data byte swap mode */ 00363 } drv_vin_setup_t; 00364 00365 /****************************************************************************** 00366 Typedef definitions 00367 ******************************************************************************/ 00368 00369 /****************************************************************************** 00370 Exported global functions (to be accessed by other files) 00371 ******************************************************************************/ 00372 drv_graphics_error_t DRV_Graphics_Init( drv_lcd_config_t * drv_lcd_config ); 00373 drv_graphics_error_t DRV_Graphics_Video_init( drv_video_input_sel_t drv_video_input_sel, drv_video_ext_in_config_t * drv_video_ext_in_config ); 00374 00375 drv_graphics_error_t DRV_Graphics_Lcd_Port_Init( PinName *pin, uint32_t pin_count ); 00376 drv_graphics_error_t DRV_Graphics_Lvds_Port_Init( PinName *pin, uint32_t pin_count ); 00377 drv_graphics_error_t DRV_Graphics_Dvinput_Port_Init( PinName *pin, uint32_t pin_count ); 00378 drv_graphics_error_t DRV_Graphics_CEU_Port_Init( PinName *pin, uint32_t pin_count ); 00379 00380 drv_graphics_error_t DRV_Graphics_Irq_Handler_Set( vdc5_int_type_t irq, uint16_t num, void (* callback)(vdc5_int_type_t) ); 00381 00382 drv_graphics_error_t DRV_Graphics_Start ( drv_graphics_layer_t layer_id ); 00383 drv_graphics_error_t DRV_Graphics_Stop ( drv_graphics_layer_t layer_id ); 00384 drv_graphics_error_t DRV_Video_Start ( drv_video_input_channel_t video_input_ch ); 00385 drv_graphics_error_t DRV_Video_Stop ( drv_video_input_channel_t video_input_ch ); 00386 00387 drv_graphics_error_t DRV_Graphics_Read_Setting ( 00388 drv_graphics_layer_t layer_id, 00389 void * framebuff, 00390 uint32_t fb_stride, 00391 drv_graphics_format_t gr_format, 00392 drv_wr_rd_swa_t wr_rd_swa, 00393 drv_rect_t * gr_rect, 00394 drv_clut_t * gr_clut ); 00395 00396 drv_graphics_error_t DRV_Graphics_Read_Change ( 00397 drv_graphics_layer_t layer_id, 00398 void * framebuff); 00399 00400 drv_graphics_error_t DRV_Video_Write_Setting ( 00401 drv_video_input_channel_t video_input_ch, 00402 drv_graphics_video_col_sys_t col_sys, 00403 void * framebuff, 00404 uint32_t fb_stride, 00405 drv_video_format_t video_format, 00406 drv_wr_rd_swa_t wr_rd_swa, 00407 uint16_t video_write_buff_vw, 00408 uint16_t video_write_buff_hw, 00409 drv_video_adc_vinsel_t video_adc_vinsel ); 00410 00411 drv_graphics_error_t DRV_Video_Write_Setting_Digital ( 00412 void * framebuff, 00413 uint32_t fb_stride, 00414 drv_video_format_t video_format, 00415 drv_wr_rd_swa_t wr_rd_swa, 00416 uint16_t video_write_buff_vw, 00417 uint16_t video_write_buff_hw, 00418 drv_rect_t * cap_area ); 00419 00420 drv_graphics_error_t DRV_Video_Write_Setting_Ceu ( 00421 void * framebuff, 00422 uint32_t fb_stride, 00423 drv_video_format_t video_format, 00424 drv_wr_rd_swa_t wr_rd_swa, 00425 uint16_t video_write_buff_vw, 00426 uint16_t video_write_buff_hw, 00427 drv_video_ext_in_config_t * drv_video_ext_in_config); 00428 00429 drv_graphics_error_t DRV_Video_Write_Setting_Mipi ( 00430 void * framebuff, 00431 uint32_t fb_stride, 00432 drv_video_format_t video_format, 00433 drv_wr_rd_swa_t wr_rd_swa, 00434 uint16_t video_write_buff_vw, 00435 uint16_t video_write_buff_hw, 00436 drv_mipi_param_t * mipi_data, 00437 drv_vin_setup_t * vin_setup); 00438 00439 drv_graphics_error_t DRV_Video_Write_Change ( 00440 drv_video_input_channel_t video_input_ch, 00441 void * framebuff, 00442 uint32_t fb_stride ); 00443 00444 #ifdef __cplusplus 00445 } 00446 #endif /* __cplusplus */ 00447 00448 #endif /* GR_BOARD_VDC5_H */
Generated on Wed Jul 13 2022 05:33:36 by
1.7.2