test public
Dependencies: HttpServer_snapshot_mbed-os
WM8978_RBSP.h
00001 /******************************************************************************* 00002 * DISCLAIMER 00003 * This software is supplied by Renesas Electronics Corporation and is only 00004 * intended for use with Renesas products. No other uses are authorized. This 00005 * software is owned by Renesas Electronics Corporation and is protected under 00006 * all applicable laws, including copyright laws. 00007 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING 00008 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT 00009 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE 00010 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. 00011 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS 00012 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE 00013 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR 00014 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE 00015 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 00016 * Renesas reserves the right, without notice, to make changes to this software 00017 * and to discontinue the availability of this software. By using this software, 00018 * you agree to the additional terms and conditions found by accessing the 00019 * following link: 00020 * http://www.renesas.com/disclaimer* 00021 * Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved. 00022 *******************************************************************************/ 00023 00024 #ifndef MBED_WM8978_RBSP_H 00025 #define MBED_WM8978_RBSP_H 00026 00027 #include "mbed.h" 00028 #include "AUDIO_RBSP.h" 00029 #include "R_BSP_Ssif.h" 00030 00031 /** WM8978_RBSP class, defined on the I2C master bus 00032 * 00033 */ 00034 class WM8978_RBSP : public AUDIO_RBSP { 00035 public: 00036 00037 /** Create a WM8978_RBSP object defined on the I2C port 00038 * 00039 * @param mosi SPI Master Out, Slave In pin 00040 * @param miso SPI Master In, Slave Out pin 00041 * @param sclk SPI Clock pin 00042 * @param ssel SPI chip select pin 00043 * @param sck SSIF serial bit clock 00044 * @param ws SSIF word selection 00045 * @param tx SSIF serial data output 00046 * @param rx SSIF serial data input 00047 * @param audio_clk audio clock 00048 * @param int_level Interupt priority (SSIF) 00049 * @param max_write_num The upper limit of write buffer (SSIF) 00050 * @param max_read_num The upper limit of read buffer (SSIF) 00051 */ 00052 WM8978_RBSP(PinName mosi, PinName miso, PinName sclk, PinName ssel, 00053 PinName sck, PinName ws, PinName tx, PinName rx, PinName audio_clk, 00054 uint8_t int_level = 0x80, int32_t max_write_num = 16, int32_t max_read_num = 16); 00055 00056 virtual ~WM8978_RBSP() {} 00057 00058 /** Overloaded power() 00059 * 00060 * @param type true=power up, false=power down 00061 */ 00062 virtual void power(bool type = true); 00063 00064 /** Set I2S interface bit length and mode 00065 * 00066 * @param length Set bit length to 16 bits 00067 * @return true = success, false = failure 00068 */ 00069 virtual bool format(char length); 00070 00071 /** Set sample frequency 00072 * 00073 * @param frequency Sample frequency of data in Hz 00074 * @return true = success, false = failure 00075 * 00076 * supports frequencies: 44.1kHz 00077 * Default is 44.1kHz 00078 */ 00079 virtual bool frequency(int hz); 00080 00081 /** Get a value of SSIF channel number 00082 * 00083 * @return SSIF channel number 00084 */ 00085 int32_t GetSsifChNo(void) { 00086 return mI2s_.GetSsifChNo(); 00087 }; 00088 00089 /** Enqueue asynchronous write request 00090 * 00091 * @param p_data Location of the data 00092 * @param data_size Number of bytes to write 00093 * @param p_data_conf Asynchronous control block structure 00094 * @return Number of bytes written on success. negative number on error. 00095 */ 00096 virtual int write(void * const p_data, uint32_t data_size, const rbsp_data_conf_t * const p_data_conf = NULL) { 00097 return mI2s_.write(p_data, data_size, p_data_conf); 00098 }; 00099 00100 /** Enqueue asynchronous read request 00101 * 00102 * @param p_data Location of the data 00103 * @param data_size Number of bytes to read 00104 * @param p_data_conf Asynchronous control block structure 00105 * @return Number of bytes read on success. negative number on error. 00106 */ 00107 virtual int read(void * const p_data, uint32_t data_size, const rbsp_data_conf_t * const p_data_conf = NULL) { 00108 return mI2s_.read(p_data, data_size, p_data_conf); 00109 }; 00110 00111 /** Headphone out volume control 00112 * 00113 * @param leftVolumeOut Left headphone-out volume 00114 * @param rightVolumeOut Right headphone-out volume 00115 * @return Returns "true" for success, "false" if parameters are out of range 00116 */ 00117 virtual bool outputVolume(float leftVolumeOut, float rightVolumeOut); 00118 00119 /** Microphone volume 00120 * 00121 * @param VolumeIn Microphone volume 00122 * @return Returns "true" for success, "false" if parameters are out of range 00123 */ 00124 virtual bool micVolume(float VolumeIn); 00125 00126 private: 00127 SPI mSpi_; 00128 R_BSP_Ssif mI2s_; 00129 ssif_channel_cfg_t ssif_cfg; 00130 /** Digital interface activation 00131 * 00132 */ 00133 void activateDigitalInterface_(void); 00134 void set_register(uint8_t reg_addr, uint16_t reg_cmd); 00135 00136 /****************************************************************************** 00137 Macro definitions 00138 ******************************************************************************/ 00139 #define WM8978_CALLBACK (0) /* 1:Callback at WM8978_RBSP, 0: Callback at SSIF */ 00140 00141 /* ==== Register Address ==== */ 00142 #define WM8978_REGADR_SOFT_RESET (0x00u) 00143 #define WM8978_REGADR_POW_MANAGE1 (0x01u) 00144 #define WM8978_REGADR_POW_MANAGE2 (0x02u) 00145 #define WM8978_REGADR_POW_MANAGE3 (0x03u) 00146 #define WM8978_REGADR_AUDIO_IF_CTL (0x04u) 00147 #define WM8978_REGADR_CLK_GEN_CTL (0x06u) 00148 #define WM8978_REGADR_DAC_CTL (0x0Au) 00149 #define WM8978_REGADR_ADC_CTL (0x0Eu) 00150 #define WM8978_REGADR_INPUT_CTL (0x2Cu) 00151 #define WM8978_REGADR_LINPPGAGAIN (0x2Du) 00152 #define WM8978_REGADR_RINPPGAGAIN (0x2Eu) 00153 #define WM8978_REGADR_LMIXER_CTL (0x32u) 00154 #define WM8978_REGADR_RMIXER_CTL (0x33u) 00155 #define WM8978_REGADR_LOUT1_VOL_CTL (0x34u) 00156 #define WM8978_REGADR_ROUT1_VOL_CTL (0x35u) 00157 00158 /* ==== Register Setting Value ==== */ 00159 /* RESET R0 */ 00160 #define WM8978_RESET_INI_VALUE (0x0000u) 00161 /* WM8978_REGADR_POW_MANAGE1 R1 */ 00162 #define WM8978_MANAGE1_INI_VALUE (0x0000u) 00163 #define WM8978_MANAGE1_VMIDSEL_75K (0x0001u) 00164 #define WM8978_MANAGE1_BUFIOEN_ON (0x0004u) 00165 #define WM8978_MANAGE1_BIASEN_ON (0x0008u) 00166 #define WM8978_MANAGE1_MICBEN_ON (0x0010u) 00167 #define WM8978_MANAGE1_PLLEN_ON (0x0020u) 00168 /* WM8978_REGADR_POW_MANAGE2 R2 */ 00169 #define WM8978_MANAGE2_INI_VALUE (0x0000u) 00170 #define WM8978_MANAGE2_ADCENL_ON (0x0001u) 00171 #define WM8978_MANAGE2_ADCENR_ON (0x0002u) 00172 #define WM8978_MANAGE2_INPPGAENL_ON (0x0004u) 00173 #define WM8978_MANAGE2_INPPGAENR_ON (0x0008u) 00174 #define WM8978_MANAGE2_BOOSTENL_ON (0x0010u) 00175 #define WM8978_MANAGE2_BOOSTENR_ON (0x0020u) 00176 #define WM8978_MANAGE2_LOUT1EN_ON (0x0080u) 00177 #define WM8978_MANAGE2_ROUT1EN_ON (0x0100u) 00178 /* WM8978_REGADR_POW_MANAGE3 R3 */ 00179 #define WM8978_MANAGE3_INI_VALUE (0x0000u) 00180 #define WM8978_MANAGE3_DACENL_ON (0x0001u) 00181 #define WM8978_MANAGE3_DACENR_ON (0x0002u) 00182 #define WM8978_MANAGE3_LMIXEN_ON (0x0004u) 00183 #define WM8978_MANAGE3_RMIXEN_ON (0x0008u) 00184 /* WM8978_REGADR_AUDIO_IF_CTL R4 */ 00185 #define WM8978_AUDIO_IF_INI_VALUE (0x0050u) 00186 #define WM8978_AUDIO_IF_WL_BIT (0x0060u) 00187 #define WM8978_AUDIO_IF_WL_16BIT (0x0000u) 00188 /* WM8978_REGADR_CLK_GEN_CTL R6 */ 00189 #define WM8978_CLK_GEN_CTL_INI_VALUE (0x0040u) 00190 #define WM8978_CLK_GEN_CTL_MCLKDIV_BIT (0x00e0u) 00191 #define WM8978_CLK_GEN_CTL_MCLKDIV_DIV1 (0x0000u) 00192 /* WM8978_REGADR_ADC_CTL R14 */ 00193 #define WM8978_ADC_CTL_INI_VALUE (0x0100u) 00194 #define WM8978_ADC_CTL_HPFEN_BIT (0x0100u) 00195 #define WM8978_ADC_CTL_ADCOSR128_ON (0x0008u) 00196 /* WM8978_REGADR_DAC_CTL R10 */ 00197 #define WM8978_DAC_CTL_INI_VALUE (0x0000u) 00198 #define WM8978_DAC_CTL_DACOSR128_ON (0x0008u) 00199 /* WM8978_REGADR_INPUT_CTL R44 */ 00200 #define WM8978_INPUTCTL_INI_VALUE (0x0033u) 00201 #define WM8978_INPUTCTL_L2_2INPPGA_ON (0x0004u) 00202 #define WM8978_INPUTCTL_R2_2INPPGA_ON (0x0040u) 00203 /* WM8978_REGADR_LINPPGAGAIN R45 */ 00204 #define WM8978_LINPPGAGAIN_INI_VOLL (0x0018u) 00205 #define WM8978_LINPPGAGAIN_MUTEL_ON (0x0040u) 00206 /* WM8978_REGADR_RINPPGAGAIN R46 */ 00207 #define WM8978_RINPPGAGAIN_INI_VOLL (0x0018u) 00208 #define WM8978_RINPPGAGAIN_MUTER_BIT (0x0040u) 00209 /* WM8978_REGADR_LMIX_CTL R50 */ 00210 #define WM8978_LMIX_CTL_INI_VALUE (0x0001u) 00211 #define WM8978_LMIX_CTL_DACL2LMIX_BIT (0x0001u) 00212 #define WM8978_LMIX_CTL_BYPL2LMIX_BIT (0x0002u) 00213 /* WM8978_REGADR_RMIX_CTL R51 */ 00214 #define WM8978_RMIX_CTL_INI_VALUE (0x0001u) 00215 #define WM8978_RMIX_CTL_DACR2RMIX_BIT (0x0001u) 00216 #define WM8978_RMIX_CTL_BYPR2RMIX_BIT (0x0002u) 00217 /* WM8978_REGADR_LOUT1_VOL_CTL R52 */ 00218 #define WM8978_LOUT1_HPVU_BIT (0x0100u) 00219 /* WM8978_REGADR_ROUT1_VOL_CTL R53 */ 00220 #define WM8978_ROUT1_HPVU_BIT (0x0100u) 00221 00222 }; 00223 00224 #endif
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