R_BSP_SsifDef.h

00001 /*******************************************************************************
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00021 * Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
00022 *******************************************************************************/
00023 /**************************************************************************//**
00024 * @file          R_BSP_SsifDef.h
00025 * @brief         SSIF defines
00026 ******************************************************************************/
00027 
00028 #ifndef R_BSP_SSIF_DEF_H
00029 #define R_BSP_SSIF_DEF_H
00030 
00031 /******************************************************************************
00032 Includes <System Includes> , "Project Includes"
00033 ******************************************************************************/
00034 
00035 #ifdef __cplusplus
00036 extern "C"
00037 {
00038 #endif /* __cplusplus */
00039 
00040 /******************************************************************************
00041  Defines
00042  *****************************************************************************/
00043 
00044 /******************************************************************************
00045  Constant Macros
00046  *****************************************************************************/
00047 #if defined(TARGET_RZA1H)
00048 #define SSIF_NUM_CHANS       (6u)    /**< Number of SSIF channels */
00049 #else
00050 #define SSIF_NUM_CHANS       (4u)    /**< Number of SSIF channels */
00051 #endif
00052 
00053 #define SSIF_CFG_DISABLE_ROMDEC_DIRECT (0x0u)        /* Disable SSIRDR->STRMDIN0 route */
00054 #define SSIF_CFG_ENABLE_ROMDEC_DIRECT  (0xDEC0DEC1u) /* Enable  SSIRDR->STRMDIN0 route */
00055 
00056 /******************************************************************************
00057  Function Macros
00058  *****************************************************************************/
00059 
00060 /******************************************************************************
00061  Enumerated Types
00062  *****************************************************************************/
00063 
00064 /** SSICR:CKS(Clock source for oversampling) */
00065 typedef enum
00066 {
00067     SSIF_CFG_CKS_AUDIO_X1  = 0,  /**< select AUDIO_X1   */
00068     SSIF_CFG_CKS_AUDIO_CLK = 1   /**< select AUIDIO_CLK */
00069 } ssif_chcfg_cks_t; 
00070 
00071 /** SSICR:CHNL(Audio channels per system word) */
00072 typedef enum
00073 {
00074     SSIF_CFG_MULTI_CH_1 = 0,     /**< 1ch within systemword (on tdm=0) */
00075     SSIF_CFG_MULTI_CH_2 = 1,     /**< 2ch within systemword (on tdm=0) */
00076     SSIF_CFG_MULTI_CH_3 = 2,     /**< 3ch within systemword (on tdm=0) */
00077     SSIF_CFG_MULTI_CH_4 = 3      /**< 4ch within systemword (on tdm=0) */
00078 } ssif_chcfg_multi_ch_t;
00079 
00080 /** SSICR:DWL(Data word length) */
00081 typedef enum
00082 {
00083     SSIF_CFG_DATA_WORD_8  = 0,   /**< Data word length 8  */
00084     SSIF_CFG_DATA_WORD_16 = 1,   /**< Data word length 16 */
00085     SSIF_CFG_DATA_WORD_18 = 2,   /**< Data word length 18 */
00086     SSIF_CFG_DATA_WORD_20 = 3,   /**< Data word length 20 */
00087     SSIF_CFG_DATA_WORD_22 = 4,   /**< Data word length 22 */
00088     SSIF_CFG_DATA_WORD_24 = 5,   /**< Data word length 24 */
00089     SSIF_CFG_DATA_WORD_32 = 6    /**< Data word length 32 */
00090 } ssif_chcfg_data_word_t;
00091 
00092 /** SSICR:SWL(System word length) */
00093 typedef enum
00094 {
00095     SSIF_CFG_SYSTEM_WORD_8   = 0,    /**< System word length 8   */
00096     SSIF_CFG_SYSTEM_WORD_16  = 1,    /**< System word length 16  */
00097     SSIF_CFG_SYSTEM_WORD_24  = 2,    /**< System word length 24  */
00098     SSIF_CFG_SYSTEM_WORD_32  = 3,    /**< System word length 32  */
00099     SSIF_CFG_SYSTEM_WORD_48  = 4,    /**< System word length 48  */
00100     SSIF_CFG_SYSTEM_WORD_64  = 5,    /**< System word length 64  */
00101     SSIF_CFG_SYSTEM_WORD_128 = 6,    /**< System word length 128 */
00102     SSIF_CFG_SYSTEM_WORD_256 = 7     /**< System word length 256 */
00103 } ssif_chcfg_system_word_t;
00104 
00105 /** SSICR:SCKP(Clock polarity) */
00106 typedef enum
00107 {
00108     SSIF_CFG_FALLING = 0,    /**< Falling edge */
00109     SSIF_CFG_RISING  = 1     /**< Rising edge  */
00110 } ssif_chcfg_clock_pol_t;
00111 
00112 /** SSICR:SWSP(Word select polarity) */
00113 typedef enum
00114 {
00115     SSIF_CFG_WS_LOW  = 0,    /**< Low for ther 1st channel(not TDM) */
00116     SSIF_CFG_WS_HIGH = 1     /**< High for the 1st channel(not TDM) */
00117 } ssif_chcfg_ws_pol_t;
00118 
00119 /** SSICR:SPDP(Serial padding polarity) */
00120 typedef enum
00121 {
00122     SSIF_CFG_PADDING_LOW  = 0,   /**< Padding bits are low  */
00123     SSIF_CFG_PADDING_HIGH = 1    /**< Padding bits are high */
00124 } ssif_chcfg_padding_pol_t;
00125 
00126 /** SSICR:SDTA(Serial data alignment) */
00127 typedef enum
00128 {
00129     SSIF_CFG_DATA_FIRST    = 0,  /**< Data first         */
00130     SSIF_CFG_PADDING_FIRST = 1   /**< Padding bits first */
00131 } ssif_chcfg_serial_alignment_t;
00132 
00133 /** SSICR:PDTA(Parallel data alignment) */
00134 typedef enum
00135 {
00136     SSIF_CFG_LEFT  = 0,  /**< Left aligned  */
00137     SSIF_CFG_RIGHT = 1   /**< Right aligned */
00138 } ssif_chcfg_parallel_alignment_t;
00139 
00140 /** SSICR:DEL(Serial data delay) */
00141 typedef enum
00142 {
00143     SSIF_CFG_DELAY    = 0,   /**< 1 clock delay */
00144     SSIF_CFG_NO_DELAY = 1    /**< No delay      */
00145 } ssif_chcfg_ws_delay_t;
00146 
00147 /** SSICR:CKDV(Serial oversampling clock division ratio) */
00148 typedef enum
00149 {
00150     SSIF_CFG_CKDV_BITS_1   = 0,
00151     SSIF_CFG_CKDV_BITS_2   = 1,
00152     SSIF_CFG_CKDV_BITS_4   = 2,
00153     SSIF_CFG_CKDV_BITS_8   = 3,
00154     SSIF_CFG_CKDV_BITS_16  = 4,
00155     SSIF_CFG_CKDV_BITS_32  = 5,
00156     SSIF_CFG_CKDV_BITS_64  = 6,
00157     SSIF_CFG_CKDV_BITS_128 = 7,
00158     SSIF_CFG_CKDV_BITS_6   = 8,
00159     SSIF_CFG_CKDV_BITS_12  = 9,
00160     SSIF_CFG_CKDV_BITS_24  = 10,
00161     SSIF_CFG_CKDV_BITS_48  = 11,
00162     SSIF_CFG_CKDV_BITS_96  = 12
00163 } ssif_chcfg_ckdv_t;
00164 
00165 
00166 /** SNCR:SSIxNL(Serial sound interface channel x noise canceler enable) */
00167 typedef enum
00168 {
00169     SSIF_CFG_DISABLE_NOISE_CANCEL = 0, /**< Not use noise cancel function */
00170     SSIF_CFG_ENABLE_NOISE_CANCEL  = 1  /**< Use noise cancel function     */
00171 } ssif_chcfg_noise_cancel_t;
00172 
00173 
00174 /** SSITDMR:TDM(TDM mode) */
00175 typedef enum
00176 {
00177     SSIF_CFG_DISABLE_TDM = 0,   /**< not TDM mode */
00178     SSIF_CFG_ENABLE_TDM  = 1    /**< set TDM mode */
00179 } ssif_chcfg_tdm_t;
00180 
00181 /******************************************************************************
00182  Structures
00183  *****************************************************************************/
00184 
00185 /** It's used for ROMDEC direct transfer mode and the call back function registration. */
00186 typedef struct
00187 {
00188     uint32_t    mode;               /**< Enable/Disable SSIRDR->STRMDIN0 route (Invalid in GR_LYCHEE) */
00189     void        (*p_cbfunc)(void);  /**< SSIF error callback function          (Invalid in GR_LYCHEE) */
00190 } ssif_chcfg_romdec_t;
00191 
00192 /** This structure contains the configuration settings */
00193 typedef struct
00194 {
00195     bool                            enabled;             /**< The enable flag for the channel       */
00196     uint8_t                         int_level;           /**< Interrupt priority for the channel    */
00197     bool                            slave_mode;          /**< Mode of operation                     */
00198     uint32_t                        sample_freq;         /**< Audio Sampling frequency(Hz)          */
00199     ssif_chcfg_cks_t                clk_select;          /**< SSICR-CKS : Audio clock select        */
00200     ssif_chcfg_multi_ch_t           multi_ch;            /**< SSICR-CHNL: Audio channels per system word */
00201     ssif_chcfg_data_word_t          data_word;           /**< SSICR-DWL : Data word length          */
00202     ssif_chcfg_system_word_t        system_word;         /**< SSICR-SWL : System word length        */
00203     ssif_chcfg_clock_pol_t          bclk_pol;            /**< SSICR-SCKP: Bit Clock polarity        */
00204     ssif_chcfg_ws_pol_t             ws_pol;              /**< SSICR-SWSP: Word Clock polarity       */
00205     ssif_chcfg_padding_pol_t        padding_pol;         /**< SSICR-SPDP: Padding polarity          */
00206     ssif_chcfg_serial_alignment_t   serial_alignment;    /**< SSICR-SDTA: Serial data alignment     */
00207     ssif_chcfg_parallel_alignment_t parallel_alignment;  /**< SSICR-PDTA: Parallel data alignment   */
00208     ssif_chcfg_ws_delay_t           ws_delay;            /**< SSICR-DEL : Serial clock delay        */
00209     ssif_chcfg_noise_cancel_t       noise_cancel;        /**< GPIO-SNCR : Noise cancel              */
00210     ssif_chcfg_tdm_t                tdm_mode;            /**< SSITDMR-TDM: TDM mode                 */
00211     ssif_chcfg_romdec_t             romdec_direct;       /**< DMA : SSIRDR->STRMDIN0 route settings (Invalid in GR_LYCHEE) */
00212 } ssif_channel_cfg_t;
00213 
00214 /******************************************************************************
00215  IOCTLS
00216  *****************************************************************************/
00217 
00218 #define SSIF_CONFIG_CHANNEL        (7)
00219 #define SSIF_GET_STATUS           (13)
00220 
00221 #ifdef __cplusplus
00222 }
00223 #endif /* __cplusplus */
00224 
00225 #endif /* R_BSP_SSIF_DEF_H */