Anh Tran
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R_BSP_Scux.cpp
00001 /******************************************************************************* 00002 * DISCLAIMER 00003 * This software is supplied by Renesas Electronics Corporation and is only 00004 * intended for use with Renesas products. No other uses are authorized. This 00005 * software is owned by Renesas Electronics Corporation and is protected under 00006 * all applicable laws, including copyright laws. 00007 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING 00008 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT 00009 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE 00010 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. 00011 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS 00012 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE 00013 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR 00014 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE 00015 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 00016 * Renesas reserves the right, without notice, to make changes to this software 00017 * and to discontinue the availability of this software. By using this software, 00018 * you agree to the additional terms and conditions found by accessing the 00019 * following link: 00020 * http://www.renesas.com/disclaimer* 00021 * Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. 00022 *******************************************************************************/ 00023 00024 #include "R_BSP_Scux.h" 00025 #if (R_BSP_SCUX_ENABLE == 1) 00026 #include "r_bsp_cmn.h" 00027 #include "scux_if.h" 00028 00029 #define CH_ERR_NUM (-1) /* Channel error number */ 00030 #define INT_LEVEL_MAX (0xF7) /* The maximum value of the interrupt level */ 00031 #define REQ_BUFF_NUM_MIN (1) /* The minimum value of the request buffer */ 00032 #define REQ_BUFF_NUM_MAX (128) /* The maximum value of the request buffer */ 00033 #define INPUT_DIV_INIT_VALUE (1000U) /* The initial value of input divide ratio */ 00034 #define OUTPUT_DIV_INIT_VALUE (0U) /* The initial value of output divide ratio */ 00035 #define INPUT_WS_INIT_VALUE (1U) /* The initial value of input WS frequency */ 00036 #define OUTPUT_WS_INIT_VALUE (96000U) /* The initial value of output WS frequency */ 00037 #define FREQ_TIOC3A_INIT_VALUE (1U) /* The initial value of frequency of TIOC3 */ 00038 #define FREQ_TIOC4A_INIT_VALUE (1U) /* The initial value of frequency of TIOC4 */ 00039 #define WAIT_SAMPLE_INIT_VALUE (0U) /* The initial value of wait time */ 00040 #define MIN_RATE_PER_INIT_VALUE (98U) /* The initial value of minimum rate */ 00041 #define DIV_RATIO_CLK_AUDIO_22050HZ (1024U) /* Divide ratio when the frequency is 22050Hz */ 00042 #define DIV_RATIO_CLK_AUDIO_44100HZ (512U) /* Divide ratio when the frequency is 44100Hz */ 00043 #define DIV_RATIO_CLK_AUDIO_88200HZ (256U) /* Divide ratio when the frequency is 88200Hz */ 00044 #define DIV_RATIO_CLK_USB_24000HZ (2000U) /* Divide ratio when the frequency is 24000Hz */ 00045 #define DIV_RATIO_CLK_USB_32000HZ (1500U) /* Divide ratio when the frequency is 36000Hz */ 00046 #define DIV_RATIO_CLK_USB_48000HZ (1000U) /* Divide ratio when the frequency is 48000Hz */ 00047 #define DIV_RATIO_CLK_USB_64000HZ (750U) /* Divide ratio when the frequency is 64000Hz */ 00048 #define DIV_RATIO_CLK_USB_96000HZ (500U) /* Divide ratio when the frequency is 96000Hz */ 00049 00050 static bool set_src_init_cfg(scux_src_cfg_t * const src_cfg); 00051 00052 R_BSP_Scux::R_BSP_Scux(scux_ch_num_t channel, uint8_t int_level, int32_t max_write_num, int32_t max_read_num) { 00053 scux_channel_cfg_t scux_cfg; 00054 int32_t result; 00055 bool init_result; 00056 00057 if (channel >= SCUX_CH_NUM) { 00058 result = EERROR; 00059 } else if (int_level > INT_LEVEL_MAX) { 00060 result = EERROR; 00061 } else if ((max_write_num < REQ_BUFF_NUM_MIN) || (max_write_num > REQ_BUFF_NUM_MAX)) { 00062 result = EERROR; 00063 } else if ((max_read_num < REQ_BUFF_NUM_MIN) || (max_read_num > REQ_BUFF_NUM_MAX)) { 00064 result = EERROR; 00065 } else { 00066 result = R_BSP_CMN_Init(); 00067 if (result == ESUCCESS) { 00068 scux_ch = (int32_t)channel; 00069 00070 scux_cfg.enabled = true; 00071 scux_cfg.int_level = int_level; 00072 00073 switch (channel) { 00074 case SCUX_CH_0: 00075 scux_cfg.route = SCUX_ROUTE_SRC0_MEM; 00076 break; 00077 case SCUX_CH_1: 00078 scux_cfg.route = SCUX_ROUTE_SRC1_MEM; 00079 break; 00080 case SCUX_CH_2: 00081 scux_cfg.route = SCUX_ROUTE_SRC2_MEM; 00082 break; 00083 case SCUX_CH_3: 00084 scux_cfg.route = SCUX_ROUTE_SRC3_MEM; 00085 break; 00086 default: 00087 /* NOTREACHED on At the time of a normal performance */ 00088 scux_cfg.route = SCUX_ROUTE_SRC0_MEM; 00089 break; 00090 } 00091 00092 init_result = set_src_init_cfg(&scux_cfg.src_cfg); 00093 if (init_result != false) { 00094 init_result = init_channel(R_SCUX_MakeCbTbl_mbed(), (int32_t)channel, &scux_cfg, max_write_num, max_read_num); 00095 if (init_result == false) { 00096 result = EERROR; 00097 } 00098 } else { 00099 result = EERROR; 00100 } 00101 } 00102 } 00103 00104 if (result != ESUCCESS) { 00105 scux_ch = CH_ERR_NUM; 00106 } 00107 } 00108 00109 R_BSP_Scux::~R_BSP_Scux(void) { 00110 } 00111 00112 bool R_BSP_Scux::TransStart(void) { 00113 return ioctl(SCUX_IOCTL_SET_START, NULL); 00114 } 00115 00116 bool R_BSP_Scux::FlushStop(void (* const callback)(int32_t)) { 00117 return ioctl(SCUX_IOCTL_SET_FLUSH_STOP, (void *)callback); 00118 } 00119 00120 bool R_BSP_Scux::ClearStop(void) { 00121 return ioctl(SCUX_IOCTL_SET_CLEAR_STOP, NULL); 00122 } 00123 00124 bool R_BSP_Scux::SetSrcCfg(const scux_src_usr_cfg_t * const p_src_param) { 00125 scux_src_cfg_t src_cfg; 00126 bool init_result; 00127 bool ret = true; 00128 int32_t i; 00129 00130 if (scux_ch == CH_ERR_NUM) { 00131 ret = false; 00132 } else if (p_src_param == NULL) { 00133 ret = false; 00134 } else if ((p_src_param->mode_sync != false) && (p_src_param->src_enable == false)) { 00135 ret = false; 00136 } else { 00137 init_result = set_src_init_cfg(&src_cfg); 00138 if (init_result != true) { 00139 ret = false; 00140 } else { 00141 src_cfg.src_enable = p_src_param->src_enable; 00142 src_cfg.mode_sync = p_src_param->mode_sync; 00143 00144 switch (p_src_param->word_len) { 00145 case SCUX_DATA_LEN_24: 00146 /* fall through */ 00147 case SCUX_DATA_LEN_16: 00148 /* fall through */ 00149 case SCUX_DATA_LEN_16_TO_24: 00150 src_cfg.word_len = p_src_param->word_len; 00151 break; 00152 default: 00153 ret = false; 00154 break; 00155 } 00156 00157 if (ret == true) { 00158 if (p_src_param->mode_sync != false) { 00159 switch (p_src_param->input_rate) { 00160 case SAMPLING_RATE_8000HZ: 00161 src_cfg.input_rate_sync = SCUX_SYNC_RATE_8; 00162 break; 00163 case SAMPLING_RATE_11025HZ: 00164 src_cfg.input_rate_sync = SCUX_SYNC_RATE_11_025; 00165 break; 00166 case SAMPLING_RATE_12000HZ: 00167 src_cfg.input_rate_sync = SCUX_SYNC_RATE_12; 00168 break; 00169 case SAMPLING_RATE_16000HZ: 00170 src_cfg.input_rate_sync = SCUX_SYNC_RATE_16; 00171 break; 00172 case SAMPLING_RATE_22050HZ: 00173 src_cfg.input_rate_sync = SCUX_SYNC_RATE_22_05; 00174 break; 00175 case SAMPLING_RATE_24000HZ: 00176 src_cfg.input_rate_sync = SCUX_SYNC_RATE_24; 00177 break; 00178 case SAMPLING_RATE_32000HZ: 00179 src_cfg.input_rate_sync = SCUX_SYNC_RATE_32; 00180 break; 00181 case SAMPLING_RATE_44100HZ: 00182 src_cfg.input_rate_sync = SCUX_SYNC_RATE_44_1; 00183 break; 00184 case SAMPLING_RATE_48000HZ: 00185 src_cfg.input_rate_sync = SCUX_SYNC_RATE_48; 00186 break; 00187 case SAMPLING_RATE_64000HZ: 00188 src_cfg.input_rate_sync = SCUX_SYNC_RATE_64; 00189 break; 00190 case SAMPLING_RATE_88200HZ: 00191 src_cfg.input_rate_sync = SCUX_SYNC_RATE_88_2; 00192 break; 00193 case SAMPLING_RATE_96000HZ: 00194 src_cfg.input_rate_sync = SCUX_SYNC_RATE_96; 00195 break; 00196 default: 00197 ret = false; 00198 break; 00199 } 00200 } else { 00201 switch (p_src_param->input_rate) { 00202 case SAMPLING_RATE_22050HZ: 00203 src_cfg.input_clk_async = SCUX_CLK_AUDIO_X1; 00204 src_cfg.input_div_async = DIV_RATIO_CLK_AUDIO_22050HZ; 00205 break; 00206 case SAMPLING_RATE_24000HZ: 00207 src_cfg.input_clk_async = SCUX_CLK_USB_X1; 00208 src_cfg.input_div_async = DIV_RATIO_CLK_USB_24000HZ; 00209 break; 00210 case SAMPLING_RATE_32000HZ: 00211 src_cfg.input_clk_async = SCUX_CLK_USB_X1; 00212 src_cfg.input_div_async = DIV_RATIO_CLK_USB_32000HZ; 00213 break; 00214 case SAMPLING_RATE_44100HZ: 00215 src_cfg.input_clk_async = SCUX_CLK_AUDIO_X1; 00216 src_cfg.input_div_async = DIV_RATIO_CLK_AUDIO_44100HZ; 00217 break; 00218 case SAMPLING_RATE_48000HZ: 00219 src_cfg.input_clk_async = SCUX_CLK_USB_X1; 00220 src_cfg.input_div_async = DIV_RATIO_CLK_USB_48000HZ; 00221 break; 00222 case SAMPLING_RATE_64000HZ: 00223 src_cfg.input_clk_async = SCUX_CLK_USB_X1; 00224 src_cfg.input_div_async = DIV_RATIO_CLK_USB_64000HZ; 00225 break; 00226 case SAMPLING_RATE_88200HZ: 00227 src_cfg.input_clk_async = SCUX_CLK_AUDIO_X1; 00228 src_cfg.input_div_async = DIV_RATIO_CLK_AUDIO_88200HZ; 00229 break; 00230 case SAMPLING_RATE_96000HZ: 00231 src_cfg.input_clk_async = SCUX_CLK_USB_X1; 00232 src_cfg.input_div_async = DIV_RATIO_CLK_USB_96000HZ; 00233 break; 00234 default: 00235 ret = false; 00236 break; 00237 } 00238 } 00239 } 00240 00241 if (ret == true) { 00242 if (p_src_param->mode_sync != false) { 00243 switch (p_src_param->output_rate) { 00244 case SAMPLING_RATE_44100HZ: 00245 src_cfg.output_rate_sync = SCUX_SYNC_RATE_44_1; 00246 break; 00247 case SAMPLING_RATE_48000HZ: 00248 src_cfg.output_rate_sync = SCUX_SYNC_RATE_48; 00249 break; 00250 case SAMPLING_RATE_96000HZ: 00251 src_cfg.output_rate_sync = SCUX_SYNC_RATE_96; 00252 break; 00253 default: 00254 ret = false; 00255 break; 00256 } 00257 } else { 00258 switch (p_src_param->output_rate) { 00259 case SAMPLING_RATE_44100HZ: 00260 src_cfg.output_ws = SAMPLING_RATE_44100HZ; 00261 break; 00262 case SAMPLING_RATE_48000HZ: 00263 src_cfg.output_ws = SAMPLING_RATE_48000HZ; 00264 break; 00265 case SAMPLING_RATE_88200HZ: 00266 src_cfg.output_ws = SAMPLING_RATE_88200HZ; 00267 break; 00268 case SAMPLING_RATE_96000HZ: 00269 src_cfg.output_ws = SAMPLING_RATE_96000HZ; 00270 break; 00271 default: 00272 ret = false; 00273 break; 00274 } 00275 } 00276 } 00277 00278 if (ret == true) { 00279 for (i = 0; i < SCUX_USE_CH_2; i++) { 00280 switch (p_src_param->select_in_data_ch[i]) { 00281 case SELECT_IN_DATA_CH_0: 00282 src_cfg.select_in_data_ch[i] = SCUX_AUDIO_CH_0; 00283 break; 00284 case SELECT_IN_DATA_CH_1: 00285 src_cfg.select_in_data_ch[i] = SCUX_AUDIO_CH_1; 00286 break; 00287 default: 00288 ret = false; 00289 break; 00290 } 00291 } 00292 } 00293 00294 if (ret == true) { 00295 ret = ioctl(SCUX_IOCTL_SET_SRC_CFG, (void *)&src_cfg); 00296 } 00297 } 00298 } 00299 00300 return ret; 00301 } 00302 00303 bool R_BSP_Scux::GetWriteStat(uint32_t * const p_write_stat) { 00304 return ioctl(SCUX_IOCTL_GET_WRITE_STAT, (void *)p_write_stat); 00305 } 00306 00307 bool R_BSP_Scux::GetReadStat(uint32_t * const p_read_stat) { 00308 return ioctl(SCUX_IOCTL_GET_READ_STAT, (void *)p_read_stat); 00309 } 00310 00311 /**************************************************************************//** 00312 * Function Name: set_src_init_cfg 00313 * @brief SRC configuration initialization. 00314 * 00315 * Description:<br> 00316 * 00317 * @param[in] src_cfg SRC configuration. 00318 * @retval true Setting success. 00319 * false Setting fails. 00320 ******************************************************************************/ 00321 static bool set_src_init_cfg(scux_src_cfg_t * const src_cfg) { 00322 bool ret = true; 00323 00324 if (src_cfg == NULL) { 00325 ret = false; 00326 } else { 00327 src_cfg->src_enable = true; 00328 src_cfg->use_ch = SCUX_USE_CH_2; 00329 src_cfg->word_len = SCUX_DATA_LEN_16; 00330 src_cfg->mode_sync = true; 00331 src_cfg->input_rate_sync = SCUX_SYNC_RATE_48; 00332 src_cfg->input_clk_async = SCUX_CLK_USB_X1; 00333 src_cfg->input_div_async = INPUT_DIV_INIT_VALUE; 00334 src_cfg->output_rate_sync = SCUX_SYNC_RATE_96; 00335 src_cfg->output_clk_async = SCUX_CLK_SSIF0_WS; 00336 src_cfg->output_div_async = OUTPUT_DIV_INIT_VALUE; 00337 src_cfg->input_ws = INPUT_WS_INIT_VALUE; 00338 src_cfg->output_ws = OUTPUT_WS_INIT_VALUE; 00339 src_cfg->freq_tioc3a = FREQ_TIOC3A_INIT_VALUE; 00340 src_cfg->freq_tioc4a = FREQ_TIOC4A_INIT_VALUE; 00341 src_cfg->delay_mode = SCUX_DELAY_NORMAL; 00342 src_cfg->wait_sample = WAIT_SAMPLE_INIT_VALUE; 00343 src_cfg->min_rate_percentage = MIN_RATE_PER_INIT_VALUE; 00344 src_cfg->select_in_data_ch[SCUX_AUDIO_CH_0] = SCUX_AUDIO_CH_0; 00345 src_cfg->select_in_data_ch[SCUX_AUDIO_CH_1] = SCUX_AUDIO_CH_1; 00346 src_cfg->select_in_data_ch[SCUX_AUDIO_CH_2] = SCUX_AUDIO_CH_2; 00347 src_cfg->select_in_data_ch[SCUX_AUDIO_CH_3] = SCUX_AUDIO_CH_3; 00348 src_cfg->select_in_data_ch[SCUX_AUDIO_CH_4] = SCUX_AUDIO_CH_4; 00349 src_cfg->select_in_data_ch[SCUX_AUDIO_CH_5] = SCUX_AUDIO_CH_5; 00350 src_cfg->select_in_data_ch[SCUX_AUDIO_CH_6] = SCUX_AUDIO_CH_6; 00351 src_cfg->select_in_data_ch[SCUX_AUDIO_CH_7] = SCUX_AUDIO_CH_7; 00352 } 00353 00354 return ret; 00355 } 00356 00357 #endif /* R_BSP_SCUX_ENABLE */
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