MT9V111_config.h

00001 
00002 #ifndef MT9V111_CONFIG_H
00003 #define MT9V111_CONFIG_H
00004 
00005 #include "mbed.h"
00006 #include "camera_config.h"
00007 
00008 class MT9V111_config : public camera_config {
00009 
00010 public:
00011 
00012     /** Initialise
00013      *
00014      * @return true = success, false = failure
00015      */
00016     virtual bool Initialise() {
00017         return true;
00018     }
00019 
00020     virtual void SetExtInConfig(DisplayBase::video_ext_in_config_t * p_cfg) {
00021         p_cfg->inp_format      = DisplayBase::VIDEO_EXTIN_FORMAT_BT601 ; /* BT601 8bit YCbCr format */
00022         p_cfg->inp_pxd_edge    = DisplayBase::EDGE_RISING ;              /* Clock edge select for capturing data          */
00023         p_cfg->inp_vs_edge     = DisplayBase::EDGE_RISING ;              /* Clock edge select for capturing Vsync signals */
00024         p_cfg->inp_hs_edge     = DisplayBase::EDGE_RISING ;              /* Clock edge select for capturing Hsync signals */
00025         p_cfg->inp_endian_on   = DisplayBase::OFF ;                      /* External input bit endian change on/off       */
00026         p_cfg->inp_swap_on     = DisplayBase::OFF ;                      /* External input B/R signal swap on/off         */
00027         p_cfg->inp_vs_inv      = DisplayBase::SIG_POL_NOT_INVERTED ;     /* External input DV_VSYNC inversion control     */
00028         p_cfg->inp_hs_inv      = DisplayBase::SIG_POL_INVERTED ;         /* External input DV_HSYNC inversion control     */
00029         p_cfg->inp_f525_625    = DisplayBase::EXTIN_LINE_525 ;           /* Number of lines for BT.656 external input */
00030         p_cfg->inp_h_pos       = DisplayBase::EXTIN_H_POS_CRYCBY ;       /* Y/Cb/Y/Cr data string start timing to Hsync reference */
00031         p_cfg->cap_vs_pos      = 6;                                     /* Capture start position from Vsync */
00032         p_cfg->cap_hs_pos      = 150;                                   /* Capture start position form Hsync */
00033         p_cfg->cap_width       = 640;                                   /* Capture width Max */
00034         p_cfg->cap_height      = 468u;                                  /* Capture height Max 468[line]
00035                                                                           Due to CMOS(MT9V111) output signal timing and VDC5 specification */
00036     }
00037 
00038 };
00039 
00040 #endif
00041