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DisplayBace.h
00001 /******************************************************************************* 00002 * DISCLAIMER 00003 * This software is supplied by Renesas Electronics Corporation and is only 00004 * intended for use with Renesas products. No other uses are authorized. This 00005 * software is owned by Renesas Electronics Corporation and is protected under 00006 * all applicable laws, including copyright laws. 00007 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING 00008 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT 00009 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE 00010 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. 00011 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS 00012 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE 00013 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR 00014 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE 00015 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 00016 * Renesas reserves the right, without notice, to make changes to this software 00017 * and to discontinue the availability of this software. By using this software, 00018 * you agree to the additional terms and conditions found by accessing the 00019 * following link: 00020 * http://www.renesas.com/disclaimer 00021 * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved. 00022 *******************************************************************************/ 00023 /**************************************************************************//** 00024 * @file DisplayBase.h 00025 * @brief Display driver wrapper class for GR-PEACH 00026 ******************************************************************************/ 00027 00028 #ifndef MBED_DISPLAYBASE_H 00029 #define MBED_DISPLAYBASE_H 00030 00031 #include "pinmap.h" 00032 00033 /*! @class DisplayBase 00034 * @brief Display driver wrapper class for GR-PEACH 00035 */ 00036 class DisplayBase 00037 { 00038 00039 public: 00040 /*! @enum video_input_channel_t 00041 @brief Video input channel select 00042 */ 00043 typedef enum { 00044 VIDEO_INPUT_CHANNEL_0 = 0, /*!< Video input channel 0 */ 00045 VIDEO_INPUT_CHANNEL_1 /*!< Video input channel 1 */ 00046 } video_input_channel_t; 00047 00048 /*! @enum video_adc_vinsel_t 00049 @brief Input pin control 00050 */ 00051 typedef enum { 00052 VIDEO_ADC_VINSEL_VIN1 = 0, /*!< VIN1 input */ 00053 VIDEO_ADC_VINSEL_VIN2 /*!< VIN2 input */ 00054 } video_adc_vinsel_t; 00055 00056 /*! @enum graphics_layer_t 00057 @brief Graphics layer select 00058 */ 00059 typedef enum { 00060 GRAPHICS_LAYER_0 = 0, /*!< Graphics layer 0 */ 00061 GRAPHICS_LAYER_1 , /*!< Graphics layer 1 */ 00062 GRAPHICS_LAYER_2 , /*!< Graphics layer 2 */ 00063 GRAPHICS_LAYER_3 /*!< Graphics layer 3 */ 00064 } graphics_layer_t; 00065 00066 /*! @enum graphics_error_t 00067 @brief Error codes 00068 */ 00069 typedef enum { 00070 GRAPHICS_OK = 0, /*!< Normal termination */ 00071 GRAPHICS_VDC5_ERR = -1, /*!< VDC5 driver error */ 00072 GRAPHICS_FORMA_ERR = -2, /*!< Not support format */ 00073 GRAPHICS_LAYER_ERR = -3, /*!< Invalid layer ID error */ 00074 GRAPHICS_CHANNLE_ERR = -4, /*!< Invalid channel error */ 00075 GRAPHICS_VIDEO_NTSC_SIZE_ERR = -5, /*!< Video write size(vw) error */ 00076 GRAPHICS_VIDEO_PAL_SIZE_ERR = -6, /*!< Video Write size(vw) error */ 00077 GRAPHICS_PARAM_RANGE_ERR = -7 /*!< Parameter range error */ 00078 } graphics_error_t; 00079 00080 /*! @enum graphics_format_t 00081 @brief Graphics layer read format selects 00082 */ 00083 typedef enum { 00084 GRAPHICS_FORMAT_YCBCR422 = 0, /*!< YCbCr422 (2byte / px) */ 00085 GRAPHICS_FORMAT_RGB565 , /*!< RGB565 (2byte / px) */ 00086 GRAPHICS_FORMAT_RGB888 , /*!< RGB888 (4byte / px) */ 00087 GRAPHICS_FORMAT_ARGB8888 , /*!< ARGB8888 (4byte / px) */ 00088 GRAPHICS_FORMAT_ARGB4444 , /*!< ARGB4444 (2byte / px) */ 00089 GRAPHICS_FORMAT_CLUT8 , /*!< CLUT8 (1byte / px) */ 00090 GRAPHICS_FORMAT_CLUT4 , /*!< CLUT4 (0.5byte / px) */ 00091 GRAPHICS_FORMAT_CLUT1 /*!< CLUT1 (0.125byte / px) */ 00092 } graphics_format_t; 00093 00094 /*! @enum video_format_t 00095 @brief Video writing format selects 00096 */ 00097 typedef enum { 00098 VIDEO_FORMAT_YCBCR422 = 0, /*!< YCbCr422 (2byte / px) */ 00099 VIDEO_FORMAT_RGB565 , /*!< RGB565 (2byte / px) */ 00100 VIDEO_FORMAT_RGB888 , /*!< RGB888 (4byte / px) */ 00101 VIDEO_FORMAT_RAW8 /*!< RAW8 (1byte / px) */ 00102 } video_format_t; 00103 00104 /*! @enum wr_rd_swa_t 00105 @brief Frame buffer swap setting 00106 */ 00107 typedef enum { 00108 WR_RD_WRSWA_NON = 0, /*!< Not swapped: 1-2-3-4-5-6-7-8 */ 00109 WR_RD_WRSWA_8BIT , /*!< Swapped in 8-bit units: 2-1-4-3-6-5-8-7 */ 00110 WR_RD_WRSWA_16BIT , /*!< Swapped in 16-bit units: 3-4-1-2-7-8-5-6 */ 00111 WR_RD_WRSWA_16_8BIT , /*!< Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5 */ 00112 WR_RD_WRSWA_32BIT , /*!< Swapped in 32-bit units: 5-6-7-8-1-2-3-4 */ 00113 WR_RD_WRSWA_32_8BIT , /*!< Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3 */ 00114 WR_RD_WRSWA_32_16BIT , /*!< Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2 */ 00115 WR_RD_WRSWA_32_16_8BIT , /*!< Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1 */ 00116 } wr_rd_swa_t; 00117 00118 /*! @enum lcd_tcon_pin_t 00119 @brief LCD tcon output pin selects 00120 */ 00121 typedef enum { 00122 LCD_TCON_PIN_NON = -1, /*!< Not using output */ 00123 LCD_TCON_PIN_0 , /*!< LCD_TCON0 */ 00124 LCD_TCON_PIN_1 , /*!< LCD_TCON1 */ 00125 LCD_TCON_PIN_2 , /*!< LCD_TCON2 */ 00126 LCD_TCON_PIN_3 , /*!< LCD_TCON3 */ 00127 LCD_TCON_PIN_4 , /*!< LCD_TCON4 */ 00128 } lcd_tcon_pin_t; 00129 00130 /*! @enum lcd_outformat_t 00131 @brief LCD output format selects 00132 */ 00133 typedef enum { 00134 LCD_OUTFORMAT_RGB888 = 0, /*!< RGB888 or LVDS */ 00135 LCD_OUTFORMAT_RGB666 , /*!< RGB666 */ 00136 LCD_OUTFORMAT_RGB565 /*!< RGB565 */ 00137 } lcd_outformat_t; 00138 00139 /*! @enum edge_t 00140 @brief Edge of a signal 00141 */ 00142 typedef enum { 00143 EDGE_RISING = 0, /*!< Rising edge */ 00144 EDGE_FALLING = 1 /*!< Falling edge */ 00145 } edge_t; 00146 00147 /*! @enum lcd_type_t 00148 @brief LCD type 00149 */ 00150 typedef enum { 00151 LCD_TYPE_LVDS = 0, /*!< LVDS control */ 00152 LCD_TYPE_PARALLEL_RGB /*!< RGB parallel signal control */ 00153 } lcd_type_t; 00154 00155 /*! @enum sig_pol_t 00156 @brief Polarity of a signal 00157 */ 00158 typedef enum { 00159 SIG_POL_NOT_INVERTED = 0, /*!< Not inverted */ 00160 SIG_POL_INVERTED /*!< Inverted */ 00161 } sig_pol_t; 00162 00163 /*! @enum int_type_t 00164 @brief Interrupt type 00165 */ 00166 typedef enum { 00167 INT_TYPE_S0_VI_VSYNC = 0, /*!< Vsync signal input to scaler 0 */ 00168 INT_TYPE_S0_LO_VSYNC , /*!< Vsync signal output from scaler 0 */ 00169 INT_TYPE_S0_VSYNCERR , /*!< Missing Vsync signal for scaler 0 */ 00170 INT_TYPE_VLINE , /*!< Specified line signal for panel output in graphics 3 */ 00171 INT_TYPE_S0_VFIELD , /*!< Field end signal for recording function in scaler 0 */ 00172 INT_TYPE_IV1_VBUFERR , /*!< Frame buffer write overflow signal for scaler 0 */ 00173 INT_TYPE_IV3_VBUFERR , /*!< Frame buffer read underflow signal for graphics 0 */ 00174 INT_TYPE_IV5_VBUFERR , /*!< Frame buffer read underflow signal for graphics 2 */ 00175 INT_TYPE_IV6_VBUFERR , /*!< Frame buffer read underflow signal for graphics 3 */ 00176 INT_TYPE_S0_WLINE , /*!< Write specification line signal input to scaling-down control block in scaler 0 */ 00177 INT_TYPE_S1_VI_VSYNC , /*!< Vsync signal input to scaler 1 */ 00178 INT_TYPE_S1_LO_VSYNC , /*!< Vsync signal output from scaler 1 */ 00179 INT_TYPE_S1_VSYNCERR , /*!< Missing Vsync signal for scaler 1 */ 00180 INT_TYPE_S1_VFIELD , /*!< Field end signal for recording function in scaler 1 */ 00181 INT_TYPE_IV2_VBUFERR , /*!< Frame buffer write overflow signal for scaler 1 */ 00182 INT_TYPE_IV4_VBUFERR , /*!< Frame buffer read underflow signal for graphics 1 */ 00183 INT_TYPE_S1_WLINE , /*!< Write specification line signal input to scaling-down control block in scaler 1 */ 00184 INT_TYPE_OIR_VI_VSYNC , /*!< Vsync signal input to output image generator */ 00185 INT_TYPE_OIR_LO_VSYNC , /*!< Vsync signal output from output image generator */ 00186 INT_TYPE_OIR_VLINE , /*!< Specified line signal for panel output in output image generator */ 00187 INT_TYPE_OIR_VFIELD , /*!< Field end signal for recording function in output image generator */ 00188 INT_TYPE_IV7_VBUFERR , /*!< Frame buffer write overflow signal for output image generator */ 00189 INT_TYPE_IV8_VBUFERR , /*!< Frame buffer read underflow signal for graphics (OIR) */ 00190 INT_TYPE_NUM /*!< The number of VDC5 interrupt types */ 00191 } int_type_t; 00192 00193 /*! @enum graphics_video_col_sys_t 00194 @brief Video color system 00195 */ 00196 typedef enum { 00197 COL_SYS_NTSC_358 = 0, /*!< NTSC-3.58 */ 00198 COL_SYS_NTSC_443 = 1, /*!< NTSC-4.43 */ 00199 COL_SYS_PAL_443 = 2, /*!< PAL-4.43 */ 00200 COL_SYS_PAL_M = 3, /*!< PAL-M */ 00201 COL_SYS_PAL_N = 4, /*!< PAL-N */ 00202 COL_SYS_SECAM = 5, /*!< SECAM */ 00203 COL_SYS_NTSC_443_60 = 6, /*!< NTSC-4.43 (60Hz) */ 00204 COL_SYS_PAL_60 = 7, /*!< PAL-60 */ 00205 } graphics_video_col_sys_t; 00206 00207 /*! @enum video_input_sel_t 00208 @brief External Input select 00209 */ 00210 typedef enum { 00211 INPUT_SEL_VDEC = 0, /*!< Video decoder output signals */ 00212 INPUT_SEL_EXT = 1, /*!< Signals supplied via the external input pins */ 00213 INPUT_SEL_CEU = 2, /*!< Signals supplied via the CEU input pins */ 00214 INPUT_SEL_MIPI = 3 /*!< Signals supplied via the MIPI input pins */ 00215 } video_input_sel_t; 00216 00217 /*! @enum video_extin_format_t 00218 @brief External input format select 00219 */ 00220 typedef enum { 00221 VIDEO_EXTIN_FORMAT_RGB888 = 0, /*!< RGB888 Not support */ 00222 VIDEO_EXTIN_FORMAT_RGB666 , /*!< RGB666 */ 00223 VIDEO_EXTIN_FORMAT_RGB565 , /*!< RGB565 */ 00224 VIDEO_EXTIN_FORMAT_BT656 , /*!< BT6556 */ 00225 VIDEO_EXTIN_FORMAT_BT601 , /*!< BT6501 */ 00226 VIDEO_EXTIN_FORMAT_YCBCR422 , /*!< YCbCr422 */ 00227 VIDEO_EXTIN_FORMAT_YCBCR444 , /*!< YCbCr444 Not support */ 00228 } video_extin_format_t; 00229 00230 /*! @enum onoff_t 00231 @brief On/off 00232 */ 00233 typedef enum { 00234 OFF = 0, /*!< Off */ 00235 ON = 1 /*!< On */ 00236 } onoff_t; 00237 00238 /*! @enum extin_input_line_t 00239 @brief Number of lines for BT.656 external input 00240 */ 00241 typedef enum { 00242 EXTIN_LINE_525 = 0, /*!< 525 lines */ 00243 EXTIN_LINE_625 = 1 /*!< 625 lines */ 00244 } extin_input_line_t; 00245 00246 /*! @enum extin_h_pos_t 00247 @brief Y/Cb/Y/Cr data string start timing 00248 */ 00249 typedef enum { 00250 EXTIN_H_POS_CBYCRY = 0, /*!< Cb/Y/Cr/Y (BT656/601), Cb/Cr (YCbCr422) */ 00251 EXTIN_H_POS_YCRYCB , /*!< Y/Cr/Y/Cb (BT656/601), setting prohibited (YCbCr422) */ 00252 EXTIN_H_POS_CRYCBY , /*!< Cr/Y/Cb/Y (BT656/601), setting prohibited (YCbCr422) */ 00253 EXTIN_H_POS_YCBYCR , /*!< Y/Cb/Y/Cr (BT656/601), Cr/Cb (YCbCr422) */ 00254 EXTIN_H_POS_NUM 00255 } extin_h_pos_t; 00256 00257 /*! @struct rect_t 00258 @brief The relative position within the graphics display area 00259 */ 00260 typedef struct { 00261 unsigned short vs ; /*!< Vertical start pos */ 00262 unsigned short vw ; /*!< Vertical width (height) */ 00263 unsigned short hs ; /*!< Horizontal start pos */ 00264 unsigned short hw ; /*!< Horizontal width */ 00265 } rect_t; 00266 00267 /*! @struct clut_t 00268 @brief CLUT setup parameter 00269 */ 00270 typedef struct { 00271 uint32_t color_num ; /*!< The number of colors in CLUT */ 00272 const uint32_t * clut ; /*!< Address of the area storing the CLUT data (in ARGB8888 format) */ 00273 } clut_t; 00274 00275 /*! @struct lcd_config_t 00276 @brief LCD configuration 00277 */ 00278 typedef struct { 00279 lcd_type_t lcd_type ; /*!< LVDS or Pararel RGB */ 00280 double intputClock ; /*!< P1 clk [MHz] ex. 66.67f */ 00281 double outputClock ; /*!< LCD clk [MHz] ex. 33.33f */ 00282 00283 lcd_outformat_t lcd_outformat ; /*!< Output format select */ 00284 edge_t lcd_edge ; /*!< Output phase control of LCD_DATA23 to LCD_DATA0 pin */ 00285 00286 unsigned short h_toatal_period ; /*!< Free-running Hsync period */ 00287 unsigned short v_toatal_period ; /*!< Free-running Vsync period */ 00288 unsigned short h_disp_widht ; /*!< LCD display area size, horizontal width */ 00289 unsigned short v_disp_widht ; /*!< LCD display area size, vertical width */ 00290 unsigned short h_back_porch ; /*!< LCD display horizontal back porch period */ 00291 unsigned short v_back_porch ; /*!< LCD display vertical back porch period */ 00292 00293 lcd_tcon_pin_t h_sync_port ; /*!< TCONn or Not use(-1) */ 00294 sig_pol_t h_sync_port_polarity ; /*!< Polarity inversion control of signal */ 00295 unsigned short h_sync_width ; /*!< Hsync width */ 00296 00297 lcd_tcon_pin_t v_sync_port ; /*!< TCONn or Not use(-1) */ 00298 sig_pol_t v_sync_port_polarity ; /*!< Polarity inversion control of signal */ 00299 unsigned short v_sync_width ; /*!< Vsync width */ 00300 00301 lcd_tcon_pin_t de_port ; /*!< TCONn or Not use(-1) */ 00302 sig_pol_t de_port_polarity ; /*!< Polarity inversion control of signal */ 00303 } lcd_config_t; 00304 00305 /*! @struct video_ext_in_config_t 00306 @brief Digital Video Input configuration 00307 */ 00308 typedef struct { 00309 video_extin_format_t inp_format ; /*!< External Input Format Select */ 00310 edge_t inp_pxd_edge ; /*!< Clock Edge Select for Capturing External Input Video Image */ 00311 edge_t inp_vs_edge ; /*!< Clock Edge Select for Capturing External Input Vsync Signal */ 00312 edge_t inp_hs_edge ; /*!< Clock Edge Select for Capturing External Input Hsync Signal */ 00313 onoff_t inp_endian_on ; /*!< External Input B/R Signal Swap On/Off Control */ 00314 onoff_t inp_swap_on ; /*!< External Input Bit Endian Change On/Off Control */ 00315 sig_pol_t inp_vs_inv ; /*!< External Input Vsync Signal DV_VSYNC Inversion Control */ 00316 sig_pol_t inp_hs_inv ; /*!< External Input Hsync Signal DV_HSYNC Inversion Control */ 00317 extin_input_line_t inp_f525_625 ; /*!< Number of lines for BT.656 external input */ 00318 extin_h_pos_t inp_h_pos ; /*!< Y/Cb/Y/Cr data string start timing to Hsync reference */ 00319 unsigned short cap_vs_pos ; /*!< Capture start position from Vsync */ 00320 unsigned short cap_hs_pos ; /*!< Capture start position form Hsync */ 00321 unsigned short cap_width ; /*!< Capture width */ 00322 unsigned short cap_height ; /*!< Capture height should be a multiple of 4.*/ 00323 } video_ext_in_config_t; 00324 00325 /* mipi phy timing struct */ 00326 typedef struct { 00327 uint16_t mipi_ths_prepare; /*!< Setting of the duration of the LP-00 state (immediately before entry to the HS-0 state) */ 00328 uint16_t mipi_ths_settle; /*!< Setting of the period in which a transition to the HS state is ignored after the TTHS_PREPARE period begins */ 00329 uint16_t mipi_tclk_prepare; /*!< Setting of the duration of the LP-00 state (immediately before entry to the HS-0) */ 00330 uint16_t mipi_tclk_settle; /*!< Setting of the period in which a transition to the HS state is ignored after the TCLK_PREPARE period begins */ 00331 uint16_t mipi_tclk_miss; /*!< Setting of the period in which the absence of the clock is detected, and the HS-RX is disabled */ 00332 uint16_t mipi_t_init_slave; /*!< Minimum duration of the INIT state */ 00333 } video_mipi_phy_timing_t; 00334 00335 /* mipi parameter struct */ 00336 typedef struct { 00337 uint8_t mipi_lanenum; /*!< Mipi Lane Num */ 00338 uint8_t mipi_vc; /*!< Mipi Virtual Channel */ 00339 uint8_t mipi_interlace; /*!< Interlace or Progressive */ 00340 uint8_t mipi_laneswap; /*!< Mipi Lane Swap Setting */ 00341 uint16_t mipi_frametop; /*!< (for Interlace)Top Field Packet ID */ 00342 uint16_t mipi_outputrate; /*!< Mipi Data Send Speed(Mbit per sec) */ 00343 video_mipi_phy_timing_t mipi_phy_timing; /*!< Mipi D-PHY timing settings */ 00344 } video_mipi_param_t; 00345 00346 /*! Vin parameter Struct */ 00347 typedef struct { 00348 uint16_t vin_preclip_starty ; /*!< Pre Area Clip Start Line */ 00349 uint16_t vin_preclip_endy ; /*!< Pre Area Clip End Line */ 00350 uint16_t vin_preclip_startx ; /*!< Pre Area Clip Start Column */ 00351 uint16_t vin_preclip_endx ; /*!< Pre Area Clip End Column */ 00352 } video_vin_preclip_t ; 00353 00354 typedef struct { 00355 uint8_t vin_scaleon; /*!< Scaling On or OFF */ 00356 uint8_t vin_interpolation; /*!< Scaling Interpolation */ 00357 uint16_t vin_scale_h; /*!< Horizontal multiple */ 00358 uint16_t vin_scale_v; /*!< vertical multiple */ 00359 } video_vin_scale_t; 00360 00361 typedef struct { 00362 uint16_t vin_afterclip_size_x; /*!< After Area Clip horizontal size */ 00363 uint16_t vin_afterclip_size_y; /*!< After Area Clip vertical size */ 00364 } video_vin_afterclip_t; 00365 00366 /*! YCbCr422 input data alignment */ 00367 typedef enum 00368 { 00369 VIN_Y_UPPER = 0, /*!< Upper bit is Y, lower bit is CbCr */ 00370 VIN_CB_UPPER , /*!< Upper bit is CbCr, lower bit is Y */ 00371 } video_vin_input_align_t ; 00372 00373 /*! Output data byte swap mode */ 00374 typedef enum 00375 { 00376 VIN_SWAP_OFF = 0, /*!< Not swap */ 00377 VIN_SWAP_ON , /*!< Swap */ 00378 } video_vin_output_swap_t ; 00379 00380 typedef struct { 00381 video_vin_preclip_t vin_preclip; /*!< Pre Area Clip Parameter */ 00382 video_vin_scale_t vin_scale; /*!< Scale Parameter */ 00383 video_vin_afterclip_t vin_afterclip; /*!< After Area Clip Parameter */ 00384 uint8_t vin_yuv_clip; /*!< YUV Range Clip Parameter */ 00385 uint8_t vin_lut; /*!< LUT Conversion On or OFF */ 00386 uint8_t vin_inputformat; /*!< Input Image Format */ 00387 uint8_t vin_outputformat; /*!< Output Image Format */ 00388 uint8_t vin_outputendian; /*!< Output Data Endian*/ 00389 uint8_t vin_dither; /*!< (for RGB565 or ARGB1555)Output Data Dithering On or Off */ 00390 uint8_t vin_interlace; /*!< (for Interlace input)Capture Method */ 00391 uint8_t vin_alpha_val8; /*!< (for ARGB8888)Alpha Value */ 00392 uint8_t vin_alpha_val1; /*!< (for ARGB1555)Alpha Value */ 00393 uint16_t vin_stride; /*!< Stride (byte) */ 00394 uint32_t vin_ycoffset; /*!< (for YC separate output)Address Offset Value */ 00395 video_vin_input_align_t vin_input_align; /*!< YCbCr422 input data alignment */ 00396 video_vin_output_swap_t vin_output_swap; /*!< Output data byte swap mode */ 00397 } video_vin_setup_t; 00398 00399 /** Constructor method of display base object 00400 */ 00401 DisplayBase( void ); 00402 00403 /** Graphics initialization processing<br> 00404 * If not using display, set NULL in parameter. 00405 * @param[in] lcd_config : LCD configuration 00406 * @retval Error code 00407 */ 00408 graphics_error_t Graphics_init( const lcd_config_t * lcd_config ); 00409 00410 /** Graphics Video initialization processing<br> 00411 * If setting INPUT_SEL_VDEC in video_input_sel parameter, set NULL in video_ext_in_config parameter. 00412 * @param[in] video_input_sel : Input select 00413 * @param[in] video_ext_in_config : Video configuration 00414 * @retval error code 00415 */ 00416 graphics_error_t Graphics_Video_init( video_input_sel_t video_input_sel, video_ext_in_config_t * video_ext_in_config ); 00417 00418 /** Graphics Video initialization processing<br> 00419 * @param[in] video_input_sel : Input select 00420 * @param[in] video_mipi_config : MIPI configuration 00421 * @param[in] video_vin_setup : MIPI configuration 00422 * @retval error code 00423 */ 00424 graphics_error_t Graphics_Video_init( video_input_sel_t video_input_sel, video_mipi_param_t * video_mipi_config, video_vin_setup_t * video_vin_setup ); 00425 00426 /** LCD output port initialization processing 00427 * @param[in] pin : Pin assign for LCD output 00428 * @param[in] pin_count : Total number of pin assign 00429 * @retval Error code 00430 */ 00431 graphics_error_t Graphics_Lcd_Port_Init( PinName *pin, unsigned int pin_count ); 00432 00433 /** LVDS output port initialization processing 00434 * @param[in] pin : Pin assign for LVDS output 00435 * @param[in] pin_count : Total number of pin assign 00436 * @retval Error code 00437 */ 00438 graphics_error_t Graphics_Lvds_Port_Init( PinName *pin, unsigned int pin_count ); 00439 00440 /** Digital video input port initialization processing 00441 * @param[in] pin : Pin assign for digital video input port 00442 * @param[in] pin_count : Total number of pin assign 00443 * @retval Error code 00444 */ 00445 graphics_error_t Graphics_Dvinput_Port_Init( PinName *pin, unsigned int pin_count ); 00446 00447 /** CEU input port initialization processing 00448 * @param[in] pin : Pin assign for CEU input port 00449 * @param[in] pin_count : Total number of pin assign 00450 * @retval Error code 00451 */ 00452 graphics_error_t Graphics_Ceu_Port_Init( PinName *pin, unsigned int pin_count ); 00453 00454 /** Interrupt callback setup 00455 * This function performs the following processing: 00456 * - Enables the interrupt when the pointer to the corresponding interrupt callback function is specified.<br> 00457 * - Registers the specified interrupt callback function.<br> 00458 * - Disables the interrupt when the pointer to the corresponding interrupt callback function is not specified.<br> 00459 * @param[in] Graphics_Irq_Handler_Set : VDC5 interrupt type 00460 * @param[in] num : Interrupt line number 00461 * @param[in] callback : Interrupt callback function pointer 00462 * @retval Error code 00463 */ 00464 graphics_error_t Graphics_Irq_Handler_Set( int_type_t Graphics_Irq_Handler_Set, unsigned short num, void (* callback)(int_type_t) ); 00465 00466 /** Start the graphics surface read process 00467 * @param[in] layer_id : Graphics layer ID <br /> 00468 * - GRAPHICS_LAYER_0 : Layer 0 00469 * - GRAPHICS_LAYER_1 : Layer 1 00470 * - GRAPHICS_LAYER_2 : Layer 2 00471 * - GRAPHICS_LAYER_3 : Layer 3 00472 * @retval Error code 00473 */ 00474 graphics_error_t Graphics_Start( graphics_layer_t layer_id ); 00475 00476 /** Stop the graphics surface read process 00477 * @param[in] layer_id : Graphics layer ID <br /> 00478 * - GRAPHICS_LAYER_0 : Layer 0 00479 * - GRAPHICS_LAYER_1 : Layer 1 00480 * - GRAPHICS_LAYER_2 : Layer 2 00481 * - GRAPHICS_LAYER_3 : Layer 3 00482 * @retval Error code 00483 */ 00484 graphics_error_t Graphics_Stop( graphics_layer_t layer_id ); 00485 00486 /** Start the video surface write process 00487 * @param[in] video_input_channel : Video input channel <br /> 00488 * - VIDEO_INPUT_CHANNEL_0 : Video channel 0 00489 * - VIDEO_INPUT_CHANNEL_1 : Video channel 1 00490 * @retval Error code 00491 */ 00492 graphics_error_t Video_Start ( video_input_channel_t video_input_channel ); 00493 00494 /** Stop the video surface write process 00495 * @param[in] video_input_channel : Video input channel <br /> 00496 * - VIDEO_INPUT_CHANNEL_0 : Video channel 0 00497 * - VIDEO_INPUT_CHANNEL_1 : Video channel 1 00498 * @retval Error code 00499 */ 00500 graphics_error_t Video_Stop ( video_input_channel_t video_input_channel ); 00501 00502 /** Graphics surface read process setting 00503 * @param[in] layer_id : Graphics layer ID <br /> 00504 * - GRAPHICS_LAYER_0 : Layer 0 00505 * - GRAPHICS_LAYER_1 : Layer 1 00506 * - GRAPHICS_LAYER_2 : Layer 2 00507 * - GRAPHICS_LAYER_3 : Layer 3 00508 * @param[in] framebuff : Base address of the frame buffer(Not set NULL) 00509 * @param[in] fb_stride : Line offset address of the frame buffer[byte] <br /> 00510 * Frame buffer stride should be set to a multiple of 32 or 128 00511 * in accordance with the frame buffer burst transfer mode. 00512 * @param[in] gr_format : Format of the frame buffer read signal <br /> 00513 * - GRAPHICS_FORMAT_YCBCR422 : YCBCR422 (2byte/px) 00514 * - GRAPHICS_FORMAT_RGB565 : RGB565 (2byte/px) 00515 * - GRAPHICS_FORMAT_RGB888 : RGB888 (4byte/px) 00516 * - GRAPHICS_FORMAT_ARGB8888 : ARGB8888 (4byte/px) 00517 * - GRAPHICS_FORMAT_CLUT8 : CLUT8 (1byte/px) 00518 * - GRAPHICS_FORMAT_CLUT4 : CLUT4 (0.5byte/px) 00519 * - GRAPHICS_FORMAT_CLUT1 : CLUT1 (0,12byte/px) 00520 * @param[in] wr_rd_swa : frame buffer swap setting <br /> 00521 * - WR_RD_WRSWA_NON : Not swapped: 1-2-3-4-5-6-7-8 00522 * - WR_RD_WRSWA_8BIT : Swapped in 8-bit units: 2-1-4-3-6-5-8-7 00523 * - WR_RD_WRSWA_16BIT : Swapped in 16-bit units: 3-4-1-2-7-8-5-6 00524 * - WR_RD_WRSWA_16_8BIT : Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5 00525 * - WR_RD_WRSWA_32BIT : Swapped in 32-bit units: 5-6-7-8-1-2-3-4 00526 * - WR_RD_WRSWA_32_8BIT : Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3 00527 * - WR_RD_WRSWA_32_16BIT : Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2 00528 * - WR_RD_WRSWA_32_16_8BIT : Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1 00529 * @param[in] gr_rect : Graphics display area 00530 * @param[in] gr_clut : CLUT setup parameter 00531 * @retval Error code 00532 */ 00533 graphics_error_t Graphics_Read_Setting ( 00534 graphics_layer_t layer_id, 00535 void * framebuff, 00536 unsigned int fb_stride, 00537 graphics_format_t gr_format, 00538 wr_rd_swa_t wr_rd_swa, 00539 rect_t * gr_rect, 00540 clut_t * gr_clut = 0 ); 00541 00542 /** Graphics surface read buffer change process 00543 * @param[in] layer_id : Graphics layer ID <br /> 00544 * - GRAPHICS_LAYER_0 : Layer 0 00545 * - GRAPHICS_LAYER_1 : Layer 1 00546 * - GRAPHICS_LAYER_2 : Layer 2 00547 * - GRAPHICS_LAYER_3 : Layer 3 00548 * @param[in] framebuff : Base address of the frame buffer(Not set NULL) 00549 * @retval Error code 00550 */ 00551 graphics_error_t Graphics_Read_Change ( 00552 graphics_layer_t layer_id, 00553 void * framebuff); 00554 00555 /** Video surface write process setting 00556 * @param[in] video_input_channel : Video input channel <br /> 00557 * If using digital input, this parameter is not referenced. <br /> 00558 * - VIDEO_INPUT_CHANNEL_0 : Video channel 0 00559 * - VIDEO_INPUT_CHANNEL_1 : Video channel 1 00560 * @param[in] col_sys : Analog video signal color system <br /> 00561 * If using digital input, this parameter is not referenced. <br /> 00562 * - COL_SYS_NTSC_358 : NTSC-3.58 00563 * - COL_SYS_NTSC_443 : NTSC-4.43 00564 * - COL_SYS_PAL_443 : PAL-4.43 00565 * - COL_SYS_PAL_M : PAL-M 00566 * - COL_SYS_PAL_N : PAL-N 00567 * - COL_SYS_SECAM : SECAM 00568 * - COL_SYS_NTSC_443_60 : NTSC-4.43 (60Hz) 00569 * - COL_SYS_PAL_60 : PAL-60 00570 * @param[in] framebuff : Base address of the frame buffer(Not set NULL) 00571 * @param[in] fb_stride : Line offset address of the frame buffer[byte] <br /> 00572 * Frame buffer stride should be set to a multiple of 32 or 128 00573 * in accordance with the frame buffer burst transfer mode. 00574 * @param[in] video_format : Frame buffer video-signal writing format <br /> 00575 * - VIDEO_FORMAT_YCBCR422 : YCBCR422 (2byte/px) 00576 * - VIDEO_FORMAT_RGB565 : RGB565 (2byte/px) 00577 * - VIDEO_FORMAT_RGB888 : RGB888 (4byte/px) 00578 * @param[in] wr_rd_swa : frame buffer swap setting <br /> 00579 * - WR_RD_WRSWA_NON : Not swapped: 1-2-3-4-5-6-7-8 00580 * - WR_RD_WRSWA_8BIT : Swapped in 8-bit units: 2-1-4-3-6-5-8-7 00581 * - WR_RD_WRSWA_16BIT : Swapped in 16-bit units: 3-4-1-2-7-8-5-6 00582 * - WR_RD_WRSWA_16_8BIT : Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5 00583 * - WR_RD_WRSWA_32BIT : Swapped in 32-bit units: 5-6-7-8-1-2-3-4 00584 * - WR_RD_WRSWA_32_8BIT : Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3 00585 * - WR_RD_WRSWA_32_16BIT : Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2 00586 * - WR_RD_WRSWA_32_16_8BIT : Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1 00587 * @param[in] video_write_buff_vw : Output height[px] <br /> 00588 * - NTSC format : Max height is 480[px] 00589 * - PAL format : Max height is 520[px] 00590 * @param[in] video_write_buff_hw : Output width[px] <br /> 00591 * - Max width : 800[px] 00592 * @param[in] video_adc_vinsel : Input pin control <br /> 00593 * - VIDEO_ADC_VINSEL_VIN1 : VIN1 input 00594 * - VIDEO_ADC_VINSEL_VIN2 : VIN2 input 00595 * @retval Error code 00596 */ 00597 graphics_error_t Video_Write_Setting ( 00598 video_input_channel_t video_input_channel, 00599 graphics_video_col_sys_t col_sys, 00600 void * framebuff, 00601 unsigned int fb_stride, 00602 video_format_t video_format, 00603 wr_rd_swa_t wr_rd_swa, 00604 unsigned short video_write_buff_vw, 00605 unsigned short video_write_buff_hw, 00606 video_adc_vinsel_t video_adc_vinsel = VIDEO_ADC_VINSEL_VIN1 ); 00607 00608 /** Video surface write buffer change process 00609 * @param[in] video_input_channel : Video input channel <br /> 00610 * - VIDEO_INPUT_CHANNEL_0 : Video channel 0 00611 * - VIDEO_INPUT_CHANNEL_1 : Video channel 1 00612 * @param[in] framebuff : Base address of the frame buffer(Not set NULL) 00613 * @param[in] fb_stride : Line offset address of the frame buffer <br /> 00614 * Frame buffer stride should be set to a multiple of 32 or 128 00615 * in accordance with the frame buffer burst transfer mode. 00616 * @retval Error code 00617 */ 00618 graphics_error_t Video_Write_Change ( 00619 video_input_channel_t video_input_channel, 00620 void * framebuff, 00621 uint32_t fb_stride ); 00622 00623 protected: 00624 lcd_config_t _lcd_config; 00625 video_input_sel_t _video_input_sel; 00626 video_ext_in_config_t _video_ext_in_config; 00627 #if defined(TARGET_RZ_A2XX) 00628 video_mipi_param_t _video_mipi_config; 00629 video_vin_setup_t _video_vin_setup; 00630 #endif 00631 }; 00632 00633 00634 #endif /* MBED_DISPLAYBASE_H */
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