Amit Gandhi / sensen_copy_2

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_usart.c@178:c26431f84b0d, 2017-11-09 (annotated)

Committer:
amithy
Date:
Thu Nov 09 22:14:37 2017 +0000
Revision:
178:c26431f84b0d
Parent:
156:95d6b41a828b 
test export

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 156:95d6b41a828b 1 /**
<> 156:95d6b41a828b 2 ******************************************************************************
<> 156:95d6b41a828b 3 * @file stm32f0xx_ll_usart.c
<> 156:95d6b41a828b 4 * @author MCD Application Team
<> 156:95d6b41a828b 5 * @version V1.4.0
<> 156:95d6b41a828b 6 * @date 27-May-2016
<> 156:95d6b41a828b 7 * @brief USART LL module driver.
<> 156:95d6b41a828b 8 ******************************************************************************
<> 156:95d6b41a828b 9 * @attention
<> 156:95d6b41a828b 10 *
<> 156:95d6b41a828b 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 156:95d6b41a828b 12 *
<> 156:95d6b41a828b 13 * Redistribution and use in source and binary forms, with or without modification,
<> 156:95d6b41a828b 14 * are permitted provided that the following conditions are met:
<> 156:95d6b41a828b 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 156:95d6b41a828b 16 * this list of conditions and the following disclaimer.
<> 156:95d6b41a828b 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 156:95d6b41a828b 18 * this list of conditions and the following disclaimer in the documentation
<> 156:95d6b41a828b 19 * and/or other materials provided with the distribution.
<> 156:95d6b41a828b 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 156:95d6b41a828b 21 * may be used to endorse or promote products derived from this software
<> 156:95d6b41a828b 22 * without specific prior written permission.
<> 156:95d6b41a828b 23 *
<> 156:95d6b41a828b 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 156:95d6b41a828b 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 156:95d6b41a828b 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 156:95d6b41a828b 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 156:95d6b41a828b 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 156:95d6b41a828b 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 156:95d6b41a828b 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 156:95d6b41a828b 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 156:95d6b41a828b 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 156:95d6b41a828b 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 156:95d6b41a828b 34 *
<> 156:95d6b41a828b 35 ******************************************************************************
<> 156:95d6b41a828b 36 */
<> 156:95d6b41a828b 37 #if defined(USE_FULL_LL_DRIVER)
<> 156:95d6b41a828b 38
<> 156:95d6b41a828b 39 /* Includes ------------------------------------------------------------------*/
<> 156:95d6b41a828b 40 #include "stm32f0xx_ll_usart.h"
<> 156:95d6b41a828b 41 #include "stm32f0xx_ll_rcc.h"
<> 156:95d6b41a828b 42 #include "stm32f0xx_ll_bus.h"
<> 156:95d6b41a828b 43 #ifdef USE_FULL_ASSERT
<> 156:95d6b41a828b 44 #include "stm32_assert.h"
<> 156:95d6b41a828b 45 #else
<> 156:95d6b41a828b 46 #define assert_param(expr) ((void)0U)
<> 156:95d6b41a828b 47 #endif
<> 156:95d6b41a828b 48
<> 156:95d6b41a828b 49 /** @addtogroup STM32F0xx_LL_Driver
<> 156:95d6b41a828b 50 * @{
<> 156:95d6b41a828b 51 */
<> 156:95d6b41a828b 52
<> 156:95d6b41a828b 53 #if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART4) || defined (USART5) || defined (USART6) || defined (USART7) || defined (USART8)
<> 156:95d6b41a828b 54
<> 156:95d6b41a828b 55 /** @addtogroup USART_LL
<> 156:95d6b41a828b 56 * @{
<> 156:95d6b41a828b 57 */
<> 156:95d6b41a828b 58
<> 156:95d6b41a828b 59 /* Private types -------------------------------------------------------------*/
<> 156:95d6b41a828b 60 /* Private variables ---------------------------------------------------------*/
<> 156:95d6b41a828b 61 /* Private constants ---------------------------------------------------------*/
<> 156:95d6b41a828b 62 /** @addtogroup USART_LL_Private_Constants
<> 156:95d6b41a828b 63 * @{
<> 156:95d6b41a828b 64 */
<> 156:95d6b41a828b 65
<> 156:95d6b41a828b 66 /**
<> 156:95d6b41a828b 67 * @}
<> 156:95d6b41a828b 68 */
<> 156:95d6b41a828b 69
<> 156:95d6b41a828b 70
<> 156:95d6b41a828b 71 /* Private macros ------------------------------------------------------------*/
<> 156:95d6b41a828b 72 /** @addtogroup USART_LL_Private_Macros
<> 156:95d6b41a828b 73 * @{
<> 156:95d6b41a828b 74 */
<> 156:95d6b41a828b 75
<> 156:95d6b41a828b 76 /* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
<> 156:95d6b41a828b 77 * divided by the smallest oversampling used on the USART (i.e. 8) */
<> 156:95d6b41a828b 78 #define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 6000000U)
<> 156:95d6b41a828b 79
<> 156:95d6b41a828b 80 #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
<> 156:95d6b41a828b 81 || ((__VALUE__) == LL_USART_DIRECTION_RX) \
<> 156:95d6b41a828b 82 || ((__VALUE__) == LL_USART_DIRECTION_TX) \
<> 156:95d6b41a828b 83 || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
<> 156:95d6b41a828b 84
<> 156:95d6b41a828b 85 #define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
<> 156:95d6b41a828b 86 || ((__VALUE__) == LL_USART_PARITY_EVEN) \
<> 156:95d6b41a828b 87 || ((__VALUE__) == LL_USART_PARITY_ODD))
<> 156:95d6b41a828b 88
<> 156:95d6b41a828b 89 #if defined(USART_7BITS_SUPPORT)
<> 156:95d6b41a828b 90 #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
<> 156:95d6b41a828b 91 || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
<> 156:95d6b41a828b 92 || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
<> 156:95d6b41a828b 93 #else
<> 156:95d6b41a828b 94 #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \
<> 156:95d6b41a828b 95 || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
<> 156:95d6b41a828b 96 #endif
<> 156:95d6b41a828b 97
<> 156:95d6b41a828b 98 #define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
<> 156:95d6b41a828b 99 || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
<> 156:95d6b41a828b 100
<> 156:95d6b41a828b 101 #define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
<> 156:95d6b41a828b 102 || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
<> 156:95d6b41a828b 103
<> 156:95d6b41a828b 104 #define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
<> 156:95d6b41a828b 105 || ((__VALUE__) == LL_USART_PHASE_2EDGE))
<> 156:95d6b41a828b 106
<> 156:95d6b41a828b 107 #define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
<> 156:95d6b41a828b 108 || ((__VALUE__) == LL_USART_POLARITY_HIGH))
<> 156:95d6b41a828b 109
<> 156:95d6b41a828b 110 #define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
<> 156:95d6b41a828b 111 || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
<> 156:95d6b41a828b 112
<> 156:95d6b41a828b 113 #if defined(USART_SMARTCARD_SUPPORT)
<> 156:95d6b41a828b 114 #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
<> 156:95d6b41a828b 115 || ((__VALUE__) == LL_USART_STOPBITS_1) \
<> 156:95d6b41a828b 116 || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
<> 156:95d6b41a828b 117 || ((__VALUE__) == LL_USART_STOPBITS_2))
<> 156:95d6b41a828b 118 #else
<> 156:95d6b41a828b 119 #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_1) \
<> 156:95d6b41a828b 120 || ((__VALUE__) == LL_USART_STOPBITS_2))
<> 156:95d6b41a828b 121 #endif
<> 156:95d6b41a828b 122
<> 156:95d6b41a828b 123 #define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
<> 156:95d6b41a828b 124 || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
<> 156:95d6b41a828b 125 || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
<> 156:95d6b41a828b 126 || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
<> 156:95d6b41a828b 127
<> 156:95d6b41a828b 128 /**
<> 156:95d6b41a828b 129 * @}
<> 156:95d6b41a828b 130 */
<> 156:95d6b41a828b 131
<> 156:95d6b41a828b 132 /* Private function prototypes -----------------------------------------------*/
<> 156:95d6b41a828b 133
<> 156:95d6b41a828b 134 /* Exported functions --------------------------------------------------------*/
<> 156:95d6b41a828b 135 /** @addtogroup USART_LL_Exported_Functions
<> 156:95d6b41a828b 136 * @{
<> 156:95d6b41a828b 137 */
<> 156:95d6b41a828b 138
<> 156:95d6b41a828b 139 /** @addtogroup USART_LL_EF_Init
<> 156:95d6b41a828b 140 * @{
<> 156:95d6b41a828b 141 */
<> 156:95d6b41a828b 142
<> 156:95d6b41a828b 143 /**
<> 156:95d6b41a828b 144 * @brief De-initialize USART registers (Registers restored to their default values).
<> 156:95d6b41a828b 145 * @param USARTx USART Instance
<> 156:95d6b41a828b 146 * @retval An ErrorStatus enumeration value:
<> 156:95d6b41a828b 147 * - SUCCESS: USART registers are de-initialized
<> 156:95d6b41a828b 148 * - ERROR: USART registers are not de-initialized
<> 156:95d6b41a828b 149 */
<> 156:95d6b41a828b 150 ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
<> 156:95d6b41a828b 151 {
<> 156:95d6b41a828b 152 ErrorStatus status = SUCCESS;
<> 156:95d6b41a828b 153
<> 156:95d6b41a828b 154 /* Check the parameters */
<> 156:95d6b41a828b 155 assert_param(IS_UART_INSTANCE(USARTx));
<> 156:95d6b41a828b 156
<> 156:95d6b41a828b 157 if (USARTx == USART1)
<> 156:95d6b41a828b 158 {
<> 156:95d6b41a828b 159 /* Force reset of USART clock */
<> 156:95d6b41a828b 160 LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_USART1);
<> 156:95d6b41a828b 161
<> 156:95d6b41a828b 162 /* Release reset of USART clock */
<> 156:95d6b41a828b 163 LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_USART1);
<> 156:95d6b41a828b 164 }
<> 156:95d6b41a828b 165 #if defined(USART2)
<> 156:95d6b41a828b 166 else if (USARTx == USART2)
<> 156:95d6b41a828b 167 {
<> 156:95d6b41a828b 168 /* Force reset of USART clock */
<> 156:95d6b41a828b 169 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
<> 156:95d6b41a828b 170
<> 156:95d6b41a828b 171 /* Release reset of USART clock */
<> 156:95d6b41a828b 172 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
<> 156:95d6b41a828b 173 }
<> 156:95d6b41a828b 174 #endif /* USART2 */
<> 156:95d6b41a828b 175 #if defined(USART3)
<> 156:95d6b41a828b 176 else if (USARTx == USART3)
<> 156:95d6b41a828b 177 {
<> 156:95d6b41a828b 178 /* Force reset of USART clock */
<> 156:95d6b41a828b 179 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
<> 156:95d6b41a828b 180
<> 156:95d6b41a828b 181 /* Release reset of USART clock */
<> 156:95d6b41a828b 182 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
<> 156:95d6b41a828b 183 }
<> 156:95d6b41a828b 184 #endif /* USART3 */
<> 156:95d6b41a828b 185 #if defined(USART4)
<> 156:95d6b41a828b 186 else if (USARTx == USART4)
<> 156:95d6b41a828b 187 {
<> 156:95d6b41a828b 188 /* Force reset of USART clock */
<> 156:95d6b41a828b 189 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART4);
<> 156:95d6b41a828b 190
<> 156:95d6b41a828b 191 /* Release reset of USART clock */
<> 156:95d6b41a828b 192 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART4);
<> 156:95d6b41a828b 193 }
<> 156:95d6b41a828b 194 #endif /* USART4 */
<> 156:95d6b41a828b 195 #if defined(USART5)
<> 156:95d6b41a828b 196 else if (USARTx == USART5)
<> 156:95d6b41a828b 197 {
<> 156:95d6b41a828b 198 /* Force reset of USART clock */
<> 156:95d6b41a828b 199 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART5);
<> 156:95d6b41a828b 200
<> 156:95d6b41a828b 201 /* Release reset of USART clock */
<> 156:95d6b41a828b 202 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART5);
<> 156:95d6b41a828b 203 }
<> 156:95d6b41a828b 204 #endif /* USART5 */
<> 156:95d6b41a828b 205 #if defined(USART6)
<> 156:95d6b41a828b 206 else if (USARTx == USART6)
<> 156:95d6b41a828b 207 {
<> 156:95d6b41a828b 208 /* Force reset of USART clock */
<> 156:95d6b41a828b 209 LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_USART6);
<> 156:95d6b41a828b 210
<> 156:95d6b41a828b 211 /* Release reset of USART clock */
<> 156:95d6b41a828b 212 LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_USART6);
<> 156:95d6b41a828b 213 }
<> 156:95d6b41a828b 214 #endif /* USART6 */
<> 156:95d6b41a828b 215 #if defined(USART7)
<> 156:95d6b41a828b 216 else if (USARTx == USART7)
<> 156:95d6b41a828b 217 {
<> 156:95d6b41a828b 218 /* Force reset of USART clock */
<> 156:95d6b41a828b 219 LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_USART7);
<> 156:95d6b41a828b 220
<> 156:95d6b41a828b 221 /* Release reset of USART clock */
<> 156:95d6b41a828b 222 LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_USART7);
<> 156:95d6b41a828b 223 }
<> 156:95d6b41a828b 224 #endif /* USART7 */
<> 156:95d6b41a828b 225 #if defined(USART8)
<> 156:95d6b41a828b 226 else if (USARTx == USART8)
<> 156:95d6b41a828b 227 {
<> 156:95d6b41a828b 228 /* Force reset of USART clock */
<> 156:95d6b41a828b 229 LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_USART8);
<> 156:95d6b41a828b 230
<> 156:95d6b41a828b 231 /* Release reset of USART clock */
<> 156:95d6b41a828b 232 LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_USART8);
<> 156:95d6b41a828b 233 }
<> 156:95d6b41a828b 234 #endif /* USART8 */
<> 156:95d6b41a828b 235 else
<> 156:95d6b41a828b 236 {
<> 156:95d6b41a828b 237 status = ERROR;
<> 156:95d6b41a828b 238 }
<> 156:95d6b41a828b 239
<> 156:95d6b41a828b 240 return (status);
<> 156:95d6b41a828b 241 }
<> 156:95d6b41a828b 242
<> 156:95d6b41a828b 243 /**
<> 156:95d6b41a828b 244 * @brief Initialize USART registers according to the specified
<> 156:95d6b41a828b 245 * parameters in USART_InitStruct.
<> 156:95d6b41a828b 246 * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
<> 156:95d6b41a828b 247 * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
<> 156:95d6b41a828b 248 * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
<> 156:95d6b41a828b 249 * @param USARTx USART Instance
<> 156:95d6b41a828b 250 * @param USART_InitStruct: pointer to a LL_USART_InitTypeDef structure
<> 156:95d6b41a828b 251 * that contains the configuration information for the specified USART peripheral.
<> 156:95d6b41a828b 252 * @retval An ErrorStatus enumeration value:
<> 156:95d6b41a828b 253 * - SUCCESS: USART registers are initialized according to USART_InitStruct content
<> 156:95d6b41a828b 254 * - ERROR: Problem occurred during USART Registers initialization
<> 156:95d6b41a828b 255 */
<> 156:95d6b41a828b 256 ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
<> 156:95d6b41a828b 257 {
<> 156:95d6b41a828b 258 ErrorStatus status = ERROR;
<> 156:95d6b41a828b 259 uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
<> 156:95d6b41a828b 260 #if defined(STM32F030x8) || defined(STM32F030xC) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F051x8) || defined(STM32F058xx) || defined(STM32F070x6) || defined(STM32F070xB) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
<> 156:95d6b41a828b 261 LL_RCC_ClocksTypeDef RCC_Clocks;
<> 156:95d6b41a828b 262 #endif
<> 156:95d6b41a828b 263
<> 156:95d6b41a828b 264 /* Check the parameters */
<> 156:95d6b41a828b 265 assert_param(IS_UART_INSTANCE(USARTx));
<> 156:95d6b41a828b 266 assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
<> 156:95d6b41a828b 267 assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
<> 156:95d6b41a828b 268 assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
<> 156:95d6b41a828b 269 assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
<> 156:95d6b41a828b 270 assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
<> 156:95d6b41a828b 271 assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
<> 156:95d6b41a828b 272 assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
<> 156:95d6b41a828b 273
<> 156:95d6b41a828b 274 /* USART needs to be in disabled state, in order to be able to configure some bits in
<> 156:95d6b41a828b 275 CRx registers */
<> 156:95d6b41a828b 276 if (LL_USART_IsEnabled(USARTx) == 0U)
<> 156:95d6b41a828b 277 {
<> 156:95d6b41a828b 278 /*---------------------------- USART CR1 Configuration -----------------------
<> 156:95d6b41a828b 279 * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
<> 156:95d6b41a828b 280 * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value
<> 156:95d6b41a828b 281 * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
<> 156:95d6b41a828b 282 * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
<> 156:95d6b41a828b 283 * - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
<> 156:95d6b41a828b 284 */
<> 156:95d6b41a828b 285 MODIFY_REG(USARTx->CR1,
<> 156:95d6b41a828b 286 (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
<> 156:95d6b41a828b 287 USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
<> 156:95d6b41a828b 288 (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
<> 156:95d6b41a828b 289 USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
<> 156:95d6b41a828b 290
<> 156:95d6b41a828b 291 /*---------------------------- USART CR2 Configuration -----------------------
<> 156:95d6b41a828b 292 * Configure USARTx CR2 (Stop bits) with parameters:
<> 156:95d6b41a828b 293 * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
<> 156:95d6b41a828b 294 * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
<> 156:95d6b41a828b 295 */
<> 156:95d6b41a828b 296 LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
<> 156:95d6b41a828b 297
<> 156:95d6b41a828b 298 /*---------------------------- USART CR3 Configuration -----------------------
<> 156:95d6b41a828b 299 * Configure USARTx CR3 (Hardware Flow Control) with parameters:
<> 156:95d6b41a828b 300 * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
<> 156:95d6b41a828b 301 */
<> 156:95d6b41a828b 302 LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
<> 156:95d6b41a828b 303
<> 156:95d6b41a828b 304 /*---------------------------- USART BRR Configuration -----------------------
<> 156:95d6b41a828b 305 * Retrieve Clock frequency used for USART Peripheral
<> 156:95d6b41a828b 306 */
<> 156:95d6b41a828b 307 if (USARTx == USART1)
<> 156:95d6b41a828b 308 {
<> 156:95d6b41a828b 309 periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE);
<> 156:95d6b41a828b 310 }
<> 156:95d6b41a828b 311 #if defined(USART2)
<> 156:95d6b41a828b 312 else if (USARTx == USART2)
<> 156:95d6b41a828b 313 {
<> 156:95d6b41a828b 314 #if defined (RCC_CFGR3_USART2SW)
<> 156:95d6b41a828b 315 periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE);
<> 156:95d6b41a828b 316 #else
<> 156:95d6b41a828b 317 /* USART2 clock is PCLK */
<> 156:95d6b41a828b 318 LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
<> 156:95d6b41a828b 319 periphclk = RCC_Clocks.PCLK1_Frequency;
<> 156:95d6b41a828b 320 #endif
<> 156:95d6b41a828b 321 }
<> 156:95d6b41a828b 322 #endif /* USART2 */
<> 156:95d6b41a828b 323 #if defined(USART3)
<> 156:95d6b41a828b 324 else if (USARTx == USART3)
<> 156:95d6b41a828b 325 {
<> 156:95d6b41a828b 326 #if defined (RCC_CFGR3_USART3SW)
<> 156:95d6b41a828b 327 periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART3_CLKSOURCE);
<> 156:95d6b41a828b 328 #else
<> 156:95d6b41a828b 329 /* USART3 clock is PCLK */
<> 156:95d6b41a828b 330 LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
<> 156:95d6b41a828b 331 periphclk = RCC_Clocks.PCLK1_Frequency;
<> 156:95d6b41a828b 332 #endif
<> 156:95d6b41a828b 333 }
<> 156:95d6b41a828b 334 #endif /* USART3 */
<> 156:95d6b41a828b 335 #if defined(USART4)
<> 156:95d6b41a828b 336 else if (USARTx == USART4)
<> 156:95d6b41a828b 337 {
<> 156:95d6b41a828b 338 /* USART4 clock is PCLK */
<> 156:95d6b41a828b 339 LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
<> 156:95d6b41a828b 340 periphclk = RCC_Clocks.PCLK1_Frequency;
<> 156:95d6b41a828b 341 }
<> 156:95d6b41a828b 342 #endif /* USART4 */
<> 156:95d6b41a828b 343 #if defined(USART5)
<> 156:95d6b41a828b 344 else if (USARTx == USART5)
<> 156:95d6b41a828b 345 {
<> 156:95d6b41a828b 346 /* USART5 clock is PCLK */
<> 156:95d6b41a828b 347 LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
<> 156:95d6b41a828b 348 periphclk = RCC_Clocks.PCLK1_Frequency;
<> 156:95d6b41a828b 349 }
<> 156:95d6b41a828b 350 #endif /* USART5 */
<> 156:95d6b41a828b 351 #if defined(USART6)
<> 156:95d6b41a828b 352 else if (USARTx == USART6)
<> 156:95d6b41a828b 353 {
<> 156:95d6b41a828b 354 /* USART6 clock is PCLK */
<> 156:95d6b41a828b 355 LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
<> 156:95d6b41a828b 356 periphclk = RCC_Clocks.PCLK1_Frequency;
<> 156:95d6b41a828b 357 }
<> 156:95d6b41a828b 358 #endif /* USART6 */
<> 156:95d6b41a828b 359 #if defined(USART7)
<> 156:95d6b41a828b 360 else if (USARTx == USART7)
<> 156:95d6b41a828b 361 {
<> 156:95d6b41a828b 362 /* USART7 clock is PCLK */
<> 156:95d6b41a828b 363 LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
<> 156:95d6b41a828b 364 periphclk = RCC_Clocks.PCLK1_Frequency;
<> 156:95d6b41a828b 365 }
<> 156:95d6b41a828b 366 #endif /* USART7 */
<> 156:95d6b41a828b 367 #if defined(USART8)
<> 156:95d6b41a828b 368 else if (USARTx == USART8)
<> 156:95d6b41a828b 369 {
<> 156:95d6b41a828b 370 /* USART8 clock is PCLK */
<> 156:95d6b41a828b 371 LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
<> 156:95d6b41a828b 372 periphclk = RCC_Clocks.PCLK1_Frequency;
<> 156:95d6b41a828b 373 }
<> 156:95d6b41a828b 374 #endif /* USART8 */
<> 156:95d6b41a828b 375 else
<> 156:95d6b41a828b 376 {
<> 156:95d6b41a828b 377 /* Nothing to do, as error code is already assigned to ERROR value */
<> 156:95d6b41a828b 378 }
<> 156:95d6b41a828b 379
<> 156:95d6b41a828b 380 /* Configure the USART Baud Rate :
<> 156:95d6b41a828b 381 - valid baud rate value (different from 0) is required
<> 156:95d6b41a828b 382 - Peripheral clock as returned by RCC service, should be valid (different from 0).
<> 156:95d6b41a828b 383 */
<> 156:95d6b41a828b 384 if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
<> 156:95d6b41a828b 385 && (USART_InitStruct->BaudRate != 0U))
<> 156:95d6b41a828b 386 {
<> 156:95d6b41a828b 387 status = SUCCESS;
<> 156:95d6b41a828b 388 LL_USART_SetBaudRate(USARTx,
<> 156:95d6b41a828b 389 periphclk,
<> 156:95d6b41a828b 390 USART_InitStruct->OverSampling,
<> 156:95d6b41a828b 391 USART_InitStruct->BaudRate);
<> 156:95d6b41a828b 392 }
<> 156:95d6b41a828b 393 }
<> 156:95d6b41a828b 394 /* Endif (=> USART not in Disabled state => return ERROR) */
<> 156:95d6b41a828b 395
<> 156:95d6b41a828b 396 return (status);
<> 156:95d6b41a828b 397 }
<> 156:95d6b41a828b 398
<> 156:95d6b41a828b 399 /**
<> 156:95d6b41a828b 400 * @brief Set each @ref LL_USART_InitTypeDef field to default value.
<> 156:95d6b41a828b 401 * @param USART_InitStruct: pointer to a @ref LL_USART_InitTypeDef structure
<> 156:95d6b41a828b 402 * whose fields will be set to default values.
<> 156:95d6b41a828b 403 * @retval None
<> 156:95d6b41a828b 404 */
<> 156:95d6b41a828b 405
<> 156:95d6b41a828b 406 void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
<> 156:95d6b41a828b 407 {
<> 156:95d6b41a828b 408 /* Set USART_InitStruct fields to default values */
<> 156:95d6b41a828b 409 USART_InitStruct->BaudRate = 9600U;
<> 156:95d6b41a828b 410 USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B;
<> 156:95d6b41a828b 411 USART_InitStruct->StopBits = LL_USART_STOPBITS_1;
<> 156:95d6b41a828b 412 USART_InitStruct->Parity = LL_USART_PARITY_NONE ;
<> 156:95d6b41a828b 413 USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX;
<> 156:95d6b41a828b 414 USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
<> 156:95d6b41a828b 415 USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16;
<> 156:95d6b41a828b 416 }
<> 156:95d6b41a828b 417
<> 156:95d6b41a828b 418 /**
<> 156:95d6b41a828b 419 * @brief Initialize USART Clock related settings according to the
<> 156:95d6b41a828b 420 * specified parameters in the USART_ClockInitStruct.
<> 156:95d6b41a828b 421 * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
<> 156:95d6b41a828b 422 * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
<> 156:95d6b41a828b 423 * @param USARTx USART Instance
<> 156:95d6b41a828b 424 * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
<> 156:95d6b41a828b 425 * that contains the Clock configuration information for the specified USART peripheral.
<> 156:95d6b41a828b 426 * @retval An ErrorStatus enumeration value:
<> 156:95d6b41a828b 427 * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
<> 156:95d6b41a828b 428 * - ERROR: Problem occurred during USART Registers initialization
<> 156:95d6b41a828b 429 */
<> 156:95d6b41a828b 430 ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
<> 156:95d6b41a828b 431 {
<> 156:95d6b41a828b 432 ErrorStatus status = SUCCESS;
<> 156:95d6b41a828b 433
<> 156:95d6b41a828b 434 /* Check USART Instance and Clock signal output parameters */
<> 156:95d6b41a828b 435 assert_param(IS_UART_INSTANCE(USARTx));
<> 156:95d6b41a828b 436 assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
<> 156:95d6b41a828b 437
<> 156:95d6b41a828b 438 /* USART needs to be in disabled state, in order to be able to configure some bits in
<> 156:95d6b41a828b 439 CRx registers */
<> 156:95d6b41a828b 440 if (LL_USART_IsEnabled(USARTx) == 0U)
<> 156:95d6b41a828b 441 {
<> 156:95d6b41a828b 442 /*---------------------------- USART CR2 Configuration -----------------------*/
<> 156:95d6b41a828b 443 /* If Clock signal has to be output */
<> 156:95d6b41a828b 444 if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
<> 156:95d6b41a828b 445 {
<> 156:95d6b41a828b 446 /* Deactivate Clock signal delivery :
<> 156:95d6b41a828b 447 * - Disable Clock Output: USART_CR2_CLKEN cleared
<> 156:95d6b41a828b 448 */
<> 156:95d6b41a828b 449 LL_USART_DisableSCLKOutput(USARTx);
<> 156:95d6b41a828b 450 }
<> 156:95d6b41a828b 451 else
<> 156:95d6b41a828b 452 {
<> 156:95d6b41a828b 453 /* Ensure USART instance is USART capable */
<> 156:95d6b41a828b 454 assert_param(IS_USART_INSTANCE(USARTx));
<> 156:95d6b41a828b 455
<> 156:95d6b41a828b 456 /* Check clock related parameters */
<> 156:95d6b41a828b 457 assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
<> 156:95d6b41a828b 458 assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
<> 156:95d6b41a828b 459 assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
<> 156:95d6b41a828b 460
<> 156:95d6b41a828b 461 /*---------------------------- USART CR2 Configuration -----------------------
<> 156:95d6b41a828b 462 * Configure USARTx CR2 (Clock signal related bits) with parameters:
<> 156:95d6b41a828b 463 * - Enable Clock Output: USART_CR2_CLKEN set
<> 156:95d6b41a828b 464 * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
<> 156:95d6b41a828b 465 * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
<> 156:95d6b41a828b 466 * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
<> 156:95d6b41a828b 467 */
<> 156:95d6b41a828b 468 MODIFY_REG(USARTx->CR2,
<> 156:95d6b41a828b 469 USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
<> 156:95d6b41a828b 470 USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
<> 156:95d6b41a828b 471 USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
<> 156:95d6b41a828b 472 }
<> 156:95d6b41a828b 473 }
<> 156:95d6b41a828b 474 /* Else (USART not in Disabled state => return ERROR */
<> 156:95d6b41a828b 475 else
<> 156:95d6b41a828b 476 {
<> 156:95d6b41a828b 477 status = ERROR;
<> 156:95d6b41a828b 478 }
<> 156:95d6b41a828b 479
<> 156:95d6b41a828b 480 return (status);
<> 156:95d6b41a828b 481 }
<> 156:95d6b41a828b 482
<> 156:95d6b41a828b 483 /**
<> 156:95d6b41a828b 484 * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
<> 156:95d6b41a828b 485 * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
<> 156:95d6b41a828b 486 * whose fields will be set to default values.
<> 156:95d6b41a828b 487 * @retval None
<> 156:95d6b41a828b 488 */
<> 156:95d6b41a828b 489 void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
<> 156:95d6b41a828b 490 {
<> 156:95d6b41a828b 491 /* Set LL_USART_ClockInitStruct fields with default values */
<> 156:95d6b41a828b 492 USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE;
<> 156:95d6b41a828b 493 USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
<> 156:95d6b41a828b 494 USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
<> 156:95d6b41a828b 495 USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
<> 156:95d6b41a828b 496 }
<> 156:95d6b41a828b 497
<> 156:95d6b41a828b 498 /**
<> 156:95d6b41a828b 499 * @}
<> 156:95d6b41a828b 500 */
<> 156:95d6b41a828b 501
<> 156:95d6b41a828b 502 /**
<> 156:95d6b41a828b 503 * @}
<> 156:95d6b41a828b 504 */
<> 156:95d6b41a828b 505
<> 156:95d6b41a828b 506 /**
<> 156:95d6b41a828b 507 * @}
<> 156:95d6b41a828b 508 */
<> 156:95d6b41a828b 509
<> 156:95d6b41a828b 510 #endif /* USART1 || USART2|| USART3 || USART4 || USART5 || USART6 || USART7 || USART8 */
<> 156:95d6b41a828b 511
<> 156:95d6b41a828b 512 /**
<> 156:95d6b41a828b 513 * @}
<> 156:95d6b41a828b 514 */
<> 156:95d6b41a828b 515
<> 156:95d6b41a828b 516 #endif /* USE_FULL_LL_DRIVER */
<> 156:95d6b41a828b 517
<> 156:95d6b41a828b 518 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 156:95d6b41a828b 519