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targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/system_clock.c@178:d650f5d4c87a, 2017-11-08 (annotated)

Committer:
AnnaBridge
Date:
Wed Nov 08 13:50:44 2017 +0000
Revision:
178:d650f5d4c87a
Parent:
171:19eb464bc2be 
This updates the lib to the mbed lib v 155

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 171:19eb464bc2be 1 /* mbed Microcontroller Library
Kojto 171:19eb464bc2be 2 * Copyright (c) 2006-2017 ARM Limited
Kojto 171:19eb464bc2be 3 *
Kojto 171:19eb464bc2be 4 * Licensed under the Apache License, Version 2.0 (the "License");
Kojto 171:19eb464bc2be 5 * you may not use this file except in compliance with the License.
Kojto 171:19eb464bc2be 6 * You may obtain a copy of the License at
Kojto 171:19eb464bc2be 7 *
Kojto 171:19eb464bc2be 8 * http://www.apache.org/licenses/LICENSE-2.0
Kojto 171:19eb464bc2be 9 *
Kojto 171:19eb464bc2be 10 * Unless required by applicable law or agreed to in writing, software
Kojto 171:19eb464bc2be 11 * distributed under the License is distributed on an "AS IS" BASIS,
Kojto 171:19eb464bc2be 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Kojto 171:19eb464bc2be 13 * See the License for the specific language governing permissions and
Kojto 171:19eb464bc2be 14 * limitations under the License.
Kojto 171:19eb464bc2be 15 */
Kojto 171:19eb464bc2be 16
Kojto 171:19eb464bc2be 17 /**
Kojto 171:19eb464bc2be 18 * This file configures the system clock as follows:
Kojto 171:19eb464bc2be 19 *--------------------------------------------------------------------
Kojto 171:19eb464bc2be 20 * System clock source | 1- USE_PLL_HSE_EXTC (external 25 MHz clock)
Kojto 171:19eb464bc2be 21 * | 2- USE_PLL_HSE_XTAL (external 25 MHz xtal)
Kojto 171:19eb464bc2be 22 * | 3- USE_PLL_HSI (internal 16 MHz clock)
Kojto 171:19eb464bc2be 23 *--------------------------------------------------------------------
Kojto 171:19eb464bc2be 24 * SYSCLK(MHz) | 216
Kojto 171:19eb464bc2be 25 * AHBCLK (MHz) | 216
Kojto 171:19eb464bc2be 26 * APB1CLK (MHz) | 54
Kojto 171:19eb464bc2be 27 * APB2CLK (MHz) | 108
Kojto 171:19eb464bc2be 28 * USB capable (48 MHz) | YES
Kojto 171:19eb464bc2be 29 *--------------------------------------------------------------------
Kojto 171:19eb464bc2be 30 **/
Kojto 171:19eb464bc2be 31
Kojto 171:19eb464bc2be 32 #include "stm32f7xx.h"
Kojto 171:19eb464bc2be 33 #include "mbed_assert.h"
Kojto 171:19eb464bc2be 34
Kojto 171:19eb464bc2be 35 /*!< Uncomment the following line if you need to relocate your vector Table in
Kojto 171:19eb464bc2be 36 Internal SRAM. */
Kojto 171:19eb464bc2be 37 /* #define VECT_TAB_SRAM */
Kojto 171:19eb464bc2be 38 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
Kojto 171:19eb464bc2be 39 This value must be a multiple of 0x200. */
Kojto 171:19eb464bc2be 40
Kojto 171:19eb464bc2be 41 // clock source is selected with CLOCK_SOURCE in json config
Kojto 171:19eb464bc2be 42 #define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
Kojto 171:19eb464bc2be 43 #define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
Kojto 171:19eb464bc2be 44 #define USE_PLL_HSI 0x2 // Use HSI internal clock
Kojto 171:19eb464bc2be 45
Kojto 171:19eb464bc2be 46 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
Kojto 171:19eb464bc2be 47 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
Kojto 171:19eb464bc2be 48 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
Kojto 171:19eb464bc2be 49
Kojto 171:19eb464bc2be 50 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
Kojto 171:19eb464bc2be 51 uint8_t SetSysClock_PLL_HSI(void);
Kojto 171:19eb464bc2be 52 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
Kojto 171:19eb464bc2be 53
Kojto 171:19eb464bc2be 54
Kojto 171:19eb464bc2be 55 /**
Kojto 171:19eb464bc2be 56 * @brief Setup the microcontroller system
Kojto 171:19eb464bc2be 57 * Initialize the Embedded Flash Interface, the PLL and update the
Kojto 171:19eb464bc2be 58 * SystemFrequency variable.
Kojto 171:19eb464bc2be 59 * @param None
Kojto 171:19eb464bc2be 60 * @retval None
Kojto 171:19eb464bc2be 61 */
Kojto 171:19eb464bc2be 62 void SystemInit(void)
Kojto 171:19eb464bc2be 63 {
Kojto 171:19eb464bc2be 64 /* FPU settings ------------------------------------------------------------*/
Kojto 171:19eb464bc2be 65 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 171:19eb464bc2be 66 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
Kojto 171:19eb464bc2be 67 #endif
Kojto 171:19eb464bc2be 68 /* Reset the RCC clock configuration to the default reset state ------------*/
Kojto 171:19eb464bc2be 69 /* Set HSION bit */
Kojto 171:19eb464bc2be 70 RCC->CR |= (uint32_t)0x00000001;
Kojto 171:19eb464bc2be 71
Kojto 171:19eb464bc2be 72 /* Reset CFGR register */
Kojto 171:19eb464bc2be 73 RCC->CFGR = 0x00000000;
Kojto 171:19eb464bc2be 74
Kojto 171:19eb464bc2be 75 /* Reset HSEON, CSSON and PLLON bits */
Kojto 171:19eb464bc2be 76 RCC->CR &= (uint32_t)0xFEF6FFFF;
Kojto 171:19eb464bc2be 77
Kojto 171:19eb464bc2be 78 /* Reset PLLCFGR register */
Kojto 171:19eb464bc2be 79 RCC->PLLCFGR = 0x24003010;
Kojto 171:19eb464bc2be 80
Kojto 171:19eb464bc2be 81 /* Reset HSEBYP bit */
Kojto 171:19eb464bc2be 82 RCC->CR &= (uint32_t)0xFFFBFFFF;
Kojto 171:19eb464bc2be 83
Kojto 171:19eb464bc2be 84 /* Disable all interrupts */
Kojto 171:19eb464bc2be 85 RCC->CIR = 0x00000000;
Kojto 171:19eb464bc2be 86
Kojto 171:19eb464bc2be 87 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
Kojto 171:19eb464bc2be 88 SystemInit_ExtMemCtl();
Kojto 171:19eb464bc2be 89 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
Kojto 171:19eb464bc2be 90
Kojto 171:19eb464bc2be 91 /* Configure the Vector Table location add offset address ------------------*/
Kojto 171:19eb464bc2be 92 #ifdef VECT_TAB_SRAM
Kojto 171:19eb464bc2be 93 SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
Kojto 171:19eb464bc2be 94 #else
Kojto 171:19eb464bc2be 95 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
Kojto 171:19eb464bc2be 96 #endif
Kojto 171:19eb464bc2be 97
Kojto 171:19eb464bc2be 98 }
Kojto 171:19eb464bc2be 99
Kojto 171:19eb464bc2be 100 /**
Kojto 171:19eb464bc2be 101 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
Kojto 171:19eb464bc2be 102 * AHB/APBx prescalers and Flash settings
Kojto 171:19eb464bc2be 103 * @note This function should be called only once the RCC clock configuration
Kojto 171:19eb464bc2be 104 * is reset to the default reset state (done in SystemInit() function).
Kojto 171:19eb464bc2be 105 * @param None
Kojto 171:19eb464bc2be 106 * @retval None
Kojto 171:19eb464bc2be 107 */
Kojto 171:19eb464bc2be 108
Kojto 171:19eb464bc2be 109 void SetSysClock(void)
Kojto 171:19eb464bc2be 110 {
Kojto 171:19eb464bc2be 111 #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
Kojto 171:19eb464bc2be 112 /* 1- Try to start with HSE and external clock */
Kojto 171:19eb464bc2be 113 if (SetSysClock_PLL_HSE(1) == 0)
Kojto 171:19eb464bc2be 114 #endif
Kojto 171:19eb464bc2be 115 {
Kojto 171:19eb464bc2be 116 #if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
Kojto 171:19eb464bc2be 117 /* 2- If fail try to start with HSE and external xtal */
Kojto 171:19eb464bc2be 118 if (SetSysClock_PLL_HSE(0) == 0)
Kojto 171:19eb464bc2be 119 #endif
Kojto 171:19eb464bc2be 120 {
Kojto 171:19eb464bc2be 121 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
Kojto 171:19eb464bc2be 122 /* 3- If fail start with HSI clock */
Kojto 171:19eb464bc2be 123 if (SetSysClock_PLL_HSI() == 0)
Kojto 171:19eb464bc2be 124 #endif
Kojto 171:19eb464bc2be 125 {
Kojto 171:19eb464bc2be 126 while(1) {
Kojto 171:19eb464bc2be 127 MBED_ASSERT(1);
Kojto 171:19eb464bc2be 128 }
Kojto 171:19eb464bc2be 129 }
Kojto 171:19eb464bc2be 130 }
Kojto 171:19eb464bc2be 131 }
Kojto 171:19eb464bc2be 132
Kojto 171:19eb464bc2be 133 // Output clock on MCO2 pin(PC9) for debugging purpose
Kojto 171:19eb464bc2be 134 // Can be visualized on uSD card CN3 connector pin 8
Kojto 171:19eb464bc2be 135 //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 216 MHz / 4 = 54 MHz
Kojto 171:19eb464bc2be 136 }
Kojto 171:19eb464bc2be 137
Kojto 171:19eb464bc2be 138 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
Kojto 171:19eb464bc2be 139 /******************************************************************************/
Kojto 171:19eb464bc2be 140 /* PLL (clocked by HSE) used as System clock source */
Kojto 171:19eb464bc2be 141 /******************************************************************************/
Kojto 171:19eb464bc2be 142 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
Kojto 171:19eb464bc2be 143 {
Kojto 171:19eb464bc2be 144 RCC_ClkInitTypeDef RCC_ClkInitStruct;
Kojto 171:19eb464bc2be 145 RCC_OscInitTypeDef RCC_OscInitStruct;
Kojto 171:19eb464bc2be 146 RCC_PeriphCLKInitTypeDef RCC_PeriphClkInitStruct;
Kojto 171:19eb464bc2be 147
Kojto 171:19eb464bc2be 148 // Enable power clock
Kojto 171:19eb464bc2be 149 __PWR_CLK_ENABLE();
Kojto 171:19eb464bc2be 150 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
Kojto 171:19eb464bc2be 151
Kojto 171:19eb464bc2be 152 // Enable HSE oscillator and activate PLL with HSE as source
Kojto 171:19eb464bc2be 153 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
Kojto 171:19eb464bc2be 154 if (bypass == 0) {
Kojto 171:19eb464bc2be 155 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External xtal on OSC_IN/OSC_OUT */
Kojto 171:19eb464bc2be 156 } else {
Kojto 171:19eb464bc2be 157 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External clock on OSC_IN */
Kojto 171:19eb464bc2be 158 }
Kojto 171:19eb464bc2be 159 // Warning: this configuration is for a 25 MHz xtal clock only
Kojto 171:19eb464bc2be 160 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
Kojto 171:19eb464bc2be 161 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
Kojto 171:19eb464bc2be 162 RCC_OscInitStruct.PLL.PLLM = 25; // VCO input clock = 1 MHz (25 MHz / 25)
Kojto 171:19eb464bc2be 163 RCC_OscInitStruct.PLL.PLLN = 432; // VCO output clock = 432 MHz (1 MHz * 432)
Kojto 171:19eb464bc2be 164 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
Kojto 171:19eb464bc2be 165 RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
Kojto 171:19eb464bc2be 166
Kojto 171:19eb464bc2be 167 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
Kojto 171:19eb464bc2be 168 return 0; // FAIL
Kojto 171:19eb464bc2be 169 }
Kojto 171:19eb464bc2be 170
Kojto 171:19eb464bc2be 171 // Activate the OverDrive to reach the 216 MHz Frequency
Kojto 171:19eb464bc2be 172 if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
Kojto 171:19eb464bc2be 173 return 0; // FAIL
Kojto 171:19eb464bc2be 174 }
Kojto 171:19eb464bc2be 175
Kojto 171:19eb464bc2be 176 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
Kojto 171:19eb464bc2be 177 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
Kojto 171:19eb464bc2be 178 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
Kojto 171:19eb464bc2be 179 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 216 MHz
Kojto 171:19eb464bc2be 180 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 54 MHz
Kojto 171:19eb464bc2be 181 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 108 MHz
Kojto 171:19eb464bc2be 182
Kojto 171:19eb464bc2be 183 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) {
Kojto 171:19eb464bc2be 184 return 0; // FAIL
Kojto 171:19eb464bc2be 185 }
Kojto 171:19eb464bc2be 186
Kojto 171:19eb464bc2be 187 RCC_PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
Kojto 171:19eb464bc2be 188 RCC_PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL;
Kojto 171:19eb464bc2be 189 if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStruct) != HAL_OK) {
Kojto 171:19eb464bc2be 190 return 0; // FAIL
Kojto 171:19eb464bc2be 191 }
Kojto 171:19eb464bc2be 192
Kojto 171:19eb464bc2be 193 return 1; // OK
Kojto 171:19eb464bc2be 194 }
Kojto 171:19eb464bc2be 195 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
Kojto 171:19eb464bc2be 196
Kojto 171:19eb464bc2be 197 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
Kojto 171:19eb464bc2be 198 /******************************************************************************/
Kojto 171:19eb464bc2be 199 /* PLL (clocked by HSI) used as System clock source */
Kojto 171:19eb464bc2be 200 /******************************************************************************/
Kojto 171:19eb464bc2be 201 uint8_t SetSysClock_PLL_HSI(void)
Kojto 171:19eb464bc2be 202 {
Kojto 171:19eb464bc2be 203 RCC_ClkInitTypeDef RCC_ClkInitStruct;
Kojto 171:19eb464bc2be 204 RCC_OscInitTypeDef RCC_OscInitStruct;
Kojto 171:19eb464bc2be 205 RCC_PeriphCLKInitTypeDef RCC_PeriphClkInitStruct;
Kojto 171:19eb464bc2be 206
Kojto 171:19eb464bc2be 207 // Enable power clock
Kojto 171:19eb464bc2be 208 __PWR_CLK_ENABLE();
Kojto 171:19eb464bc2be 209
Kojto 171:19eb464bc2be 210 // Enable HSI oscillator and activate PLL with HSI as source
Kojto 171:19eb464bc2be 211 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
Kojto 171:19eb464bc2be 212 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
Kojto 171:19eb464bc2be 213 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
Kojto 171:19eb464bc2be 214 RCC_OscInitStruct.HSICalibrationValue = 16;
Kojto 171:19eb464bc2be 215 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
Kojto 171:19eb464bc2be 216 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
Kojto 171:19eb464bc2be 217 RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
Kojto 171:19eb464bc2be 218 RCC_OscInitStruct.PLL.PLLN = 216; // VCO output clock = 432 MHz (2 MHz * 216)
Kojto 171:19eb464bc2be 219 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
Kojto 171:19eb464bc2be 220 RCC_OscInitStruct.PLL.PLLQ = 9;
Kojto 171:19eb464bc2be 221
Kojto 171:19eb464bc2be 222 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
Kojto 171:19eb464bc2be 223 return 0; // FAIL
Kojto 171:19eb464bc2be 224 }
Kojto 171:19eb464bc2be 225
Kojto 171:19eb464bc2be 226 // Activate the OverDrive to reach the 216 MHz Frequency
Kojto 171:19eb464bc2be 227 if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
Kojto 171:19eb464bc2be 228 return 0; // FAIL
Kojto 171:19eb464bc2be 229 }
Kojto 171:19eb464bc2be 230
Kojto 171:19eb464bc2be 231 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
Kojto 171:19eb464bc2be 232 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
Kojto 171:19eb464bc2be 233 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
Kojto 171:19eb464bc2be 234 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 216 MHz
Kojto 171:19eb464bc2be 235 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 54 MHz
Kojto 171:19eb464bc2be 236 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 108 MHz
Kojto 171:19eb464bc2be 237
Kojto 171:19eb464bc2be 238 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) {
Kojto 171:19eb464bc2be 239 return 0; // FAIL
Kojto 171:19eb464bc2be 240 }
Kojto 171:19eb464bc2be 241
Kojto 171:19eb464bc2be 242 RCC_PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
Kojto 171:19eb464bc2be 243 RCC_PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL;
Kojto 171:19eb464bc2be 244 if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStruct) != HAL_OK) {
Kojto 171:19eb464bc2be 245 return 0; // FAIL
Kojto 171:19eb464bc2be 246 }
Kojto 171:19eb464bc2be 247
Kojto 171:19eb464bc2be 248 return 1; // OK
Kojto 171:19eb464bc2be 249 }
Kojto 171:19eb464bc2be 250 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */