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targets/TARGET_Maxim/TARGET_MAX32630/device/wdt_regs.h@178:d650f5d4c87a, 2017-11-08 (annotated)

Committer:
AnnaBridge
Date:
Wed Nov 08 13:50:44 2017 +0000
Revision:
178:d650f5d4c87a
Parent:
157:ff67d9f36b67 
This updates the lib to the mbed lib v 155

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 157:ff67d9f36b67 1 /**
<> 157:ff67d9f36b67 2 * @file
<> 157:ff67d9f36b67 3 * @brief Type definitions for the Watchdog Timer Peripheral
<> 157:ff67d9f36b67 4 *
<> 157:ff67d9f36b67 5 */
<> 157:ff67d9f36b67 6 /* ****************************************************************************
<> 157:ff67d9f36b67 7 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 157:ff67d9f36b67 8 *
<> 157:ff67d9f36b67 9 * Permission is hereby granted, free of charge, to any person obtaining a
<> 157:ff67d9f36b67 10 * copy of this software and associated documentation files (the "Software"),
<> 157:ff67d9f36b67 11 * to deal in the Software without restriction, including without limitation
<> 157:ff67d9f36b67 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 157:ff67d9f36b67 13 * and/or sell copies of the Software, and to permit persons to whom the
<> 157:ff67d9f36b67 14 * Software is furnished to do so, subject to the following conditions:
<> 157:ff67d9f36b67 15 *
<> 157:ff67d9f36b67 16 * The above copyright notice and this permission notice shall be included
<> 157:ff67d9f36b67 17 * in all copies or substantial portions of the Software.
<> 157:ff67d9f36b67 18 *
<> 157:ff67d9f36b67 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 157:ff67d9f36b67 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 157:ff67d9f36b67 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 157:ff67d9f36b67 22 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 157:ff67d9f36b67 23 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 157:ff67d9f36b67 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 157:ff67d9f36b67 25 * OTHER DEALINGS IN THE SOFTWARE.
<> 157:ff67d9f36b67 26 *
<> 157:ff67d9f36b67 27 * Except as contained in this notice, the name of Maxim Integrated
<> 157:ff67d9f36b67 28 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 157:ff67d9f36b67 29 * Products, Inc. Branding Policy.
<> 157:ff67d9f36b67 30 *
<> 157:ff67d9f36b67 31 * The mere transfer of this software does not imply any licenses
<> 157:ff67d9f36b67 32 * of trade secrets, proprietary technology, copyrights, patents,
<> 157:ff67d9f36b67 33 * trademarks, maskwork rights, or any other form of intellectual
<> 157:ff67d9f36b67 34 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 157:ff67d9f36b67 35 * ownership rights.
<> 157:ff67d9f36b67 36 *
<> 157:ff67d9f36b67 37 * $Date: 2016-10-10 19:53:06 -0500 (Mon, 10 Oct 2016) $
<> 157:ff67d9f36b67 38 * $Revision: 24677 $
<> 157:ff67d9f36b67 39 *
<> 157:ff67d9f36b67 40 *
<> 157:ff67d9f36b67 41 **************************************************************************** */
<> 157:ff67d9f36b67 42
<> 157:ff67d9f36b67 43 /* Define to prevent redundant inclusion */
<> 157:ff67d9f36b67 44 #ifndef _MXC_WDT_REGS_H_
<> 157:ff67d9f36b67 45 #define _MXC_WDT_REGS_H_
<> 157:ff67d9f36b67 46
<> 157:ff67d9f36b67 47 /* **** Includes **** */
<> 157:ff67d9f36b67 48 #include <stdint.h>
<> 157:ff67d9f36b67 49
<> 157:ff67d9f36b67 50 #ifdef __cplusplus
<> 157:ff67d9f36b67 51 extern "C" {
<> 157:ff67d9f36b67 52 #endif
<> 157:ff67d9f36b67 53
<> 157:ff67d9f36b67 54
<> 157:ff67d9f36b67 55 ///@cond
<> 157:ff67d9f36b67 56 /*
<> 157:ff67d9f36b67 57 If types are not defined elsewhere (CMSIS) define them here
<> 157:ff67d9f36b67 58 */
<> 157:ff67d9f36b67 59 #ifndef __IO
<> 157:ff67d9f36b67 60 #define __IO volatile
<> 157:ff67d9f36b67 61 #endif
<> 157:ff67d9f36b67 62 #ifndef __I
<> 157:ff67d9f36b67 63 #define __I volatile const
<> 157:ff67d9f36b67 64 #endif
<> 157:ff67d9f36b67 65 #ifndef __O
<> 157:ff67d9f36b67 66 #define __O volatile
<> 157:ff67d9f36b67 67 #endif
<> 157:ff67d9f36b67 68 #ifndef __RO
<> 157:ff67d9f36b67 69 #define __RO volatile const
<> 157:ff67d9f36b67 70 #endif
<> 157:ff67d9f36b67 71 ///@endcond
<> 157:ff67d9f36b67 72
<> 157:ff67d9f36b67 73 /**
<> 157:ff67d9f36b67 74 * @ingroup wdt0
<> 157:ff67d9f36b67 75 * @defgroup wdt_registers Registers
<> 157:ff67d9f36b67 76 * @brief Registers, Bit Masks and Bit Positions
<> 157:ff67d9f36b67 77 * @{
<> 157:ff67d9f36b67 78 */
<> 157:ff67d9f36b67 79 /*
<> 157:ff67d9f36b67 80 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
<> 157:ff67d9f36b67 81 access to each register in module.
<> 157:ff67d9f36b67 82 */
<> 157:ff67d9f36b67 83 /**
<> 157:ff67d9f36b67 84 * Structure type to access the WDT Registers, see #MXC_WDT_GET_WDT(i) to get a pointer to the WDT[i] register structure.
<> 157:ff67d9f36b67 85 * @note For the Always-On Watch Dog Timer, see \ref wdt2.
<> 157:ff67d9f36b67 86 */
<> 157:ff67d9f36b67 87 typedef struct {
<> 157:ff67d9f36b67 88 __IO uint32_t ctrl; /**< <tt>\b 0x0000:</tt> WDT_CTRL Register - WDT Control Register */
<> 157:ff67d9f36b67 89 __IO uint32_t clear; /**< <tt>\b 0x0004:</tt> WDT_CLEAR Register - WDT Clear Register to prevent a WDT Reset (Feed Dog) */
<> 157:ff67d9f36b67 90 __IO uint32_t flags; /**< <tt>\b 0x0008:</tt> WDT_FLAGS Register - WDT Interrupt and Reset Flags */
<> 157:ff67d9f36b67 91 __IO uint32_t enable; /**< <tt>\b 0x000C:</tt> WDT_ENABLE Register - WDT Reset and Interrupt Enable/Disable Controls */
<> 157:ff67d9f36b67 92 __RO uint32_t rsv010; /**< <tt>\b 0x0010:</tt> RESERVED, DO NOT MODIFY. */
<> 157:ff67d9f36b67 93 __IO uint32_t lock_ctrl; /**< <tt>\b 0x0014:</tt> WDT_LOCK_CTRL Register - Lock for Control Register */
<> 157:ff67d9f36b67 94 } mxc_wdt_regs_t;
<> 157:ff67d9f36b67 95 /**@} end of group wdt_registers.*/
<> 157:ff67d9f36b67 96
<> 157:ff67d9f36b67 97 /*
<> 157:ff67d9f36b67 98 Register offsets for module WDT.
<> 157:ff67d9f36b67 99 */
<> 157:ff67d9f36b67 100 /**
<> 157:ff67d9f36b67 101 * @ingroup wdt_registers
<> 157:ff67d9f36b67 102 * @defgroup WDT_Register_Offsets Register Offsets
<> 157:ff67d9f36b67 103 * @brief Watchdog Timer Register Offsets from the WDT[n] Base Peripheral Address, where n is between 0 and #MXC_CFG_WDT_INSTANCES for the \MXIM_Device.
<> 157:ff67d9f36b67 104 * @details Use #MXC_WDT_GET_BASE(i) to get the base address for a specific watchdog timer instance.
<> 157:ff67d9f36b67 105 * @note See \ref wdt2 for the Always-On Watchdog Timer Peripheral driver.
<> 157:ff67d9f36b67 106 * @{
<> 157:ff67d9f36b67 107 */
<> 157:ff67d9f36b67 108 #define MXC_R_WDT_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from the WDT[i] Base Peripheral Address : WDT_CTRL : <tt>\b 0x0000 </tt> */
<> 157:ff67d9f36b67 109 #define MXC_R_WDT_OFFS_CLEAR ((uint32_t)0x00000004UL) /**< Offset from the WDT[i] Base Peripheral Address : WDT_CLEAR : <tt>\b 0x0004 </tt> */
<> 157:ff67d9f36b67 110 #define MXC_R_WDT_OFFS_FLAGS ((uint32_t)0x00000008UL) /**< Offset from the WDT[i] Base Peripheral Address : WDT_FLAGS : <tt>\b 0x0008 </tt> */
<> 157:ff67d9f36b67 111 #define MXC_R_WDT_OFFS_ENABLE ((uint32_t)0x0000000CUL) /**< Offset from the WDT[i] Base Peripheral Address : WDT_ENABLE : <tt>\b 0x000C </tt> */
<> 157:ff67d9f36b67 112 #define MXC_R_WDT_OFFS_LOCK_CTRL ((uint32_t)0x00000014UL) /**< Offset from the WDT[i] Base Peripheral Address : WDT_LOCK_CTRL : <tt>\b 0x0014 </tt> */
<> 157:ff67d9f36b67 113 /**@} end of group WDT_Register_Offsets */
<> 157:ff67d9f36b67 114
<> 157:ff67d9f36b67 115 /*
<> 157:ff67d9f36b67 116 Field positions and masks for module WDT.
<> 157:ff67d9f36b67 117 */
<> 157:ff67d9f36b67 118 /**
<> 157:ff67d9f36b67 119 * @ingroup wdt_registers
<> 157:ff67d9f36b67 120 * @defgroup WDT_CTRL_Register WDT_CTRL Register
<> 157:ff67d9f36b67 121 * @brief Field Positions and Bit Masks for the WDT_CTRL register
<> 157:ff67d9f36b67 122 * @{
<> 157:ff67d9f36b67 123 */
<> 157:ff67d9f36b67 124 #define MXC_F_WDT_CTRL_INT_PERIOD_POS 0 /**< INT_PERIOD Field Position */
<> 157:ff67d9f36b67 125 #define MXC_F_WDT_CTRL_INT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< INT_PERIOD Field Mask - This field is used to set the interrupt period on the WDT. */
<> 157:ff67d9f36b67 126 #define MXC_F_WDT_CTRL_RST_PERIOD_POS 4 /**< RST_PERIOD Field Position */
<> 157:ff67d9f36b67 127 #define MXC_F_WDT_CTRL_RST_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< RST_PERIOD Field Mask - This field sets the time after an
<> 157:ff67d9f36b67 128 * interrupt period has expired before the device resets. If the
<> 157:ff67d9f36b67 129 * INT_PERIOD Flag is cleared prior to the RST_PERIOD expiration,
<> 157:ff67d9f36b67 130 * the device will not reset. */
<> 157:ff67d9f36b67 131 #define MXC_F_WDT_CTRL_EN_TIMER_POS 8 /**< EN_TIMER Field Position */
<> 157:ff67d9f36b67 132 #define MXC_F_WDT_CTRL_EN_TIMER ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_TIMER_POS)) /**< EN_TIMER Field Mask */
<> 157:ff67d9f36b67 133 #define MXC_F_WDT_CTRL_EN_CLOCK_POS 9 /**< EN_CLOCK Field Position */
<> 157:ff67d9f36b67 134 #define MXC_F_WDT_CTRL_EN_CLOCK ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_CLOCK_POS)) /**< EN_CLOCK Field Mask */
<> 157:ff67d9f36b67 135 #define MXC_F_WDT_CTRL_WAIT_PERIOD_POS 12 /**< WAIT_PERIOD Field Position */
<> 157:ff67d9f36b67 136 #define MXC_F_WDT_CTRL_WAIT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< WAIT_PERIOD Field Mask */
<> 157:ff67d9f36b67 137 /**@} end of group WDT_CTRL */
<> 157:ff67d9f36b67 138 /**
<> 157:ff67d9f36b67 139 * @ingroup wdt_registers
<> 157:ff67d9f36b67 140 * @defgroup WDT_FLAGS_Register WDT_FLAGS Register
<> 157:ff67d9f36b67 141 * @brief Field Positions and Bit Masks for the WDT_FLAGS register. Watchdog Timer Flags for Interrupts and Reset.
<> 157:ff67d9f36b67 142 * @{
<> 157:ff67d9f36b67 143 */
<> 157:ff67d9f36b67 144 #define MXC_F_WDT_FLAGS_TIMEOUT_POS 0 /**< TIMEOUT Flag Position */
<> 157:ff67d9f36b67 145 #define MXC_F_WDT_FLAGS_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_TIMEOUT_POS)) /**< TIMEOUT Flag Mask - if this flag is set it indicates the Watchdog Timer timed out. */
<> 157:ff67d9f36b67 146 #define MXC_F_WDT_FLAGS_PRE_WIN_POS 1 /**< PRE_WIN Flag Position */
<> 157:ff67d9f36b67 147 #define MXC_F_WDT_FLAGS_PRE_WIN ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_PRE_WIN_POS)) /**< PRE_WIN Flag Mask - If the PRE_WIN flag is set it indicates the Watchdog Timer was cleared by firmware writing to the WDT_CLEAR register <b><em> during the pre-window period</em></b>. */
<> 157:ff67d9f36b67 148 #define MXC_F_WDT_FLAGS_RESET_OUT_POS 2 /**< RESET_OUT Flag Position */
<> 157:ff67d9f36b67 149 #define MXC_F_WDT_FLAGS_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_RESET_OUT_POS)) /**< RESET_FLAG Flag Mask - This flag indicates that the watchdog timer timed out and the reset period elapsed without the timer being cleared. This will result in a system restart. */
<> 157:ff67d9f36b67 150 /**@} end of group WDT_FLAGS */
<> 157:ff67d9f36b67 151
<> 157:ff67d9f36b67 152 /**
<> 157:ff67d9f36b67 153 * @ingroup wdt_registers
<> 157:ff67d9f36b67 154 * @defgroup WDT_ENABLE_Register WDT_ENABLE Register
<> 157:ff67d9f36b67 155 * @brief Field Positions and Bit Masks for the WDT_ENABLE register.
<> 157:ff67d9f36b67 156 * @{
<> 157:ff67d9f36b67 157 */
<> 157:ff67d9f36b67 158 #define MXC_F_WDT_ENABLE_TIMEOUT_POS 0 /**< ENABLE_TIMEOUT Field Position */
<> 157:ff67d9f36b67 159 #define MXC_F_WDT_ENABLE_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_TIMEOUT_POS)) /**< ENABLE_TIMEOUT Field Mask */
<> 157:ff67d9f36b67 160 #define MXC_F_WDT_ENABLE_PRE_WIN_POS 1 /**< ENABLE_PRE_WIN Field Position */
<> 157:ff67d9f36b67 161 #define MXC_F_WDT_ENABLE_PRE_WIN ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_PRE_WIN_POS)) /**< ENABLE_PRE_WIN Field Mask */
<> 157:ff67d9f36b67 162 #define MXC_F_WDT_ENABLE_RESET_OUT_POS 2 /**< ENABLE_RESET_OUT Field Position */
<> 157:ff67d9f36b67 163 #define MXC_F_WDT_ENABLE_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_RESET_OUT_POS)) /**< ENABLE_RESET_OUT Field Mask */
<> 157:ff67d9f36b67 164 /**@} end of group WDT_ENABLE */
<> 157:ff67d9f36b67 165
<> 157:ff67d9f36b67 166 /**
<> 157:ff67d9f36b67 167 * @ingroup wdt_registers
<> 157:ff67d9f36b67 168 * @defgroup WDT_LOCK_CTRL_Register WDT_LOCK_CTRL Register
<> 157:ff67d9f36b67 169 * @brief The WDT_LOCK_CTRL register controls read/write access to the \ref WDT_CTRL_Register.
<> 157:ff67d9f36b67 170 * @{
<> 157:ff67d9f36b67 171 */
<> 157:ff67d9f36b67 172 #define MXC_F_WDT_LOCK_CTRL_WDLOCK_POS 0 /**< WDLOCK Field's position in the WDT_LOCK_CTRL register. */
<> 157:ff67d9f36b67 173 #define MXC_F_WDT_LOCK_CTRL_WDLOCK ((uint32_t)(0x000000FFUL << MXC_F_WDT_LOCK_CTRL_WDLOCK_POS)) /**< WDLOCK Field mask for the WDT_LOCK_CTRL register. Reading a value of */
<> 157:ff67d9f36b67 174 /**@} end of group WDT_ENABLE */
<> 157:ff67d9f36b67 175
<> 157:ff67d9f36b67 176
<> 157:ff67d9f36b67 177
<> 157:ff67d9f36b67 178 /*
<> 157:ff67d9f36b67 179 Field values and shifted values for module WDT.
<> 157:ff67d9f36b67 180 */
<> 157:ff67d9f36b67 181 /**
<> 157:ff67d9f36b67 182 * @ingroup WDT_CTRL_Register
<> 157:ff67d9f36b67 183 * @defgroup WDT_CTRL_field_values WDT_CTRL Register Field and Shifted Field Values
<> 157:ff67d9f36b67 184 * @brief Field values and Shifted Field values for the WDT_CTRL register.
<> 157:ff67d9f36b67 185 * @details Shifted field values are field values shifted to the loacation of the field in the register.
<> 157:ff67d9f36b67 186 */
<> 157:ff67d9f36b67 187 /**
<> 157:ff67d9f36b67 188 * @ingroup WDT_CTRL_field_values
<> 157:ff67d9f36b67 189 * @defgroup WDT_CTRL_INT_PERIOD_Value Watchdog Timer Interrupt Period
<> 157:ff67d9f36b67 190 * @brief Sets the duration of the watchdog interrupt period.
<> 157:ff67d9f36b67 191 * @details The INT_PERIOD field sets the duration of the watchdog interrupt
<> 157:ff67d9f36b67 192 * period, which is the time period from the WDT being
<> 157:ff67d9f36b67 193 * enabled/cleared until the WDT flag, #MXC_F_WDT_FLAGS_TIMEOUT, is
<> 157:ff67d9f36b67 194 * set.
<> 157:ff67d9f36b67 195 * The values defined are in the number of watchdog clock cycles.
<> 157:ff67d9f36b67 196 * @{
<> 157:ff67d9f36b67 197 */
<> 157:ff67d9f36b67 198 #define MXC_V_WDT_CTRL_INT_PERIOD_2_31_CLKS ((uint32_t)(0x00000000UL)) /**< Interupt Period of \f$ 2^{31} \f$ WDT CLK Cycles */
<> 157:ff67d9f36b67 199 #define MXC_V_WDT_CTRL_INT_PERIOD_2_30_CLKS ((uint32_t)(0x00000001UL)) /**< Interupt Period of \f$ 2^{30} \f$ WDT CLK Cycles */
<> 157:ff67d9f36b67 200 #define MXC_V_WDT_CTRL_INT_PERIOD_2_29_CLKS ((uint32_t)(0x00000002UL)) /**< Interupt Period of \f$ 2^{29} \f$ WDT CLK Cycles */
<> 157:ff67d9f36b67 201 #define MXC_V_WDT_CTRL_INT_PERIOD_2_28_CLKS ((uint32_t)(0x00000003UL)) /**< Interupt Period of \f$ 2^{28} \f$ WDT CLK Cycles */
<> 157:ff67d9f36b67 202 #define MXC_V_WDT_CTRL_INT_PERIOD_2_27_CLKS ((uint32_t)(0x00000004UL)) /**< Interupt Period of \f$ 2^{27} \f$ WDT CLK Cycles */
<> 157:ff67d9f36b67 203 #define MXC_V_WDT_CTRL_INT_PERIOD_2_26_CLKS ((uint32_t)(0x00000005UL)) /**< Interupt Period of \f$ 2^{26} \f$ WDT CLK Cycles */
<> 157:ff67d9f36b67 204 #define MXC_V_WDT_CTRL_INT_PERIOD_2_25_CLKS ((uint32_t)(0x00000006UL)) /**< Interupt Period of \f$ 2^{25} \f$ WDT CLK Cycles */
<> 157:ff67d9f36b67 205 #define MXC_V_WDT_CTRL_INT_PERIOD_2_24_CLKS ((uint32_t)(0x00000007UL)) /**< Interupt Period of \f$ 2^{24} \f$ WDT CLK Cycles */
<> 157:ff67d9f36b67 206 #define MXC_V_WDT_CTRL_INT_PERIOD_2_23_CLKS ((uint32_t)(0x00000008UL)) /**< Interupt Period of \f$ 2^{23} \f$ WDT CLK Cycles */
<> 157:ff67d9f36b67 207 #define MXC_V_WDT_CTRL_INT_PERIOD_2_22_CLKS ((uint32_t)(0x00000009UL)) /**< Interupt Period of \f$ 2^{22} \f$ WDT CLK Cycles */
<> 157:ff67d9f36b67 208 #define MXC_V_WDT_CTRL_INT_PERIOD_2_21_CLKS ((uint32_t)(0x0000000AUL)) /**< Interupt Period of \f$ 2^{21} \f$ WDT CLK Cycles */
<> 157:ff67d9f36b67 209 #define MXC_V_WDT_CTRL_INT_PERIOD_2_20_CLKS ((uint32_t)(0x0000000BUL)) /**< Interupt Period of \f$ 2^{20} \f$ WDT CLK Cycles */
<> 157:ff67d9f36b67 210 #define MXC_V_WDT_CTRL_INT_PERIOD_2_19_CLKS ((uint32_t)(0x0000000CUL)) /**< Interupt Period of \f$ 2^{19} \f$ WDT CLK Cycles */
<> 157:ff67d9f36b67 211 #define MXC_V_WDT_CTRL_INT_PERIOD_2_18_CLKS ((uint32_t)(0x0000000DUL)) /**< Interupt Period of \f$ 2^{18} \f$ WDT CLK Cycles */
<> 157:ff67d9f36b67 212 #define MXC_V_WDT_CTRL_INT_PERIOD_2_17_CLKS ((uint32_t)(0x0000000EUL)) /**< Interupt Period of \f$ 2^{17} \f$ WDT CLK Cycles */
<> 157:ff67d9f36b67 213 #define MXC_V_WDT_CTRL_INT_PERIOD_2_16_CLKS ((uint32_t)(0x0000000FUL)) /**< Interupt Period of \f$ 2^{16} \f$ WDT CLK Cycles */
<> 157:ff67d9f36b67 214 /**@} end of group WDT_CTRL_INT_PERIOD_Value */
<> 157:ff67d9f36b67 215
<> 157:ff67d9f36b67 216 /**
<> 157:ff67d9f36b67 217 * @ingroup WDT_CTRL_field_values
<> 157:ff67d9f36b67 218 * @defgroup WDT_CTRL_INT_PERIOD_Shifted Watchdog Timer Interrupt Period Shifted Values
<> 157:ff67d9f36b67 219 * @brief Shifted values for the \ref WDT_CTRL_INT_PERIOD_Value
<> 157:ff67d9f36b67 220 * @details The shifted value is
<> 157:ff67d9f36b67 221 * shifted to align with the fields location in the WDT_CTRL register.
<> 157:ff67d9f36b67 222 * @{
<> 157:ff67d9f36b67 223 */
<> 157:ff67d9f36b67 224 #define MXC_S_WDT_CTRL_INT_PERIOD_2_31_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_31_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_31_CLKS */
<> 157:ff67d9f36b67 225 #define MXC_S_WDT_CTRL_INT_PERIOD_2_30_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_30_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_30_CLKS */
<> 157:ff67d9f36b67 226 #define MXC_S_WDT_CTRL_INT_PERIOD_2_29_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_29_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_29_CLKS */
<> 157:ff67d9f36b67 227 #define MXC_S_WDT_CTRL_INT_PERIOD_2_28_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_28_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_28_CLKS */
<> 157:ff67d9f36b67 228 #define MXC_S_WDT_CTRL_INT_PERIOD_2_27_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_27_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_27_CLKS */
<> 157:ff67d9f36b67 229 #define MXC_S_WDT_CTRL_INT_PERIOD_2_26_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_26_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_26_CLKS */
<> 157:ff67d9f36b67 230 #define MXC_S_WDT_CTRL_INT_PERIOD_2_25_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_25_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_25_CLKS */
<> 157:ff67d9f36b67 231 #define MXC_S_WDT_CTRL_INT_PERIOD_2_24_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_24_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_24_CLKS */
<> 157:ff67d9f36b67 232 #define MXC_S_WDT_CTRL_INT_PERIOD_2_23_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_23_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_23_CLKS */
<> 157:ff67d9f36b67 233 #define MXC_S_WDT_CTRL_INT_PERIOD_2_22_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_22_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_22_CLKS */
<> 157:ff67d9f36b67 234 #define MXC_S_WDT_CTRL_INT_PERIOD_2_21_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_21_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_21_CLKS */
<> 157:ff67d9f36b67 235 #define MXC_S_WDT_CTRL_INT_PERIOD_2_20_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_20_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_20_CLKS */
<> 157:ff67d9f36b67 236 #define MXC_S_WDT_CTRL_INT_PERIOD_2_19_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_19_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_19_CLKS */
<> 157:ff67d9f36b67 237 #define MXC_S_WDT_CTRL_INT_PERIOD_2_18_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_18_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_18_CLKS */
<> 157:ff67d9f36b67 238 #define MXC_S_WDT_CTRL_INT_PERIOD_2_17_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_17_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_17_CLKS */
<> 157:ff67d9f36b67 239 #define MXC_S_WDT_CTRL_INT_PERIOD_2_16_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_16_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_16_CLKS */
<> 157:ff67d9f36b67 240 /**@} end of group WDT_CTRL_INT_PERIOD_Shifted */
<> 157:ff67d9f36b67 241 /**
<> 157:ff67d9f36b67 242 * @ingroup WDT_CTRL_field_values
<> 157:ff67d9f36b67 243 * @defgroup WDT_CTRL_RST_PERIOD_Value Watchdog Timer Reset Period
<> 157:ff67d9f36b67 244 * @brief Sets the duration of the watchdog reset period.
<> 157:ff67d9f36b67 245 * @details The RST_PERIOD field sets the duration of the watchdog reset
<> 157:ff67d9f36b67 246 * period, which is the time period from the WDT being
<> 157:ff67d9f36b67 247 * enabled/cleared until the WDT flag, #MXC_F_WDT_CTRL_RST_PERIOD is
<> 157:ff67d9f36b67 248 * set.
<> 157:ff67d9f36b67 249 * The values defined are in the number of watchdog clock cycles.
<> 157:ff67d9f36b67 250 * @{
<> 157:ff67d9f36b67 251 */
<> 157:ff67d9f36b67 252 #define MXC_V_WDT_CTRL_RST_PERIOD_2_31_CLKS ((uint32_t)(0x00000000UL)) /**< Reset Period of \f$ 2^{31} \f$ WDT CLK CYCLES */
<> 157:ff67d9f36b67 253 #define MXC_V_WDT_CTRL_RST_PERIOD_2_30_CLKS ((uint32_t)(0x00000001UL)) /**< Reset Period of \f$ 2^{30} \f$ WDT CLK CYCLES */
<> 157:ff67d9f36b67 254 #define MXC_V_WDT_CTRL_RST_PERIOD_2_29_CLKS ((uint32_t)(0x00000002UL)) /**< Reset Period of \f$ 2^{29} \f$ WDT CLK CYCLES */
<> 157:ff67d9f36b67 255 #define MXC_V_WDT_CTRL_RST_PERIOD_2_28_CLKS ((uint32_t)(0x00000003UL)) /**< Reset Period of \f$ 2^{28} \f$ WDT CLK CYCLES */
<> 157:ff67d9f36b67 256 #define MXC_V_WDT_CTRL_RST_PERIOD_2_27_CLKS ((uint32_t)(0x00000004UL)) /**< Reset Period of \f$ 2^{27} \f$ WDT CLK CYCLES */
<> 157:ff67d9f36b67 257 #define MXC_V_WDT_CTRL_RST_PERIOD_2_26_CLKS ((uint32_t)(0x00000005UL)) /**< Reset Period of \f$ 2^{26} \f$ WDT CLK CYCLES */
<> 157:ff67d9f36b67 258 #define MXC_V_WDT_CTRL_RST_PERIOD_2_25_CLKS ((uint32_t)(0x00000006UL)) /**< Reset Period of \f$ 2^{25} \f$ WDT CLK CYCLES */
<> 157:ff67d9f36b67 259 #define MXC_V_WDT_CTRL_RST_PERIOD_2_24_CLKS ((uint32_t)(0x00000007UL)) /**< Reset Period of \f$ 2^{24} \f$ WDT CLK CYCLES */
<> 157:ff67d9f36b67 260 #define MXC_V_WDT_CTRL_RST_PERIOD_2_23_CLKS ((uint32_t)(0x00000008UL)) /**< Reset Period of \f$ 2^{23} \f$ WDT CLK CYCLES */
<> 157:ff67d9f36b67 261 #define MXC_V_WDT_CTRL_RST_PERIOD_2_22_CLKS ((uint32_t)(0x00000009UL)) /**< Reset Period of \f$ 2^{22} \f$ WDT CLK CYCLES */
<> 157:ff67d9f36b67 262 #define MXC_V_WDT_CTRL_RST_PERIOD_2_21_CLKS ((uint32_t)(0x0000000AUL)) /**< Reset Period of \f$ 2^{21} \f$ WDT CLK CYCLES */
<> 157:ff67d9f36b67 263 #define MXC_V_WDT_CTRL_RST_PERIOD_2_20_CLKS ((uint32_t)(0x0000000BUL)) /**< Reset Period of \f$ 2^{20} \f$ WDT CLK CYCLES */
<> 157:ff67d9f36b67 264 #define MXC_V_WDT_CTRL_RST_PERIOD_2_19_CLKS ((uint32_t)(0x0000000CUL)) /**< Reset Period of \f$ 2^{19} \f$ WDT CLK CYCLES */
<> 157:ff67d9f36b67 265 #define MXC_V_WDT_CTRL_RST_PERIOD_2_18_CLKS ((uint32_t)(0x0000000DUL)) /**< Reset Period of \f$ 2^{18} \f$ WDT CLK CYCLES */
<> 157:ff67d9f36b67 266 #define MXC_V_WDT_CTRL_RST_PERIOD_2_17_CLKS ((uint32_t)(0x0000000EUL)) /**< Reset Period of \f$ 2^{17} \f$ WDT CLK CYCLES */
<> 157:ff67d9f36b67 267 #define MXC_V_WDT_CTRL_RST_PERIOD_2_16_CLKS ((uint32_t)(0x0000000FUL)) /**< Reset Period of \f$ 2^{16} \f$ WDT CLK CYCLES */
<> 157:ff67d9f36b67 268 /**@} end of group WDT_CTRL_RST_PERIOD_Value */
<> 157:ff67d9f36b67 269
<> 157:ff67d9f36b67 270 /**
<> 157:ff67d9f36b67 271 * @ingroup WDT_CTRL_field_values
<> 157:ff67d9f36b67 272 * @defgroup WDT_CTRL_RST_PERIOD_Shifted Watchdog Timer Reset Period Shifted Values
<> 157:ff67d9f36b67 273 * @brief Shifted values for the \ref WDT_CTRL_RST_PERIOD_Value
<> 157:ff67d9f36b67 274 * @details These values are shifted to align with the field's location in the WDT_CTRL register.
<> 157:ff67d9f36b67 275 * @{
<> 157:ff67d9f36b67 276 */
<> 157:ff67d9f36b67 277 #define MXC_S_WDT_CTRL_RST_PERIOD_2_31_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_31_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_31_CLKS */
<> 157:ff67d9f36b67 278 #define MXC_S_WDT_CTRL_RST_PERIOD_2_30_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_30_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_30_CLKS */
<> 157:ff67d9f36b67 279 #define MXC_S_WDT_CTRL_RST_PERIOD_2_29_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_29_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_29_CLKS */
<> 157:ff67d9f36b67 280 #define MXC_S_WDT_CTRL_RST_PERIOD_2_28_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_28_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_28_CLKS */
<> 157:ff67d9f36b67 281 #define MXC_S_WDT_CTRL_RST_PERIOD_2_27_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_27_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_27_CLKS */
<> 157:ff67d9f36b67 282 #define MXC_S_WDT_CTRL_RST_PERIOD_2_26_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_26_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_26_CLKS */
<> 157:ff67d9f36b67 283 #define MXC_S_WDT_CTRL_RST_PERIOD_2_25_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_25_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_25_CLKS */
<> 157:ff67d9f36b67 284 #define MXC_S_WDT_CTRL_RST_PERIOD_2_24_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_24_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_24_CLKS */
<> 157:ff67d9f36b67 285 #define MXC_S_WDT_CTRL_RST_PERIOD_2_23_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_23_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_23_CLKS */
<> 157:ff67d9f36b67 286 #define MXC_S_WDT_CTRL_RST_PERIOD_2_22_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_22_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_22_CLKS */
<> 157:ff67d9f36b67 287 #define MXC_S_WDT_CTRL_RST_PERIOD_2_21_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_21_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_21_CLKS */
<> 157:ff67d9f36b67 288 #define MXC_S_WDT_CTRL_RST_PERIOD_2_20_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_20_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_20_CLKS */
<> 157:ff67d9f36b67 289 #define MXC_S_WDT_CTRL_RST_PERIOD_2_19_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_19_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_19_CLKS */
<> 157:ff67d9f36b67 290 #define MXC_S_WDT_CTRL_RST_PERIOD_2_18_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_18_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_18_CLKS */
<> 157:ff67d9f36b67 291 #define MXC_S_WDT_CTRL_RST_PERIOD_2_17_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_17_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_17_CLKS */
<> 157:ff67d9f36b67 292 #define MXC_S_WDT_CTRL_RST_PERIOD_2_16_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_16_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_16_CLKS */
<> 157:ff67d9f36b67 293 /**@} end of group WDT_CTRL_RST_PERIOD_Shifted */
<> 157:ff67d9f36b67 294 /**
<> 157:ff67d9f36b67 295 * @ingroup WDT_CTRL_field_values
<> 157:ff67d9f36b67 296 * @defgroup WDT_CTRL_WAIT_PERIOD_Value Watchdog Timer Wait Period
<> 157:ff67d9f36b67 297 * @brief Sets the duration of the watchdog wait window period.
<> 157:ff67d9f36b67 298 * @details The WAIT_PERIOD field sets the duration of the watchdog pre-window
<> 157:ff67d9f36b67 299 * period. If the watchdog is reset before the wait period has finished, an out-of-window interrupt will occur.
<> 157:ff67d9f36b67 300 * This sets the minimum amount of time between watchdog enable/clear to resetting the WDT count and assists in detecting
<> 157:ff67d9f36b67 301 * overclocking or an invalid clock.
<> 157:ff67d9f36b67 302 * The values defined are in the number of watchdog clock cycles.
<> 157:ff67d9f36b67 303 * @{
<> 157:ff67d9f36b67 304 */
<> 157:ff67d9f36b67 305 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_31_CLKS ((uint32_t)(0x00000000UL)) /**< Wait Period of \f$ 2^{31} \f$ WDT CLK CYCLES */
<> 157:ff67d9f36b67 306 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_30_CLKS ((uint32_t)(0x00000001UL)) /**< Wait Period of \f$ 2^{30} \f$ WDT CLK CYCLES */
<> 157:ff67d9f36b67 307 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_29_CLKS ((uint32_t)(0x00000002UL)) /**< Wait Period of \f$ 2^{29} \f$ WDT CLK CYCLES */
<> 157:ff67d9f36b67 308 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_28_CLKS ((uint32_t)(0x00000003UL)) /**< Wait Period of \f$ 2^{28} \f$ WDT CLK CYCLES */
<> 157:ff67d9f36b67 309 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_27_CLKS ((uint32_t)(0x00000004UL)) /**< Wait Period of \f$ 2^{27} \f$ WDT CLK CYCLES */
<> 157:ff67d9f36b67 310 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_26_CLKS ((uint32_t)(0x00000005UL)) /**< Wait Period of \f$ 2^{26} \f$ WDT CLK CYCLES */
<> 157:ff67d9f36b67 311 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_25_CLKS ((uint32_t)(0x00000006UL)) /**< Wait Period of \f$ 2^{25} \f$ WDT CLK CYCLES */
<> 157:ff67d9f36b67 312 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_24_CLKS ((uint32_t)(0x00000007UL)) /**< Wait Period of \f$ 2^{24} \f$ WDT CLK CYCLES */
<> 157:ff67d9f36b67 313 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_23_CLKS ((uint32_t)(0x00000008UL)) /**< Wait Period of \f$ 2^{23} \f$ WDT CLK CYCLES */
<> 157:ff67d9f36b67 314 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_22_CLKS ((uint32_t)(0x00000009UL)) /**< Wait Period of \f$ 2^{22} \f$ WDT CLK CYCLES */
<> 157:ff67d9f36b67 315 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_21_CLKS ((uint32_t)(0x0000000AUL)) /**< Wait Period of \f$ 2^{21} \f$ WDT CLK CYCLES */
<> 157:ff67d9f36b67 316 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_20_CLKS ((uint32_t)(0x0000000BUL)) /**< Wait Period of \f$ 2^{20} \f$ WDT CLK CYCLES */
<> 157:ff67d9f36b67 317 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_19_CLKS ((uint32_t)(0x0000000CUL)) /**< Wait Period of \f$ 2^{19} \f$ WDT CLK CYCLES */
<> 157:ff67d9f36b67 318 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_18_CLKS ((uint32_t)(0x0000000DUL)) /**< Wait Period of \f$ 2^{18} \f$ WDT CLK CYCLES */
<> 157:ff67d9f36b67 319 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_17_CLKS ((uint32_t)(0x0000000EUL)) /**< Wait Period of \f$ 2^{17} \f$ WDT CLK CYCLES */
<> 157:ff67d9f36b67 320 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_16_CLKS ((uint32_t)(0x0000000FUL)) /**< Wait Period of \f$ 2^{16} \f$ WDT CLK CYCLES */
<> 157:ff67d9f36b67 321 /**@} end of group WDT_CTRL_WAIT_PERIOD_Value */
<> 157:ff67d9f36b67 322
<> 157:ff67d9f36b67 323 /**
<> 157:ff67d9f36b67 324 * @ingroup WDT_CTRL_field_values
<> 157:ff67d9f36b67 325 * @defgroup WDT_CTRL_WAIT_PERIOD_Shifted Watchdog Timer Wait Period Shifted Values
<> 157:ff67d9f36b67 326 * @brief Shifted values for the \ref WDT_CTRL_WAIT_PERIOD_Value
<> 157:ff67d9f36b67 327 * @details These values are shifted to align with the WAIT_PERIOD field's location in the WDT_CTRL register.
<> 157:ff67d9f36b67 328 * @{
<> 157:ff67d9f36b67 329 */
<> 157:ff67d9f36b67 330 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_31_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_31_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_31_CLKS */
<> 157:ff67d9f36b67 331 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_30_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_30_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_30_CLKS */
<> 157:ff67d9f36b67 332 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_29_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_29_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_29_CLKS */
<> 157:ff67d9f36b67 333 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_28_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_28_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_28_CLKS */
<> 157:ff67d9f36b67 334 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_27_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_27_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_27_CLKS */
<> 157:ff67d9f36b67 335 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_26_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_26_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_26_CLKS */
<> 157:ff67d9f36b67 336 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_25_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_25_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_25_CLKS */
<> 157:ff67d9f36b67 337 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_24_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_24_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_24_CLKS */
<> 157:ff67d9f36b67 338 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_23_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_23_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_23_CLKS */
<> 157:ff67d9f36b67 339 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_22_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_22_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_22_CLKS */
<> 157:ff67d9f36b67 340 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_21_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_21_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_21_CLKS */
<> 157:ff67d9f36b67 341 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_20_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_20_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_20_CLKS */
<> 157:ff67d9f36b67 342 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_19_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_19_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_19_CLKS */
<> 157:ff67d9f36b67 343 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_18_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_18_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_18_CLKS */
<> 157:ff67d9f36b67 344 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_17_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_17_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_17_CLKS */
<> 157:ff67d9f36b67 345 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_16_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_16_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_16_CLKS */
<> 157:ff67d9f36b67 346 /**@} end of group WDT_CTRL_WAIT_PERIOD_Shifted */
<> 157:ff67d9f36b67 347
<> 157:ff67d9f36b67 348 /**
<> 157:ff67d9f36b67 349 * @ingroup WDT_LOCK_CTRL_Register
<> 157:ff67d9f36b67 350 * @defgroup WDT_LOCK_field_values Watchdog Timer WDT_LOCK field values
<> 157:ff67d9f36b67 351 * @brief Lock/Unlock values for the watchdog timer \ref WDT_CTRL_Register.
<> 157:ff67d9f36b67 352 * @{
<> 157:ff67d9f36b67 353 */
<> 157:ff67d9f36b67 354 #define MXC_V_WDT_LOCK_KEY 0x24 /**< Writing this value to the WDT_LOCK field of the \ref WDT_LOCK_CTRL_Register \b locks the \ref WDT_CTRL_Register making it read only. */
<> 157:ff67d9f36b67 355 #define MXC_V_WDT_UNLOCK_KEY 0x42 /**< Writing this value to the WDT_LOCK field of the \ref WDT_LOCK_CTRL_Register \b unlocks the \ref WDT_CTRL_Register making it read/write. */
<> 157:ff67d9f36b67 356 /**@} end of group WDT_LOCK_field_values */
<> 157:ff67d9f36b67 357 ///@cond
<> 157:ff67d9f36b67 358 /*
<> 157:ff67d9f36b67 359 * @internal
<> 157:ff67d9f36b67 360 * @ingroup WDT_CLEAR_Register
<> 157:ff67d9f36b67 361 * @defgroup WDT_CLEAR_field_values Watchdog Timer Clear Sequence Values
<> 157:ff67d9f36b67 362 * @brief Writing the sequence of #MXC_V_WDT_RESET_KEY_0, #MXC_V_WDT_RESET_KEY_1 to the \ref WDT_CLEAR_Register will clear/reset the watchdog timer count.
<> 157:ff67d9f36b67 363 * @note The values #MXC_V_WDT_RESET_KEY_0, #MXC_V_WDT_RESET_KEY_1 must be written sequentially to the \ref WDT_CLEAR_Register to clear the watchdog counter.
<> 157:ff67d9f36b67 364 * @{
<> 157:ff67d9f36b67 365 */
<> 157:ff67d9f36b67 366 #define MXC_V_WDT_RESET_KEY_0 0xA5 /**< First value to write to the \ref WDT_CLEAR_Register to perform a WDT clear. */
<> 157:ff67d9f36b67 367 #define MXC_V_WDT_RESET_KEY_1 0x5A /**< Second value to write to the \ref WDT_CLEAR_Register to perform a WDT clear. */
<> 157:ff67d9f36b67 368 /**
<> 157:ff67d9f36b67 369 * @} end of group WDT_CLEAR_field_values
<> 157:ff67d9f36b67 370 * @endinternal
<> 157:ff67d9f36b67 371 */
<> 157:ff67d9f36b67 372 ///@endcond
<> 157:ff67d9f36b67 373 /**@} wdt_registers*/
<> 157:ff67d9f36b67 374
<> 157:ff67d9f36b67 375 #ifdef __cplusplus
<> 157:ff67d9f36b67 376 }
<> 157:ff67d9f36b67 377 #endif
<> 157:ff67d9f36b67 378
<> 157:ff67d9f36b67 379 #endif /* _MXC_WDT_REGS_H_ */
<> 157:ff67d9f36b67 380