Amit Gandhi / mbed-dev

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Fork of mbed-dev by mbed official

targets/TARGET_Maxim/TARGET_MAX32630/device/rtc_regs.h@178:d650f5d4c87a, 2017-11-08 (annotated)

Committer:
AnnaBridge
Date:
Wed Nov 08 13:50:44 2017 +0000
Revision:
178:d650f5d4c87a
Parent:
157:ff67d9f36b67 
This updates the lib to the mbed lib v 155

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 157:ff67d9f36b67 1 /**
<> 157:ff67d9f36b67 2 * @file
<> 157:ff67d9f36b67 3 * @brief Registers, Bit Masks and Bit Positions for the Real-Time Clock.
<> 157:ff67d9f36b67 4 *
<> 157:ff67d9f36b67 5 */
<> 157:ff67d9f36b67 6 /* ****************************************************************************
<> 157:ff67d9f36b67 7 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 157:ff67d9f36b67 8 *
<> 157:ff67d9f36b67 9 * Permission is hereby granted, free of charge, to any person obtaining a
<> 157:ff67d9f36b67 10 * copy of this software and associated documentation files (the "Software"),
<> 157:ff67d9f36b67 11 * to deal in the Software without restriction, including without limitation
<> 157:ff67d9f36b67 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 157:ff67d9f36b67 13 * and/or sell copies of the Software, and to permit persons to whom the
<> 157:ff67d9f36b67 14 * Software is furnished to do so, subject to the following conditions:
<> 157:ff67d9f36b67 15 *
<> 157:ff67d9f36b67 16 * The above copyright notice and this permission notice shall be included
<> 157:ff67d9f36b67 17 * in all copies or substantial portions of the Software.
<> 157:ff67d9f36b67 18 *
<> 157:ff67d9f36b67 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 157:ff67d9f36b67 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 157:ff67d9f36b67 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 157:ff67d9f36b67 22 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 157:ff67d9f36b67 23 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 157:ff67d9f36b67 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 157:ff67d9f36b67 25 * OTHER DEALINGS IN THE SOFTWARE.
<> 157:ff67d9f36b67 26 *
<> 157:ff67d9f36b67 27 * Except as contained in this notice, the name of Maxim Integrated
<> 157:ff67d9f36b67 28 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 157:ff67d9f36b67 29 * Products, Inc. Branding Policy.
<> 157:ff67d9f36b67 30 *
<> 157:ff67d9f36b67 31 * The mere transfer of this software does not imply any licenses
<> 157:ff67d9f36b67 32 * of trade secrets, proprietary technology, copyrights, patents,
<> 157:ff67d9f36b67 33 * trademarks, maskwork rights, or any other form of intellectual
<> 157:ff67d9f36b67 34 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 157:ff67d9f36b67 35 * ownership rights.
<> 157:ff67d9f36b67 36 *
<> 157:ff67d9f36b67 37 * $Date: 2016-10-10 19:28:26 -0500 (Mon, 10 Oct 2016) $
<> 157:ff67d9f36b67 38 * $Revision: 24670 $
<> 157:ff67d9f36b67 39 *
<> 157:ff67d9f36b67 40 **************************************************************************** */
<> 157:ff67d9f36b67 41
<> 157:ff67d9f36b67 42 /* Define to prevent redundant inclusion */
<> 157:ff67d9f36b67 43 #ifndef _MXC_RTC_REGS_H_
<> 157:ff67d9f36b67 44 #define _MXC_RTC_REGS_H_
<> 157:ff67d9f36b67 45
<> 157:ff67d9f36b67 46 /* **** Includes **** */
<> 157:ff67d9f36b67 47 #include <stdint.h>
<> 157:ff67d9f36b67 48
<> 157:ff67d9f36b67 49 #ifdef __cplusplus
<> 157:ff67d9f36b67 50 extern "C" {
<> 157:ff67d9f36b67 51 #endif
<> 157:ff67d9f36b67 52
<> 157:ff67d9f36b67 53 /*
<> 157:ff67d9f36b67 54 If types are not defined elsewhere (CMSIS) define them here
<> 157:ff67d9f36b67 55 */
<> 157:ff67d9f36b67 56 /// @cond
<> 157:ff67d9f36b67 57 #ifndef __IO
<> 157:ff67d9f36b67 58 #define __IO volatile
<> 157:ff67d9f36b67 59 #endif
<> 157:ff67d9f36b67 60 #ifndef __I
<> 157:ff67d9f36b67 61 #define __I volatile const
<> 157:ff67d9f36b67 62 #endif
<> 157:ff67d9f36b67 63 #ifndef __O
<> 157:ff67d9f36b67 64 #define __O volatile
<> 157:ff67d9f36b67 65 #endif
<> 157:ff67d9f36b67 66 #ifndef __RO
<> 157:ff67d9f36b67 67 #define __RO volatile const
<> 157:ff67d9f36b67 68 #endif
<> 157:ff67d9f36b67 69 /// @endcond
<> 157:ff67d9f36b67 70
<> 157:ff67d9f36b67 71 /**
<> 157:ff67d9f36b67 72 * @ingroup rtc
<> 157:ff67d9f36b67 73 * @defgroup rtc_registers RTC Registers
<> 157:ff67d9f36b67 74 * @brief Registers, Bit Masks and Bit Positions
<> 157:ff67d9f36b67 75 * @{
<> 157:ff67d9f36b67 76 */
<> 157:ff67d9f36b67 77
<> 157:ff67d9f36b67 78 /**
<> 157:ff67d9f36b67 79 * Structure type for the Real-Time Clock module registers allowing direct 32-bit access to each register.
<> 157:ff67d9f36b67 80 */
<> 157:ff67d9f36b67 81 typedef struct {
<> 157:ff67d9f36b67 82 __IO uint32_t ctrl; /**< <tt>\b 0x0000: </tt> RTC_CTRL Register - RTC Timer Control */
<> 157:ff67d9f36b67 83 __IO uint32_t timer; /**< <tt>\b 0x0004: </tt> RTC_TIMER Register - RTC Timer Count Value */
<> 157:ff67d9f36b67 84 __IO uint32_t comp[2]; /**< <tt>\b 0x0008-0x000C: </tt> RTC_COMP0/RTC_COMP1 Registers - RTC Time of Day Alarm [0..1] Compare Register */
<> 157:ff67d9f36b67 85 __IO uint32_t flags; /**< <tt>\b 0x0010: </tt> RTC_FLAGS Register - CPU Interrupt and RTC Domain Flags */
<> 157:ff67d9f36b67 86 __IO uint32_t snz_val; /**< <tt>\b 0x0014: </tt> RTC_SNZ_VAL Register - RTC Timer Alarm Snooze Value */
<> 157:ff67d9f36b67 87 __IO uint32_t inten; /**< <tt>\b 0x0018: </tt> RTC_INTEN Register - Interrupt Enable Controls */
<> 157:ff67d9f36b67 88 __IO uint32_t prescale; /**< <tt>\b 0x001C: </tt> RTC_PRESCALE Register - RTC Timer Prescale Setting */
<> 157:ff67d9f36b67 89 __RO uint32_t rsv020; /**< <tt>\b 0x0020: </tt> RESERVED */
<> 157:ff67d9f36b67 90 __IO uint32_t prescale_mask; /**< <tt>\b 0x0024: </tt> RTC_PRESCALE_MASK Register - RTC Timer Prescale Compare Mask */
<> 157:ff67d9f36b67 91 __IO uint32_t trim_ctrl; /**< <tt>\b 0x0028: </tt> RTC_TRIM_CTRL Register - RTC Timer Trim Controls */
<> 157:ff67d9f36b67 92 __IO uint32_t trim_value; /**< <tt>\b 0x002C: </tt> RTC_TRIM_VALUE Register - RTC Timer Trim Adjustment Interval */
<> 157:ff67d9f36b67 93 } mxc_rtctmr_regs_t;
<> 157:ff67d9f36b67 94
<> 157:ff67d9f36b67 95
<> 157:ff67d9f36b67 96 /**
<> 157:ff67d9f36b67 97 * Structure type for access to the RTC CFG hardware.
<> 157:ff67d9f36b67 98 */
<> 157:ff67d9f36b67 99 typedef struct {
<> 157:ff67d9f36b67 100 __IO uint32_t nano_cntr; /**< <tt>\b 0x0000: </tt> - RTCCFG_NANO_CNTR - Nano Oscillator Counter Read Register */
<> 157:ff67d9f36b67 101 __IO uint32_t clk_ctrl; /**< <tt>\b 0x0004: </tt> - RTCCFG_CLK_CTRL - RTC Clock Control Settings */
<> 157:ff67d9f36b67 102 __RO uint32_t rsv008; /**< <tt>\b 0x0008: </tt> - RESERVED */
<> 157:ff67d9f36b67 103 __IO uint32_t osc_ctrl; /**< <tt>\b 0x000C: </tt> - RTCCFG_OSC_CTRL - RTC Oscillator Control */
<> 157:ff67d9f36b67 104 } mxc_rtccfg_regs_t;
<> 157:ff67d9f36b67 105 /**@} end of group rtc_registers.*/
<> 157:ff67d9f36b67 106
<> 157:ff67d9f36b67 107 /*
<> 157:ff67d9f36b67 108 Register offsets for module RTC.
<> 157:ff67d9f36b67 109 */
<> 157:ff67d9f36b67 110 /**
<> 157:ff67d9f36b67 111 * @ingroup rtc_registers
<> 157:ff67d9f36b67 112 * @defgroup RTC_Register_Offsets Register Offsets
<> 157:ff67d9f36b67 113 * @brief Real-Time Clock Register Offsets from the RTC Base Peripheral Address.
<> 157:ff67d9f36b67 114 * @{
<> 157:ff67d9f36b67 115 */
<> 157:ff67d9f36b67 116 #define MXC_R_RTCTMR_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0000</tt> */
<> 157:ff67d9f36b67 117 #define MXC_R_RTCTMR_OFFS_TIMER ((uint32_t)0x00000004UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0004</tt> */
<> 157:ff67d9f36b67 118 #define MXC_R_RTCTMR_OFFS_COMP0 ((uint32_t)0x00000008UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0008</tt> */
<> 157:ff67d9f36b67 119 #define MXC_R_RTCTMR_OFFS_COMP1 ((uint32_t)0x0000000CUL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x000C</tt> */
<> 157:ff67d9f36b67 120 #define MXC_R_RTCTMR_OFFS_FLAGS ((uint32_t)0x00000010UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0010</tt> */
<> 157:ff67d9f36b67 121 #define MXC_R_RTCTMR_OFFS_SNZ_VAL ((uint32_t)0x00000014UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0014</tt> */
<> 157:ff67d9f36b67 122 #define MXC_R_RTCTMR_OFFS_INTEN ((uint32_t)0x00000018UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0018</tt> */
<> 157:ff67d9f36b67 123 #define MXC_R_RTCTMR_OFFS_PRESCALE ((uint32_t)0x0000001CUL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x001C</tt> */
<> 157:ff67d9f36b67 124 #define MXC_R_RTCTMR_OFFS_PRESCALE_MASK ((uint32_t)0x00000024UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0024</tt> */
<> 157:ff67d9f36b67 125 #define MXC_R_RTCTMR_OFFS_TRIM_CTRL ((uint32_t)0x00000028UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0028</tt> */
<> 157:ff67d9f36b67 126 #define MXC_R_RTCTMR_OFFS_TRIM_VALUE ((uint32_t)0x0000002CUL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x002C</tt> */
<> 157:ff67d9f36b67 127 /**@} end of group RTC_Register_Offsets */
<> 157:ff67d9f36b67 128 /**
<> 157:ff67d9f36b67 129 * @ingroup rtc_registers
<> 157:ff67d9f36b67 130 * @defgroup RTCCFG_Register_Offsets RTCCFG Register Offsets
<> 157:ff67d9f36b67 131 * @brief Real-Time Clock CFG Register Offsets from the RTCCFG Base Peripheral Address.
<> 157:ff67d9f36b67 132 * @{
<> 157:ff67d9f36b67 133 */
<> 157:ff67d9f36b67 134 #define MXC_R_RTCCFG_OFFS_NANO_CNTR ((uint32_t)0x00000000UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0000</tt> */
<> 157:ff67d9f36b67 135 #define MXC_R_RTCCFG_OFFS_CLK_CTRL ((uint32_t)0x00000004UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0004</tt> */
<> 157:ff67d9f36b67 136 #define MXC_R_RTCCFG_OFFS_OSC_CTRL ((uint32_t)0x0000000CUL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x000C</tt> */
<> 157:ff67d9f36b67 137 /**@} end of group RTCCFG_Register_Offsets */
<> 157:ff67d9f36b67 138
<> 157:ff67d9f36b67 139 /*
<> 157:ff67d9f36b67 140 Field positions and masks for module RTC.
<> 157:ff67d9f36b67 141 */
<> 157:ff67d9f36b67 142 /**
<> 157:ff67d9f36b67 143 * @ingroup rtc_registers
<> 157:ff67d9f36b67 144 * @defgroup RTC_CTRL_Register RTC_CTRL
<> 157:ff67d9f36b67 145 * @{
<> 157:ff67d9f36b67 146 */
<> 157:ff67d9f36b67 147 #define MXC_F_RTC_CTRL_ENABLE_POS 0 /**< ENABLE Position */
<> 157:ff67d9f36b67 148 #define MXC_F_RTC_CTRL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ENABLE_POS)) /**< ENABLE Mask */
<> 157:ff67d9f36b67 149 #define MXC_F_RTC_CTRL_CLEAR_POS 1 /**< CLEAR Position */
<> 157:ff67d9f36b67 150 #define MXC_F_RTC_CTRL_CLEAR ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CLEAR_POS)) /**< CLEAR Mask */
<> 157:ff67d9f36b67 151 #define MXC_F_RTC_CTRL_PENDING_POS 2 /**< PENDING Position */
<> 157:ff67d9f36b67 152 #define MXC_F_RTC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PENDING_POS)) /**< PENDING Mask */
<> 157:ff67d9f36b67 153 #define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS 3 /**< USE_ASYNC_FLAGS Position */
<> 157:ff67d9f36b67 154 #define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS)) /**< USE_ASYNC_FLAGS Mask */
<> 157:ff67d9f36b67 155 #define MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS 4 /**< AGGRESSIVE_RST Position */
<> 157:ff67d9f36b67 156 #define MXC_F_RTC_CTRL_AGGRESSIVE_RST ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS)) /**< AGGRESSIVE_RST Mask */
<> 157:ff67d9f36b67 157 #define MXC_F_RTC_CTRL_AUTO_UPDATE_DISABLE_POS 5 /**< AUTO_UPDATE_DISABLE Position */
<> 157:ff67d9f36b67 158 #define MXC_F_RTC_CTRL_AUTO_UPDATE_DISABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_AUTO_UPDATE_DISABLE_POS)) /**< AUTO_UPDATE_DISABLE Mask */
<> 157:ff67d9f36b67 159 #define MXC_F_RTC_CTRL_SNOOZE_ENABLE_POS 6 /**< SNOOZE_ENABLE Position */
<> 157:ff67d9f36b67 160 #define MXC_F_RTC_CTRL_SNOOZE_ENABLE ((uint32_t)(0x00000003UL << MXC_F_RTC_CTRL_SNOOZE_ENABLE_POS)) /**< SNOOZE_ENABLE Mask */
<> 157:ff67d9f36b67 161 #define MXC_F_RTC_CTRL_RTC_ENABLE_ACTIVE_POS 16 /**< RTC_ENABLE_ACTIVE Position */
<> 157:ff67d9f36b67 162 #define MXC_F_RTC_CTRL_RTC_ENABLE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_RTC_ENABLE_ACTIVE_POS)) /**< RTC_ENABLE_ACTIVE Mask */
<> 157:ff67d9f36b67 163 #define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS 17 /**< OSC_GOTO_LOW_ACTIVE Position */
<> 157:ff67d9f36b67 164 #define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS)) /**< OSC_GOTO_LOW_ACTIVE Mask */
<> 157:ff67d9f36b67 165 #define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS 18 /**< OSC_FRCE_SM_EN_ACTIVE Position */
<> 157:ff67d9f36b67 166 #define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS)) /**< OSC_FRCE_SM_EN_ACTIVE Mask */
<> 157:ff67d9f36b67 167 #define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS 19 /**< OSC_FRCE_ST_ACTIVE Position */
<> 157:ff67d9f36b67 168 #define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS)) /**< OSC_FRCE_ST_ACTIVE Mask */
<> 157:ff67d9f36b67 169 #define MXC_F_RTC_CTRL_RTC_SET_ACTIVE_POS 20 /**< RTC_SET_ACTIVE Position */
<> 157:ff67d9f36b67 170 #define MXC_F_RTC_CTRL_RTC_SET_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_RTC_SET_ACTIVE_POS)) /**< RTC_SET_ACTIVE Mask */
<> 157:ff67d9f36b67 171 #define MXC_F_RTC_CTRL_RTC_CLR_ACTIVE_POS 21 /**< RTC_CLR_ACTIVE Position */
<> 157:ff67d9f36b67 172 #define MXC_F_RTC_CTRL_RTC_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_RTC_CLR_ACTIVE_POS)) /**< RTC_CLR_ACTIVE Mask */
<> 157:ff67d9f36b67 173 #define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS 22 /**< ROLLOVER_CLR_ACTIVE Position */
<> 157:ff67d9f36b67 174 #define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS)) /**< ROLLOVER_CLR_ACTIVE Mask */
<> 157:ff67d9f36b67 175 #define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS 23 /**< PRESCALE_CMPR0_ACTIVE Position */
<> 157:ff67d9f36b67 176 #define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS)) /**< PRESCALE_CMPR0_ACTIVE Mask */
<> 157:ff67d9f36b67 177 #define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS 24 /**< PRESCALE_UPDATE_ACTIVE Position */
<> 157:ff67d9f36b67 178 #define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS)) /**< PRESCALE_UPDATE_ACTIVE Mask */
<> 157:ff67d9f36b67 179 #define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS 25 /**< CMPR1_CLR_ACTIVE Position */
<> 157:ff67d9f36b67 180 #define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS)) /**< CMPR1_CLR_ACTIVE Mask */
<> 157:ff67d9f36b67 181 #define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS 26 /**< CMPR0_CLR_ACTIVE Position */
<> 157:ff67d9f36b67 182 #define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS)) /**< CMPR0_CLR_ACTIVE Mask */
<> 157:ff67d9f36b67 183 #define MXC_F_RTC_CTRL_TRIM_ENABLE_ACTIVE_POS 27 /**< TRIM_ENABLE_ACTIVE Position */
<> 157:ff67d9f36b67 184 #define MXC_F_RTC_CTRL_TRIM_ENABLE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_TRIM_ENABLE_ACTIVE_POS)) /**< TRIM_ENABLE_ACTIVE Mask */
<> 157:ff67d9f36b67 185 #define MXC_F_RTC_CTRL_TRIM_SLOWER_ACTIVE_POS 28 /**< TRIM_SLOWER_ACTIVE Position */
<> 157:ff67d9f36b67 186 #define MXC_F_RTC_CTRL_TRIM_SLOWER_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_TRIM_SLOWER_ACTIVE_POS)) /**< TRIM_SLOWER_ACTIVE Mask */
<> 157:ff67d9f36b67 187 #define MXC_F_RTC_CTRL_TRIM_CLR_ACTIVE_POS 29 /**< TRIM_CLR_ACTIVE Position */
<> 157:ff67d9f36b67 188 #define MXC_F_RTC_CTRL_TRIM_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_TRIM_CLR_ACTIVE_POS)) /**< TRIM_CLR_ACTIVE Mask */
<> 157:ff67d9f36b67 189 #define MXC_F_RTC_CTRL_ACTIVE_TRANS_0_POS 30 /**< ACTIVE_TRANS_0 Position */
<> 157:ff67d9f36b67 190 #define MXC_F_RTC_CTRL_ACTIVE_TRANS_0 ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ACTIVE_TRANS_0_POS)) /**< ACTIVE_TRANS_0 Mask */
<> 157:ff67d9f36b67 191 /**@} end of group RTC_CTRL*/
<> 157:ff67d9f36b67 192 /**
<> 157:ff67d9f36b67 193 * @ingroup rtc_registers
<> 157:ff67d9f36b67 194 * @defgroup RTC_FLAGS_Register RTC_FLAGS
<> 157:ff67d9f36b67 195 * @{
<> 157:ff67d9f36b67 196 */
<> 157:ff67d9f36b67 197 #define MXC_F_RTC_FLAGS_COMP0_POS 0 /**< COMP0 Position */
<> 157:ff67d9f36b67 198 #define MXC_F_RTC_FLAGS_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_POS)) /**< COMP0 Mask */
<> 157:ff67d9f36b67 199 #define MXC_F_RTC_FLAGS_COMP1_POS 1 /**< COMP1 Position */
<> 157:ff67d9f36b67 200 #define MXC_F_RTC_FLAGS_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_POS)) /**< COMP1 Mask */
<> 157:ff67d9f36b67 201 #define MXC_F_RTC_FLAGS_PRESCALE_COMP_POS 2 /**< PRESCALE_COMP Position */
<> 157:ff67d9f36b67 202 #define MXC_F_RTC_FLAGS_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCALE_COMP_POS)) /**< PRESCALE_COMP Mask */
<> 157:ff67d9f36b67 203 #define MXC_F_RTC_FLAGS_OVERFLOW_POS 3 /**< OVERFLOW Position */
<> 157:ff67d9f36b67 204 #define MXC_F_RTC_FLAGS_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_POS)) /**< OVERFLOW Mask */
<> 157:ff67d9f36b67 205 #define MXC_F_RTC_FLAGS_TRIM_POS 4 /**< TRIM Position */
<> 157:ff67d9f36b67 206 #define MXC_F_RTC_FLAGS_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_POS)) /**< TRIM Mask */
<> 157:ff67d9f36b67 207 #define MXC_F_RTC_FLAGS_SNOOZE_POS 5 /**< SNOOZE Position */
<> 157:ff67d9f36b67 208 #define MXC_F_RTC_FLAGS_SNOOZE ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_SNOOZE_POS)) /**< SNOOZE Mask */
<> 157:ff67d9f36b67 209 #define MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS 8 /**< COMP0_FLAG_A Position */
<> 157:ff67d9f36b67 210 #define MXC_F_RTC_FLAGS_COMP0_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS)) /**< COMP0_FLAG_A Mask */
<> 157:ff67d9f36b67 211 #define MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS 9 /**< COMP1_FLAG_A Position */
<> 157:ff67d9f36b67 212 #define MXC_F_RTC_FLAGS_COMP1_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS)) /**< COMP1_FLAG_A Mask */
<> 157:ff67d9f36b67 213 #define MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS 10 /**< PRESCL_FLAG_A Position */
<> 157:ff67d9f36b67 214 #define MXC_F_RTC_FLAGS_PRESCL_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS)) /**< PRESCL_FLAG_A Mask */
<> 157:ff67d9f36b67 215 #define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS 11 /**< OVERFLOW_FLAG_A Position */
<> 157:ff67d9f36b67 216 #define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS)) /**< OVERFLOW_FLAG_A Mask */
<> 157:ff67d9f36b67 217 #define MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS 12 /**< TRIM_FLAG_A Position */
<> 157:ff67d9f36b67 218 #define MXC_F_RTC_FLAGS_TRIM_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS)) /**< TRIM_FLAG_A Mask */
<> 157:ff67d9f36b67 219 #define MXC_F_RTC_FLAGS_SNOOZE_A_POS 28 /**< SNOOZE_A Position */
<> 157:ff67d9f36b67 220 #define MXC_F_RTC_FLAGS_SNOOZE_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_SNOOZE_A_POS)) /**< SNOOZE_A Mask */
<> 157:ff67d9f36b67 221 #define MXC_F_RTC_FLAGS_SNOOZE_B_POS 29 /**< SNOOZE_B Position */
<> 157:ff67d9f36b67 222 #define MXC_F_RTC_FLAGS_SNOOZE_B ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_SNOOZE_B_POS)) /**< SNOOZE_B Mask */
<> 157:ff67d9f36b67 223 #define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS 31 /**< ASYNC_CLR_FLAGS Position */
<> 157:ff67d9f36b67 224 #define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS)) /**< ASYNC_CLR_FLAGS Mask */
<> 157:ff67d9f36b67 225 /**@} end of group RTC_FLAGS_Register */
<> 157:ff67d9f36b67 226 /**
<> 157:ff67d9f36b67 227 * @ingroup rtc_registers
<> 157:ff67d9f36b67 228 * @defgroup RTC_SNZ_VAL_Register RTC_SNZ_VAL.
<> 157:ff67d9f36b67 229 * @{
<> 157:ff67d9f36b67 230 */
<> 157:ff67d9f36b67 231 #define MXC_F_RTC_SNZ_VAL_VALUE_POS 0 /**< VALUE Position */
<> 157:ff67d9f36b67 232 #define MXC_F_RTC_SNZ_VAL_VALUE ((uint32_t)(0x000003FFUL << MXC_F_RTC_SNZ_VAL_VALUE_POS)) /**< VALUE Mask */
<> 157:ff67d9f36b67 233 /**@} end of group RTC_SNZ_VAL_Register */
<> 157:ff67d9f36b67 234 /**
<> 157:ff67d9f36b67 235 * @ingroup rtc_registers
<> 157:ff67d9f36b67 236 * @defgroup RTC_INTEN_Register RTC_INTEN.
<> 157:ff67d9f36b67 237 * @{
<> 157:ff67d9f36b67 238 */
<> 157:ff67d9f36b67 239 #define MXC_F_RTC_INTEN_COMP0_POS 0 /**< COMP0 Position */
<> 157:ff67d9f36b67 240 #define MXC_F_RTC_INTEN_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP0_POS)) /**< COMP0 Mask */
<> 157:ff67d9f36b67 241 #define MXC_F_RTC_INTEN_COMP1_POS 1 /**< COMP1 Position */
<> 157:ff67d9f36b67 242 #define MXC_F_RTC_INTEN_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP1_POS)) /**< COMP1 Mask */
<> 157:ff67d9f36b67 243 #define MXC_F_RTC_INTEN_PRESCALE_COMP_POS 2 /**< PRESCALE_COMP Position */
<> 157:ff67d9f36b67 244 #define MXC_F_RTC_INTEN_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_PRESCALE_COMP_POS)) /**< PRESCALE_COMP Mask */
<> 157:ff67d9f36b67 245 #define MXC_F_RTC_INTEN_OVERFLOW_POS 3 /**< OVERFLOW Position */
<> 157:ff67d9f36b67 246 #define MXC_F_RTC_INTEN_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_OVERFLOW_POS)) /**< OVERFLOW Mask */
<> 157:ff67d9f36b67 247 #define MXC_F_RTC_INTEN_TRIM_POS 4 /**< TRIM Position */
<> 157:ff67d9f36b67 248 #define MXC_F_RTC_INTEN_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_TRIM_POS)) /**< TRIM Mask */
<> 157:ff67d9f36b67 249 /**@} end of group RTC_INTEN_Register */
<> 157:ff67d9f36b67 250 /**
<> 157:ff67d9f36b67 251 * @ingroup rtc_registers
<> 157:ff67d9f36b67 252 * @defgroup RTC_PRESCALE_Register RTC_PRESCALE.
<> 157:ff67d9f36b67 253 * @{
<> 157:ff67d9f36b67 254 */
<> 157:ff67d9f36b67 255 #define MXC_F_RTC_PRESCALE_PRESCALE_POS 0 /**< PRESCALE Position */
<> 157:ff67d9f36b67 256 #define MXC_F_RTC_PRESCALE_PRESCALE ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_PRESCALE_POS)) /**< PRESCALE Mask */
<> 157:ff67d9f36b67 257 /**@} end of group RTC_INTEN_Register */
<> 157:ff67d9f36b67 258 /**
<> 157:ff67d9f36b67 259 * @ingroup rtc_registers
<> 157:ff67d9f36b67 260 * @defgroup RTC_PRESCALE_MASK_Register RTC_PRESCALE_MASK.
<> 157:ff67d9f36b67 261 * @{
<> 157:ff67d9f36b67 262 */
<> 157:ff67d9f36b67 263 #define MXC_F_RTC_PRESCALE_MASK_PRESCALE_MASK_POS 0 /**< PRESCALE_MASK Position */
<> 157:ff67d9f36b67 264 #define MXC_F_RTC_PRESCALE_MASK_PRESCALE_MASK ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_MASK_PRESCALE_MASK_POS)) /**< PRESCALE_MASK Mask */
<> 157:ff67d9f36b67 265 /**@} end of group RTC_PRESCALE_MASK_Register */
<> 157:ff67d9f36b67 266 /**
<> 157:ff67d9f36b67 267 * @ingroup rtc_registers
<> 157:ff67d9f36b67 268 * @defgroup RTC_TRIM_CTRL_Register RTC_TRIM_CTRL.
<> 157:ff67d9f36b67 269 * @{
<> 157:ff67d9f36b67 270 */
<> 157:ff67d9f36b67 271 #define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS 0 /**< TRIM_ENABLE_R Position */
<> 157:ff67d9f36b67 272 #define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS)) /**< TRIM_ENABLE_R Mask */
<> 157:ff67d9f36b67 273 #define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS 1 /**< TRIM_FASTER_OVR_R Position */
<> 157:ff67d9f36b67 274 #define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS)) /**< TRIM_FASTER_OVR_R Mask */
<> 157:ff67d9f36b67 275 #define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS 2 /**< TRIM_SLOWER_R Position */
<> 157:ff67d9f36b67 276 #define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS)) /**< TRIM_SLOWER_R Mask */
<> 157:ff67d9f36b67 277 /**@} end of group RTC_TRIM_CTRL_Register */
<> 157:ff67d9f36b67 278 /**
<> 157:ff67d9f36b67 279 * @ingroup rtc_registers
<> 157:ff67d9f36b67 280 * @defgroup RTC_TRIM_VALUE_Register RTC_TRIM_VALUE.
<> 157:ff67d9f36b67 281 * @{
<> 157:ff67d9f36b67 282 */
<> 157:ff67d9f36b67 283 #define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS 0 /**< TRIM_VALUE Position */
<> 157:ff67d9f36b67 284 #define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE ((uint32_t)(0x0003FFFFUL << MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS)) /**< TRIM_VALUE Mask */
<> 157:ff67d9f36b67 285 #define MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL_POS 18 /**< TRIM_SLOWER_CONTROL Position */
<> 157:ff67d9f36b67 286 #define MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL_POS)) /**< TRIM_SLOWER_CONTROL Mask */
<> 157:ff67d9f36b67 287 /**@} end of group RTC_TRIM_VALUE_Register */
<> 157:ff67d9f36b67 288 /**
<> 157:ff67d9f36b67 289 * @ingroup rtc_registers
<> 157:ff67d9f36b67 290 * @defgroup RTC_NANO_CNTR_Register RTC_NANO_CNTR.
<> 157:ff67d9f36b67 291 * @{
<> 157:ff67d9f36b67 292 */
<> 157:ff67d9f36b67 293 #define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS 0 /**< NANORING_COUNTER Position */
<> 157:ff67d9f36b67 294 #define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER ((uint32_t)(0x0000FFFFUL << MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS)) /**< NANORING_COUNTER Mask */
<> 157:ff67d9f36b67 295 /**@} end of group RTC_NANO_CNTR_Register */
<> 157:ff67d9f36b67 296 /**
<> 157:ff67d9f36b67 297 * @ingroup rtc_registers
<> 157:ff67d9f36b67 298 * @defgroup RTC_CLK_CTRL_Register RTC_CLK_CTRL.
<> 157:ff67d9f36b67 299 * @{
<> 157:ff67d9f36b67 300 */
<> 157:ff67d9f36b67 301 #define MXC_F_RTC_CLK_CTRL_OSC1_EN_POS 0 /**< OSC1_EN Position */
<> 157:ff67d9f36b67 302 #define MXC_F_RTC_CLK_CTRL_OSC1_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC1_EN_POS)) /**< OSC1_EN Mask */
<> 157:ff67d9f36b67 303 #define MXC_F_RTC_CLK_CTRL_OSC2_EN_POS 1 /**< OSC2_EN Position */
<> 157:ff67d9f36b67 304 #define MXC_F_RTC_CLK_CTRL_OSC2_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC2_EN_POS)) /**< OSC2_EN Mask */
<> 157:ff67d9f36b67 305 #define MXC_F_RTC_CLK_CTRL_NANO_EN_POS 2 /**< NANO_EN Position */
<> 157:ff67d9f36b67 306 #define MXC_F_RTC_CLK_CTRL_NANO_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_NANO_EN_POS)) /**< NANO_EN Mask */
<> 157:ff67d9f36b67 307 /**@} end of group RTC_CLK_CTRL_Register */
<> 157:ff67d9f36b67 308 /**
<> 157:ff67d9f36b67 309 * @ingroup rtc_registers
<> 157:ff67d9f36b67 310 * @defgroup RTC_OSC_CTRL_Register RTC_OSC_CTRL.
<> 157:ff67d9f36b67 311 * @{
<> 157:ff67d9f36b67 312 */
<> 157:ff67d9f36b67 313 #define MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS 0 /**< OSC_BYPASS Position */
<> 157:ff67d9f36b67 314 #define MXC_F_RTC_OSC_CTRL_OSC_BYPASS ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS)) /**< OSC_BYPASS Mask */
<> 157:ff67d9f36b67 315 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS 1 /**< OSC_DISABLE_R Position */
<> 157:ff67d9f36b67 316 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS)) /**< OSC_DISABLE_R Mask */
<> 157:ff67d9f36b67 317 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS 2 /**< OSC_DISABLE_SEL Position */
<> 157:ff67d9f36b67 318 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS)) /**< OSC_DISABLE_SEL Mask */
<> 157:ff67d9f36b67 319 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS 3 /**< OSC_DISABLE_O Position */
<> 157:ff67d9f36b67 320 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS)) /**< OSC_DISABLE_O Mask */
<> 157:ff67d9f36b67 321 #define MXC_F_RTC_OSC_CTRL_OSC_WARMUP_ENABLE_POS 14 /**< OSC_WARMUP_ENABLE Position */
<> 157:ff67d9f36b67 322 #define MXC_F_RTC_OSC_CTRL_OSC_WARMUP_ENABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_WARMUP_ENABLE_POS)) /**< OSC_WARMUP_ENABLE Mask */
<> 157:ff67d9f36b67 323 /**@} end of group RTC_OSC_CTRL_Register */
<> 157:ff67d9f36b67 324
<> 157:ff67d9f36b67 325 /*
<> 157:ff67d9f36b67 326 Field values
<> 157:ff67d9f36b67 327 */
<> 157:ff67d9f36b67 328 /**
<> 157:ff67d9f36b67 329 * @ingroup RTC_CTRL_Register
<> 157:ff67d9f36b67 330 * @defgroup rtc_snz_mode_values RTC SNOOZE MODE Values
<> 157:ff67d9f36b67 331 * @{
<> 157:ff67d9f36b67 332 */
<> 157:ff67d9f36b67 333 #define MXC_V_RTC_CTRL_SNOOZE_DISABLE ((uint32_t)(0x00000000UL)) /**< SNOOZE Mode Disable */
<> 157:ff67d9f36b67 334 #define MXC_V_RTC_CTRL_SNOOZE_MODE_A ((uint32_t)(0x00000001UL)) /**< SNOOZE Mode A */
<> 157:ff67d9f36b67 335 #define MXC_V_RTC_CTRL_SNOOZE_MODE_B ((uint32_t)(0x00000002UL)) /**< SNOOZE Mode B */
<> 157:ff67d9f36b67 336 /**@} end of group rtc_snz_mode_values */
<> 157:ff67d9f36b67 337 /**
<> 157:ff67d9f36b67 338 * @ingroup RTC_PRESCALE_Register
<> 157:ff67d9f36b67 339 * @defgroup rtc_prescale_values RTC Prescale Values
<> 157:ff67d9f36b67 340 * @{
<> 157:ff67d9f36b67 341 */
<> 157:ff67d9f36b67 342 #define MXC_V_RTC_PRESCALE_DIV_2_0 ((uint32_t)(0x00000000UL)) /**< RTC Prescale Divide by \f$ 2^{0} \f$.*/
<> 157:ff67d9f36b67 343 #define MXC_V_RTC_PRESCALE_DIV_2_1 ((uint32_t)(0x00000001UL)) /**< RTC Prescale Divide by \f$ 2^{1} \f$.*/
<> 157:ff67d9f36b67 344 #define MXC_V_RTC_PRESCALE_DIV_2_2 ((uint32_t)(0x00000002UL)) /**< RTC Prescale Divide by \f$ 2^{2} \f$.*/
<> 157:ff67d9f36b67 345 #define MXC_V_RTC_PRESCALE_DIV_2_3 ((uint32_t)(0x00000003UL)) /**< RTC Prescale Divide by \f$ 2^{3} \f$.*/
<> 157:ff67d9f36b67 346 #define MXC_V_RTC_PRESCALE_DIV_2_4 ((uint32_t)(0x00000004UL)) /**< RTC Prescale Divide by \f$ 2^{4} \f$.*/
<> 157:ff67d9f36b67 347 #define MXC_V_RTC_PRESCALE_DIV_2_5 ((uint32_t)(0x00000005UL)) /**< RTC Prescale Divide by \f$ 2^{5} \f$.*/
<> 157:ff67d9f36b67 348 #define MXC_V_RTC_PRESCALE_DIV_2_6 ((uint32_t)(0x00000006UL)) /**< RTC Prescale Divide by \f$ 2^{6} \f$.*/
<> 157:ff67d9f36b67 349 #define MXC_V_RTC_PRESCALE_DIV_2_7 ((uint32_t)(0x00000007UL)) /**< RTC Prescale Divide by \f$ 2^{7} \f$.*/
<> 157:ff67d9f36b67 350 #define MXC_V_RTC_PRESCALE_DIV_2_8 ((uint32_t)(0x00000008UL)) /**< RTC Prescale Divide by \f$ 2^{8} \f$.*/
<> 157:ff67d9f36b67 351 #define MXC_V_RTC_PRESCALE_DIV_2_9 ((uint32_t)(0x00000009UL)) /**< RTC Prescale Divide by \f$ 2^{9} \f$.*/
<> 157:ff67d9f36b67 352 #define MXC_V_RTC_PRESCALE_DIV_2_10 ((uint32_t)(0x0000000AUL)) /**< RTC Prescale Divide by \f$ 2^{10} \f$.*/
<> 157:ff67d9f36b67 353 #define MXC_V_RTC_PRESCALE_DIV_2_11 ((uint32_t)(0x0000000BUL)) /**< RTC Prescale Divide by \f$ 2^{11} \f$.*/
<> 157:ff67d9f36b67 354 #define MXC_V_RTC_PRESCALE_DIV_2_12 ((uint32_t)(0x0000000CUL)) /**< RTC Prescale Divide by \f$ 2^{12} \f$.*/
<> 157:ff67d9f36b67 355 /**@} end of group rtc_prescale_values*/
<> 157:ff67d9f36b67 356
<> 157:ff67d9f36b67 357 #ifdef __cplusplus
<> 157:ff67d9f36b67 358 }
<> 157:ff67d9f36b67 359 #endif
<> 157:ff67d9f36b67 360
<> 157:ff67d9f36b67 361 #endif /* _MXC_RTC_REGS_H_ */
<> 157:ff67d9f36b67 362